From nobody Mon Feb 9 02:27:34 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1487364414442204.1765229069449; Fri, 17 Feb 2017 12:46:54 -0800 (PST) Received: from localhost ([::1]:55828 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cepQa-0001bQ-Vl for importer@patchew.org; Fri, 17 Feb 2017 15:46:53 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44519) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ceocM-0004YL-Ma for qemu-devel@nongnu.org; Fri, 17 Feb 2017 14:55:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ceocK-0005xl-IY for qemu-devel@nongnu.org; Fri, 17 Feb 2017 14:54:58 -0500 Received: from mail.kernel.org ([198.145.29.136]:34646) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ceocK-0005vP-4A for qemu-devel@nongnu.org; Fri, 17 Feb 2017 14:54:56 -0500 Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0BAB920220; Fri, 17 Feb 2017 19:54:54 +0000 (UTC) Received: from redhat.com (pool-96-237-235-121.bstnma.fios.verizon.net [96.237.235.121]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 5974E201FE; Fri, 17 Feb 2017 19:54:52 +0000 (UTC) Date: Fri, 17 Feb 2017 21:54:51 +0200 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Message-ID: <1487361200-29966-19-git-send-email-mst@redhat.com> References: <1487361200-29966-1-git-send-email-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1487361200-29966-1-git-send-email-mst@redhat.com> X-Mailer: git-send-email 2.8.0.287.g0deeb61 X-Mutt-Fcc: =sent X-Virus-Scanned: ClamAV using ClamSMTP X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 198.145.29.136 Subject: [Qemu-devel] [PULL 18/23] intel_iommu: add "caching-mode" option X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Eduardo Habkost , Aviv Ben-David , Peter Xu , Paolo Bonzini , Jason Wang , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Aviv Ben-David This capability asks the guest to invalidate cache before each map operatio= n. We can use this invalidation to trap map operations in the hypervisor. Signed-off-by: Aviv Ben-David [peterx: using "caching-mode" instead of "cache-mode" to align with spec] [peterx: re-write the subject to make it short and clear] Reviewed-by: Jason Wang Signed-off-by: Peter Xu Signed-off-by: Aviv Ben-David Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/i386/intel_iommu_internal.h | 1 + include/hw/i386/intel_iommu.h | 2 ++ hw/i386/intel_iommu.c | 5 +++++ 3 files changed, 8 insertions(+) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 356f188..4104121 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -202,6 +202,7 @@ #define VTD_CAP_MAMV (VTD_MAMV << 48) #define VTD_CAP_PSI (1ULL << 39) #define VTD_CAP_SLLPS ((1ULL << 34) | (1ULL << 35)) +#define VTD_CAP_CM (1ULL << 7) =20 /* Supported Adjusted Guest Address Widths */ #define VTD_CAP_SAGAW_SHIFT 8 diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index 405c9d1..fe645aa 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -257,6 +257,8 @@ struct IntelIOMMUState { uint8_t womask[DMAR_REG_SIZE]; /* WO (write only - read returns 0) */ uint32_t version; =20 + bool caching_mode; /* RO - is cap CM enabled? */ + dma_addr_t root; /* Current root table pointer */ bool root_extended; /* Type of root table (extended or not= ) */ bool dmar_enabled; /* Set if DMA remapping is enabled */ diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 3270fb9..50251c3 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2115,6 +2115,7 @@ static Property vtd_properties[] =3D { DEFINE_PROP_ON_OFF_AUTO("eim", IntelIOMMUState, intr_eim, ON_OFF_AUTO_AUTO), DEFINE_PROP_BOOL("x-buggy-eim", IntelIOMMUState, buggy_eim, false), + DEFINE_PROP_BOOL("caching-mode", IntelIOMMUState, caching_mode, FALSE), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -2496,6 +2497,10 @@ static void vtd_init(IntelIOMMUState *s) s->ecap |=3D VTD_ECAP_DT; } =20 + if (s->caching_mode) { + s->cap |=3D VTD_CAP_CM; + } + vtd_reset_context_cache(s); vtd_reset_iotlb(s); =20 --=20 MST