From nobody Fri Apr 26 16:21:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1486704507298244.3252129161201; Thu, 9 Feb 2017 21:28:27 -0800 (PST) Received: from localhost ([::1]:41896 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cc3kv-0007ys-QO for importer@patchew.org; Fri, 10 Feb 2017 00:28:25 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40165) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cc3iv-00064Z-3m for qemu-devel@nongnu.org; Fri, 10 Feb 2017 00:26:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cc3iu-0001Ud-2V for qemu-devel@nongnu.org; Fri, 10 Feb 2017 00:26:21 -0500 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:36695) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cc3iq-0001Rb-Ta; Fri, 10 Feb 2017 00:26:17 -0500 Received: by mail-pg0-x244.google.com with SMTP id 75so2187593pgf.3; Thu, 09 Feb 2017 21:26:16 -0800 (PST) Received: from surajjs.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id r78sm1308298pfl.63.2017.02.09.21.26.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 Feb 2017 21:26:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6TqYMhObFO6GN7l44/8LosSyjUpoN9zkftBSZzmFk28=; b=a64eZOxsgnwWI/qlRg3TcKJTLGOCj/I8+YrGXy4Fl+uPFslSzjmfcK7YSphifZoPbs w58397yM/4id4Fy+uH1x2IK0lpAPeJ5SSIZ8KdVu3quDSCqxZMWvaWLR9h5o774uoqeY WptNqMOwN9rSxriG4f0QBQ5FbNoth/WhFmk4RVqca87qJxjcn7JwvIIl1G0mDEGIhJs4 fsEneStSZp7i3ngCc6dJYX17GCrLnxMaol6gMqJExe/veCa2HBtWZ/Qk8KXla+ysVlcZ OoJr/yVaUSBa0n1rpMVTtXI/6bSCC3r7a348XTSPkwBKCCANYd54CJFhhETANx9l/E87 HAyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6TqYMhObFO6GN7l44/8LosSyjUpoN9zkftBSZzmFk28=; b=ue/YTfJ60kdtD/HuJ6UGMYbt9nwBBYWXTpf6fEqfrt2gl6I53YQ4VO7Y3kj3q3SwVu QfjduABj3WAit/rk5NlDxf3z5t4A4IkWvWzVQIWUeqW/1tR4tRy5751Yn/k8pC6+lVLb OW2LOYEP5+0wt2yXXmR01dzVAttFrl8V+ELGRshEcMtydgGjs72wbWdFeMdvcarBeQ8f mVfE1azDKqzozuJx1NTDAT5q7tZVrEKRwyXPRDgDJoPu22uxNtA9G6owYKT+0RErjc7a Pk/k77UyhSxTjkEydBuTwrz82JjW3i/efmA+Xj5bEGe9CJyC8G8/q5uapFj0otJ3dU8R VHsw== X-Gm-Message-State: AMke39nnns5dU7+TC/KVD4oPhKW3EHlmNu0UPx730wnx88/oLdPUqEq2LOGuLmo5oJfaQw== X-Received: by 10.84.164.231 with SMTP id l36mr9090174plg.166.1486704376065; Thu, 09 Feb 2017 21:26:16 -0800 (PST) From: Suraj Jitindar Singh To: qemu-ppc@nongnu.org Date: Fri, 10 Feb 2017 16:25:51 +1100 Message-Id: <1486704360-27361-2-git-send-email-sjitindarsingh@gmail.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1486704360-27361-1-git-send-email-sjitindarsingh@gmail.com> References: <1486704360-27361-1-git-send-email-sjitindarsingh@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [QEMU-PPC] [PATCH V2 01/10] target/ppc/POWER9: Add ISAv3.00 MMU definition X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, Suraj Jitindar Singh , agraf@suse.de, sam.bobroff@au1.ibm.com, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" POWER9 processors implement the mmu as defined in version 3.00 of the ISA. Add a definition for this mmu model and set the POWER9 cpu model to use this mmu model. Signed-off-by: Suraj Jitindar Singh --- target/ppc/cpu-qom.h | 5 ++++- target/ppc/mmu_helper.c | 2 ++ target/ppc/translate_init.c | 3 +-- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index b7977ba..4e3132b 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -86,10 +86,13 @@ enum powerpc_mmu_t { POWERPC_MMU_2_07 =3D POWERPC_MMU_64 | POWERPC_MMU_1TSEG | POWERPC_MMU_64K | POWERPC_MMU_AMR | 0x00000004, - /* FIXME Add POWERPC_MMU_3_OO defines */ /* Architecture 2.07 "degraded" (no 1T segments) */ POWERPC_MMU_2_07a =3D POWERPC_MMU_64 | POWERPC_MMU_AMR | 0x00000004, + /* Architecture 3.00 variant */ + POWERPC_MMU_3_00 =3D POWERPC_MMU_64 | POWERPC_MMU_1TSEG + | POWERPC_MMU_64K + | POWERPC_MMU_AMR | 0x00000005, }; =20 /*************************************************************************= ****/ diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index f746f53..172a305 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -1935,6 +1935,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) case POWERPC_MMU_2_06a: case POWERPC_MMU_2_07: case POWERPC_MMU_2_07a: + case POWERPC_MMU_3_00: #endif /* defined(TARGET_PPC64) */ env->tlb_need_flush =3D 0; tlb_flush(CPU(cpu)); @@ -1974,6 +1975,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_= ulong addr) case POWERPC_MMU_2_06a: case POWERPC_MMU_2_07: case POWERPC_MMU_2_07a: + case POWERPC_MMU_3_00: /* tlbie invalidate TLBs for all segments */ /* XXX: given the fact that there are too many segments to invalid= ate, * and we still don't have a tlb_flush_mask(env, n, mask) in = QEMU, diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index 76f79fa..84bf125 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -8816,8 +8816,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) (1ull << MSR_PMM) | (1ull << MSR_RI) | (1ull << MSR_LE); - /* Using 2.07 defines until new radix model is added. */ - pcc->mmu_model =3D POWERPC_MMU_2_07; + pcc->mmu_model =3D POWERPC_MMU_3_00; #if defined(CONFIG_SOFTMMU) pcc->handle_mmu_fault =3D ppc_hash64_handle_mmu_fault; /* segment page size remain the same */ --=20 2.5.5 From nobody Fri Apr 26 16:21:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1486704501775434.7303613997598; Thu, 9 Feb 2017 21:28:21 -0800 (PST) Received: from localhost ([::1]:41895 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cc3ko-0007rw-8q for importer@patchew.org; Fri, 10 Feb 2017 00:28:18 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40202) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cc3ix-000673-KQ for qemu-devel@nongnu.org; Fri, 10 Feb 2017 00:26:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cc3iw-0001W5-O9 for qemu-devel@nongnu.org; Fri, 10 Feb 2017 00:26:23 -0500 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:35701) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cc3iu-0001Ub-KU; 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h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ocJzN6UsnrJOUPHIcR9uy2pD3nLE9ifzGAzc5XEBoJw=; b=G6vOhPbazWFC+FoVIdjED8T7ly7HWu/BFrgEDs8Y3LBZEhEWXx45i6qPorlK0PI38B AMIHEYRnxm2hKgw13JdrLGb1q6vzHP9kmtSU8mX1wtfBTsbuodEVPsozENj3yXNkM5S3 3Mg92I8yCAh3AkMQvfpTkgUSdyc1fW2sXe1oF6j0A/JO0VudI3FZi54e1o1r35qEfpDL RKvZ+WUN6lz/XYx2pB6KkLQVrUWygZTLk6N59VWH095SmklLEkbWUe2HVIsmvDgt5rBf GTcvLNg4Jb1a3/L8WmA7gE9+BUoOYsUoylV/RdyiECEenEDC3nfhIebvUMhtOfAdSOhX AKkA== X-Gm-Message-State: AMke39l9QUx0VxAk4yo/hBBQpKuIUVJx4WlFyVjfpf4wtQvcpQC2t3zXz+Y3TSSEp4HbMA== X-Received: by 10.99.53.195 with SMTP id c186mr8422370pga.24.1486704379792; Thu, 09 Feb 2017 21:26:19 -0800 (PST) From: Suraj Jitindar Singh To: qemu-ppc@nongnu.org Date: Fri, 10 Feb 2017 16:25:52 +1100 Message-Id: <1486704360-27361-3-git-send-email-sjitindarsingh@gmail.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1486704360-27361-1-git-send-email-sjitindarsingh@gmail.com> References: <1486704360-27361-1-git-send-email-sjitindarsingh@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [QEMU-PPC] [PATCH V2 02/10] target/ppc: Fix LPCR DPFD mask define X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, Suraj Jitindar Singh , agraf@suse.de, sam.bobroff@au1.ibm.com, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The DPFD field in the LPCR is 3 bits wide. This has always been defined as 0x3 << shift which indicates a 2 bit field, which is incorrect. Correct this. Signed-off-by: Suraj Jitindar Singh --- target/ppc/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index bc2a2ce..bb96dd5 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -381,7 +381,7 @@ struct ppc_slb_t { #define LPCR_ISL (1ull << (63 - 2)) #define LPCR_KBV (1ull << (63 - 3)) #define LPCR_DPFD_SHIFT (63 - 11) -#define LPCR_DPFD (0x3ull << LPCR_DPFD_SHIFT) +#define LPCR_DPFD (0x7ull << LPCR_DPFD_SHIFT) #define LPCR_VRMASD_SHIFT (63 - 16) #define LPCR_VRMASD (0x1full << LPCR_VRMASD_SHIFT) #define LPCR_RMLS_SHIFT (63 - 37) --=20 2.5.5 From nobody Fri Apr 26 16:21:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1486704818434857.3493730933502; Thu, 9 Feb 2017 21:33:38 -0800 (PST) Received: from localhost ([::1]:41930 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cc3pw-0004Gm-14 for importer@patchew.org; Fri, 10 Feb 2017 00:33:36 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40306) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cc3j4-0006Cs-Dl for qemu-devel@nongnu.org; Fri, 10 Feb 2017 00:26:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cc3j3-0001YH-2k for qemu-devel@nongnu.org; Fri, 10 Feb 2017 00:26:30 -0500 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:32818) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cc3iy-0001WV-C9; Fri, 10 Feb 2017 00:26:24 -0500 Received: by mail-pg0-x244.google.com with SMTP id 194so2208259pgd.0; Thu, 09 Feb 2017 21:26:24 -0800 (PST) Received: from surajjs.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id r78sm1308298pfl.63.2017.02.09.21.26.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 Feb 2017 21:26:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PzhvIcrBi9btcPVpigl/k+BtcF450gg0JR7bQDRAdiY=; b=PgKXBN/1VjFTRqsDF0TA6UR4g/EPto7U6CcisGVwusxeTkwQ1EOlJxsQUw0xqV3IFN XjfHarfIHx28iFqBpNKwpduQ1NhsTICMn0VdSedZW1fl3hRv+/pit8cUQVcw5sz1B8k8 F7XdEKileziskdk/FW/aF4AAy33ju8aZc3qVxSkuHmUY8Udgju1jB9uwAyvpmmTdElK4 0v8aYtWbhtojShe9kL1rILEhqSoHJARh/kBRyvWTNSsvJEDpD0xPVKC/vZsqw6gwcqva +LDBdZqFThSIqoiU2CPGEIcWyOL/gzVj5iKJurkDPX072Efyj+LdZBdnhHHAdtEiWQQZ 1IHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PzhvIcrBi9btcPVpigl/k+BtcF450gg0JR7bQDRAdiY=; b=XRimpAm717Q4CylbBjXSdQYysS+mqiN87OpHltruoks3VDc25Ep0yv2du292B5EzPa y78DBuZgvg7/AGKlywjIqYyqzvvsAn9AcAUWXyocy9Vp15Dq4IYt/Ab0qXAq7MBLZjbH 9lNxsulQNFgYn5wa9qhs1n+vg4CK8e3Kw0G/Wqde6mTjex6HlgoR+SJr0c6gsRQ4mqdy sD3/3TFj1K6q7VT12gk/Sh++up+TS5zXt4vfwowEbNZaT5OA2edx9YEKe+mDuMAXJd+1 bb4uQXjyG0FxCU5KDDxtbFvfq8HoDi9f2J2Z6OA/z33KWPU2ihyFfD3HwCLuOZfA/qOX 48Tw== X-Gm-Message-State: AMke39nzpXqpODq34klbG9Nh7Yg1QJUTO71TFnX84uIDFrPzrAmASRCke5jLorK52n9mQQ== X-Received: by 10.84.139.195 with SMTP id 61mr9043305plr.116.1486704383586; Thu, 09 Feb 2017 21:26:23 -0800 (PST) From: Suraj Jitindar Singh To: qemu-ppc@nongnu.org Date: Fri, 10 Feb 2017 16:25:53 +1100 Message-Id: <1486704360-27361-4-git-send-email-sjitindarsingh@gmail.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1486704360-27361-1-git-send-email-sjitindarsingh@gmail.com> References: <1486704360-27361-1-git-send-email-sjitindarsingh@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [QEMU-PPC] [PATCH V2 03/10] target/ppc/POWER9: Adapt LPCR handling for POWER9 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, Suraj Jitindar Singh , agraf@suse.de, sam.bobroff@au1.ibm.com, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The logical partitioning control register controls a threads operation based on the partition it is currently executing. Add new definitions and update the mask used when writing to the LPCR based on the POWER9 spec. Signed-off-by: Suraj Jitindar Singh --- target/ppc/cpu.h | 18 ++++++++++++++++++ target/ppc/mmu-hash64.c | 8 ++++++++ target/ppc/translate_init.c | 24 ++++++++++++++++++------ 3 files changed, 44 insertions(+), 6 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index bb96dd5..425e79d 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -384,12 +384,19 @@ struct ppc_slb_t { #define LPCR_DPFD (0x7ull << LPCR_DPFD_SHIFT) #define LPCR_VRMASD_SHIFT (63 - 16) #define LPCR_VRMASD (0x1full << LPCR_VRMASD_SHIFT) +/* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask */ +#define LPCR_PECE_U_SHIFT (63 - 19) +#define LPCR_PECE_U_MASK (0x7ull << LPCR_PECE_U_SHIFT) +#define LPCR_HVEE (1ull << (63 - 17)) /* Hypervisor Virt Exit Enab= le */ #define LPCR_RMLS_SHIFT (63 - 37) #define LPCR_RMLS (0xfull << LPCR_RMLS_SHIFT) #define LPCR_ILE (1ull << (63 - 38)) #define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */ #define LPCR_AIL (3ull << LPCR_AIL_SHIFT) +#define LPCR_UPRT (1ull << (63 - 41)) /* Use Process Table */ +#define LPCR_EVIRT (1ull << (63 - 42)) /* Enhanced Virtualisation */ #define LPCR_ONL (1ull << (63 - 45)) +#define LPCR_LD (1ull << (63 - 46)) /* Large Decrementer */ #define LPCR_P7_PECE0 (1ull << (63 - 49)) #define LPCR_P7_PECE1 (1ull << (63 - 50)) #define LPCR_P7_PECE2 (1ull << (63 - 51)) @@ -398,11 +405,22 @@ struct ppc_slb_t { #define LPCR_P8_PECE2 (1ull << (63 - 49)) #define LPCR_P8_PECE3 (1ull << (63 - 50)) #define LPCR_P8_PECE4 (1ull << (63 - 51)) +/* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask */ +#define LPCR_PECE_L_SHIFT (63 - 51) +#define LPCR_PECE_L_MASK (0x1full << LPCR_PECE_L_SHIFT) +#define LPCR_PDEE (1ull << (63 - 47)) /* Privileged Doorbell Exit = EN */ +#define LPCR_HDEE (1ull << (63 - 48)) /* Hyperv Doorbell Exit Enab= le */ +#define LPCR_EEE (1ull << (63 - 49)) /* External Exit Enable = */ +#define LPCR_DEE (1ull << (63 - 50)) /* Decrementer Exit Enable = */ +#define LPCR_OEE (1ull << (63 - 51)) /* Other Exit Enable = */ #define LPCR_MER (1ull << (63 - 52)) +#define LPCR_GTSE (1ull << (63 - 53)) /* Guest Translation Shootdo= wn */ #define LPCR_TC (1ull << (63 - 54)) +#define LPCR_HEIC (1ull << (63 - 59)) /* HV Extern Interrupt Contr= ol */ #define LPCR_LPES0 (1ull << (63 - 60)) #define LPCR_LPES1 (1ull << (63 - 61)) #define LPCR_RMI (1ull << (63 - 62)) +#define LPCR_HVICE (1ull << (63 - 62)) /* HV Virtualisation Int Ena= ble */ #define LPCR_HDICE (1ull << (63 - 63)) =20 #define msr_sf ((env->msr >> MSR_SF) & 1) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index bb78fb5..24d9901 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -1050,6 +1050,14 @@ void helper_store_lpcr(CPUPPCState *env, target_ulon= g val) LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE); break; + case POWERPC_MMU_3_00: /* P9 */ + lpcr =3D val & (LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | + (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL= | + LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | + (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EE= E | + LPCR_DEE | LPCR_OEE)) | LPCR_MER | LPCR_GTSE | LPCR_= TC | + LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE); + break; default: ; } diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index 84bf125..be35cbd 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -8870,12 +8870,24 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu) lpcr->default_value &=3D ~LPCR_RMLS; lpcr->default_value |=3D 1ull << LPCR_RMLS_SHIFT; =20 - /* P7 and P8 has slightly different PECE bits, mostly because P8 adds - * bit 47 and 48 which are reserved on P7. Here we set them all, which - * will work as expected for both implementations - */ - lpcr->default_value |=3D LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2= | - LPCR_P8_PECE3 | LPCR_P8_PECE4; + switch (env->mmu_model) { + case POWERPC_MMU_3_00: + /* By default we choose legacy mode and switch to new hash or radix + * when a register process table hcall is made. So disable process + * tables and guest translation shootdown by default + */ + lpcr->default_value &=3D ~(LPCR_UPRT | LPCR_GTSE); + lpcr->default_value |=3D LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_D= EE | + LPCR_OEE; + break; + default: + /* P7 and P8 has slightly different PECE bits, mostly because P8 a= dds + * bit 47 and 48 which are reserved on P7. Here we set them all, w= hich + * will work as expected for both implementations + */ + lpcr->default_value |=3D LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_P= ECE2 | + LPCR_P8_PECE3 | LPCR_P8_PECE4; + } =20 /* We should be followed by a CPU reset but update the active value * just in case... --=20 2.5.5 From nobody Fri Apr 26 16:21:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1486704508655315.2479158952651; Thu, 9 Feb 2017 21:28:28 -0800 (PST) Received: from localhost ([::1]:41897 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cc3kx-000807-7d for importer@patchew.org; Fri, 10 Feb 2017 00:28:27 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40321) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cc3j5-0006DV-1A for qemu-devel@nongnu.org; Fri, 10 Feb 2017 00:26:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cc3j4-0001ZD-5Z for qemu-devel@nongnu.org; Fri, 10 Feb 2017 00:26:31 -0500 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]:32825) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cc3j2-0001Xa-5y; Fri, 10 Feb 2017 00:26:28 -0500 Received: by mail-pg0-x241.google.com with SMTP id 194so2208413pgd.0; Thu, 09 Feb 2017 21:26:28 -0800 (PST) Received: from surajjs.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id r78sm1308298pfl.63.2017.02.09.21.26.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 Feb 2017 21:26:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+FgwE+zW7NOf3GKKlR3f4TtJtf7N8IbzIyHtDhimvNE=; b=qjLKdyaaclHiJDR/UbBebvD7NIoIkd2/Qb/hWkdWk5vU7wyh5rGG5pFbpmQDl71Xoy bqvHU6+o2w8s9KE9LIEoKP8BwtKuST1zNFEAhup/hDNtPCaFjDKCpkLrsdmEbWsv8Dlp ORDBxmxs4a0+c8ZlKQAyAELi8iESvuQR40W7wtD6+x3FOTiBPI/5vjQcVzWKBI85bQJQ 4BYw5CkOFxs4tkCMqyuKIVepbfbOTcEkp2J9X7jS5fULmXe5cWzsj2tN4eSv0MPw32wJ DiJNlnfnfqn7G+7Px0c22rXVjAjBoyFywB4JRhQrmu6crXkla1G3VEjGWzqYGbFH/mjD EhhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+FgwE+zW7NOf3GKKlR3f4TtJtf7N8IbzIyHtDhimvNE=; b=cU5MQyxUW7POodLX1r7ox7h1XFOvMjgHKLBtY27UVJ/pUwozVrfND/KOhZVlTk3EVt 2kZSGRHLFv0d+Ja9vwDkyV7036nUvkAda5XMk7GOVTshd5ekiOQ7C+1m/MIb7+TZ84l/ zJGtM30hBIZVLwOl1uOZ/0VKSvGZGTDnLCFuOagpvb/rr4GXHgI0Xcr5yNAlnd8VDHPm CswaadyGdjtCsAqrtgHVyH8SebweqkIwscR9djHmTHIqCqgrIIioHBstE9uygXp/ipN8 XfhyJh0jcmJCQT8mHpgKWmrzWfFjfDWl77l/Uj2M/d/86SzuSpZ04YXi7eFJ+H+b/Ulr Vtjw== X-Gm-Message-State: AMke39kjLBxEk34d8BKvuvlgFpgiwklaN/xko6j1a8fyHOkNyBLLVp7unmjeed9W7yb0qw== X-Received: by 10.84.176.131 with SMTP id v3mr9123576plb.20.1486704387377; Thu, 09 Feb 2017 21:26:27 -0800 (PST) From: Suraj Jitindar Singh To: qemu-ppc@nongnu.org Date: Fri, 10 Feb 2017 16:25:54 +1100 Message-Id: <1486704360-27361-5-git-send-email-sjitindarsingh@gmail.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1486704360-27361-1-git-send-email-sjitindarsingh@gmail.com> References: <1486704360-27361-1-git-send-email-sjitindarsingh@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [QEMU-PPC] [PATCH V2 04/10] target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, Suraj Jitindar Singh , agraf@suse.de, sam.bobroff@au1.ibm.com, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The vpm0 bit was removed from the LPCR in POWER9, this bit controlled whether ISI and DSI interrupts were directed to the hypervisor or the partition. These interrupts now go to the hypervisor irrespective, thus it is no longer necessary to check the vmp0 bit in the LPCR. Signed-off-by: Suraj Jitindar Singh --- target/ppc/mmu-hash64.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 24d9901..7c5d589 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -640,7 +640,15 @@ static void ppc_hash64_set_isi(CPUState *cs, CPUPPCSta= te *env, if (msr_ir) { vpm =3D !!(env->spr[SPR_LPCR] & LPCR_VPM1); } else { - vpm =3D !!(env->spr[SPR_LPCR] & LPCR_VPM0); + switch (env->mmu_model) { + case POWERPC_MMU_3_00: + /* Field deprecated in ISAv3.00 - interrupts always go to hype= rv */ + vpm =3D true; + break; + default: + vpm =3D !!(env->spr[SPR_LPCR] & LPCR_VPM0); + break; + } } if (vpm && !msr_hv) { cs->exception_index =3D POWERPC_EXCP_HISI; @@ -658,7 +666,15 @@ static void ppc_hash64_set_dsi(CPUState *cs, CPUPPCSta= te *env, uint64_t dar, if (msr_dr) { vpm =3D !!(env->spr[SPR_LPCR] & LPCR_VPM1); } else { - vpm =3D !!(env->spr[SPR_LPCR] & LPCR_VPM0); + switch (env->mmu_model) { + case POWERPC_MMU_3_00: + /* Field deprecated in ISAv3.00 - interrupts always go to hype= rv */ + vpm =3D true; + break; + default: + vpm =3D !!(env->spr[SPR_LPCR] & LPCR_VPM0); + break; + } } if (vpm && !msr_hv) { cs->exception_index =3D POWERPC_EXCP_HDSI; --=20 2.5.5 From nobody Fri Apr 26 16:21:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 148670506606766.14516090936979; Thu, 9 Feb 2017 21:37:46 -0800 (PST) Received: from localhost ([::1]:41964 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cc3tw-0008Dh-Qe for importer@patchew.org; Fri, 10 Feb 2017 00:37:44 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40382) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cc3jB-0006K8-Oc for qemu-devel@nongnu.org; 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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IoE9u474s98ohhvXeptESpieBTQT79l+jYO8QvdzUNI=; b=LvzCpPY2f0OHfQECu7OjAgg9HR4yuGg0AO0yCqAnKQFZeoPI1LWET3CHkMCrRkY2+8 48nKDdoFSkoU42XahXa+T9+/9xcuHiOZkKTeS0FUTIdeJouP9ZsOxi5GTZ9UAZJDv/pc 4cO6Ohnj/fmhOT1I6DDzOA32IqUUMVDpXXCD57yBS/3H3oGjXYD61e1vwOvC86T1f2Fz 7GhbTLYKnsjz/ZfI9EQ5vtwSRSzNP1iUwz0+xaVugFfDSsNlmZQE9x8Tq51xQnURBK5v ekWw9IZ2QY6dEsRzFDvf5aBsh9is6Bx9NLf0MiRIJ9rFWaFUircD2aA+wd+YPuUEJh3H qo1Q== X-Gm-Message-State: AMke39kdAD2mk6XZkd/JlMcDGkxpElGzT0N5DUNih9iaaIGf+9I1kNu+Qw/PmFsOS3m/Eg== X-Received: by 10.98.55.66 with SMTP id e63mr8086053pfa.156.1486704391097; Thu, 09 Feb 2017 21:26:31 -0800 (PST) From: Suraj Jitindar Singh To: qemu-ppc@nongnu.org Date: Fri, 10 Feb 2017 16:25:55 +1100 Message-Id: <1486704360-27361-6-git-send-email-sjitindarsingh@gmail.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1486704360-27361-1-git-send-email-sjitindarsingh@gmail.com> References: <1486704360-27361-1-git-send-email-sjitindarsingh@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [QEMU-PPC] [PATCH V2 05/10] target/ppc: Add patb_entry to sPAPRMachineState X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, Suraj Jitindar Singh , agraf@suse.de, sam.bobroff@au1.ibm.com, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" ISA v3.00 adds the idea of a partition table which is used to store the address translation details for all partitions on the system. The partition table consists of double word entries indexed by partition id where the sec= ond double word contains the location of the process table in guest memory. The process table is registered by the guest via a h-call. We need somewhere to store the address of the process table so we add an en= try to the sPAPRMachineState struct called patb_entry to represent the second doubleword of a single partition table entry corresponding to the current guest. We need to store this value so we know if the guest is using radix or hash translation and the location of the corresponding process table in gue= st memory. Since we only have a single guest per qemu instance, we only need o= ne entry. Since the partition table is technically a hypervisor resource we require t= hat access to it is abstracted by the virtual hypervisor through the calls [set/get]_patbe(). Currently the value of the entry is never set (and thus defaults to 0 indicating hash), but it will be required to both implement POWER9 kvm support and tcg radix support. We also add this field to be migrated as part of the sPAPRMachineState as we will need it on the receiving side as the guest will never tell us this information again and we need it to perform translation. Signed-off-by: Suraj Jitindar Singh --- hw/ppc/spapr.c | 19 +++++++++++++++++++ include/hw/ppc/spapr.h | 1 + target/ppc/cpu.h | 2 ++ 3 files changed, 22 insertions(+) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index e465d7a..057adae 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1018,6 +1018,20 @@ static void emulate_spapr_hypercall(PPCVirtualHyperv= isor *vhyp, } } =20 +static void spapr_set_patbe(PPCVirtualHypervisor *vhyp, uint64_t val) +{ + sPAPRMachineState *spapr =3D SPAPR_MACHINE(qdev_get_machine()); + + spapr->patb_entry =3D val; +} + +static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp) +{ + sPAPRMachineState *spapr =3D SPAPR_MACHINE(qdev_get_machine()); + + return spapr->patb_entry; +} + #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VAL= ID) #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPT= E_DIRTY) @@ -1141,6 +1155,8 @@ static void ppc_spapr_reset(void) /* Check for unknown sysbus devices */ foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); =20 + spapr->patb_entry =3D 0; + /* Allocate and/or reset the hash page table */ spapr_reallocate_hpt(spapr, spapr_hpt_shift_for_ramsize(machine->maxram_size), @@ -1340,6 +1356,7 @@ static const VMStateDescription vmstate_spapr =3D { VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_= 3), =20 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), + VMSTATE_UINT64(patb_entry, sPAPRMachineState), VMSTATE_END_OF_LIST() }, .subsections =3D (const VMStateDescription*[]) { @@ -2733,6 +2750,8 @@ static void spapr_machine_class_init(ObjectClass *oc,= void *data) nc->nmi_monitor_handler =3D spapr_nmi; smc->phb_placement =3D spapr_phb_placement; vhc->hypercall =3D emulate_spapr_hypercall; + vhc->set_patbe =3D spapr_set_patbe; + vhc->get_patbe =3D spapr_get_patbe; } =20 static const TypeInfo spapr_machine_info =3D { diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index a2d8964..c6a929a 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -63,6 +63,7 @@ struct sPAPRMachineState { =20 void *htab; uint32_t htab_shift; + uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROCESS_TAB= LE */ hwaddr rma_size; int vrma_adjust; ssize_t rtas_size; diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 425e79d..a148729 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1218,6 +1218,8 @@ struct PPCVirtualHypervisor { struct PPCVirtualHypervisorClass { InterfaceClass parent; void (*hypercall)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu); + void (*set_patbe)(PPCVirtualHypervisor *vhyp, uint64_t val); + uint64_t (*get_patbe)(PPCVirtualHypervisor *vhyp); }; =20 #define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor" --=20 2.5.5 From nobody Fri Apr 26 16:21:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1486704778423576.9992411744928; Thu, 9 Feb 2017 21:32:58 -0800 (PST) Received: from localhost ([::1]:41928 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cc3pJ-0003nD-43 for importer@patchew.org; Fri, 10 Feb 2017 00:32:57 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40412) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cc3jF-0006Qq-9B for qemu-devel@nongnu.org; Fri, 10 Feb 2017 00:26:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cc3jD-0001cI-Ht for qemu-devel@nongnu.org; Fri, 10 Feb 2017 00:26:41 -0500 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:36731) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cc3j9-0001av-VC; Fri, 10 Feb 2017 00:26:36 -0500 Received: by mail-pg0-x244.google.com with SMTP id 75so2188374pgf.3; Thu, 09 Feb 2017 21:26:35 -0800 (PST) Received: from surajjs.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id r78sm1308298pfl.63.2017.02.09.21.26.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 Feb 2017 21:26:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fUVEUn5xQae3RBX1ygyR0RkUUOp4pqgcUjJ1eezuALY=; b=lh2/+DOYNra8UA+PGz7B8ZtlGYfdkg6sW6nVldPD5IWLN4wLq9LE1NIqQT/TwtbieE x8Z2yd6dHAoW+A/eTuaJ/NP3xBu58EG4bUJ9l+2IF+zEQGznG3V0/PRCzYBd54U3StN/ cwQH+vg2704expOCIwpPHvrP9WOZqCsBQXtXSjPt/UBnCkeC4MNcD2HCenFMsDthpHwn qLY0hOhKiykNDD7Fv796idwf/m5uzH5J0JCmIQVLfLWHAniriXCsSwV9it+l0VGp3wqY FP23/HqFzDCJn/1p+R4D9lrBQ0rQPhpyAYP4keolEhyjN2Nj40Z9EJJZtD7hgwco+AtM B7Cg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fUVEUn5xQae3RBX1ygyR0RkUUOp4pqgcUjJ1eezuALY=; b=k+qcyWVfjf2E0cYiagiJDetozN/jLJtPDH9cSVM3RudwCa1Kt6p/cFdwEsTZ0N/O9S lbVNwNjOiXoQZpgqz5oy5cB9s4YcXbV7QRD+Qwu+LySbEFBcZ8pKiuWUBi+mlLXSCjzX ikpC3h6rCY6XUZodIKHHqBEbcrinFixhLLIfK+bSWZ7GYDyQWl1VwJiAs0zuzUbIC0Ey dMeiqG1XICmwjKSfYFNNZa3Kg08kvR7sCs5al1S/kw23crMNYpHM9qfMe0/IYLua+eN5 NYnC5g7rMBwTKmnklYRg5Jay6qgiEg4LhfbyCCXQzxIWg6935upScSx63FEBLT8e1FlH pdNQ== X-Gm-Message-State: AMke39n8q/PJmq6ESx8o7EdgZCGhEpU100srS0L/eqWb9nB8UNaNkxy/0tICnwiOslPseA== X-Received: by 10.84.208.227 with SMTP id c32mr8958210plj.71.1486704395139; Thu, 09 Feb 2017 21:26:35 -0800 (PST) From: Suraj Jitindar Singh To: qemu-ppc@nongnu.org Date: Fri, 10 Feb 2017 16:25:56 +1100 Message-Id: <1486704360-27361-7-git-send-email-sjitindarsingh@gmail.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1486704360-27361-1-git-send-email-sjitindarsingh@gmail.com> References: <1486704360-27361-1-git-send-email-sjitindarsingh@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [QEMU-PPC] [PATCH V2 06/10] target/ppc: Don't use SDR1 when running under a POWER9 cpu model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, Suraj Jitindar Singh , agraf@suse.de, sam.bobroff@au1.ibm.com, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The SDR1 register was used on pre-POWER9 processors to store the location of the hash page table, however now this information will be stored in the partition table so we don't have SDR1 anymore. Additionally this register was only applicable for powernv as it is a hypervisor resource and thus shouldn't be accessed on a pseries machine. We no longer generate the SDR1 register if we are on a POWER9 or later cpu. We also rename the functions ppc_hash64_set_sdr1->ppc_hash64_set_htab and ppc_store_sdr1->ppc_store_htab to indicate that they are primarily concerned with setting htab_[base/mask]. We still set SDR1 in ppc_hash64_set_external_hpt for non-POWER9 cpus as this is used for kvm-pr to tell the hypervisor where the hash table is, note this means kvm-pr isn't yet supported on a POWER9 cpu model. We set SDR1 in ppc_store_htab for non-POWER9 cpus as this is the called by the powernv machine code to restore the sdr1 (and htab_[mask/base]) on incoming migration, note this means that the powernv machine isn't yet supported on a POWER9 cpu model. We also adapt the debug code to only print the SDR1 value if the register has been created. Signed-off-by: Suraj Jitindar Singh --- target/ppc/cpu.h | 2 +- target/ppc/kvm.c | 2 +- target/ppc/machine.c | 4 ++-- target/ppc/misc_helper.c | 3 ++- target/ppc/mmu-hash64.c | 12 +++++++++--- target/ppc/mmu-hash64.h | 2 +- target/ppc/mmu_helper.c | 12 +++++++++--- target/ppc/translate.c | 7 +++++-- target/ppc/translate_init.c | 17 ++++++++++++++--- 9 files changed, 44 insertions(+), 17 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index a148729..1ae0719 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1265,7 +1265,7 @@ int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr add= ress, int rw, #endif =20 #if !defined(CONFIG_USER_ONLY) -void ppc_store_sdr1 (CPUPPCState *env, target_ulong value); +void ppc_store_htab(CPUPPCState *env, target_ulong value); #endif /* !defined(CONFIG_USER_ONLY) */ void ppc_store_msr (CPUPPCState *env, target_ulong value); =20 diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 663d2e7..5e2323c 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -1228,7 +1228,7 @@ static int kvmppc_get_books_sregs(PowerPCCPU *cpu) } =20 if (!env->external_htab) { - ppc_store_sdr1(env, sregs.u.s.sdr1); + ppc_store_htab(env, sregs.u.s.sdr1); } =20 /* Sync SLB */ diff --git a/target/ppc/machine.c b/target/ppc/machine.c index df9f7a4..f6d5ade 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -77,7 +77,7 @@ static int cpu_load_old(QEMUFile *f, void *opaque, int ve= rsion_id) for (i =3D 0; i < 1024; i++) qemu_get_betls(f, &env->spr[i]); if (!env->external_htab) { - ppc_store_sdr1(env, sdr1); + ppc_store_htab(env, sdr1); } qemu_get_be32s(f, &env->vscr); qemu_get_be64s(f, &env->spe_acc); @@ -230,7 +230,7 @@ static int cpu_post_load(void *opaque, int version_id) =20 if (!env->external_htab) { /* Restore htab_base and htab_mask variables */ - ppc_store_sdr1(env, env->spr[SPR_SDR1]); + ppc_store_htab(env, env->spr[SPR_SDR1]); } =20 /* Invalidate all msr bits except MSR_TGPR/MSR_HVB before restoring */ diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index ab432ba..49ba767 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -84,7 +84,8 @@ void helper_store_sdr1(CPUPPCState *env, target_ulong val) =20 if (!env->external_htab) { if (env->spr[SPR_SDR1] !=3D val) { - ppc_store_sdr1(env, val); + env->spr[SPR_SDR1] =3D val; + ppc_store_htab(env, val); tlb_flush(CPU(cpu)); } } diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 7c5d589..e658873 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -285,13 +285,12 @@ target_ulong helper_load_slb_vsid(CPUPPCState *env, t= arget_ulong rb) /* * 64-bit hash table MMU handling */ -void ppc_hash64_set_sdr1(PowerPCCPU *cpu, target_ulong value, +void ppc_hash64_set_htab(PowerPCCPU *cpu, target_ulong value, Error **errp) { CPUPPCState *env =3D &cpu->env; target_ulong htabsize =3D value & SDR_64_HTABSIZE; =20 - env->spr[SPR_SDR1] =3D value; if (htabsize > 28) { error_setg(errp, "Invalid HTABSIZE 0x" TARGET_FMT_lx" stored in SDR1", @@ -313,7 +312,14 @@ void ppc_hash64_set_external_hpt(PowerPCCPU *cpu, void= *hpt, int shift, } else { env->external_htab =3D MMU_HASH64_KVM_MANAGED_HPT; } - ppc_hash64_set_sdr1(cpu, (target_ulong)(uintptr_t)hpt | (shift - 18), + switch (env->mmu_model) { + case POWERPC_MMU_3_00: + break; /* Power 9 doesn't have an SDR1 */ + default: + env->spr[SPR_SDR1] =3D (target_ulong) hpt | (shift - 18); + break; + } + ppc_hash64_set_htab(cpu, (target_ulong)(uintptr_t)hpt | (shift - 18), &local_err); if (local_err) { error_propagate(errp, local_err); diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h index 7a0b7fc..e930934 100644 --- a/target/ppc/mmu-hash64.h +++ b/target/ppc/mmu-hash64.h @@ -91,7 +91,7 @@ void ppc_hash64_update_rmls(CPUPPCState *env); #define HPTE64_V_1TB_SEG 0x4000000000000000ULL #define HPTE64_V_VRMA_MASK 0x4001ffffff000000ULL =20 -void ppc_hash64_set_sdr1(PowerPCCPU *cpu, target_ulong value, +void ppc_hash64_set_htab(PowerPCCPU *cpu, target_ulong value, Error **errp); void ppc_hash64_set_external_hpt(PowerPCCPU *cpu, void *hpt, int shift, Error **errp); diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index 172a305..e893e72 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -1995,17 +1995,23 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, targe= t_ulong addr) =20 /*************************************************************************= ****/ /* Special registers manipulation */ -void ppc_store_sdr1(CPUPPCState *env, target_ulong value) +void ppc_store_htab(CPUPPCState *env, target_ulong value) { qemu_log_mask(CPU_LOG_MMU, "%s: " TARGET_FMT_lx "\n", __func__, value); assert(!env->external_htab); - env->spr[SPR_SDR1] =3D value; + switch (env->mmu_model) { + case POWERPC_MMU_3_00: /* POWER 9 doesn't have an SDR1 */ + break; + default: /* Pre-POWER9 does */ + env->spr[SPR_SDR1] =3D value; + break; + } #if defined(TARGET_PPC64) if (env->mmu_model & POWERPC_MMU_64) { PowerPCCPU *cpu =3D ppc_env_get_cpu(env); Error *local_err =3D NULL; =20 - ppc_hash64_set_sdr1(cpu, value, &local_err); + ppc_hash64_set_htab(cpu, value, &local_err); if (local_err) { error_report_err(local_err); error_free(local_err); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index b48abae..473a40a 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -6850,9 +6850,12 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprin= tf_function cpu_fprintf, case POWERPC_MMU_2_06a: case POWERPC_MMU_2_07: case POWERPC_MMU_2_07a: + case POWERPC_MMU_3_00: #endif - cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx - " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1], + if (env->spr_cb[SPR_SDR1].name) { + cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); + } + cpu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n= ", env->spr[SPR_DAR], env->spr[SPR_DSISR]); break; case POWERPC_MMU_BOOKE206: diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index be35cbd..f401d31 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -32,6 +32,7 @@ #include "qapi/visitor.h" #include "hw/qdev-properties.h" #include "hw/ppc/ppc.h" +#include "mmu.h" =20 //#define PPC_DUMP_CPU //#define PPC_DEBUG_SPR @@ -722,8 +723,8 @@ static void gen_spr_generic (CPUPPCState *env) 0x00000000); } =20 -/* SPR common to all non-embedded PowerPC, including 601 */ -static void gen_spr_ne_601 (CPUPPCState *env) +/* SPR common to all non-embedded PowerPC, including POWER9 */ +static void gen_spr_ne_power9(CPUPPCState *env) { /* Exception processing */ spr_register_kvm(env, SPR_DSISR, "DSISR", @@ -739,6 +740,12 @@ static void gen_spr_ne_601 (CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_decr, &spr_write_decr, 0x00000000); +} + +/* SPR common to all non-embedded PowerPC, including 601 */ +static void gen_spr_ne_601(CPUPPCState *env) +{ + gen_spr_ne_power9(env); /* Memory management */ spr_register(env, SPR_SDR1, "SDR1", SPR_NOACCESS, SPR_NOACCESS, @@ -8200,7 +8207,6 @@ static void gen_spr_power8_rpr(CPUPPCState *env) =20 static void init_proc_book3s_64(CPUPPCState *env, int version) { - gen_spr_ne_601(env); gen_tbl(env); gen_spr_book3s_altivec(env); gen_spr_book3s_pmu_sup(env); @@ -8258,6 +8264,11 @@ static void init_proc_book3s_64(CPUPPCState *env, in= t version) gen_spr_power8_book4(env); gen_spr_power8_rpr(env); } + if (version >=3D BOOK3S_CPU_POWER9) { + gen_spr_ne_power9(env); + } else { + gen_spr_ne_601(env); + } if (version < BOOK3S_CPU_POWER8) { gen_spr_book3s_dbg(env); } else { --=20 2.5.5 From nobody Fri Apr 26 16:21:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MYt8xoPEe8yQn2HdDyLf/JRAyvuGJHHUMuBBSsfGFOg=; b=uTmLCHu9VqED+QXmUsq975Q+SykypF6QbKMKbGbAEy43HGHT/+DLa6uVIMHDWvHE5R cdroOiTKDmqUBV2ur2Npjqdd7zR+ngeW4fDlzVX7Mq/FO8J77Krhn59F8YS+Waaei8Sn b2Y3cEn91qHVyot0VUT4jebHq3wnvsfMMcaZE00KBdxk7zc7kaiod1k/BEPAEHcDM2KD LDziD1w8eRNEgx6XcBpmaCA8thgI+H2yWteVTrV8C3KwtDoqNMchQwAcsRkb9U+wb6Hc fTpml/PXhW9h9fBl0cWaeKnQvy0ojMLw9Z2mJCzRMlm3bjSju+CLoqcIRY5WzvN1dxVg /H4Q== X-Gm-Message-State: AMke39l66HrK4jeOgAskkF53FiPExXn9nOfmX226x1MSMihTQBETmUczhSejQvIij6WUzA== X-Received: by 10.99.95.151 with SMTP id t145mr8298338pgb.75.1486704399169; Thu, 09 Feb 2017 21:26:39 -0800 (PST) From: Suraj Jitindar Singh To: qemu-ppc@nongnu.org Date: Fri, 10 Feb 2017 16:25:57 +1100 Message-Id: <1486704360-27361-8-git-send-email-sjitindarsingh@gmail.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1486704360-27361-1-git-send-email-sjitindarsingh@gmail.com> References: <1486704360-27361-1-git-send-email-sjitindarsingh@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [QEMU-PPC] [PATCH V2 07/10] target/ppc/POWER9: Add POWER9 mmu fault handler X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, Suraj Jitindar Singh , agraf@suse.de, sam.bobroff@au1.ibm.com, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add a new mmu fault handler for the POWER9 cpu and add it as the handler for the POWER9 cpu definition. This handler checks if the guest is radix or hash based on the value in the partition table entry and calls the correct fault handler accordingly. The hash fault handling code has also been updated to check if the partition is using segment tables. Currently only legacy hash (no segment tables) is supported. Signed-off-by: Suraj Jitindar Singh --- target/ppc/mmu-hash64.c | 9 ++++++++ target/ppc/mmu.h | 50 +++++++++++++++++++++++++++++++++++++++++= ++++ target/ppc/mmu_helper.c | 40 ++++++++++++++++++++++++++++++++++++ target/ppc/translate_init.c | 2 +- 4 files changed, 100 insertions(+), 1 deletion(-) create mode 100644 target/ppc/mmu.h diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index e658873..ada8876 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -27,6 +27,7 @@ #include "kvm_ppc.h" #include "mmu-hash64.h" #include "exec/log.h" +#include "mmu.h" =20 //#define DEBUG_SLB =20 @@ -766,6 +767,14 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr= eaddr, /* 2. Translation is on, so look up the SLB */ slb =3D slb_lookup(cpu, eaddr); if (!slb) { + /* No entry found, check if in-memory segment tables are in use */ + if (ppc64_use_proc_tbl(cpu)) { + /* TODO - Unsupported */ + qemu_log_mask(LOG_UNIMP, "%s: unimplemented - segment table su= pport", + __func__); + /* Not much we can do here, generate a segment interrupt */ + } + /* Segment still not found, generate the appropriate interrupt */ if (rwx =3D=3D 2) { cs->exception_index =3D POWERPC_EXCP_ISEG; env->error_code =3D 0; diff --git a/target/ppc/mmu.h b/target/ppc/mmu.h new file mode 100644 index 0000000..9375921 --- /dev/null +++ b/target/ppc/mmu.h @@ -0,0 +1,50 @@ +/* + * PowerPC emulation generic mmu definitions for qemu. + * + * Copyright (c) 2017 Suraj Jitindar Singh, IBM Corporation + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef MMU_H +#define MMU_H + +#ifndef CONFIG_USER_ONLY + +/* Partition Table Entry Fields */ +#define PATBE1_GR 0x8000000000000000 + +#ifdef TARGET_PPC64 + +static inline bool ppc64_use_proc_tbl(PowerPCCPU *cpu) +{ + return !!(cpu->env.spr[SPR_LPCR] & LPCR_UPRT); +} + +static inline bool ppc64_radix_guest(PowerPCCPU *cpu) +{ + PPCVirtualHypervisorClass *vhc =3D + PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); + + return !!(vhc->get_patbe(cpu->vhyp) & PATBE1_GR); +} + +int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx, + int mmu_idx); + +#endif /* TARGET_PPC64 */ + +#endif /* CONFIG_USER_ONLY */ + +#endif /* MMU_H */ diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index e893e72..71ad771 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -28,6 +28,8 @@ #include "exec/cpu_ldst.h" #include "exec/log.h" #include "helper_regs.h" +#include "qemu/error-report.h" +#include "mmu.h" =20 //#define DEBUG_MMU //#define DEBUG_BATS @@ -1280,6 +1282,17 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf,= CPUPPCState *env) case POWERPC_MMU_2_07a: dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env)); break; + case POWERPC_MMU_3_00: + if (ppc64_radix_guest(ppc_env_get_cpu(env))) { + /* TODO - Unsupported */ + } else { + if (ppc64_use_proc_tbl(ppc_env_get_cpu(env))) { + /* TODO - Unsupported */ + } else { + dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env)); + break; + } + } #endif default: qemu_log_mask(LOG_UNIMP, "%s: unimplemented\n", __func__); @@ -1421,6 +1434,17 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vad= dr addr) case POWERPC_MMU_2_07: case POWERPC_MMU_2_07a: return ppc_hash64_get_phys_page_debug(cpu, addr); + case POWERPC_MMU_3_00: + if (ppc64_radix_guest(ppc_env_get_cpu(env))) { + /* TODO - Unsupported */ + } else { + if (ppc64_use_proc_tbl(ppc_env_get_cpu(env))) { + /* TODO - Unsupported */ + } else { + return ppc_hash64_get_phys_page_debug(cpu, addr); + } + } + break; #endif =20 case POWERPC_MMU_32B: @@ -2913,3 +2937,19 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAc= cessType access_type, retaddr); } } + +/*************************************************************************= *****/ + +/* ISA v3.00 (POWER9) Generic MMU Helpers */ + +int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx, + int mmu_idx) +{ + if (ppc64_radix_guest(cpu)) { /* Guest uses radix */ + /* TODO - Unsupported */ + error_report("Guest Radix Support Unimplemented"); + abort(); + } else { /* Guest uses hash */ + return ppc_hash64_handle_mmu_fault(cpu, eaddr, rwx, mmu_idx); + } +} diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index f401d31..a3a23d8 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -8829,7 +8829,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) (1ull << MSR_LE); pcc->mmu_model =3D POWERPC_MMU_3_00; #if defined(CONFIG_SOFTMMU) - pcc->handle_mmu_fault =3D ppc_hash64_handle_mmu_fault; + pcc->handle_mmu_fault =3D ppc64_v3_handle_mmu_fault; /* segment page size remain the same */ pcc->sps =3D &POWER7_POWER8_sps; #endif --=20 2.5.5 From nobody Fri Apr 26 16:21:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1486704778011922.4329950132945; Thu, 9 Feb 2017 21:32:58 -0800 (PST) Received: from localhost ([::1]:41929 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cc3pI-0003nw-KS for importer@patchew.org; Fri, 10 Feb 2017 00:32:56 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40463) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cc3jL-0006jt-01 for qemu-devel@nongnu.org; Fri, 10 Feb 2017 00:26:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cc3jK-0001fk-BH for qemu-devel@nongnu.org; Fri, 10 Feb 2017 00:26:47 -0500 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:33979) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cc3jH-0001eY-P7; Fri, 10 Feb 2017 00:26:43 -0500 Received: by mail-pf0-x241.google.com with SMTP id o64so777116pfb.1; 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b=goV8bs44uMuWyKAewGs7SwfSkqdgXVrrdoBmxe1WMkaMUnU6XQR5z46srte0EAqrqI MXSiXuWeMpOWBIQX/FXOGV900ToAUBqIJR9ZNkhCnTxuQKy9Pg+tat/mahbA/cCrl6f8 3no0ChAOhnJTApG4vBa99dfwUji3AoPX/0yca7ruNUdXjFd2lwTWlR2ezTyhT8egWVMm xrIqSeDFl4ReFxRpIaFq4bMZPiYaudMxMv8WTBzMot94ogWAdZOjjBZOQoGwmoVxwPPG 2bVJwL0Ct0TmKq8kuJ5FcEFDuiSh2R0pox89QHWWFVse85b15lcJGm/jEhRa9dicJAAm VN2g== X-Gm-Message-State: AMke39nRbOLE9yVU4vEGDL1ZmM8Q3phYepm1Ab3gyJUPQsg1dr1Awpo/hmZVbkhAH7hu4w== X-Received: by 10.99.43.136 with SMTP id r130mr8477439pgr.83.1486704403013; Thu, 09 Feb 2017 21:26:43 -0800 (PST) From: Suraj Jitindar Singh To: qemu-ppc@nongnu.org Date: Fri, 10 Feb 2017 16:25:58 +1100 Message-Id: <1486704360-27361-9-git-send-email-sjitindarsingh@gmail.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1486704360-27361-1-git-send-email-sjitindarsingh@gmail.com> References: <1486704360-27361-1-git-send-email-sjitindarsingh@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [QEMU-PPC] [PATCH V2 08/10] target/ppc/POWER9: Add POWER9 pa-features definition X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, Suraj Jitindar Singh , agraf@suse.de, sam.bobroff@au1.ibm.com, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add a pa-features definition which includes all of the new fields which have been added, note we don't claim support for any of these new features at this stage. Signed-off-by: Suraj Jitindar Singh Reviewed-by: David Gibson --- hw/ppc/spapr.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 057adae..44eb014 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -356,6 +356,20 @@ static void spapr_populate_pa_features(CPUPPCState *en= v, void *fdt, int offset) 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; + /* Currently we don't advertise any of the "new" ISAv3.00 functionalit= y */ + uint8_t pa_features_300[] =3D { 64, 0, + 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ + 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ + 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ + 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 24 - 29 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 30 - 35 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 36 - 41 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 42 - 47 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 48 - 53 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 54 - 59 */ + 0x00, 0x00, 0x00, 0x00 }; /* 60 - 63 */ + uint8_t *pa_features; size_t pa_size; =20 @@ -370,6 +384,10 @@ static void spapr_populate_pa_features(CPUPPCState *en= v, void *fdt, int offset) pa_features =3D pa_features_207; pa_size =3D sizeof(pa_features_207); break; + case POWERPC_MMU_3_00: + pa_features =3D pa_features_300; + pa_size =3D sizeof(pa_features_300); + break; default: return; } --=20 2.5.5 From nobody Fri Apr 26 16:21:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1486705039043471.2323218681569; Thu, 9 Feb 2017 21:37:19 -0800 (PST) Received: from localhost ([::1]:41963 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cc3tV-0007mZ-Nk for importer@patchew.org; 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Thu, 09 Feb 2017 21:26:46 -0800 (PST) From: Suraj Jitindar Singh To: qemu-ppc@nongnu.org Date: Fri, 10 Feb 2017 16:25:59 +1100 Message-Id: <1486704360-27361-10-git-send-email-sjitindarsingh@gmail.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1486704360-27361-1-git-send-email-sjitindarsingh@gmail.com> References: <1486704360-27361-1-git-send-email-sjitindarsingh@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [QEMU-PPC] [PATCH V2 09/10] target/ppc/POWER9: Add cpu_has_work function for POWER9 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, Suraj Jitindar Singh , agraf@suse.de, sam.bobroff@au1.ibm.com, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The cpu has work function is used to mask interrupts used to determine if there is work for the cpu based on the LPCR. Add a function to do this for POWER9 and add it to the POWER9 cpu definition. This is similar to that for POWER8 except using the LPCR bits as defined for POWER9. Signed-off-by: Suraj Jitindar Singh Reviewed-by: David Gibson --- target/ppc/translate_init.c | 45 +++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 45 insertions(+) diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index a3a23d8..cc8ab1f 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -8776,10 +8776,54 @@ static bool ppc_pvr_match_power9(PowerPCCPUClass *p= cc, uint32_t pvr) return false; } =20 +static bool cpu_has_work_POWER9(CPUState *cs) +{ + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + CPUPPCState *env =3D &cpu->env; + + if (cs->halted) { + if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { + return false; + } + /* External Exception */ + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && + (env->spr[SPR_LPCR] & LPCR_EEE)) { + return true; + } + /* Decrementer Exception */ + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && + (env->spr[SPR_LPCR] & LPCR_DEE)) { + return true; + } + /* Machine Check or Hypervisor Maintenance Exception */ + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | + 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { + return true; + } + /* Privileged Doorbell Exception */ + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && + (env->spr[SPR_LPCR] & LPCR_PDEE)) { + return true; + } + /* Hypervisor Doorbell Exception */ + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && + (env->spr[SPR_LPCR] & LPCR_HDEE)) { + return true; + } + if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { + return true; + } + return false; + } else { + return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); + } +} + POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); PowerPCCPUClass *pcc =3D POWERPC_CPU_CLASS(oc); + CPUClass *cc =3D CPU_CLASS(oc); =20 dc->fw_name =3D "PowerPC,POWER9"; dc->desc =3D "POWER9"; @@ -8790,6 +8834,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) PCR_COMPAT_2_05; pcc->init_proc =3D init_proc_POWER9; pcc->check_pow =3D check_pow_nocheck; + cc->has_work =3D cpu_has_work_POWER9; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB= | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | --=20 2.5.5 From nobody Fri Apr 26 16:21:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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charset="utf-8" Add POWER9 cpu to list of spapr core models which allows it to be specified as the cpu model for a pseries guest (e.g. -machine pseries -cpu POWER9). This now allows a POWER9 cpu to boot to userspace in tcg emulation for a pseries machine with a legacy kernel. Signed-off-by: Suraj Jitindar Singh Reviewed-by: David Gibson --- hw/ppc/spapr_cpu_core.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 9dddaeb..71253f9 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -360,6 +360,9 @@ static const char *spapr_core_models[] =3D { =20 /* POWER8NVL */ "POWER8NVL_v1.0", + + /* POWER9 */ + "POWER9_v1.0", }; =20 void spapr_cpu_core_class_init(ObjectClass *oc, void *data) --=20 2.5.5