[Qemu-devel] [QEMU-PPC] [PATCH V2 00/10] target/ppc: Implement POWER9 pseries tcg

Suraj Jitindar Singh posted 10 patches 164 weeks ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/1486704360-27361-1-git-send-email-sjitindarsingh@gmail.com
Test checkpatch passed
Test docker failed
Test s390x failed
hw/ppc/spapr.c              | 37 ++++++++++++++++++
hw/ppc/spapr_cpu_core.c     |  3 ++
include/hw/ppc/spapr.h      |  1 +
target/ppc/cpu-qom.h        |  5 ++-
target/ppc/cpu.h            | 24 +++++++++++-
target/ppc/kvm.c            |  2 +-
target/ppc/machine.c        |  4 +-
target/ppc/misc_helper.c    |  3 +-
target/ppc/mmu-hash64.c     | 49 +++++++++++++++++++++---
target/ppc/mmu-hash64.h     |  2 +-
target/ppc/mmu.h            | 50 +++++++++++++++++++++++++
target/ppc/mmu_helper.c     | 54 +++++++++++++++++++++++++--
target/ppc/translate.c      |  7 +++-
target/ppc/translate_init.c | 91 +++++++++++++++++++++++++++++++++++++++------
14 files changed, 302 insertions(+), 30 deletions(-)
create mode 100644 target/ppc/mmu.h

[Qemu-devel] [QEMU-PPC] [PATCH V2 00/10] target/ppc: Implement POWER9 pseries tcg

Posted by Suraj Jitindar Singh 164 weeks ago
This is V2 of the patch series to implement tcg emulation support for a
POWER9 cpu model for the pseries machine type running a legacy kernel.
That is a kernel which doesn't use the new radix mmu mode or the new hash
mmu mode with segment tables.

To use a POWER9 cpu provide the command line option "-cpu POWER9".

This series attempts to avoid precluding KVM-HV support for the POWER9
cpu model but doesn't attempt to support KVM-PR or the powernv machine
for the POWER9 cpu model as these aren't currently supported or
implemented and further code changes will be required in the event these
are implemented.

This series will be followed shortly by one to implement radix support and
currently trying to boot a kernel with support for radix with this series
will fail on the H_REGISTER_PROCESS_TABLE hcall.

The changes from V1 are as follows:

 - Drop patches which have already been merged.
 - Instead of allocating a whole partition table we allocate a single
   entry in the sPAPRMachineState and access it via the virtual hypv.
 - Changes to how we handle SDR1 and renaming of associated functions.
 - Drop patch to use the new pte format, guest kernels expect the old
   format anyway, so this will only be applicable when POWER9 powernv
   support is added, so delay adding support for this until then.
 - Rename the mmu fault handler to ppc64_v3_handle_mmu_fault.
 - Move segment table searching into the fault handler instead of in
   slb_lookup().
 - Move adding the POWER9 pseries cpu model to the end of the series.

Suraj Jitindar Singh (10):
  target/ppc/POWER9: Add ISAv3.00 MMU definition
  target/ppc: Fix LPCR DPFD mask define
  target/ppc/POWER9: Adapt LPCR handling for POWER9
  target/ppc/POWER9: Direct all instr and data storage interrupts to the
    hypv
  target/ppc: Add patb_entry to sPAPRMachineState
  target/ppc: Don't use SDR1 when running under a POWER9 cpu model
  target/ppc/POWER9: Add POWER9 mmu fault handler
  target/ppc/POWER9: Add POWER9 pa-features definition
  target/ppc/POWER9: Add cpu_has_work function for POWER9
  hw/ppc/spapr: Add POWER9 to pseries cpu models

 hw/ppc/spapr.c              | 37 ++++++++++++++++++
 hw/ppc/spapr_cpu_core.c     |  3 ++
 include/hw/ppc/spapr.h      |  1 +
 target/ppc/cpu-qom.h        |  5 ++-
 target/ppc/cpu.h            | 24 +++++++++++-
 target/ppc/kvm.c            |  2 +-
 target/ppc/machine.c        |  4 +-
 target/ppc/misc_helper.c    |  3 +-
 target/ppc/mmu-hash64.c     | 49 +++++++++++++++++++++---
 target/ppc/mmu-hash64.h     |  2 +-
 target/ppc/mmu.h            | 50 +++++++++++++++++++++++++
 target/ppc/mmu_helper.c     | 54 +++++++++++++++++++++++++--
 target/ppc/translate.c      |  7 +++-
 target/ppc/translate_init.c | 91 +++++++++++++++++++++++++++++++++++++++------
 14 files changed, 302 insertions(+), 30 deletions(-)
 create mode 100644 target/ppc/mmu.h

-- 
2.5.5


Re: [Qemu-devel] [QEMU-PPC] [PATCH V2 00/10] target/ppc: Implement POWER9 pseries tcg

Posted by Suraj Jitindar Singh 164 weeks ago
On Fri, 2017-02-10 at 16:25 +1100, Suraj Jitindar Singh wrote:
> This is V2 of the patch series to implement tcg emulation support for
> a
> POWER9 cpu model for the pseries machine type running a legacy
> kernel.
> That is a kernel which doesn't use the new radix mmu mode or the new
> hash
> mmu mode with segment tables.
FWIW tree available here:
https://gitlab.ozlabs.ibm.com/surajjs/qemu/tree/POWER9-LEGACY
> 
> To use a POWER9 cpu provide the command line option "-cpu POWER9".
> 
> This series attempts to avoid precluding KVM-HV support for the
> POWER9
> cpu model but doesn't attempt to support KVM-PR or the powernv
> machine
> for the POWER9 cpu model as these aren't currently supported or
> implemented and further code changes will be required in the event
> these
> are implemented.
> 
> This series will be followed shortly by one to implement radix
> support and
> currently trying to boot a kernel with support for radix with this
> series
> will fail on the H_REGISTER_PROCESS_TABLE hcall.
> 
> The changes from V1 are as follows:
> 
>  - Drop patches which have already been merged.
>  - Instead of allocating a whole partition table we allocate a single
>    entry in the sPAPRMachineState and access it via the virtual hypv.
>  - Changes to how we handle SDR1 and renaming of associated
> functions.
>  - Drop patch to use the new pte format, guest kernels expect the old
>    format anyway, so this will only be applicable when POWER9 powernv
>    support is added, so delay adding support for this until then.
>  - Rename the mmu fault handler to ppc64_v3_handle_mmu_fault.
>  - Move segment table searching into the fault handler instead of in
>    slb_lookup().
>  - Move adding the POWER9 pseries cpu model to the end of the series.
> 
> Suraj Jitindar Singh (10):
>   target/ppc/POWER9: Add ISAv3.00 MMU definition
>   target/ppc: Fix LPCR DPFD mask define
>   target/ppc/POWER9: Adapt LPCR handling for POWER9
>   target/ppc/POWER9: Direct all instr and data storage interrupts to
> the
>     hypv
>   target/ppc: Add patb_entry to sPAPRMachineState
>   target/ppc: Don't use SDR1 when running under a POWER9 cpu model
>   target/ppc/POWER9: Add POWER9 mmu fault handler
>   target/ppc/POWER9: Add POWER9 pa-features definition
>   target/ppc/POWER9: Add cpu_has_work function for POWER9
>   hw/ppc/spapr: Add POWER9 to pseries cpu models
> 
>  hw/ppc/spapr.c              | 37 ++++++++++++++++++
>  hw/ppc/spapr_cpu_core.c     |  3 ++
>  include/hw/ppc/spapr.h      |  1 +
>  target/ppc/cpu-qom.h        |  5 ++-
>  target/ppc/cpu.h            | 24 +++++++++++-
>  target/ppc/kvm.c            |  2 +-
>  target/ppc/machine.c        |  4 +-
>  target/ppc/misc_helper.c    |  3 +-
>  target/ppc/mmu-hash64.c     | 49 +++++++++++++++++++++---
>  target/ppc/mmu-hash64.h     |  2 +-
>  target/ppc/mmu.h            | 50 +++++++++++++++++++++++++
>  target/ppc/mmu_helper.c     | 54 +++++++++++++++++++++++++--
>  target/ppc/translate.c      |  7 +++-
>  target/ppc/translate_init.c | 91
> +++++++++++++++++++++++++++++++++++++++------
>  14 files changed, 302 insertions(+), 30 deletions(-)
>  create mode 100644 target/ppc/mmu.h
> 

Re: [Qemu-devel] [QEMU-PPC] [PATCH V2 00/10] target/ppc: Implement POWER9 pseries tcg

Posted by Suraj Jitindar Singh 164 weeks ago
On Fri, 2017-02-10 at 16:28 +1100, Suraj Jitindar Singh wrote:
> On Fri, 2017-02-10 at 16:25 +1100, Suraj Jitindar Singh wrote:
> > 
> > This is V2 of the patch series to implement tcg emulation support
> > for
> > a
> > POWER9 cpu model for the pseries machine type running a legacy
> > kernel.
> > That is a kernel which doesn't use the new radix mmu mode or the
> > new
> > hash
> > mmu mode with segment tables.
> FWIW tree available here:
> https://gitlab.ozlabs.ibm.com/surajjs/qemu/tree/POWER9-LEGACY
Scratch that, this:
https://github.ibm.com/surajjs/qemu/tree/POWER9-LEGACY
> > 
> > 
> > To use a POWER9 cpu provide the command line option "-cpu POWER9".
> > 
> > This series attempts to avoid precluding KVM-HV support for the
> > POWER9
> > cpu model but doesn't attempt to support KVM-PR or the powernv
> > machine
> > for the POWER9 cpu model as these aren't currently supported or
> > implemented and further code changes will be required in the event
> > these
> > are implemented.
> > 
> > This series will be followed shortly by one to implement radix
> > support and
> > currently trying to boot a kernel with support for radix with this
> > series
> > will fail on the H_REGISTER_PROCESS_TABLE hcall.
> > 
> > The changes from V1 are as follows:
> > 
> >  - Drop patches which have already been merged.
> >  - Instead of allocating a whole partition table we allocate a
> > single
> >    entry in the sPAPRMachineState and access it via the virtual
> > hypv.
> >  - Changes to how we handle SDR1 and renaming of associated
> > functions.
> >  - Drop patch to use the new pte format, guest kernels expect the
> > old
> >    format anyway, so this will only be applicable when POWER9
> > powernv
> >    support is added, so delay adding support for this until then.
> >  - Rename the mmu fault handler to ppc64_v3_handle_mmu_fault.
> >  - Move segment table searching into the fault handler instead of
> > in
> >    slb_lookup().
> >  - Move adding the POWER9 pseries cpu model to the end of the
> > series.
> > 
> > Suraj Jitindar Singh (10):
> >   target/ppc/POWER9: Add ISAv3.00 MMU definition
> >   target/ppc: Fix LPCR DPFD mask define
> >   target/ppc/POWER9: Adapt LPCR handling for POWER9
> >   target/ppc/POWER9: Direct all instr and data storage interrupts
> > to
> > the
> >     hypv
> >   target/ppc: Add patb_entry to sPAPRMachineState
> >   target/ppc: Don't use SDR1 when running under a POWER9 cpu model
> >   target/ppc/POWER9: Add POWER9 mmu fault handler
> >   target/ppc/POWER9: Add POWER9 pa-features definition
> >   target/ppc/POWER9: Add cpu_has_work function for POWER9
> >   hw/ppc/spapr: Add POWER9 to pseries cpu models
> > 
> >  hw/ppc/spapr.c              | 37 ++++++++++++++++++
> >  hw/ppc/spapr_cpu_core.c     |  3 ++
> >  include/hw/ppc/spapr.h      |  1 +
> >  target/ppc/cpu-qom.h        |  5 ++-
> >  target/ppc/cpu.h            | 24 +++++++++++-
> >  target/ppc/kvm.c            |  2 +-
> >  target/ppc/machine.c        |  4 +-
> >  target/ppc/misc_helper.c    |  3 +-
> >  target/ppc/mmu-hash64.c     | 49 +++++++++++++++++++++---
> >  target/ppc/mmu-hash64.h     |  2 +-
> >  target/ppc/mmu.h            | 50 +++++++++++++++++++++++++
> >  target/ppc/mmu_helper.c     | 54 +++++++++++++++++++++++++--
> >  target/ppc/translate.c      |  7 +++-
> >  target/ppc/translate_init.c | 91
> > +++++++++++++++++++++++++++++++++++++++------
> >  14 files changed, 302 insertions(+), 30 deletions(-)
> >  create mode 100644 target/ppc/mmu.h

Re: [Qemu-devel] [QEMU-PPC] [PATCH V2 00/10] target/ppc: Implement POWER9 pseries tcg

Posted by no-reply@patchew.org 164 weeks ago
Hi,

Your series failed automatic build test. Please find the testing commands and
their output below. If you have docker installed, you can probably reproduce it
locally.

Subject: [Qemu-devel] [QEMU-PPC] [PATCH V2 00/10] target/ppc: Implement POWER9 pseries tcg
Message-id: 1486704360-27361-1-git-send-email-sjitindarsingh@gmail.com
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash
set -e
git submodule update --init dtc
# Let docker tests dump environment info
export SHOW_ENV=1
export J=16
make docker-test-quick@centos6
make docker-test-mingw@fedora
make docker-test-build@min-glib
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
d20592c hw/ppc/spapr: Add POWER9 to pseries cpu models
09ac3a9 target/ppc/POWER9: Add cpu_has_work function for POWER9
2ae4ad5 target/ppc/POWER9: Add POWER9 pa-features definition
a0e8faf target/ppc/POWER9: Add POWER9 mmu fault handler
2754f17 target/ppc: Don't use SDR1 when running under a POWER9 cpu model
1321794 target/ppc: Add patb_entry to sPAPRMachineState
b165815 target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv
d5142fa target/ppc/POWER9: Adapt LPCR handling for POWER9
91ae6e4 target/ppc: Fix LPCR DPFD mask define
ff2da10 target/ppc/POWER9: Add ISAv3.00 MMU definition

=== OUTPUT BEGIN ===
Submodule 'dtc' (git://git.qemu-project.org/dtc.git) registered for path 'dtc'
fatal: read error: Connection reset by peer
Cloning into 'dtc'...
Clone of 'git://git.qemu-project.org/dtc.git' into submodule path 'dtc' failed
=== OUTPUT END ===

Test command exited with code: 1


---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@freelists.org

Re: [Qemu-devel] [QEMU-PPC] [PATCH V2 00/10] target/ppc: Implement POWER9 pseries tcg

Posted by David Gibson 164 weeks ago
On Fri, Feb 10, 2017 at 04:25:50PM +1100, Suraj Jitindar Singh wrote:
> This is V2 of the patch series to implement tcg emulation support for a
> POWER9 cpu model for the pseries machine type running a legacy kernel.
> That is a kernel which doesn't use the new radix mmu mode or the new hash
> mmu mode with segment tables.
> 
> To use a POWER9 cpu provide the command line option "-cpu POWER9".
> 
> This series attempts to avoid precluding KVM-HV support for the POWER9
> cpu model but doesn't attempt to support KVM-PR or the powernv machine
> for the POWER9 cpu model as these aren't currently supported or
> implemented and further code changes will be required in the event these
> are implemented.
> 
> This series will be followed shortly by one to implement radix support and
> currently trying to boot a kernel with support for radix with this series
> will fail on the H_REGISTER_PROCESS_TABLE hcall.

I've applied 1-4 to ppc-for-2.9.  That leaves something rather
incomplete, but then that's pretty much already true for our POWER9
support.

> 
> The changes from V1 are as follows:
> 
>  - Drop patches which have already been merged.
>  - Instead of allocating a whole partition table we allocate a single
>    entry in the sPAPRMachineState and access it via the virtual hypv.
>  - Changes to how we handle SDR1 and renaming of associated functions.
>  - Drop patch to use the new pte format, guest kernels expect the old
>    format anyway, so this will only be applicable when POWER9 powernv
>    support is added, so delay adding support for this until then.
>  - Rename the mmu fault handler to ppc64_v3_handle_mmu_fault.
>  - Move segment table searching into the fault handler instead of in
>    slb_lookup().
>  - Move adding the POWER9 pseries cpu model to the end of the series.
> 
> Suraj Jitindar Singh (10):
>   target/ppc/POWER9: Add ISAv3.00 MMU definition
>   target/ppc: Fix LPCR DPFD mask define
>   target/ppc/POWER9: Adapt LPCR handling for POWER9
>   target/ppc/POWER9: Direct all instr and data storage interrupts to the
>     hypv
>   target/ppc: Add patb_entry to sPAPRMachineState
>   target/ppc: Don't use SDR1 when running under a POWER9 cpu model
>   target/ppc/POWER9: Add POWER9 mmu fault handler
>   target/ppc/POWER9: Add POWER9 pa-features definition
>   target/ppc/POWER9: Add cpu_has_work function for POWER9
>   hw/ppc/spapr: Add POWER9 to pseries cpu models
> 
>  hw/ppc/spapr.c              | 37 ++++++++++++++++++
>  hw/ppc/spapr_cpu_core.c     |  3 ++
>  include/hw/ppc/spapr.h      |  1 +
>  target/ppc/cpu-qom.h        |  5 ++-
>  target/ppc/cpu.h            | 24 +++++++++++-
>  target/ppc/kvm.c            |  2 +-
>  target/ppc/machine.c        |  4 +-
>  target/ppc/misc_helper.c    |  3 +-
>  target/ppc/mmu-hash64.c     | 49 +++++++++++++++++++++---
>  target/ppc/mmu-hash64.h     |  2 +-
>  target/ppc/mmu.h            | 50 +++++++++++++++++++++++++
>  target/ppc/mmu_helper.c     | 54 +++++++++++++++++++++++++--
>  target/ppc/translate.c      |  7 +++-
>  target/ppc/translate_init.c | 91 +++++++++++++++++++++++++++++++++++++++------
>  14 files changed, 302 insertions(+), 30 deletions(-)
>  create mode 100644 target/ppc/mmu.h
> 

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson