From nobody Sun Feb 8 20:12:45 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1486504488948518.2095331842074; Tue, 7 Feb 2017 13:54:48 -0800 (PST) Received: from localhost ([::1]:56556 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cbDip-0006jA-KC for importer@patchew.org; Tue, 07 Feb 2017 16:54:47 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48934) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cbDdq-0002zO-7P for qemu-devel@nongnu.org; Tue, 07 Feb 2017 16:49:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cbDdp-0007cZ-1S for qemu-devel@nongnu.org; Tue, 07 Feb 2017 16:49:38 -0500 Received: from mx1.redhat.com ([209.132.183.28]:40892) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cbDdl-0007XN-6K; Tue, 07 Feb 2017 16:49:33 -0500 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 4A913274872; Tue, 7 Feb 2017 21:49:33 +0000 (UTC) Received: from apm-mustang-ev3-30.khw.lab.eng.bos.redhat.com (apm-mustang-ev3-30.khw.lab.eng.bos.redhat.com [10.16.184.124]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id v17LnVCH006452; Tue, 7 Feb 2017 16:49:32 -0500 From: Wei Huang To: qemu-devel@nongnu.org Date: Tue, 7 Feb 2017 16:49:29 -0500 Message-Id: <1486504171-26807-3-git-send-email-wei@redhat.com> In-Reply-To: <1486504171-26807-1-git-send-email-wei@redhat.com> References: <1486504171-26807-1-git-send-email-wei@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.22 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.38]); Tue, 07 Feb 2017 21:49:33 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH V3 2/4] target-arm: Add support for AArch64 PMU register PMXEVTYPER_EL0 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In order to support Linux perf, which uses PMXEVTYPER register, this patch adds read/write access support for PMXEVTYPER. The access is CONSTRAINED UNPREDICTABLE when PMSELR is not 0x1f. Additionally this patch adds support for PMXEVTYPER_EL0. Signed-off-by: Wei Huang --- target/arm/cpu.h | 1 - target/arm/helper.c | 30 +++++++++++++++++++++++++----- 2 files changed, 25 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8a82c73..f46607e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -307,7 +307,6 @@ typedef struct CPUARMState { uint64_t c9_pmcr; /* performance monitor control register */ uint64_t c9_pmcnten; /* perf monitor counter enables */ uint32_t c9_pmovsr; /* perf monitor overflow status */ - uint32_t c9_pmxevtyper; /* perf monitor event type */ uint32_t c9_pmuserenr; /* perf monitor user enable */ uint64_t c9_pmselr; /* perf monitor counter selection register */ uint32_t c9_pminten; /* perf monitor interrupt enables */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 67520ea..ec5cf1f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1054,7 +1054,25 @@ static void pmovsr_write(CPUARMState *env, const ARM= CPRegInfo *ri, static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - env->cp15.c9_pmxevtyper =3D value & 0xff; + /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when + * PMSELR value is equal to or greater than the number of implemented + * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI. + */ + if (env->cp15.c9_pmselr =3D=3D 0x1f) { + pmccfiltr_write(env, ri, value); + } +} + +static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + /* We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER + * are CONSTRAINED UNPREDICTABLE. See comments in pmxevtyper_write(). + */ + if (env->cp15.c9_pmselr =3D=3D 0x1f) { + return env->cp15.pmccfiltr_el0; + } else { + return 0; + } } =20 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -1234,10 +1252,12 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.pmccfiltr_el0), .resetvalue =3D 0, }, { .name =3D "PMXEVTYPER", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 = =3D 0, .opc2 =3D 1, - .access =3D PL0_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmxevtyper), - .accessfn =3D pmreg_access, .writefn =3D pmxevtyper_write, - .raw_writefn =3D raw_write }, + .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW, .accessfn =3D pmreg_acc= ess, + .writefn =3D pmxevtyper_write, .readfn =3D pmxevtyper_read }, + { .name =3D "PMXEVTYPER_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 13, .opc2 =3D 1, + .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW, .accessfn =3D pmreg_acc= ess, + .writefn =3D pmxevtyper_write, .readfn =3D pmxevtyper_read }, /* Unimplemented, RAZ/WI. */ { .name =3D "PMXEVCNTR", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 = =3D 0, .opc2 =3D 2, .access =3D PL0_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0, --=20 1.8.3.1