From nobody Sun Feb 8 18:43:19 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 148650436526741.93668083308194; Tue, 7 Feb 2017 13:52:45 -0800 (PST) Received: from localhost ([::1]:56547 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cbDgp-000568-OS for importer@patchew.org; Tue, 07 Feb 2017 16:52:43 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48929) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cbDdq-0002zH-4D for qemu-devel@nongnu.org; Tue, 07 Feb 2017 16:49:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cbDdp-0007ce-24 for qemu-devel@nongnu.org; Tue, 07 Feb 2017 16:49:38 -0500 Received: from mx1.redhat.com ([209.132.183.28]:36744) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cbDdl-0007XG-2j; Tue, 07 Feb 2017 16:49:33 -0500 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id B2DF781F01; Tue, 7 Feb 2017 21:49:32 +0000 (UTC) Received: from apm-mustang-ev3-30.khw.lab.eng.bos.redhat.com (apm-mustang-ev3-30.khw.lab.eng.bos.redhat.com [10.16.184.124]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id v17LnVCG006452; Tue, 7 Feb 2017 16:49:32 -0500 From: Wei Huang To: qemu-devel@nongnu.org Date: Tue, 7 Feb 2017 16:49:28 -0500 Message-Id: <1486504171-26807-2-git-send-email-wei@redhat.com> In-Reply-To: <1486504171-26807-1-git-send-email-wei@redhat.com> References: <1486504171-26807-1-git-send-email-wei@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.22 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.25]); Tue, 07 Feb 2017 21:49:32 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH V3 1/4] target-arm: Add support for PMU register PMSELR_EL0 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch adds support for AArch64 register PMSELR_EL0. The existing PMSELR definition is revised accordingly. Signed-off-by: Wei Huang Reviewed-by: Peter Maydell --- target/arm/cpu.h | 1 + target/arm/helper.c | 25 ++++++++++++++++++++----- 2 files changed, 21 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 39bff86..8a82c73 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -309,6 +309,7 @@ typedef struct CPUARMState { uint32_t c9_pmovsr; /* perf monitor overflow status */ uint32_t c9_pmxevtyper; /* perf monitor event type */ uint32_t c9_pmuserenr; /* perf monitor user enable */ + uint64_t c9_pmselr; /* perf monitor counter selection register */ uint32_t c9_pminten; /* perf monitor interrupt enables */ union { /* Memory attribute redirection */ struct { diff --git a/target/arm/helper.c b/target/arm/helper.c index c23df1b..67520ea 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -975,6 +975,17 @@ static uint64_t pmccntr_read(CPUARMState *env, const A= RMCPRegInfo *ri) return total_ticks - env->cp15.c15_ccnt; } =20 +static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and + * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the + * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are + * accessed. + */ + env->cp15.c9_pmselr =3D value & 0x1f; +} + static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -1194,12 +1205,16 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { /* Unimplemented so WI. */ { .name =3D "PMSWINC", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D = 0, .opc2 =3D 4, .access =3D PL0_W, .accessfn =3D pmreg_access, .type =3D ARM_CP_NOP = }, - /* Since we don't implement any events, writing to PMSELR is UNPREDICT= ABLE. - * We choose to RAZ/WI. - */ { .name =3D "PMSELR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 5, - .access =3D PL0_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0, - .accessfn =3D pmreg_access }, + .access =3D PL0_RW, .type =3D ARM_CP_ALIAS, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmselr), + .accessfn =3D pmreg_access, .writefn =3D pmselr_write, + .raw_writefn =3D raw_write}, + { .name =3D "PMSELR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 5, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmselr), + .writefn =3D pmselr_write, .raw_writefn =3D raw_write, }, #ifndef CONFIG_USER_ONLY { .name =3D "PMCCNTR", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 =3D = 0, .opc2 =3D 0, .access =3D PL0_RW, .resetvalue =3D 0, .type =3D ARM_CP_IO, --=20 1.8.3.1