From nobody Sat Apr 27 18:22:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1486144278119924.2941612512619; Fri, 3 Feb 2017 09:51:18 -0800 (PST) Received: from localhost ([::1]:36157 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cZi0y-0007Mb-3Q for importer@patchew.org; Fri, 03 Feb 2017 12:51:16 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42185) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cZhyq-0006Hu-H0 for qemu-devel@nongnu.org; Fri, 03 Feb 2017 12:49:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cZhyp-0003jQ-Fa for qemu-devel@nongnu.org; Fri, 03 Feb 2017 12:49:04 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:48384) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cZhyn-0003iE-8Z; Fri, 03 Feb 2017 12:49:01 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1cZhyj-0002fV-1C; Fri, 03 Feb 2017 17:48:57 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Fri, 3 Feb 2017 17:48:54 +0000 Message-Id: <1486144135-4894-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1486144135-4894-1-git-send-email-peter.maydell@linaro.org> References: <1486144135-4894-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH v2 1/2] target/arm: Abstract out pbit/wbit tests in ARM ldr/str decode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E. Iglesias" , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In the ARM ldr/str decode path, rather than directly testing "insn & (1 << 21)" and "insn & (1 << 24)", abstract these bits out into wbit and pbit local flags. (We will want to do more tests against them to determine whether we need to provide syndrome information.) Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias --- target/arm/translate.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 493c627..175b4c1 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8782,6 +8782,8 @@ static void disas_arm_insn(DisasContext *s, unsigned = int insn) } else { int address_offset; bool load =3D insn & (1 << 20); + bool wbit =3D insn & (1 << 21); + bool pbit =3D insn & (1 << 24); bool doubleword =3D false; /* Misc load/store */ rn =3D (insn >> 16) & 0xf; @@ -8799,8 +8801,9 @@ static void disas_arm_insn(DisasContext *s, unsigned = int insn) } =20 addr =3D load_reg(s, rn); - if (insn & (1 << 24)) + if (pbit) { gen_add_datah_offset(s, insn, 0, addr); + } address_offset =3D 0; =20 if (doubleword) { @@ -8849,10 +8852,10 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) ensure correct behavior with overlapping index register= s. ldrd with base writeback is undefined if the destination and index registers overlap. */ - if (!(insn & (1 << 24))) { + if (!pbit) { gen_add_datah_offset(s, insn, address_offset, addr); store_reg(s, rn, addr); - } else if (insn & (1 << 21)) { + } else if (wbit) { if (address_offset) tcg_gen_addi_i32(addr, addr, address_offset); store_reg(s, rn, addr); --=20 2.7.4 From nobody Sat Apr 27 18:22:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1486144277468727.1418988979626; Fri, 3 Feb 2017 09:51:17 -0800 (PST) Received: from localhost ([::1]:36156 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cZi0x-0007LY-Hn for importer@patchew.org; Fri, 03 Feb 2017 12:51:15 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42213) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cZhyv-0006KB-Lm for qemu-devel@nongnu.org; Fri, 03 Feb 2017 12:49:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cZhys-0003kL-VC for qemu-devel@nongnu.org; Fri, 03 Feb 2017 12:49:09 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:48384) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cZhyo-0003iE-2s; Fri, 03 Feb 2017 12:49:02 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1cZhyj-0002fg-GU; Fri, 03 Feb 2017 17:48:57 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Fri, 3 Feb 2017 17:48:55 +0000 Message-Id: <1486144135-4894-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1486144135-4894-1-git-send-email-peter.maydell@linaro.org> References: <1486144135-4894-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH v2 2/2] target/arm: A32, T32: Create Instruction Syndromes for Data Aborts X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E. Iglesias" , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for generating the ISS (Instruction Specific Syndrome) for Data Abort exceptions taken from AArch32. These syndromes are used by hypervisors for example to trap and emulate memory accesses. This is the equivalent for AArch32 guests of the work done for AArch64 guests in commit aaa1f954d4cab243. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias --- target/arm/translate.c | 198 +++++++++++++++++++++++++++++++++++++--------= ---- 1 file changed, 149 insertions(+), 49 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 175b4c1..fc0ddcd 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -102,6 +102,63 @@ void arm_translate_init(void) a64_translate_init(); } =20 +static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn) +{ + /* We don't need to save all of the syndrome so we mask and shift + * out uneeded bits to help the sleb128 encoder do a better job. + */ + syn &=3D ARM_INSN_START_WORD2_MASK; + syn >>=3D ARM_INSN_START_WORD2_SHIFT; + + /* We check and clear insn_start_idx to catch multiple updates. */ + assert(s->insn_start_idx !=3D 0); + tcg_set_insn_param(s->insn_start_idx, 2, syn); + s->insn_start_idx =3D 0; +} + +/* Flags for the disas_set_da_iss info argument: + * lower bits hold the Rt register number, higher bits are flags. + */ +typedef enum ISSInfo { + ISSNone =3D 0, + ISSRegMask =3D 0x1f, + ISSInvalid =3D (1 << 5), + ISSIsAcqRel =3D (1 << 6), + ISSIsWrite =3D (1 << 7), + ISSIs16Bit =3D (1 << 8), +} ISSInfo; + +/* Save the syndrome information for a Data Abort */ +static void disas_set_da_iss(DisasContext *s, TCGMemOp memop, ISSInfo issi= nfo) +{ + uint32_t syn; + int sas =3D memop & MO_SIZE; + bool sse =3D memop & MO_SIGN; + bool is_acqrel =3D issinfo & ISSIsAcqRel; + bool is_write =3D issinfo & ISSIsWrite; + bool is_16bit =3D issinfo & ISSIs16Bit; + int srt =3D issinfo & ISSRegMask; + + if (issinfo & ISSInvalid) { + /* Some callsites want to conditionally provide ISS info, + * eg "only if this was not a writeback" + */ + return; + } + + if (srt =3D=3D 15) { + /* For AArch32, insns where the src/dest is R15 never generate + * ISS information. Catching that here saves checking at all + * the call sites. + */ + return; + } + + syn =3D syn_data_abort_with_iss(0, sas, sse, srt, 0, is_acqrel, + 0, 0, 0, is_write, 0, is_16bit); + disas_set_insn_syndrome(s, syn); +} + static inline ARMMMUIdx get_a32_user_mem_index(DisasContext *s) { /* Return the mmu_idx to use for A32/T32 "unprivileged load/store" @@ -933,6 +990,14 @@ static inline void gen_aa32_ld##SUFF(DisasContext *s, = TCGv_i32 val, \ TCGv_i32 a32, int index) \ { \ gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data); \ +} \ +static inline void gen_aa32_ld##SUFF##_iss(DisasContext *s, \ + TCGv_i32 val, \ + TCGv_i32 a32, int index, \ + ISSInfo issinfo) \ +{ \ + gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data); \ + disas_set_da_iss(s, OPC, issinfo); \ } =20 #define DO_GEN_ST(SUFF, OPC) \ @@ -940,6 +1005,14 @@ static inline void gen_aa32_st##SUFF(DisasContext *s,= TCGv_i32 val, \ TCGv_i32 a32, int index) \ { \ gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data); \ +} \ +static inline void gen_aa32_st##SUFF##_iss(DisasContext *s, \ + TCGv_i32 val, \ + TCGv_i32 a32, int index, \ + ISSInfo issinfo) \ +{ \ + gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data); \ + disas_set_da_iss(s, OPC, issinfo | ISSIsWrite); \ } =20 static inline void gen_aa32_frob64(DisasContext *s, TCGv_i64 val) @@ -8682,16 +8755,19 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) tmp =3D tcg_temp_new_i32(); switch (op1) { case 0: /* lda */ - gen_aa32_ld32u(s, tmp, addr, - get_mem_index(s)); + gen_aa32_ld32u_iss(s, tmp, addr, + get_mem_index(s), + rd | ISSIsAcqRel); break; case 2: /* ldab */ - gen_aa32_ld8u(s, tmp, addr, - get_mem_index(s)); + gen_aa32_ld8u_iss(s, tmp, addr, + get_mem_index(s), + rd | ISSIsAcqRel); break; case 3: /* ldah */ - gen_aa32_ld16u(s, tmp, addr, - get_mem_index(s)); + gen_aa32_ld16u_iss(s, tmp, addr, + get_mem_index(s), + rd | ISSIsAcqRel); break; default: abort(); @@ -8702,16 +8778,19 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) tmp =3D load_reg(s, rm); switch (op1) { case 0: /* stl */ - gen_aa32_st32(s, tmp, addr, - get_mem_index(s)); + gen_aa32_st32_iss(s, tmp, addr, + get_mem_index(s), + rm | ISSIsAcqRel); break; case 2: /* stlb */ - gen_aa32_st8(s, tmp, addr, - get_mem_index(s)); + gen_aa32_st8_iss(s, tmp, addr, + get_mem_index(s), + rm | ISSIsAcqRel); break; case 3: /* stlh */ - gen_aa32_st16(s, tmp, addr, - get_mem_index(s)); + gen_aa32_st16_iss(s, tmp, addr, + get_mem_index(s), + rm | ISSIsAcqRel); break; default: abort(); @@ -8785,10 +8864,15 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) bool wbit =3D insn & (1 << 21); bool pbit =3D insn & (1 << 24); bool doubleword =3D false; + ISSInfo issinfo; + /* Misc load/store */ rn =3D (insn >> 16) & 0xf; rd =3D (insn >> 12) & 0xf; =20 + /* ISS not valid if writeback */ + issinfo =3D (pbit & !wbit) ? rd : ISSInvalid; + if (!load && (sh & 2)) { /* doubleword */ ARCH(5TE); @@ -8832,20 +8916,23 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) tmp =3D tcg_temp_new_i32(); switch (sh) { case 1: - gen_aa32_ld16u(s, tmp, addr, get_mem_index(s)); + gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), + issinfo); break; case 2: - gen_aa32_ld8s(s, tmp, addr, get_mem_index(s)); + gen_aa32_ld8s_iss(s, tmp, addr, get_mem_index(s), + issinfo); break; default: case 3: - gen_aa32_ld16s(s, tmp, addr, get_mem_index(s)); + gen_aa32_ld16s_iss(s, tmp, addr, get_mem_index(s), + issinfo); break; } } else { /* store */ tmp =3D load_reg(s, rd); - gen_aa32_st16(s, tmp, addr, get_mem_index(s)); + gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), issi= nfo); tcg_temp_free_i32(tmp); } /* Perform base writeback before the loaded value to @@ -9198,17 +9285,17 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) /* load */ tmp =3D tcg_temp_new_i32(); if (insn & (1 << 22)) { - gen_aa32_ld8u(s, tmp, tmp2, i); + gen_aa32_ld8u_iss(s, tmp, tmp2, i, rd); } else { - gen_aa32_ld32u(s, tmp, tmp2, i); + gen_aa32_ld32u_iss(s, tmp, tmp2, i, rd); } } else { /* store */ tmp =3D load_reg(s, rd); if (insn & (1 << 22)) { - gen_aa32_st8(s, tmp, tmp2, i); + gen_aa32_st8_iss(s, tmp, tmp2, i, rd); } else { - gen_aa32_st32(s, tmp, tmp2, i); + gen_aa32_st32_iss(s, tmp, tmp2, i, rd); } tcg_temp_free_i32(tmp); } @@ -9669,13 +9756,16 @@ static int disas_thumb2_insn(CPUARMState *env, Disa= sContext *s, uint16_t insn_hw tmp =3D tcg_temp_new_i32(); switch (op) { case 0: /* ldab */ - gen_aa32_ld8u(s, tmp, addr, get_mem_index(s)); + gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(= s), + rs | ISSIsAcqRel); break; case 1: /* ldah */ - gen_aa32_ld16u(s, tmp, addr, get_mem_index(s)); + gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index= (s), + rs | ISSIsAcqRel); break; case 2: /* lda */ - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); + gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index= (s), + rs | ISSIsAcqRel); break; default: abort(); @@ -9685,13 +9775,16 @@ static int disas_thumb2_insn(CPUARMState *env, Disa= sContext *s, uint16_t insn_hw tmp =3D load_reg(s, rs); switch (op) { case 0: /* stlb */ - gen_aa32_st8(s, tmp, addr, get_mem_index(s)); + gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s= ), + rs | ISSIsAcqRel); break; case 1: /* stlh */ - gen_aa32_st16(s, tmp, addr, get_mem_index(s)); + gen_aa32_st16_iss(s, tmp, addr, get_mem_index(= s), + rs | ISSIsAcqRel); break; case 2: /* stl */ - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); + gen_aa32_st32_iss(s, tmp, addr, get_mem_index(= s), + rs | ISSIsAcqRel); break; default: abort(); @@ -10637,6 +10730,8 @@ static int disas_thumb2_insn(CPUARMState *env, Disa= sContext *s, uint16_t insn_hw int postinc =3D 0; int writeback =3D 0; int memidx; + ISSInfo issinfo; + if ((insn & 0x01100000) =3D=3D 0x01000000) { if (disas_neon_ls_insn(s, insn)) { goto illegal_op; @@ -10740,24 +10835,27 @@ static int disas_thumb2_insn(CPUARMState *env, Di= sasContext *s, uint16_t insn_hw } } } + + issinfo =3D writeback ? ISSInvalid : rs; + if (insn & (1 << 20)) { /* Load. */ tmp =3D tcg_temp_new_i32(); switch (op) { case 0: - gen_aa32_ld8u(s, tmp, addr, memidx); + gen_aa32_ld8u_iss(s, tmp, addr, memidx, issinfo); break; case 4: - gen_aa32_ld8s(s, tmp, addr, memidx); + gen_aa32_ld8s_iss(s, tmp, addr, memidx, issinfo); break; case 1: - gen_aa32_ld16u(s, tmp, addr, memidx); + gen_aa32_ld16u_iss(s, tmp, addr, memidx, issinfo); break; case 5: - gen_aa32_ld16s(s, tmp, addr, memidx); + gen_aa32_ld16s_iss(s, tmp, addr, memidx, issinfo); break; case 2: - gen_aa32_ld32u(s, tmp, addr, memidx); + gen_aa32_ld32u_iss(s, tmp, addr, memidx, issinfo); break; default: tcg_temp_free_i32(tmp); @@ -10774,13 +10872,13 @@ static int disas_thumb2_insn(CPUARMState *env, Di= sasContext *s, uint16_t insn_hw tmp =3D load_reg(s, rs); switch (op) { case 0: - gen_aa32_st8(s, tmp, addr, memidx); + gen_aa32_st8_iss(s, tmp, addr, memidx, issinfo); break; case 1: - gen_aa32_st16(s, tmp, addr, memidx); + gen_aa32_st16_iss(s, tmp, addr, memidx, issinfo); break; case 2: - gen_aa32_st32(s, tmp, addr, memidx); + gen_aa32_st32_iss(s, tmp, addr, memidx, issinfo); break; default: tcg_temp_free_i32(tmp); @@ -10917,7 +11015,8 @@ static void disas_thumb_insn(CPUARMState *env, Disa= sContext *s) addr =3D tcg_temp_new_i32(); tcg_gen_movi_i32(addr, val); tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); + gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), + rd | ISSIs16Bit); tcg_temp_free_i32(addr); store_reg(s, rd, tmp); break; @@ -11120,28 +11219,28 @@ static void disas_thumb_insn(CPUARMState *env, Di= sasContext *s) =20 switch (op) { case 0: /* str */ - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); + gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16= Bit); break; case 1: /* strh */ - gen_aa32_st16(s, tmp, addr, get_mem_index(s)); + gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16= Bit); break; case 2: /* strb */ - gen_aa32_st8(s, tmp, addr, get_mem_index(s)); + gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16B= it); break; case 3: /* ldrsb */ - gen_aa32_ld8s(s, tmp, addr, get_mem_index(s)); + gen_aa32_ld8s_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16= Bit); break; case 4: /* ldr */ - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); + gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs1= 6Bit); break; case 5: /* ldrh */ - gen_aa32_ld16u(s, tmp, addr, get_mem_index(s)); + gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs1= 6Bit); break; case 6: /* ldrb */ - gen_aa32_ld8u(s, tmp, addr, get_mem_index(s)); + gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16= Bit); break; case 7: /* ldrsh */ - gen_aa32_ld16s(s, tmp, addr, get_mem_index(s)); + gen_aa32_ld16s_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs1= 6Bit); break; } if (op >=3D 3) { /* load */ @@ -11185,12 +11284,12 @@ static void disas_thumb_insn(CPUARMState *env, Di= sasContext *s) if (insn & (1 << 11)) { /* load */ tmp =3D tcg_temp_new_i32(); - gen_aa32_ld8u(s, tmp, addr, get_mem_index(s)); + gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16= Bit); store_reg(s, rd, tmp); } else { /* store */ tmp =3D load_reg(s, rd); - gen_aa32_st8(s, tmp, addr, get_mem_index(s)); + gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16B= it); tcg_temp_free_i32(tmp); } tcg_temp_free_i32(addr); @@ -11207,12 +11306,12 @@ static void disas_thumb_insn(CPUARMState *env, Di= sasContext *s) if (insn & (1 << 11)) { /* load */ tmp =3D tcg_temp_new_i32(); - gen_aa32_ld16u(s, tmp, addr, get_mem_index(s)); + gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs1= 6Bit); store_reg(s, rd, tmp); } else { /* store */ tmp =3D load_reg(s, rd); - gen_aa32_st16(s, tmp, addr, get_mem_index(s)); + gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16= Bit); tcg_temp_free_i32(tmp); } tcg_temp_free_i32(addr); @@ -11228,12 +11327,12 @@ static void disas_thumb_insn(CPUARMState *env, Di= sasContext *s) if (insn & (1 << 11)) { /* load */ tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); + gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs1= 6Bit); store_reg(s, rd, tmp); } else { /* store */ tmp =3D load_reg(s, rd); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); + gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16= Bit); tcg_temp_free_i32(tmp); } tcg_temp_free_i32(addr); @@ -11715,6 +11814,7 @@ void gen_intermediate_code(CPUARMState *env, Transl= ationBlock *tb) store_cpu_field(tmp, condexec_bits); } do { + dc->insn_start_idx =3D tcg_op_buf_count(); tcg_gen_insn_start(dc->pc, (dc->condexec_cond << 4) | (dc->condexec_mask >= > 1), 0); --=20 2.7.4