From nobody Tue Feb 10 04:55:11 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1486142033454351.12376328445384; Fri, 3 Feb 2017 09:13:53 -0800 (PST) Received: from localhost ([::1]:35969 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cZhQk-0001Kg-Cm for importer@patchew.org; Fri, 03 Feb 2017 12:13:50 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60802) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cZhKb-0004jh-77 for qemu-devel@nongnu.org; Fri, 03 Feb 2017 12:07:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cZhKX-0002gy-7h for qemu-devel@nongnu.org; Fri, 03 Feb 2017 12:07:29 -0500 Received: from greensocs.com ([193.104.36.180]:39115) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cZhKW-0002go-T5 for qemu-devel@nongnu.org; Fri, 03 Feb 2017 12:07:25 -0500 Received: from localhost (localhost [127.0.0.1]) by greensocs.com (Postfix) with ESMTP id 3B459164DB9; Fri, 3 Feb 2017 18:07:24 +0100 (CET) Received: from greensocs.com ([127.0.0.1]) by localhost (gs-01.greensocs.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id RR2Ch-4JxcxF; Fri, 3 Feb 2017 18:07:23 +0100 (CET) Received: by greensocs.com (Postfix, from userid 998) id 28A4C2E8DF9; Fri, 3 Feb 2017 18:07:23 +0100 (CET) Received: from corsair.home (bd231-7-88-127-3-24.fbx.proxad.net [88.127.3.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: fred.konrad@greensocs.com) by greensocs.com (Postfix) with ESMTPSA id 5F5F3164DB9; Fri, 3 Feb 2017 18:07:22 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1486141644; bh=WWL0abNXIJMY+OeqbXzF5PHT2OOBAypIao+1S4u5zn0=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=iXog1Q/0jrXoJWtjkGbJBJLL+im1VC7VwS49Ws+uMIju68VMyU3DN1zPeP5KOip0N 6A/x5yFC/OiEL4dz2Fdh1QP7BSo/3TZhwjIdiG5ugOabM/nLfw30vBrNPJ8i3dEZN6 sI+WUughVn81/PGQK390X6ZKDjhcDQYE4CVYdSW8= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com header.b=NNS0TZWr; dkim=pass (1024-bit key) header.d=greensocs.com header.b=yHKK+8OU DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1486141643; bh=WWL0abNXIJMY+OeqbXzF5PHT2OOBAypIao+1S4u5zn0=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=NNS0TZWrn9kZBx0p4z84pREOOE+iAJIL5K4rdgRVrRwHlNQ5pQFFQq/IJqrxs4Q0e RYILp2TqH7QDvfW7WFGi3pdbAnLEfepZU/Y9u3/j3mMKSiezhj/SpKqJ0ZtiVq0r8+ 2UZz+/ZYzR1LwsDq0d9vvRNRN8eoc8Eiy1n6IJ+U= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1486141642; bh=WWL0abNXIJMY+OeqbXzF5PHT2OOBAypIao+1S4u5zn0=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=yHKK+8OU56OaTS8imx59OCV8l3NdELldbLhoyLm/LxsIrmkhqNederqnM279HCT3N DfgI8DP2E0n+Z3ZbTOA3SZMMUzu/FU9Nbqwnfqvv4SKvUZerTKZ3/fxv9N014+0u++ 1FJtK0QIHIGKpRd3r6ttxNHhHzCv0e4MekwI0zN8= From: fred.konrad@greensocs.com To: qemu-devel@nongnu.org Date: Fri, 3 Feb 2017 18:06:37 +0100 Message-Id: <1486141597-13941-6-git-send-email-fred.konrad@greensocs.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1486141597-13941-1-git-send-email-fred.konrad@greensocs.com> References: <1486141597-13941-1-git-send-email-fred.konrad@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [RFC 5/5] xilinx_spips: allow mmio execution X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, mark.burton@greensocs.com, alistair.francis@xilinx.com, clg@kaod.org, pbonzini@redhat.com, fred.konrad@greensocs.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: KONRAD Frederic This allows to execute from the lqspi area. When the request_ptr is called the device loads 1024bytes from the SPI devi= ce. Then this code can be executed by the guest. Signed-off-by: KONRAD Frederic --- hw/ssi/xilinx_spips.c | 74 ++++++++++++++++++++++++++++++++++++++---------= ---- 1 file changed, 55 insertions(+), 19 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index da8adfa..e833028 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -496,6 +496,18 @@ static const MemoryRegionOps spips_ops =3D { .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 +static void xilinx_qspips_invalidate_mmio_ptr(XilinxQSPIPS *q) +{ + XilinxSPIPS *s =3D &q->parent_obj; + + if (q->lqspi_cached_addr !=3D ~0ULL) { + /* Invalidate the current mapped mmio */ + memory_region_invalidate_mmio_ptr(&s->mmlqspi, q->lqspi_cached_add= r, + LQSPI_CACHE_SIZE); + q->lqspi_cached_addr =3D ~0ULL; + } +} + static void xilinx_qspips_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { @@ -505,7 +517,7 @@ static void xilinx_qspips_write(void *opaque, hwaddr ad= dr, addr >>=3D 2; =20 if (addr =3D=3D R_LQSPI_CFG) { - q->lqspi_cached_addr =3D ~0ULL; + xilinx_qspips_invalidate_mmio_ptr(q); } } =20 @@ -517,27 +529,20 @@ static const MemoryRegionOps qspips_ops =3D { =20 #define LQSPI_CACHE_SIZE 1024 =20 -static uint64_t -lqspi_read(void *opaque, hwaddr addr, unsigned int size) +static void lqspi_load_cache(void *opaque, hwaddr addr) { - int i; XilinxQSPIPS *q =3D opaque; XilinxSPIPS *s =3D opaque; - uint32_t ret; - - if (addr >=3D q->lqspi_cached_addr && - addr <=3D q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { - uint8_t *retp =3D &q->lqspi_buf[addr - q->lqspi_cached_addr]; - ret =3D cpu_to_le32(*(uint32_t *)retp); - DB_PRINT_L(1, "addr: %08x, data: %08x\n", (unsigned)addr, - (unsigned)ret); - return ret; - } else { - int flash_addr =3D (addr / num_effective_busses(s)); - int slave =3D flash_addr >> LQSPI_ADDRESS_BITS; - int cache_entry =3D 0; - uint32_t u_page_save =3D s->regs[R_LQSPI_STS] & ~LQSPI_CFG_U_PAGE; - + int i; + int flash_addr =3D ((addr & ~(LQSPI_CACHE_SIZE - 1)) + / num_effective_busses(s)); + int slave =3D flash_addr >> LQSPI_ADDRESS_BITS; + int cache_entry =3D 0; + uint32_t u_page_save =3D s->regs[R_LQSPI_STS] & ~LQSPI_CFG_U_PAGE; + + if (addr < q->lqspi_cached_addr || + addr > q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { + xilinx_qspips_invalidate_mmio_ptr(q); s->regs[R_LQSPI_STS] &=3D ~LQSPI_CFG_U_PAGE; s->regs[R_LQSPI_STS] |=3D slave ? LQSPI_CFG_U_PAGE : 0; =20 @@ -589,12 +594,43 @@ lqspi_read(void *opaque, hwaddr addr, unsigned int si= ze) xilinx_spips_update_cs_lines(s); =20 q->lqspi_cached_addr =3D flash_addr * num_effective_busses(s); + } +} + +static void *lqspi_request_mmio_ptr(void *opaque, hwaddr addr, unsigned *s= ize, + unsigned *offset) +{ + XilinxQSPIPS *q =3D opaque; + hwaddr offset_within_the_region =3D addr & ~(LQSPI_CACHE_SIZE - 1); + + lqspi_load_cache(opaque, offset_within_the_region); + *size =3D LQSPI_CACHE_SIZE; + *offset =3D offset_within_the_region; + return q->lqspi_buf; +} + +static uint64_t +lqspi_read(void *opaque, hwaddr addr, unsigned int size) +{ + XilinxQSPIPS *q =3D opaque; + uint32_t ret; + + if (addr >=3D q->lqspi_cached_addr && + addr <=3D q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { + uint8_t *retp =3D &q->lqspi_buf[addr - q->lqspi_cached_addr]; + ret =3D cpu_to_le32(*(uint32_t *)retp); + DB_PRINT_L(1, "addr: %08x, data: %08x\n", (unsigned)addr, + (unsigned)ret); + return ret; + } else { + lqspi_load_cache(opaque, addr); return lqspi_read(opaque, addr, size); } } =20 static const MemoryRegionOps lqspi_ops =3D { .read =3D lqspi_read, + .request_ptr =3D lqspi_request_mmio_ptr, .endianness =3D DEVICE_NATIVE_ENDIAN, .valid =3D { .min_access_size =3D 1, --=20 1.8.3.1