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[173.29.146.33]) by smtp.gmail.com with ESMTPSA id n184sm6517218itg.9.2017.11.26.13.59.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 26 Nov 2017 13:59:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=F2nGHHpOBxZXvkCeKld5QOa9LzVghfBK41dhV0Ihz4I=; b=Z1R0tUlJcw74EICZ8TRveJ1Gj4O1JM6DyZ0JNV3UTDuDjjaNbgBhaO33N1TON8YPmu O9yBjvW0KtMQWAY/6H82tsstUmB11BDlLE63bpJ1qC3Zdx5IsKQs11xYOuMX9bDkr6hB S7zCH8p9r5OMv69r9kQ3wb++OnL0uZwJYAUuJl/Wd1rJKgHiz3oNIq/BZDzSQ7tfLn3L DtJ6/ySSWACQjyWI4AdeRKMAbYxn/iPlbtRbjFZyacQF779L9m2octNlFx++6IveyQD4 37h7GNrBvALQJtNURp5vzado+MOk9clwH2E4pGnx03ivBINgJrLsRmd8fyWWYI/u0KO9 Qtmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=F2nGHHpOBxZXvkCeKld5QOa9LzVghfBK41dhV0Ihz4I=; b=L87BS0oL3aYsT4WuRdTzRKUvmYn5ycq6wm8fZRs+Io89d1oR1s1WKvo8lXPdfcXK4M SPryJOPpqgWr3H7GMGHxuzXrRnqxtYNWCBSoi5oLqhQuXLEQJ9eOg/NQkKqVu2vzyp0z YMGHg2pvhCDnfTsscOsJCkWDZV42oJdjOcnqkbyZQqErdO5Pe3iT84UU5NsaM4ExYWd4 yofh0zSuLGjq6bPpW/+kpKf40INNVioZgeFicMbCXMRFLPPo0vUGpZc30kCyRPGxr49w QDPNpnlYXen+3AtZKB6bzUYrgQWLrxaZKV0L8PShncoIzM1oXuvMLr/FEsshAY9FIJlo qEow== X-Gm-Message-State: AJaThX5UzJMRyrYIMJGyHO3R8xqfxC1YUCiiwA5UdGF7KKyeQvpljWWq CWUlitthFhxuuxWmfLENF/kkqQ== X-Google-Smtp-Source: AGs4zMaUJMHob3TSK6uoYRRsYfbtkJECwVs7qfe42fdfy0Lj+6z72wQwOO/PfB/3kayVFggzUcTQ/w== X-Received: by 10.107.34.206 with SMTP id i197mr37915182ioi.134.1511733590389; Sun, 26 Nov 2017 13:59:50 -0800 (PST) From: Michael Davidsaver To: Alexander Graf , David Gibson Date: Sun, 26 Nov 2017 15:59:06 -0600 Message-Id: <11edba0f74534a8013e6264f8a4f0cdf064a9ecd.1511731946.git.mdavidsaver@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c06::244 Subject: [Qemu-devel] [PATCH 08/17] e500: additional CCSR registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Davidsaver , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add CCSRBAR to allow CCSR region to be relocated. Guest memory size introspection via RAM config registers. Dummy RAM error controls. Clock introspection via Power on Reset PLL Status Register. Signed-off-by: Michael Davidsaver ccsrbase also update iack --- hw/ppc/e500.c | 5 ++- hw/ppc/e500_ccsr.c | 93 ++++++++++++++++++++++++++++++++++++++++++++++++++= ++-- 2 files changed, 95 insertions(+), 3 deletions(-) diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index b90f4231a6..e22919f4f1 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -51,7 +51,9 @@ =20 #define RAM_SIZES_ALIGN (64UL << 20) =20 -/* TODO: parameterize */ +/* TODO: parameterize + * Some CCSR offsets duplicated in e500_ccsr.c + */ #define MPC8544_CCSRBAR_SIZE 0x00100000ULL #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL #define MPC8544_MSI_REGS_OFFSET 0x41600ULL @@ -856,6 +858,7 @@ void ppce500_init(MachineState *machine, PPCE500Params = *params) object_property_add_child(qdev_get_machine(), "e500-ccsr", OBJECT(dev), NULL); qdev_prop_set_uint32(dev, "base", params->ccsrbar_base); + qdev_prop_set_uint32(dev, "ram-size", ram_size); qdev_init_nofail(dev); ccsr_addr_space =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); =20 diff --git a/hw/ppc/e500_ccsr.c b/hw/ppc/e500_ccsr.c index 1b586c3f42..9400d7cf13 100644 --- a/hw/ppc/e500_ccsr.c +++ b/hw/ppc/e500_ccsr.c @@ -30,13 +30,26 @@ #include "hw/sysbus.h" =20 /* E500_ denotes registers common to all */ +/* Some CCSR offsets duplicated in e500.c */ =20 +#define E500_CCSRBAR (0) + +#define E500_CS0_BNDS (0x2000) + +#define E500_CS0_CONFIG (0x2080) + +#define E500_ERR_DETECT (0x2e40) +#define E500_ERR_DISABLE (0x2e44) + +#define E500_PORPLLSR (0xE0000) #define E500_PVR (0xE00A0) #define E500_SVR (0xE00A4) =20 #define MPC8544_RSTCR (0xE00B0) #define MPC8544_RSTCR_RESET (0x02) =20 +#define E500_MPIC_OFFSET (0x40000ULL) + typedef struct { /*< private >*/ SysBusDevice parent_obj; @@ -44,19 +57,59 @@ typedef struct { =20 MemoryRegion iomem; =20 - uint32_t defbase; + uint32_t defbase, base; + uint32_t ram_size; + uint32_t merrd; + + uint32_t porpllsr; + + DeviceState *pic; } CCSRState; =20 #define TYPE_E500_CCSR "e500-ccsr" #define E500_CCSR(obj) OBJECT_CHECK(CCSRState, (obj), TYPE_E500_CCSR) =20 +/* call after changing CCSRState::base */ +static void e500_ccsr_post_move(CCSRState *ccsr) +{ + CPUState *cs; + + CPU_FOREACH(cs) { + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + CPUPPCState *env =3D &cpu->env; + + env->mpic_iack =3D ccsr->base + + E500_MPIC_OFFSET + 0xa0; + } + + sysbus_mmio_map(SYS_BUS_DEVICE(ccsr), 0, ccsr->base); +} + static uint64_t e500_ccsr_read(void *opaque, hwaddr addr, unsigned size) { + CCSRState *ccsr =3D opaque; PowerPCCPU *cpu =3D POWERPC_CPU(current_cpu); CPUPPCState *env =3D &cpu->env; =20 switch (addr) { + case E500_CCSRBAR: + return ccsr->base >> 12; + case E500_CS0_BNDS: + /* we model all RAM in a single chip with addresses [0, ram_size) = */ + return (ccsr->ram_size - 1) >> 24; + case E500_CS0_CONFIG: + return 1 << 31; + case E500_ERR_DETECT: + return 0; /* (errors not modeled) */ + case E500_ERR_DISABLE: + return ccsr->merrd; + case E500_PORPLLSR: + if (!ccsr->porpllsr) { + qemu_log_mask(LOG_UNIMP, + "Machine does not provide valid PORPLLSR\n"); + } + return ccsr->porpllsr; case E500_PVR: return env->spr[SPR_PVR]; case E500_SVR: @@ -72,10 +125,22 @@ static uint64_t e500_ccsr_read(void *opaque, hwaddr ad= dr, static void e500_ccsr_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { + CCSRState *ccsr =3D opaque; PowerPCCPU *cpu =3D POWERPC_CPU(current_cpu); CPUPPCState *env =3D &cpu->env; uint32_t svr =3D env->spr[SPR_E500_SVR] >> 16; =20 + switch (addr) { + case E500_CCSRBAR: + value &=3D 0x000fff00; + ccsr->base =3D value << 12; + e500_ccsr_post_move(ccsr); + return; + case E500_ERR_DISABLE: + ccsr->merrd =3D value & 0xd; + return; + } + switch (svr) { case 0: /* generic. assumed to be mpc8544ds or e500plat board */ case 0x8034: /* mpc8544 */ @@ -104,11 +169,20 @@ static const MemoryRegionOps e500_ccsr_ops =3D { } }; =20 +static int e500_ccsr_post_load(void *opaque, int version_id) +{ + CCSRState *ccsr =3D opaque; + + e500_ccsr_post_move(ccsr); + return 0; +} + static void e500_ccsr_reset(DeviceState *dev) { CCSRState *ccsr =3D E500_CCSR(dev); =20 - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ccsr->defbase); + ccsr->base =3D ccsr->defbase; + e500_ccsr_post_move(ccsr); } =20 static void e500_ccsr_initfn(Object *obj) @@ -123,15 +197,30 @@ static void e500_ccsr_initfn(Object *obj) =20 static Property e500_ccsr_props[] =3D { DEFINE_PROP_UINT32("base", CCSRState, defbase, 0xff700000), + DEFINE_PROP_UINT32("ram-size", CCSRState, ram_size, 0), + DEFINE_PROP_UINT32("porpllsr", CCSRState, porpllsr, 0), DEFINE_PROP_END_OF_LIST() }; =20 +static const VMStateDescription vmstate_e500_ccsr =3D { + .name =3D TYPE_E500_CCSR, + .version_id =3D 1, + .minimum_version_id =3D 1, + .post_load =3D e500_ccsr_post_load, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(base, CCSRState), + VMSTATE_UINT32(merrd, CCSRState), + VMSTATE_END_OF_LIST() + } +}; + static void e500_ccsr_class_initfn(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->props =3D e500_ccsr_props; + dc->vmsd =3D &vmstate_e500_ccsr; dc->reset =3D e500_ccsr_reset; } =20 --=20 2.11.0