From nobody Sun May 19 03:54:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=bt.com ARC-Seal: i=1; a=rsa-sha256; t=1563429785; cv=none; d=zoho.com; s=zohoarc; b=mj/TzSsJPN2qINTHpvOlH2yb/bgNN9/KsLIqFkj5r8vo6yXj7jH5TtWbmVSagI2KOUtknuOOspQ/FJ5CWjJy3VWqAvnpEhf+vCLt7gukZUYUbSOguGQbQ/9DKFtRVxvW8SwrNIXD2PAJu24/AcK4mLSxuDC1tSpT0cRdnubtR0I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1563429785; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:To:ARC-Authentication-Results; bh=K1U/MGr5HMCXY2gHSqhicGcQ2sqVaHYLqPexRdauQ8o=; b=Dudj67KMhaO2VRnAsPm4W+U30e2le3OWXE61gIxvuN306P9Dpe0yXIk3hQ60jvaqqoMxj8p21npdlRxE/txTJ577fPvc9mR7/hFw/ChzCtvUeJVRXTigwx8j/KfDZ2PMm2UHPJPVgCe62QAKb6/XcYaNaX3ZMmeJI+3zUFkbHYY= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1563429785802435.9600642007599; Wed, 17 Jul 2019 23:03:05 -0700 (PDT) Received: from localhost ([::1]:34506 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hnzVQ-00071t-Mr for importer@patchew.org; Thu, 18 Jul 2019 02:03:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42096) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hnzU9-0002M6-AL for qemu-devel@nongnu.org; Thu, 18 Jul 2019 02:01:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hnzU3-0004uy-Mp for qemu-devel@nongnu.org; Thu, 18 Jul 2019 02:01:43 -0400 Received: from smtpe1.intersmtp.com ([213.121.35.80]:26234) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hnzU1-0004s9-48 for qemu-devel@nongnu.org; Thu, 18 Jul 2019 02:01:39 -0400 Received: from tpw09926dag18e.domain1.systemhost.net (10.9.212.18) by BWP09926085.bt.com (10.36.82.116) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.1713.5; Thu, 18 Jul 2019 07:01:41 +0100 Received: from tpw09926dag18e.domain1.systemhost.net (10.9.212.18) by tpw09926dag18e.domain1.systemhost.net (10.9.212.18) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 18 Jul 2019 07:01:31 +0100 Received: from tpw09926dag18e.domain1.systemhost.net ([fe80::a946:6348:ccf4:fa6c]) by tpw09926dag18e.domain1.systemhost.net ([fe80::a946:6348:ccf4:fa6c%12]) with mapi id 15.00.1395.000; Thu, 18 Jul 2019 07:01:31 +0100 From: To: Thread-Topic: [Qemu-devel] [PATCH] configure: Define target access alignment in configure Thread-Index: AQHVPS4/W4amfRivg0WZqWA+8xdBLw== Date: Thu, 18 Jul 2019 06:01:31 +0000 Message-ID: <11e818d38ebc40e986cfa62dd7d0afdc@tpw09926dag18e.domain1.systemhost.net> Accept-Language: en-AU, en-GB, en-US Content-Language: en-AU X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.187.101.36] Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 213.121.35.80 Subject: [Qemu-devel] [PATCH] configure: Define target access alignment in configure X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, rth@twiddle.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" This patch moves the define of target access alignment earlier from target/foo/cpu.h to configure. Suggested in Richard Henderson's reply to "[PATCH 1/4] tcg: TCGMemOp is now accelerator independent MemOp" Signed-off-by: Tony Nguyen Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- configure | 12 ++++++++++-- include/exec/poison.h | 1 + include/qom/cpu.h | 2 +- target/alpha/cpu.h | 2 -- target/hppa/cpu.h | 1 - target/mips/cpu.h | 2 -- target/sh4/cpu.h | 2 -- target/sparc/cpu.h | 2 -- target/xtensa/cpu.h | 2 -- tcg/tcg.c | 2 +- tcg/tcg.h | 8 +++++--- 11 files changed, 18 insertions(+), 18 deletions(-) diff --git a/configure b/configure index eb635c3b9a..c07687c656 100755 --- a/configure +++ b/configure @@ -7424,11 +7424,16 @@ for target in $target_list; do target_dir=3D"$target" config_target_mak=3D$target_dir/config-target.mak target_name=3D$(echo $target | cut -d '-' -f 1) +target_aligned_only=3D"no" +case "$target_name" in + alpha|hppa|mips64el|mips64|mipsel|mips|mipsn32|mipsn32el|sh4|sh4eb|sparc= |sparc64|sparc32plus|xtensa|xtensaeb) + target_aligned_only=3D"yes" + ;; +esac target_bigendian=3D"no" - case "$target_name" in armeb|aarch64_be|hppa|lm32|m68k|microblaze|mips|mipsn32|mips64|moxie|or1= k|ppc|ppc64|ppc64abi32|s390x|sh4eb|sparc|sparc64|sparc32plus|xtensaeb) - target_bigendian=3Dyes + target_bigendian=3D"yes" ;; esac target_softmmu=3D"no" @@ -7710,6 +7715,9 @@ fi if supported_whpx_target $target; then echo "CONFIG_WHPX=3Dy" >> $config_target_mak fi +if test "$target_aligned_only" =3D "yes" ; then + echo "TARGET_ALIGNED_ONLY=3Dy" >> $config_target_mak +fi if test "$target_bigendian" =3D "yes" ; then echo "TARGET_WORDS_BIGENDIAN=3Dy" >> $config_target_mak fi diff --git a/include/exec/poison.h b/include/exec/poison.h index b862320fa6..955eb863ab 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -35,6 +35,7 @@ #pragma GCC poison TARGET_UNICORE32 #pragma GCC poison TARGET_XTENSA =20 +#pragma GCC poison TARGET_ALIGNED_ONLY #pragma GCC poison TARGET_HAS_BFLT #pragma GCC poison TARGET_NAME #pragma GCC poison TARGET_SUPPORTS_MTTCG diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 5ee0046b62..9b50b73339 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -89,7 +89,7 @@ struct TranslationBlock; * @do_unassigned_access: Callback for unassigned access handling. * (this is deprecated: new targets should use do_transaction_failed inste= ad) * @do_unaligned_access: Callback for unaligned access handling, if - * the target defines #ALIGNED_ONLY. + * the target defines #TARGET_ALIGNED_ONLY. * @do_transaction_failed: Callback for handling failed memory transactions * (ie bus faults or external aborts; not MMU faults) * @virtio_is_big_endian: Callback to return %true if a CPU which supports diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index b3e8a823e1..16eb8047cf 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -23,8 +23,6 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" =20 -#define ALIGNED_ONLY - /* Alpha processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) =20 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index aab251bc4b..2be67c289a 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -30,7 +30,6 @@ basis. It's probably easier to fall back to a strong memory model. */ #define TCG_GUEST_DEFAULT_MO TCG_MO_ALL =20 -#define ALIGNED_ONLY #define MMU_KERNEL_IDX 0 #define MMU_USER_IDX 3 #define MMU_PHYS_IDX 4 diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 21c0615e02..c13cd4eb31 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1,8 +1,6 @@ #ifndef MIPS_CPU_H #define MIPS_CPU_H =20 -#define ALIGNED_ONLY - #include "cpu-qom.h" #include "exec/cpu-defs.h" #include "fpu/softfloat.h" diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index aee733eaaa..ecaa7a18a9 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -23,8 +23,6 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" =20 -#define ALIGNED_ONLY - /* CPU Subtypes */ #define SH_CPU_SH7750 (1 << 0) #define SH_CPU_SH7750S (1 << 1) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 8ed2250cd0..1406f0ba2e 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -5,8 +5,6 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" =20 -#define ALIGNED_ONLY - #if !defined(TARGET_SPARC64) #define TARGET_DPREGS 16 #else diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 2c277134f1..0459243e6b 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -32,8 +32,6 @@ #include "exec/cpu-defs.h" #include "xtensa-isa.h" =20 -#define ALIGNED_ONLY - /* Xtensa processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) =20 diff --git a/tcg/tcg.c b/tcg/tcg.c index be2c33c400..8d23fb0592 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1926,7 +1926,7 @@ static const char * const ldst_name[] =3D }; =20 static const char * const alignment_name[(MO_AMASK >> MO_ASHIFT) + 1] =3D { -#ifdef ALIGNED_ONLY +#ifdef TARGET_ALIGNED_ONLY [MO_UNALN >> MO_ASHIFT] =3D "un+", [MO_ALIGN >> MO_ASHIFT] =3D "", #else diff --git a/tcg/tcg.h b/tcg/tcg.h index b411e17a28..529acb2ed8 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -333,10 +333,12 @@ typedef enum TCGMemOp { MO_TE =3D MO_LE, #endif =20 - /* MO_UNALN accesses are never checked for alignment. + /* + * MO_UNALN accesses are never checked for alignment. * MO_ALIGN accesses will result in a call to the CPU's * do_unaligned_access hook if the guest address is not aligned. - * The default depends on whether the target CPU defines ALIGNED_ONLY. + * The default depends on whether the target CPU defines + * TARGET_ALIGNED_ONLY. * * Some architectures (e.g. ARMv8) need the address which is aligned * to a size more than the size of the memory access. @@ -353,7 +355,7 @@ typedef enum TCGMemOp { */ MO_ASHIFT =3D 4, MO_AMASK =3D 7 << MO_ASHIFT, -#ifdef ALIGNED_ONLY +#ifdef TARGET_ALIGNED_ONLY MO_ALIGN =3D 0, MO_UNALN =3D MO_AMASK, #else --=20 2.17.2