From nobody Mon Feb 9 04:33:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660750014301656.4384629006025; Wed, 17 Aug 2022 08:26:54 -0700 (PDT) Received: from localhost ([::1]:45256 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oOKwT-00012s-GA for importer@patchew.org; Wed, 17 Aug 2022 11:26:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39714) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oOKer-0004jt-2H; Wed, 17 Aug 2022 11:08:38 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:43907) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oOKeo-0002xo-5v; Wed, 17 Aug 2022 11:08:36 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id C257874633E; Wed, 17 Aug 2022 17:08:32 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 8E04D746324; Wed, 17 Aug 2022 17:08:32 +0200 (CEST) Message-Id: <10eae70509ca4bd74858fc2c0a0f0e4eb9330199.1660746880.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v2 14/31] ppc4xx: Move EBC model to ppc4xx_devs.c MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Wed, 17 Aug 2022 17:08:32 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660750014696100001 Content-Type: text/plain; charset="utf-8" The EBC is shared between 405 and 440 so move it to shared file. Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405.h | 15 ---- hw/ppc/ppc405_uc.c | 191 ---------------------------------------- hw/ppc/ppc4xx_devs.c | 191 ++++++++++++++++++++++++++++++++++++++++ include/hw/ppc/ppc4xx.h | 15 ++++ 4 files changed, 206 insertions(+), 206 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index 8521be317d..57e1494b05 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -85,21 +85,6 @@ struct Ppc405OpbaState { uint8_t pr; }; =20 -/* Peripheral controller */ -#define TYPE_PPC405_EBC "ppc405-ebc" -OBJECT_DECLARE_SIMPLE_TYPE(Ppc405EbcState, PPC405_EBC); -struct Ppc405EbcState { - Ppc4xxDcrDeviceState parent_obj; - - uint32_t addr; - uint32_t bcr[8]; - uint32_t bap[8]; - uint32_t bear; - uint32_t besr0; - uint32_t besr1; - uint32_t cfg; -}; - /* DMA controller */ #define TYPE_PPC405_DMA "ppc405-dma" OBJECT_DECLARE_SIMPLE_TYPE(Ppc405DmaState, PPC405_DMA); diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 4e875288be..c4268e4c40 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -299,192 +299,6 @@ static void ppc405_opba_class_init(ObjectClass *oc, v= oid *data) /* Code decompression controller */ /* XXX: TODO */ =20 -/*************************************************************************= ****/ -/* Peripheral controller */ -enum { - EBC0_CFGADDR =3D 0x012, - EBC0_CFGDATA =3D 0x013, -}; - -static uint32_t dcr_read_ebc(void *opaque, int dcrn) -{ - Ppc405EbcState *ebc =3D opaque; - uint32_t ret; - - switch (dcrn) { - case EBC0_CFGADDR: - ret =3D ebc->addr; - break; - case EBC0_CFGDATA: - switch (ebc->addr) { - case 0x00: /* B0CR */ - ret =3D ebc->bcr[0]; - break; - case 0x01: /* B1CR */ - ret =3D ebc->bcr[1]; - break; - case 0x02: /* B2CR */ - ret =3D ebc->bcr[2]; - break; - case 0x03: /* B3CR */ - ret =3D ebc->bcr[3]; - break; - case 0x04: /* B4CR */ - ret =3D ebc->bcr[4]; - break; - case 0x05: /* B5CR */ - ret =3D ebc->bcr[5]; - break; - case 0x06: /* B6CR */ - ret =3D ebc->bcr[6]; - break; - case 0x07: /* B7CR */ - ret =3D ebc->bcr[7]; - break; - case 0x10: /* B0AP */ - ret =3D ebc->bap[0]; - break; - case 0x11: /* B1AP */ - ret =3D ebc->bap[1]; - break; - case 0x12: /* B2AP */ - ret =3D ebc->bap[2]; - break; - case 0x13: /* B3AP */ - ret =3D ebc->bap[3]; - break; - case 0x14: /* B4AP */ - ret =3D ebc->bap[4]; - break; - case 0x15: /* B5AP */ - ret =3D ebc->bap[5]; - break; - case 0x16: /* B6AP */ - ret =3D ebc->bap[6]; - break; - case 0x17: /* B7AP */ - ret =3D ebc->bap[7]; - break; - case 0x20: /* BEAR */ - ret =3D ebc->bear; - break; - case 0x21: /* BESR0 */ - ret =3D ebc->besr0; - break; - case 0x22: /* BESR1 */ - ret =3D ebc->besr1; - break; - case 0x23: /* CFG */ - ret =3D ebc->cfg; - break; - default: - ret =3D 0x00000000; - break; - } - break; - default: - ret =3D 0x00000000; - break; - } - - return ret; -} - -static void dcr_write_ebc(void *opaque, int dcrn, uint32_t val) -{ - Ppc405EbcState *ebc =3D opaque; - - switch (dcrn) { - case EBC0_CFGADDR: - ebc->addr =3D val; - break; - case EBC0_CFGDATA: - switch (ebc->addr) { - case 0x00: /* B0CR */ - break; - case 0x01: /* B1CR */ - break; - case 0x02: /* B2CR */ - break; - case 0x03: /* B3CR */ - break; - case 0x04: /* B4CR */ - break; - case 0x05: /* B5CR */ - break; - case 0x06: /* B6CR */ - break; - case 0x07: /* B7CR */ - break; - case 0x10: /* B0AP */ - break; - case 0x11: /* B1AP */ - break; - case 0x12: /* B2AP */ - break; - case 0x13: /* B3AP */ - break; - case 0x14: /* B4AP */ - break; - case 0x15: /* B5AP */ - break; - case 0x16: /* B6AP */ - break; - case 0x17: /* B7AP */ - break; - case 0x20: /* BEAR */ - break; - case 0x21: /* BESR0 */ - break; - case 0x22: /* BESR1 */ - break; - case 0x23: /* CFG */ - break; - default: - break; - } - break; - default: - break; - } -} - -static void ppc405_ebc_reset(DeviceState *dev) -{ - Ppc405EbcState *ebc =3D PPC405_EBC(dev); - int i; - - ebc->addr =3D 0x00000000; - ebc->bap[0] =3D 0x7F8FFE80; - ebc->bcr[0] =3D 0xFFE28000; - for (i =3D 0; i < 8; i++) { - ebc->bap[i] =3D 0x00000000; - ebc->bcr[i] =3D 0x00000000; - } - ebc->besr0 =3D 0x00000000; - ebc->besr1 =3D 0x00000000; - ebc->cfg =3D 0x80400000; -} - -static void ppc405_ebc_realize(DeviceState *dev, Error **errp) -{ - Ppc405EbcState *ebc =3D PPC405_EBC(dev); - Ppc4xxDcrDeviceState *dcr =3D PPC4xx_DCR_DEVICE(dev); - - ppc4xx_dcr_register(dcr, EBC0_CFGADDR, ebc, &dcr_read_ebc, &dcr_write_= ebc); - ppc4xx_dcr_register(dcr, EBC0_CFGDATA, ebc, &dcr_read_ebc, &dcr_write_= ebc); -} - -static void ppc405_ebc_class_init(ObjectClass *oc, void *data) -{ - DeviceClass *dc =3D DEVICE_CLASS(oc); - - dc->realize =3D ppc405_ebc_realize; - dc->reset =3D ppc405_ebc_reset; - /* Reason: only works as function of a ppc4xx SoC */ - dc->user_creatable =3D false; -} - /*************************************************************************= ****/ /* DMA controller */ enum { @@ -1456,11 +1270,6 @@ static const TypeInfo ppc405_types[] =3D { .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(Ppc405OpbaState), .class_init =3D ppc405_opba_class_init, - }, { - .name =3D TYPE_PPC405_EBC, - .parent =3D TYPE_PPC4xx_DCR_DEVICE, - .instance_size =3D sizeof(Ppc405EbcState), - .class_init =3D ppc405_ebc_class_init, }, { .name =3D TYPE_PPC405_DMA, .parent =3D TYPE_PPC4xx_DCR_DEVICE, diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index 3baa2fa2b3..00bb3fe974 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -747,6 +747,192 @@ static void ppc405_plb_class_init(ObjectClass *oc, vo= id *data) dc->user_creatable =3D false; } =20 +/*************************************************************************= ****/ +/* Peripheral controller */ +enum { + EBC0_CFGADDR =3D 0x012, + EBC0_CFGDATA =3D 0x013, +}; + +static uint32_t dcr_read_ebc(void *opaque, int dcrn) +{ + Ppc405EbcState *ebc =3D opaque; + uint32_t ret; + + switch (dcrn) { + case EBC0_CFGADDR: + ret =3D ebc->addr; + break; + case EBC0_CFGDATA: + switch (ebc->addr) { + case 0x00: /* B0CR */ + ret =3D ebc->bcr[0]; + break; + case 0x01: /* B1CR */ + ret =3D ebc->bcr[1]; + break; + case 0x02: /* B2CR */ + ret =3D ebc->bcr[2]; + break; + case 0x03: /* B3CR */ + ret =3D ebc->bcr[3]; + break; + case 0x04: /* B4CR */ + ret =3D ebc->bcr[4]; + break; + case 0x05: /* B5CR */ + ret =3D ebc->bcr[5]; + break; + case 0x06: /* B6CR */ + ret =3D ebc->bcr[6]; + break; + case 0x07: /* B7CR */ + ret =3D ebc->bcr[7]; + break; + case 0x10: /* B0AP */ + ret =3D ebc->bap[0]; + break; + case 0x11: /* B1AP */ + ret =3D ebc->bap[1]; + break; + case 0x12: /* B2AP */ + ret =3D ebc->bap[2]; + break; + case 0x13: /* B3AP */ + ret =3D ebc->bap[3]; + break; + case 0x14: /* B4AP */ + ret =3D ebc->bap[4]; + break; + case 0x15: /* B5AP */ + ret =3D ebc->bap[5]; + break; + case 0x16: /* B6AP */ + ret =3D ebc->bap[6]; + break; + case 0x17: /* B7AP */ + ret =3D ebc->bap[7]; + break; + case 0x20: /* BEAR */ + ret =3D ebc->bear; + break; + case 0x21: /* BESR0 */ + ret =3D ebc->besr0; + break; + case 0x22: /* BESR1 */ + ret =3D ebc->besr1; + break; + case 0x23: /* CFG */ + ret =3D ebc->cfg; + break; + default: + ret =3D 0x00000000; + break; + } + break; + default: + ret =3D 0x00000000; + break; + } + + return ret; +} + +static void dcr_write_ebc(void *opaque, int dcrn, uint32_t val) +{ + Ppc405EbcState *ebc =3D opaque; + + switch (dcrn) { + case EBC0_CFGADDR: + ebc->addr =3D val; + break; + case EBC0_CFGDATA: + switch (ebc->addr) { + case 0x00: /* B0CR */ + break; + case 0x01: /* B1CR */ + break; + case 0x02: /* B2CR */ + break; + case 0x03: /* B3CR */ + break; + case 0x04: /* B4CR */ + break; + case 0x05: /* B5CR */ + break; + case 0x06: /* B6CR */ + break; + case 0x07: /* B7CR */ + break; + case 0x10: /* B0AP */ + break; + case 0x11: /* B1AP */ + break; + case 0x12: /* B2AP */ + break; + case 0x13: /* B3AP */ + break; + case 0x14: /* B4AP */ + break; + case 0x15: /* B5AP */ + break; + case 0x16: /* B6AP */ + break; + case 0x17: /* B7AP */ + break; + case 0x20: /* BEAR */ + break; + case 0x21: /* BESR0 */ + break; + case 0x22: /* BESR1 */ + break; + case 0x23: /* CFG */ + break; + default: + break; + } + break; + default: + break; + } +} + +static void ppc405_ebc_reset(DeviceState *dev) +{ + Ppc405EbcState *ebc =3D PPC405_EBC(dev); + int i; + + ebc->addr =3D 0x00000000; + ebc->bap[0] =3D 0x7F8FFE80; + ebc->bcr[0] =3D 0xFFE28000; + for (i =3D 0; i < 8; i++) { + ebc->bap[i] =3D 0x00000000; + ebc->bcr[i] =3D 0x00000000; + } + ebc->besr0 =3D 0x00000000; + ebc->besr1 =3D 0x00000000; + ebc->cfg =3D 0x80400000; +} + +static void ppc405_ebc_realize(DeviceState *dev, Error **errp) +{ + Ppc405EbcState *ebc =3D PPC405_EBC(dev); + Ppc4xxDcrDeviceState *dcr =3D PPC4xx_DCR_DEVICE(dev); + + ppc4xx_dcr_register(dcr, EBC0_CFGADDR, ebc, &dcr_read_ebc, &dcr_write_= ebc); + ppc4xx_dcr_register(dcr, EBC0_CFGDATA, ebc, &dcr_read_ebc, &dcr_write_= ebc); +} + +static void ppc405_ebc_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D ppc405_ebc_realize; + dc->reset =3D ppc405_ebc_reset; + /* Reason: only works as function of a ppc4xx SoC */ + dc->user_creatable =3D false; +} + /* PPC4xx_DCR_DEVICE */ =20 void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque, @@ -788,6 +974,11 @@ static const TypeInfo ppc4xx_types[] =3D { .parent =3D TYPE_PPC4xx_DCR_DEVICE, .instance_size =3D sizeof(Ppc4xxPlbState), .class_init =3D ppc405_plb_class_init, + }, { + .name =3D TYPE_PPC405_EBC, + .parent =3D TYPE_PPC4xx_DCR_DEVICE, + .instance_size =3D sizeof(Ppc405EbcState), + .class_init =3D ppc405_ebc_class_init, }, { .name =3D TYPE_PPC4xx_DCR_DEVICE, .parent =3D TYPE_SYS_BUS_DEVICE, diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h index b19e59271b..4472ec254e 100644 --- a/include/hw/ppc/ppc4xx.h +++ b/include/hw/ppc/ppc4xx.h @@ -94,4 +94,19 @@ struct Ppc4xxPlbState { uint32_t besr; }; =20 +/* Peripheral controller */ +#define TYPE_PPC405_EBC "ppc405-ebc" +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405EbcState, PPC405_EBC); +struct Ppc405EbcState { + Ppc4xxDcrDeviceState parent_obj; + + uint32_t addr; + uint32_t bcr[8]; + uint32_t bap[8]; + uint32_t bear; + uint32_t besr0; + uint32_t besr1; + uint32_t cfg; +}; + #endif /* PPC4XX_H */ --=20 2.30.4