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X-Received-From: 216.71.153.144 X-Mailman-Approved-At: Fri, 04 May 2018 17:46:56 -0400 Subject: [Qemu-devel] [PATCH v1 1/4] hw/riscv/sifive_u: Create a U54 SoC object X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, mjc@sifive.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Create a SiFive Unleashed U54 SoC and use that in the sifive_u machine. We leave the SoC, RAM, device tree and reset/fdt loading as part of the machine. All the other device creation has been moved to the SoC. Signed-off-by: Alistair Francis --- hw/riscv/sifive_u.c | 90 ++++++++++++++++++++++++++++--------- include/hw/riscv/sifive_u.h | 16 ++++++- 2 files changed, 82 insertions(+), 24 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 9f3d184b72..4924f92262 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -114,10 +114,10 @@ static void create_fdt(SiFiveUState *s, const struct = MemmapEntry *memmap, qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); =20 - for (cpu =3D s->soc.num_harts - 1; cpu >=3D 0; cpu--) { + for (cpu =3D s->soc.cpus.num_harts - 1; cpu >=3D 0; cpu--) { nodename =3D g_strdup_printf("/cpus/cpu@%d", cpu); char *intc =3D g_strdup_printf("/cpus/cpu@%d/interrupt-controller"= , cpu); - char *isa =3D riscv_isa_string(&s->soc.harts[cpu]); + char *isa =3D riscv_isa_string(&s->soc.cpus.harts[cpu]); qemu_fdt_add_subnode(fdt, nodename); qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", SIFIVE_U_CLOCK_FREQ); @@ -138,8 +138,8 @@ static void create_fdt(SiFiveUState *s, const struct Me= mmapEntry *memmap, g_free(nodename); } =20 - cells =3D g_new0(uint32_t, s->soc.num_harts * 4); - for (cpu =3D 0; cpu < s->soc.num_harts; cpu++) { + cells =3D g_new0(uint32_t, s->soc.cpus.num_harts * 4); + for (cpu =3D 0; cpu < s->soc.cpus.num_harts; cpu++) { nodename =3D g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); uint32_t intc_phandle =3D qemu_fdt_get_phandle(fdt, nodename); @@ -157,12 +157,12 @@ static void create_fdt(SiFiveUState *s, const struct = MemmapEntry *memmap, 0x0, memmap[SIFIVE_U_CLINT].base, 0x0, memmap[SIFIVE_U_CLINT].size); qemu_fdt_setprop(fdt, nodename, "interrupts-extended", - cells, s->soc.num_harts * sizeof(uint32_t) * 4); + cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4); g_free(cells); g_free(nodename); =20 - cells =3D g_new0(uint32_t, s->soc.num_harts * 4); - for (cpu =3D 0; cpu < s->soc.num_harts; cpu++) { + cells =3D g_new0(uint32_t, s->soc.cpus.num_harts * 4); + for (cpu =3D 0; cpu < s->soc.cpus.num_harts; cpu++) { nodename =3D g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); uint32_t intc_phandle =3D qemu_fdt_get_phandle(fdt, nodename); @@ -179,7 +179,7 @@ static void create_fdt(SiFiveUState *s, const struct Me= mmapEntry *memmap, qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); qemu_fdt_setprop(fdt, nodename, "interrupts-extended", - cells, s->soc.num_harts * sizeof(uint32_t) * 4); + cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4); qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0, memmap[SIFIVE_U_PLIC].base, 0x0, memmap[SIFIVE_U_PLIC].size); @@ -215,17 +215,12 @@ static void riscv_sifive_u_init(MachineState *machine) SiFiveUState *s =3D g_new0(SiFiveUState, 1); MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); - MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); int i; =20 - /* Initialize SOC */ - object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY); + /* Initialize SoC */ + object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_U54_SOC); object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc), &error_abort); - object_property_set_str(OBJECT(&s->soc), SIFIVE_U_CPU, "cpu-type", - &error_abort); - object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts", - &error_abort); object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_abort); =20 @@ -233,17 +228,11 @@ static void riscv_sifive_u_init(MachineState *machine) memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram", machine->ram_size, &error_fatal); memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base, - main_mem); + main_mem); =20 /* create device tree */ create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); =20 - /* boot rom */ - memory_region_init_rom(mask_rom, NULL, "riscv.sifive.u.mrom", - memmap[SIFIVE_U_MROM].size, &error_fatal); - memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base, - mask_rom); - if (machine->kernel_filename) { load_kernel(machine->kernel_filename); } @@ -282,6 +271,39 @@ static void riscv_sifive_u_init(MachineState *machine) rom_add_blob_fixed_as("mrom.fdt", s->fdt, s->fdt_size, memmap[SIFIVE_U_MROM].base + sizeof(reset_vec), &address_space_memory); +} + +static void riscv_sifive_u54_init(Object *obj) +{ + const struct MemmapEntry *memmap =3D sifive_u_memmap; + + SiFiveU54State *s =3D RISCV_U54_SOC(obj); + MemoryRegion *system_memory =3D get_system_memory(); + MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); + + object_initialize(&s->cpus, sizeof(s->cpus), TYPE_RISCV_HART_ARRAY); + object_property_add_child(obj, "cpus", OBJECT(&s->cpus), + &error_abort); + object_property_set_str(OBJECT(&s->cpus), SIFIVE_U_CPU, "cpu-type", + &error_abort); + object_property_set_int(OBJECT(&s->cpus), smp_cpus, "num-harts", + &error_abort); + + /* boot rom */ + memory_region_init_rom(mask_rom, NULL, "riscv.sifive.u.mrom", + memmap[SIFIVE_U_MROM].size, &error_fatal); + memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base, + mask_rom); +} + +static void riscv_sifive_u54_realize(DeviceState *dev, Error **errp) +{ + SiFiveU54State *s =3D RISCV_U54_SOC(dev); + const struct MemmapEntry *memmap =3D sifive_u_memmap; + MemoryRegion *system_memory =3D get_system_memory(); + + object_property_set_bool(OBJECT(&s->cpus), true, "realized", + &error_abort); =20 /* MMIO */ s->plic =3D sifive_plic_create(memmap[SIFIVE_U_PLIC].base, @@ -312,3 +334,27 @@ static void riscv_sifive_u_machine_init(MachineClass *= mc) } =20 DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init) + +static void riscv_sifive_u54_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D riscv_sifive_u54_realize; + /* Reason: Uses serial_hds in realize function, thus can't be used twi= ce */ + dc->user_creatable =3D false; +} + +static const TypeInfo riscv_sifive_u54_type_info =3D { + .name =3D TYPE_RISCV_U54_SOC, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(SiFiveU54State), + .instance_init =3D riscv_sifive_u54_init, + .class_init =3D riscv_sifive_u54_class_init, +}; + +static void riscv_sifive_u54_register_types(void) +{ + type_register_static(&riscv_sifive_u54_type_info); +} + +type_init(riscv_sifive_u54_register_types) diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 94a390566e..0f8bdd8fab 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -19,13 +19,25 @@ #ifndef HW_SIFIVE_U_H #define HW_SIFIVE_U_H =20 -typedef struct SiFiveUState { +#define TYPE_RISCV_U54_SOC "riscv.sifive.u54" +#define RISCV_U54_SOC(obj) \ + OBJECT_CHECK(SiFiveU54State, (obj), TYPE_RISCV_U54_SOC) + +typedef struct SiFiveU54State { /*< private >*/ SysBusDevice parent_obj; =20 /*< public >*/ - RISCVHartArrayState soc; + RISCVHartArrayState cpus; DeviceState *plic; +} SiFiveU54State; + +typedef struct SiFiveUState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + SiFiveU54State soc; void *fdt; int fdt_size; } SiFiveUState; --=20 2.17.0