From nobody Mon Feb 9 05:37:27 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16630994371081015.1440463941163; Tue, 13 Sep 2022 13:03:57 -0700 (PDT) Received: from localhost ([::1]:33000 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oYC8R-0001Pj-Nn for importer@patchew.org; Tue, 13 Sep 2022 16:03:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57038) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYBxa-0001fx-Le; Tue, 13 Sep 2022 15:52:42 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]:12578) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYBxX-000531-Lq; Tue, 13 Sep 2022 15:52:42 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 2B2A074637E; Tue, 13 Sep 2022 21:52:38 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 0937874632B; Tue, 13 Sep 2022 21:52:38 +0200 (CEST) Message-Id: <09a0ad26c9f088650a0254ceb3f2a82d346384c9.1663097286.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v3 11/20] ppc440_sdram: Get rid of the init RAM hack MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Tue, 13 Sep 2022 21:52:38 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1663099438840100001 Content-Type: text/plain; charset="utf-8" Remove the do_init parameter of ppc440_sdram_init and enable SDRAM controller from the board via DCR access instead. Firmware does this so it may not be needed when booting firmware only with -kernel but we enable it unconditionally to preserve previous behaviour. Signed-off-by: BALATON Zoltan --- v2: replace 0x08000000 with BIT(27) hw/ppc/ppc440.h | 3 +-- hw/ppc/ppc440_uc.c | 8 ++------ hw/ppc/sam460ex.c | 8 +++++++- 3 files changed, 10 insertions(+), 9 deletions(-) diff --git a/hw/ppc/ppc440.h b/hw/ppc/ppc440.h index e6c905b7d6..01d76b8000 100644 --- a/hw/ppc/ppc440.h +++ b/hw/ppc/ppc440.h @@ -17,8 +17,7 @@ void ppc4xx_l2sram_init(CPUPPCState *env); void ppc4xx_cpr_init(CPUPPCState *env); void ppc4xx_sdr_init(CPUPPCState *env); void ppc440_sdram_init(CPUPPCState *env, int nbanks, - Ppc4xxSdramBank *ram_banks, - int do_init); + Ppc4xxSdramBank *ram_banks); void ppc4xx_ahb_init(CPUPPCState *env); void ppc4xx_dma_init(CPUPPCState *env, int dcr_base); void ppc460ex_pcie_init(CPUPPCState *env); diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c index 3c442eaecc..b3f56c49b5 100644 --- a/hw/ppc/ppc440_uc.c +++ b/hw/ppc/ppc440_uc.c @@ -723,12 +723,11 @@ static void sdram_reset(void *opaque) ppc440_sdram_t *sdram =3D opaque; =20 sdram->addr =3D 0; - sdram->mcopt2 =3D BIT(27); + sdram->mcopt2 =3D 0; } =20 void ppc440_sdram_init(CPUPPCState *env, int nbanks, - Ppc4xxSdramBank *ram_banks, - int do_init) + Ppc4xxSdramBank *ram_banks) { ppc440_sdram_t *sdram; int i; @@ -745,9 +744,6 @@ void ppc440_sdram_init(CPUPPCState *env, int nbanks, sdram, &dcr_read_sdram, &dcr_write_sdram); ppc_dcr_register(env, SDRAM0_CFGDATA, sdram, &dcr_read_sdram, &dcr_write_sdram); - if (do_init) { - sdram_map_bcr(sdram); - } =20 ppc_dcr_register(env, SDRAM_R0BAS, sdram, &dcr_read_sdram, &dcr_write_sdram); diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index f4c2a693fb..dac329d482 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -345,7 +345,13 @@ static void sam460ex_init(MachineState *machine) ppc4xx_sdram_banks(machine->ram, 1, ram_banks, ppc460ex_sdram_bank_siz= es); =20 /* FIXME: does 460EX have ECC interrupts? */ - ppc440_sdram_init(env, 1, ram_banks, 1); + ppc440_sdram_init(env, 1, ram_banks); + /* Enable SDRAM memory regions as we may boot without firmware */ + if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x21) || + ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x08000000)) { + error_report("Couldn't enable memory regions"); + exit(1); + } =20 /* IIC controllers and devices */ dev =3D sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700, --=20 2.30.4