From nobody Mon Feb 9 14:02:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1768897533; cv=none; d=zohomail.com; s=zohoarc; b=FFXAku20UB81O4gSLblqiC4/yrfOI/iCnOEAfQqdBW6aFEbIlCGmDOrVcGn1U4NPeX56lVxi3dIrSJZPYW102ri53YDyNOUau7gCYsXbPHJLOxr+1B28G9gWK9nFyuDw0k7P6Yjqa674icO0Rz6SXg9iyNOMImAhjkFwMOlLIvA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768897533; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=2vWZi5duXXkyD/HWruu4ist4eS//a3QiftKxssXv66g=; b=dOIANZqOxg/VvdUZ/8HBxK4iUHml6y5QcioSqi+T2g3oMspXvIL8JtZbAzwR3LFCmlQ15YNBlXLSFSh7gknq5JTCLd6QodRObunLGoHUuvmd2UdsFoevtWFxNkJUlHhXhwkxl4pa1FtEooepWzaIiyKKECr8w/yyU6eXMcTAKnI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768897533446422.16445299029135; Tue, 20 Jan 2026 00:25:33 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vi72W-0005h1-9d; Tue, 20 Jan 2026 03:24:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vi72U-0005dg-DF for qemu-devel@nongnu.org; Tue, 20 Jan 2026 03:24:38 -0500 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vi72S-00035a-Ar for qemu-devel@nongnu.org; Tue, 20 Jan 2026 03:24:38 -0500 Received: by mail-pg1-x541.google.com with SMTP id 41be03b00d2f7-c3e921afad1so2116836a12.1 for ; Tue, 20 Jan 2026 00:24:36 -0800 (PST) Received: from ZEVORN-PC.bbrouter ([183.195.21.37]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-35274573a7esm4273592a91.11.2026.01.20.00.24.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jan 2026 00:24:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1768897475; x=1769502275; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2vWZi5duXXkyD/HWruu4ist4eS//a3QiftKxssXv66g=; b=A75TnMhDDgnvr1qyzX9c5OaUq4shz5VeM02y8kQ319tDDxNrSE0woUaONkvDsIUUj7 mePZMnAUYoszT++vdLu0WeimAxj1Mlk22iLqohBQB8UHBb1x6g4akQEhj25Z8YiKz1DF I8OTCQraBW1EpA5G8ZXRMeATBB7AzfJCwfGtahfZqRoGy9C1WMoiiWjwxh7eoDNFMsAx 8xWYQDRTNdvsRryPEnqHgZ5tgcgKFGOrcCkzbiRa0W/j0sSd4l0vHHr+JPM4hmKQX+Xd Mc2mSQ1xaCN0vGmCE1i6J+ffCnuHzOr2oDpNUY3Qa6cCs4musMM7/JG61NCeLrQiT1pk qQ+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768897475; x=1769502275; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=2vWZi5duXXkyD/HWruu4ist4eS//a3QiftKxssXv66g=; b=KKUprCCbC5vbqhMtr1KVZaSU9Gnr51uq+YDcgf6FO1qt+QdWCr4vEjP/bUHH0iQKUE ZYNQEBWG1JPTLLAOpsCrVymYmmtdL+tYvVHNFeh/NohWuuU9f25E7edXbIiKb/ONaW9F 57U7druoywCDTubNx8/W694hH8AA9ry5bWxfmsxypC+o08jAlpwt0dIcB5OG+0KC0O4k YgDPw5+UwN4n6Pi19laIVyu8s2nr1+48mJXQiecthKAkSROKNQpS7Cw18vWnAsoGeU1F 96ateVUCVSHmUC8wLmVG1VKR6YmCSYMuQ3jpHPyxvemo6BsAbfKps5cC1p/AU6fIbJbd s5DA== X-Gm-Message-State: AOJu0YzqkAG7dOh7OKVM0S08xa9aKKzpw6rMysxd9N5x7DnTAuIZB573 TzXot9oov/WGcd4O9CvLDuzi4/qgM1D278HA76uwJOCmil2YAEezdUZEF5n6cG8qIHG8oQ== X-Gm-Gg: AZuq6aLrhIl+d9HVphDrq5vizPN/1/PVj0CJkLMUuFVDynFKlrUpo4kveYh4aJNfPs7 /rFLzqVIjy+DDpH4aeLjwKWvnJcKU00MzFkgAwOEY6+9Dd4idbwGnL2wN+zfR86VLHXy5jZAoah q/TRn0T6B4hg2FBWZRBug2yYV8iFH9L7FlJezJwtktHn0xRP4I7Kamz9YBXz6oMryGbgr+M5vB/ vuIGgrLyIzsJPgZwrYZXDSazsCKPKXQR2VqoCnXyH6egH3iLEbvtxuuQMnlSVFTQJ67N/PY8Fn2 v74gBdONt9fPMfXiIbXSOvTf6njYvQK1nsK69eF/Yle7GWPPurzVoj3o+pQ0f/NNktA2SGyCwHR uh2zlxdvR/oDJadoyvHy4au3LrtjoE8SlUDNA3ZDnH3SmiW9x9u7fZZ19kjCqNDg0Yy2kpNpufN jkB5CxA/DWO5KRXvyHFqfI115QfAWWfUgItPrCywNAhsH3NxxykujjL7qlbg== X-Received: by 2002:a17:90b:56c8:b0:341:2150:4856 with SMTP id 98e67ed59e1d1-352c404682cmr1203860a91.17.1768897475019; Tue, 20 Jan 2026 00:24:35 -0800 (PST) From: Chao Liu To: Alistair Francis , Daniel Henrique Barboza , Palmer Dabbelt , Weiwei Li , Liu Zhiwei Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, wangjingwei@iscas.ac.cn, Chao Liu Subject: [RFC PATCH v2 6/7] target/riscv: add sdext single-step support Date: Tue, 20 Jan 2026 16:24:02 +0800 Message-ID: <07aaa807546ca59e185a3e5c0ad56cebf2165014.1768892407.git.chao.liu.zevorn@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::541; envelope-from=chao.liu.zevorn@gmail.com; helo=mail-pg1-x541.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1768897535451158500 Content-Type: text/plain; charset="utf-8" RISC-V Debug Specification: https://github.com/riscv/riscv-debug-spec/releases/tag/1.0 Use a TB flag when dcsr.step is set (and we are not in Debug Mode). When the flag is on, build 1-insn TBs and do not chain to the next TB. Add a TB-exit helper that enters Debug Mode with cause=3Dstep and sets dpc to the next pc, then stops with EXCP_DEBUG. If dcsr.stepie is 0, do not take interrupts while stepping. Treat WFI as a nop so the hart does not sleep during a step. PS: This patch references Max Chou's handling of ext_tb_flags. https://lore.kernel.org/qemu-devel/20260108132631.9429-6-max.chou@sifive.co= m/ Signed-off-by: Chao Liu --- include/exec/translation-block.h | 4 ++-- target/riscv/cpu.h | 2 ++ target/riscv/cpu_helper.c | 6 ++++++ target/riscv/helper.h | 1 + target/riscv/op_helper.c | 20 ++++++++++++++++++++ target/riscv/tcg/tcg-cpu.c | 5 +++++ target/riscv/translate.c | 15 +++++++++++++-- 7 files changed, 49 insertions(+), 4 deletions(-) diff --git a/include/exec/translation-block.h b/include/exec/translation-bl= ock.h index 40cc699031..ee15608c89 100644 --- a/include/exec/translation-block.h +++ b/include/exec/translation-block.h @@ -64,8 +64,8 @@ struct TranslationBlock { * x86: the original user, the Code Segment virtual base, * arm: an extension of tb->flags, * s390x: instruction data for EXECUTE, - * sparc: the next pc of the instruction queue (for delay slots). - * riscv: an extension of tb->flags, + * sparc: the next pc of the instruction queue (for delay slots), + * riscv: an extension of tb->flags. */ uint64_t cs_base; =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 62732957a4..0d6b70c9f0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -712,6 +712,8 @@ FIELD(TB_FLAGS, PM_SIGNEXTEND, 31, 1) =20 FIELD(EXT_TB_FLAGS, MISA_EXT, 0, 32) FIELD(EXT_TB_FLAGS, ALTFMT, 32, 1) +/* sdext single-step needs a TB flag to build 1-insn TBs */ +FIELD(EXT_TB_FLAGS, SDEXT_STEP, 33, 1) =20 #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 05a991fccc..2ca6040d20 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -638,6 +638,12 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interr= upt_request) if (interrupt_request & mask) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; + + if (cpu->cfg.ext_sdext && !env->debug_mode && + (env->dcsr & DCSR_STEP) && !(env->dcsr & DCSR_STEPIE)) { + return false; + } + int interruptno =3D riscv_cpu_local_irq_pending(env); if (interruptno >=3D 0) { cs->exception_index =3D RISCV_EXCP_INT_FLAG | interruptno; diff --git a/target/riscv/helper.h b/target/riscv/helper.h index bbfe7548d2..cadb97f637 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -141,6 +141,7 @@ DEF_HELPER_1(tlb_flush_all, void, env) DEF_HELPER_4(ctr_add_entry, void, env, tl, tl, tl) /* Native Debug */ DEF_HELPER_1(itrigger_match, void, env) +DEF_HELPER_1(sdext_step, void, env) DEF_HELPER_2(sdext_ebreak, void, env, tl) #endif =20 diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index dfe5388ab7..6fe29ce905 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -470,6 +470,22 @@ target_ulong helper_dret(CPURISCVState *env) #endif } =20 +void helper_sdext_step(CPURISCVState *env) +{ +#ifndef CONFIG_USER_ONLY + CPUState *cs =3D env_cpu(env); + + if (!riscv_cpu_cfg(env)->ext_sdext || env->debug_mode || + !(env->dcsr & DCSR_STEP)) { + return; + } + + riscv_cpu_enter_debug_mode(env, env->pc, DCSR_CAUSE_STEP); + cs->exception_index =3D EXCP_DEBUG; + cpu_loop_exit_restore(cs, GETPC()); +#endif +} + void helper_sdext_ebreak(CPURISCVState *env, target_ulong pc) { #ifndef CONFIG_USER_ONLY @@ -604,6 +620,10 @@ void helper_wfi(CPURISCVState *env) (prv_u || (prv_s && get_field(env->hstatus, HSTATUS_VTW))))= { riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); } else { + if (riscv_cpu_cfg(env)->ext_sdext && !env->debug_mode && + (env->dcsr & DCSR_STEP)) { + return; + } cs->halted =3D 1; cs->exception_index =3D EXCP_HLT; cpu_loop_exit(cs); diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index c6beac3d50..9166ec0404 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -193,6 +193,11 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *= cs) flags =3D FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext); =20 ext_flags =3D FIELD_DP64(ext_flags, EXT_TB_FLAGS, MISA_EXT, env->misa_= ext); +#ifndef CONFIG_USER_ONLY + if (cpu->cfg.ext_sdext && !env->debug_mode && (env->dcsr & DCSR_STEP))= { + ext_flags =3D FIELD_DP64(ext_flags, EXT_TB_FLAGS, SDEXT_STEP, 1); + } +#endif =20 return (TCGTBCPUState){ .pc =3D env->xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc, diff --git a/target/riscv/translate.c b/target/riscv/translate.c index bf403785b5..f2f12fe269 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -111,6 +111,8 @@ typedef struct DisasContext { bool ztso; /* Use icount trigger for native debug */ bool itrigger; + /* Enter Debug Mode after next instruction (sdext single-step). */ + bool sdext_step; /* FRM is known to contain a valid value. */ bool frm_valid; bool insn_start_updated; @@ -293,6 +295,9 @@ static void lookup_and_goto_ptr(DisasContext *ctx) if (ctx->itrigger) { gen_helper_itrigger_match(tcg_env); } + if (ctx->sdext_step) { + gen_helper_sdext_step(tcg_env); + } #endif tcg_gen_lookup_and_goto_ptr(); } @@ -303,6 +308,9 @@ static void exit_tb(DisasContext *ctx) if (ctx->itrigger) { gen_helper_itrigger_match(tcg_env); } + if (ctx->sdext_step) { + gen_helper_sdext_step(tcg_env); + } #endif tcg_gen_exit_tb(NULL, 0); } @@ -316,7 +324,8 @@ static void gen_goto_tb(DisasContext *ctx, unsigned tb_= slot_idx, * Under itrigger, instruction executes one by one like singlestep, * direct block chain benefits will be small. */ - if (translator_use_goto_tb(&ctx->base, dest) && !ctx->itrigger) { + if (translator_use_goto_tb(&ctx->base, dest) && + !ctx->itrigger && !ctx->sdext_step) { /* * For pcrel, the pc must always be up-to-date on entry to * the linked TB, so that it can use simple additions for all @@ -1351,6 +1360,7 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->bcfi_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, BCFI_ENABLED); ctx->fcfi_lp_expected =3D FIELD_EX32(tb_flags, TB_FLAGS, FCFI_LP_EXPEC= TED); ctx->fcfi_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, FCFI_ENABLED); + ctx->sdext_step =3D FIELD_EX64(ext_tb_flags, EXT_TB_FLAGS, SDEXT_STEP); ctx->zero =3D tcg_constant_tl(0); ctx->virt_inst_excp =3D false; ctx->decoders =3D cpu->decoders; @@ -1401,7 +1411,8 @@ static void riscv_tr_translate_insn(DisasContextBase = *dcbase, CPUState *cpu) =20 /* Only the first insn within a TB is allowed to cross a page boundary= . */ if (ctx->base.is_jmp =3D=3D DISAS_NEXT) { - if (ctx->itrigger || !translator_is_same_page(&ctx->base, ctx->bas= e.pc_next)) { + if (ctx->itrigger || ctx->sdext_step || + !translator_is_same_page(&ctx->base, ctx->base.pc_next)) { ctx->base.is_jmp =3D DISAS_TOO_MANY; } else { unsigned page_ofs =3D ctx->base.pc_next & ~TARGET_PAGE_MASK; --=20 2.52.0