From nobody Mon Feb 9 07:43:01 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1492771607168684.6195652757172; Fri, 21 Apr 2017 03:46:47 -0700 (PDT) Received: from localhost ([::1]:58504 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d1W5N-0007ZB-Jx for importer@patchew.org; Fri, 21 Apr 2017 06:46:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55889) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d1W1M-0004Cg-Uq for qemu-devel@nongnu.org; Fri, 21 Apr 2017 06:42:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d1W1K-00005e-Jd for qemu-devel@nongnu.org; Fri, 21 Apr 2017 06:42:36 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]:25228) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1d1W1K-0008W3-8B; Fri, 21 Apr 2017 06:42:34 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 276A17456BB; Fri, 21 Apr 2017 12:42:32 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 697DB7456D1; Fri, 21 Apr 2017 12:42:31 +0200 (CEST) Message-Id: <05a1c43d060f8e8a3d143eff6f037488e2f4b0f9.1492770667.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Date: Fri, 21 Apr 2017 12:31:07 +0200 To: qemu-devel@nongnu.org, qemu-trivial@nongnu.org X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 152.66.115.2 Subject: [Qemu-devel] [PATCH v6 06/13] sm501: Add emulation of chip connected via PCI X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Magnus Damm , Aurelien Jarno , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Only the display controller part is created automatically on PCI Signed-off-by: BALATON Zoltan Reviewed-by: Peter Maydell --- v2: Split off removing dependency on base address to separate patch v3: Added reset function and PCI ID constant definitions in pci_ids.h v4: Return error for invalid VRAM size, set bit in misc_control for PCI bus hw/display/sm501.c | 65 ++++++++++++++++++++++++++++++++++++++++++++= ++++ include/hw/pci/pci_ids.h | 3 +++ 2 files changed, 68 insertions(+) diff --git a/hw/display/sm501.c b/hw/display/sm501.c index 09c023d..c92a5fa 100644 --- a/hw/display/sm501.c +++ b/hw/display/sm501.c @@ -32,6 +32,7 @@ #include "ui/console.h" #include "hw/devices.h" #include "hw/sysbus.h" +#include "hw/pci/pci.h" #include "qemu/range.h" #include "ui/pixel_ops.h" #include "exec/address-spaces.h" @@ -1547,9 +1548,73 @@ static const TypeInfo sm501_sysbus_info =3D { .class_init =3D sm501_sysbus_class_init, }; =20 +#define TYPE_PCI_SM501 "sm501" +#define PCI_SM501(obj) OBJECT_CHECK(SM501PCIState, (obj), TYPE_PCI_SM501) + +typedef struct { + /*< private >*/ + PCIDevice parent_obj; + /*< public >*/ + SM501State state; + uint32_t vram_size; +} SM501PCIState; + +static void sm501_realize_pci(PCIDevice *dev, Error **errp) +{ + SM501PCIState *s =3D PCI_SM501(dev); + + sm501_init(&s->state, DEVICE(dev), s->vram_size); + if (get_local_mem_size(&s->state) !=3D s->vram_size) { + error_setg(errp, "Invalid VRAM size, nearest valid size is %" PRIu= 32, + get_local_mem_size(&s->state)); + return; + } + pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, + &s->state.local_mem_region); + pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, + &s->state.mmio_region); +} + +static Property sm501_pci_properties[] =3D { + DEFINE_PROP_UINT32("vram-size", SM501PCIState, vram_size, 64 * M_BYTE), + DEFINE_PROP_END_OF_LIST(), +}; + +static void sm501_reset_pci(DeviceState *dev) +{ + SM501PCIState *s =3D PCI_SM501(dev); + sm501_reset(&s->state); + /* Bits 2:0 of misc_control register is 001 for PCI */ + s->state.misc_control |=3D 1; +} + +static void sm501_pci_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); + + k->realize =3D sm501_realize_pci; + k->vendor_id =3D PCI_VENDOR_ID_SILICON_MOTION; + k->device_id =3D PCI_DEVICE_ID_SM501; + k->class_id =3D PCI_CLASS_DISPLAY_OTHER; + set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); + dc->desc =3D "SM501 Display Controller"; + dc->props =3D sm501_pci_properties; + dc->reset =3D sm501_reset_pci; + dc->hotpluggable =3D false; +} + +static const TypeInfo sm501_pci_info =3D { + .name =3D TYPE_PCI_SM501, + .parent =3D TYPE_PCI_DEVICE, + .instance_size =3D sizeof(SM501PCIState), + .class_init =3D sm501_pci_class_init, +}; + static void sm501_register_types(void) { type_register_static(&sm501_sysbus_info); + type_register_static(&sm501_pci_info); } =20 type_init(sm501_register_types) diff --git a/include/hw/pci/pci_ids.h b/include/hw/pci/pci_ids.h index d22ad8d..3752ddc 100644 --- a/include/hw/pci/pci_ids.h +++ b/include/hw/pci/pci_ids.h @@ -207,6 +207,9 @@ =20 #define PCI_VENDOR_ID_MARVELL 0x11ab =20 +#define PCI_VENDOR_ID_SILICON_MOTION 0x126f +#define PCI_DEVICE_ID_SM501 0x0501 + #define PCI_VENDOR_ID_ENSONIQ 0x1274 #define PCI_DEVICE_ID_ENSONIQ_ES1370 0x5000 =20 --=20 2.7.4