From nobody Mon Feb 9 16:21:58 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1612426074; cv=none; d=zohomail.com; s=zohoarc; b=YrUpuubG9/MlBJSWFLEvnvzTqFadTVMtC84OEvzB64UHGE/f1ggF4WyWF5jK639nvieq9Zg0VMjdvIqpxH1KwTPnGKx9xSWYq3gxka/SnuLTi3JvmY4UDBBQW4xPXMyLLLO+FKq8gzndoljTtqAXkWivG7HFuOZ703S2r5q5zrU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612426074; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=cE/9ZiHi7R28Kcf19qDkLLNXv5kn7wcTp9w5yvzvBgc=; b=kc+H1anlW5fcsDbFlpkBVvkfew/kwkITFfiIy6hoKhULi4LQNyvunVuNHlG1nxJ6ZKRJTirGwaXhTAQmw9k3sD8N3Okan4lSYF0Qoxu318yOaTD2/dQ/Co6zZS0k0EyNov5/0RCzp89NnS52aAb5vrHaQNfj0gQ9FpmQ9aWTnrE= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612426074182508.8259767625666; Thu, 4 Feb 2021 00:07:54 -0800 (PST) Received: from localhost ([::1]:58514 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l7Zg9-0001X2-0L for importer@patchew.org; Thu, 04 Feb 2021 03:07:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54524) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7ZeN-00004v-Ik for qemu-devel@nongnu.org; Thu, 04 Feb 2021 03:06:03 -0500 Received: from mga05.intel.com ([192.55.52.43]:43412) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l7ZeL-0007VQ-Fi for qemu-devel@nongnu.org; Thu, 04 Feb 2021 03:06:03 -0500 Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 00:05:45 -0800 Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 00:05:44 -0800 IronPort-SDR: Kk1bJEqdLwxCwEw72WNn1Ziugp7BaBPX+aZJdZkSTNjhDm7UE9ej61/9CERyRgu+DDl6VTvJGh K50IYUFCLHTw== X-IronPort-AV: E=McAfee;i="6000,8403,9884"; a="266025486" X-IronPort-AV: E=Sophos;i="5.79,400,1602572400"; d="scan'208";a="266025486" IronPort-SDR: hNxORws1avm9T/7bsPJBVsp80ZyqY8GN1bwNRTYriO1hqnnnZzwDTwwsBHnr5qPjI05ST2qcY6 AfbpF+TGXofQ== X-IronPort-AV: E=Sophos;i="5.79,400,1602572400"; d="scan'208";a="372302438" From: isaku.yamahata@gmail.com To: qemu-devel@nongnu.org, imammedo@redhat.com, mst@redhat.com, marcel.apfelbaum@gmail.com Subject: [PATCH 3/4] hw/i386: declare ACPI mother board resource for MMCONFIG region Date: Thu, 4 Feb 2021 00:04:10 -0800 Message-Id: <052f8372cd04dcab1940c2fbf530d06fd8c85cc4.1612424814.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.43; envelope-from=isaku.yamahata@intel.com; helo=mga05.intel.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_ADSP_CUSTOM_MED=0.001, FORGED_GMAIL_RCVD=1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NML_ADSP_CUSTOM_MED=0.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Isaku Yamahata Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Isaku Yamahata Declare PNP0C01 device to reserve MMCONFIG region to conform to the spec better and play nice with guest BIOSes/OSes. According to PCI Firmware Specification, MMCONFIG region must be reserved by declaring a motherboard resource. It's optional to reserve the region in memory map by Int 15 E820h or EFIGetMemoryMap. If guest BIOS doesn't reserve the region in memory map without the reservation by mother board resource, guest linux abandons to use MMCFG. TDVF [0] [1] doesn't reserve MMCONFIG the region in memory map. On the other hand OVMF reserves it in memory map without declaring a motherboard resource. With memory map reservation, linux guest uses MMCONFIG region. However it doesn't comply to PCI Firmware specification. [0] TDX: Intel Trust Domain Extension https://software.intel.com/content/www/us/en/develop/articles/intel-tru= st-domain-extensions.html [1] TDX Virtual Firmware https://github.com/tianocore/edk2-staging/tree/TDVF Signed-off-by: Isaku Yamahata Acked-by: Jiewen Yao --- hw/i386/acpi-build.c | 172 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 172 insertions(+) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 005bcc2886..6e38f67120 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1062,6 +1062,177 @@ static void build_q35_pci0_int(Aml *table) aml_append(table, sb_scope); } =20 +static Aml *build_q35_dram_controller(void) +{ + /* + * DSDT is created with revision 1 which means 32bit integer. + * When the method of _CRS is called to determine MMCONFIG region, + * only port io is allowed to access PCI configuration space. + * It means qword access isn't allowed. + * + * Device(DRAC) + * { + * Name(_HID, EisaId("PNP0C01")) + * OperationRegion(DRR0, PCI_Config, 0x0000000000000060, 0x8) + * Field(DRR0, DWordAcc, Lock, Preserve) + * { + * PEBL, 4, + * PEBH, 4 + * } + * Name(RBUF, ResourceTemplate() + * { + * QWordMemory(ResourceConsumer, + * PosDecode, + * MinFixed, + * MaxFixed, + * NonCacheable, + * ReadWrite, + * 0x0000000000000000, // Granularity + * 0x0000000000000000, // Range Minimum + * 0x0000000000000000, // Range Maxium + * 0x0000000000000000, // Translation Offset, + * 0x0000000000000000, // Length, + * ,, + * _MCF, + * AddressRangeMemory, + * TypeStatic + * ) + * }) + * Method(_CRS, 0x0, NotSerialized) + * { + * CreateDWordField(RBUF, DRAC._MCF._MIN, MINL) + * CreateDWordField(RBUF, DRAC._MCF._MIN + 4, MINH) + * CreateDWordField(RBUF, DRAC._MCF._MAX, MAXL) + * CreateDWordField(RBUF, DRAC._MCF._MAX + 4, MAXH) + * CreateQWordField(RBUF, DRAC._MCF._LEN, _LEN) + * + * Local0 =3D PEBL + * Local1 =3D Local0 & 0x1 // PCIEXBAR PCIEBAREN + * Local2 =3D Local0 & 0x6 // PCIEXBAR LENGTH + * Local3 =3D Local0 & ~0x7 // PCIEXBAR base address low 32bit + * Local4 =3D PEBH // PCIEXBAR base address high 32bit + * If (Local1 =3D=3D 1) { + * MINL =3D Local3 + * MINH =3D Local4 + * MAXL =3D Local3 + * MAXH =3D Local4 + * + * If (Local2 =3D=3D 0) { + * _LEN =3D 256 * 1024 * 1024 + * } + * If (Local2 =3D=3D 0x2) { + * _LEN =3D 128 * 1024 * 1024 + * } + * If (Local2 =3D=3D 0x4) { + * _LEN =3D 64 * 1024 * 1024 + * } + * } + * return (RBUF) + * } + * } + */ + + Aml *dev; + Aml *field; + Aml *rbuf; + Aml *resource_template; + Aml *crs; + + /* DRAM controller */ + dev =3D aml_device("DRAC"); + + aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01"))); + /* 5.1.6 PCIEXBAR: Bus 0:Device 0:Function 0:offset 0x60 */ + aml_append(dev, aml_operation_region("DRR0", AML_PCI_CONFIG, + aml_int(0x0000000000000060), 0x8)= ); + field =3D aml_field("DRR0", AML_DWORD_ACC, AML_NOLOCK, AML_PRESERVE); + aml_append(field, aml_named_field("PEBL", 32)); + aml_append(field, aml_named_field("PEBH", 32)); + aml_append(dev, field); + + resource_template =3D aml_resource_template(); + aml_append(resource_template, aml_qword_memory(AML_POS_DECODE, + AML_MIN_FIXED, + AML_MAX_FIXED, + AML_NON_CACHEABLE, + AML_READ_WRITE, + 0x0000000000000000, + 0x0000000000000000, + 0x0000000000000000, + 0x0000000000000000, + 0x0000000000000000)); + rbuf =3D aml_name_decl("RBUF", resource_template); + aml_append(dev, rbuf); + + crs =3D aml_method("_CRS", 0, AML_SERIALIZED); + { + Aml *rbuf_name; + Aml *local0; + Aml *local1; + Aml *local2; + Aml *local3; + Aml *local4; + Aml *ifc; + + rbuf_name =3D aml_name("RBUF"); + aml_append(crs, aml_create_dword_field(rbuf_name, + aml_int(14), "MINL")); + aml_append(crs, aml_create_dword_field(rbuf_name, + aml_int(14 + 4), "MINH")); + aml_append(crs, aml_create_dword_field(rbuf_name, + aml_int(22), "MAXL")); + aml_append(crs, aml_create_dword_field(rbuf_name, + aml_int(22 + 4), "MAXH")); + aml_append(crs, aml_create_qword_field(rbuf_name, + aml_int(38), "_LEN")); + + local0 =3D aml_local(0); + aml_append(crs, aml_store(aml_name("PEBL"), local0)); + local1 =3D aml_local(1); + aml_append(crs, aml_and(local0, aml_int(0x1), local1)); + local2 =3D aml_local(2); + aml_append(crs, aml_and(local0, aml_int(0x6), local2)); + local3 =3D aml_local(3); + aml_append(crs, aml_and(local0, aml_int((uint32_t)~0x7), local3)); + local4 =3D aml_local(4); + aml_append(crs, aml_store(aml_name("PEBH"), local4)); + + ifc =3D aml_if(aml_equal(local1, aml_int(0x1))); + { + Aml *_len; + Aml *ifc0; + Aml *ifc2; + Aml *ifc4; + + aml_append(ifc, aml_store(local3, aml_name("MINL"))); + aml_append(ifc, aml_store(local4, aml_name("MINH"))); + aml_append(ifc, aml_store(local3, aml_name("MAXL"))); + aml_append(ifc, aml_store(local4, aml_name("MAXH"))); + + _len =3D aml_name("_LEN"); + ifc0 =3D aml_if(aml_equal(local2, aml_int(0x0))); + aml_append(ifc0, + aml_store(aml_int(256 * 1024 * 1024), _len)); + aml_append(ifc, ifc0); + + ifc2 =3D aml_if(aml_equal(local2, aml_int(0x2))); + aml_append(ifc2, + aml_store(aml_int(128 * 1024 * 1024), _len)); + aml_append(ifc, ifc2); + + ifc4 =3D aml_if(aml_equal(local2, aml_int(0x4))); + aml_append(ifc4, + aml_store(aml_int(64 * 1024 * 1024), _len)); + aml_append(ifc, ifc4); + } + aml_append(crs, ifc); + aml_append(crs, aml_return(rbuf_name)); + } + aml_append(dev, crs); + + return dev; +} + static void build_q35_isa_bridge(Aml *table) { Aml *dev; @@ -1246,6 +1417,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, aml_append(dev, aml_name_decl("_UID", aml_int(0))); aml_append(dev, build_q35_osc_method()); aml_append(sb_scope, dev); + aml_append(sb_scope, build_q35_dram_controller()); =20 if (pm->smi_on_cpuhp) { /* reserve SMI block resources, IO ports 0xB2, 0xB3 */ --=20 2.17.1