From nobody Mon Feb 9 19:08:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1553512332228679.3398965168334; Mon, 25 Mar 2019 04:12:12 -0700 (PDT) Received: from localhost ([127.0.0.1]:40634 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h8NWO-0004bb-JB for importer@patchew.org; Mon, 25 Mar 2019 07:12:04 -0400 Received: from eggs.gnu.org ([209.51.188.92]:58827) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h8NNf-0005Tb-Je for qemu-devel@nongnu.org; Mon, 25 Mar 2019 07:03:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h8NNe-00085W-6G for qemu-devel@nongnu.org; Mon, 25 Mar 2019 07:03:03 -0400 Received: from greensocs.com ([193.104.36.180]:38379) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h8NNW-0007sT-Uo; Mon, 25 Mar 2019 07:02:56 -0400 Received: from localhost (localhost [127.0.0.1]) by greensocs.com (Postfix) with ESMTP id 4CA6C7D78B5; Mon, 25 Mar 2019 12:02:34 +0100 (CET) Received: from greensocs.com ([127.0.0.1]) by localhost (gs-01.greensocs.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id YwN9RSmXw0fS; Mon, 25 Mar 2019 12:02:33 +0100 (CET) Received: by greensocs.com (Postfix, from userid 998) id 667B17D7887; Mon, 25 Mar 2019 12:02:31 +0100 (CET) Received: from kouign-amann.bar.greensocs.com (antfield.tima.u-ga.fr [147.171.129.253]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: damien.hedde@greensocs.com) by greensocs.com (Postfix) with ESMTPSA id 4349E7D78BC; Mon, 25 Mar 2019 12:02:30 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1553511754; bh=WYEcYLOEIGBkhOa2aU0abUg66uqcWe4gaMtFGotmZkU=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=M576576ccElMb0mSy/n9bbkSbmxqkB8QdzV2s3AS2Hb149TiygRO/N5575OGSSh1J y+1mg4+49qijZlv1FbE4x/Ifs+XYllyFAOmQPAtYv4hmj/8VAK6g7dyKPSgJBzw4j9 8cA/OKCqWkcbSHmDcMwD+it/C8zSvzjs0NP5l+Gw= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com header.b=dJTBW0M2; dkim=pass (1024-bit key) header.d=greensocs.com header.b=DCYeiaZ7 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1553511752; bh=WYEcYLOEIGBkhOa2aU0abUg66uqcWe4gaMtFGotmZkU=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=dJTBW0M2is/2YCfUp4+QJ6ORlYrrXG/4xiGNRekIuQCYgxDQMf/5LMPXida4LJ1QY Oh1e+SeVA1K9vrHYYCrSUkH6egpqBQgz3ZsgJggJxr10xwBsPIF65cvN13lUz/bxDT Kz98GjhcOb9hGUxjoVR8kgFoSbekBVaLQvUIz8ng= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1553511750; bh=WYEcYLOEIGBkhOa2aU0abUg66uqcWe4gaMtFGotmZkU=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=DCYeiaZ7Txq3XDAmFnR36pIeypmNDiDxPYYOvhv438a42zSd5eZyz0glG9AePRVs3 GcBTQWWK6pQa5liMoSfC//ARoJma/8WLy8m89wm8noOCRkanDA5BSK5NSG32HGsclg fdTZAYC+E4od48qMSakc3XqykkOJhI4o1+gavKYE= From: Damien Hedde To: qemu-devel@nongnu.org Date: Mon, 25 Mar 2019 12:01:57 +0100 Message-Id: <052e5afb8c6cbaf6fac894ee7bfdc7ed03d38788.1553510737.git.damien.hedde@greensocs.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [RFC PATCH 14/17] convert cadence_uart to 3-phases reset X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, mark.burton@greensocs.com, Damien Hedde , qemu-arm@nongnu.org, alistair.francis@wdc.com, marcandre.lureau@redhat.com, pbonzini@redhat.com, philmd@redhat.com, luc.michel@greensocs.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 3 invalid signatures) Content-Type: text/plain; charset="utf-8" Split the existing reset procedure into 3 phases. Test the resetting flag to discard register accesses and character reception. Also adds a active high reset io. Signed-off-by: Damien Hedde --- hw/char/cadence_uart.c | 48 ++++++++++++++++++++++++++++++++++++++---- 1 file changed, 44 insertions(+), 4 deletions(-) diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index fbdbd463bb..694c8ea614 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -222,6 +222,10 @@ static int uart_can_receive(void *opaque) int ret =3D MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE); uint32_t ch_mode =3D s->r[R_MR] & UART_MR_CHMODE; =20 + if (qdev_is_resetting((DeviceState *) opaque)) { + return 0; + } + if (ch_mode =3D=3D NORMAL_MODE || ch_mode =3D=3D ECHO_MODE) { ret =3D MIN(ret, CADENCE_UART_RX_FIFO_SIZE - s->rx_count); } @@ -337,6 +341,10 @@ static void uart_receive(void *opaque, const uint8_t *= buf, int size) CadenceUARTState *s =3D opaque; uint32_t ch_mode =3D s->r[R_MR] & UART_MR_CHMODE; =20 + if (qdev_is_resetting((DeviceState *) opaque)) { + return; + } + if (ch_mode =3D=3D NORMAL_MODE || ch_mode =3D=3D ECHO_MODE) { uart_write_rx_fifo(opaque, buf, size); } @@ -350,6 +358,10 @@ static void uart_event(void *opaque, int event) CadenceUARTState *s =3D opaque; uint8_t buf =3D '\0'; =20 + if (qdev_is_resetting((DeviceState *) opaque)) { + return; + } + if (event =3D=3D CHR_EVENT_BREAK) { uart_write_rx_fifo(opaque, &buf, 1); } @@ -382,6 +394,10 @@ static void uart_write(void *opaque, hwaddr offset, { CadenceUARTState *s =3D opaque; =20 + if (qdev_is_resetting((DeviceState *)opaque)) { + return; + } + DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value); offset >>=3D 2; if (offset >=3D CADENCE_UART_R_MAX) { @@ -440,6 +456,10 @@ static uint64_t uart_read(void *opaque, hwaddr offset, CadenceUARTState *s =3D opaque; uint32_t c =3D 0; =20 + if (qdev_is_resetting((DeviceState *)opaque)) { + return 0; + } + offset >>=3D 2; if (offset >=3D CADENCE_UART_R_MAX) { c =3D 0; @@ -459,9 +479,9 @@ static const MemoryRegionOps uart_ops =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 -static void cadence_uart_reset(DeviceState *dev) +static void cadence_uart_reset_init(Object *obj, bool cold) { - CadenceUARTState *s =3D CADENCE_UART(dev); + CadenceUARTState *s =3D CADENCE_UART(obj); =20 s->r[R_CR] =3D 0x00000128; s->r[R_IMR] =3D 0; @@ -470,6 +490,18 @@ static void cadence_uart_reset(DeviceState *dev) s->r[R_BRGR] =3D 0x0000028B; s->r[R_BDIV] =3D 0x0000000F; s->r[R_TTRIG] =3D 0x00000020; +} + +static void cadence_uart_reset_hold(Object *obj) +{ + CadenceUARTState *s =3D CADENCE_UART(obj); + + qemu_set_irq(s->irq, 0); +} + +static void cadence_uart_reset_exit(Object *obj) +{ + CadenceUARTState *s =3D CADENCE_UART(obj); =20 uart_rx_reset(s); uart_tx_reset(s); @@ -498,6 +530,8 @@ static void cadence_uart_init(Object *obj) sysbus_init_irq(sbd, &s->irq); =20 s->char_tx_time =3D (NANOSECONDS_PER_SECOND / 9600) * 10; + + qdev_init_warm_reset_gpio(DEVICE(obj), "rst", DEVICE_ACTIVE_HIGH); } =20 static int cadence_uart_post_load(void *opaque, int version_id) @@ -532,6 +566,10 @@ static const VMStateDescription vmstate_cadence_uart = =3D { VMSTATE_UINT32(rx_wpos, CadenceUARTState), VMSTATE_TIMER_PTR(fifo_trigger_handle, CadenceUARTState), VMSTATE_END_OF_LIST() + }, + .subsections =3D (const VMStateDescription * []) { + &device_vmstate_reset, + NULL } }; =20 @@ -546,9 +584,11 @@ static void cadence_uart_class_init(ObjectClass *klass= , void *data) =20 dc->realize =3D cadence_uart_realize; dc->vmsd =3D &vmstate_cadence_uart; - dc->reset =3D cadence_uart_reset; + dc->reset_phases.init =3D cadence_uart_reset_init; + dc->reset_phases.hold =3D cadence_uart_reset_hold; + dc->reset_phases.exit =3D cadence_uart_reset_exit; dc->props =3D cadence_uart_properties; - } +} =20 static const TypeInfo cadence_uart_info =3D { .name =3D TYPE_CADENCE_UART, --=20 2.21.0