From nobody Mon Feb 9 08:30:23 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1562152069; cv=none; d=zoho.com; s=zohoarc; b=STaMuvR7r1SqJpNfotez0+P7tzHnirzJqoAU/kMCAKVpTUvVh/iVP7o9fa+5HVLPDh+qvRnuZuI31RV4WGy7Rmf/Y1igIleZxoMTdplf6iave/tUJBdO+9Dx+W3z7cSwTvzYSnwUnNpzcCpRiorp5Chb9Dn28DIHvAtqJ9SlNH4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1562152069; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=8M100xGr92RX0swSJ6YayKzQzfEcMCYqljsvK9HtFVU=; b=ba38VKfvcGFDMVIlMuycl2Ua3BQjXIc4YespXHKG0Uut12keerB5h+k42kv852VBZKImUXdO29wdduzDqfWy869KZ4iPpDn9b75fli3VYZHaMRkYXis5/e2BvMhM6ETJoxv+1CkTdII9xYM3hJ9IexhgMjW8HUIbmYmwRVnNLTc= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1562152069803874.7115962906271; Wed, 3 Jul 2019 04:07:49 -0700 (PDT) Received: from localhost ([::1]:34912 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hid76-0007S4-Qv for importer@patchew.org; Wed, 03 Jul 2019 07:07:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59961) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hid1E-0000mE-Og for qemu-devel@nongnu.org; Wed, 03 Jul 2019 07:01:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hid1D-0005EK-Bd for qemu-devel@nongnu.org; Wed, 03 Jul 2019 07:01:44 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:44208) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hid1C-00054V-RV for qemu-devel@nongnu.org; Wed, 03 Jul 2019 07:01:43 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 9E4787461AA; Wed, 3 Jul 2019 13:01:38 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 149AA7462AA; Wed, 3 Jul 2019 13:01:38 +0200 (CEST) Message-Id: <04b67ff483223d4722b0b044192558e7d17b36b5.1562151410.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Date: Wed, 03 Jul 2019 12:56:50 +0200 MIME-Version: 1.0 To: qemu-devel@nongnu.org Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:738:2001:2001::2001 Subject: [Qemu-devel] [PATCH 1/3] ati-vga: Improve readability of ati_2d_blt function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Gerd Hoffmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Move common parts before the switch to remove code duplication and improve readibility. Signed-off-by: BALATON Zoltan --- hw/display/ati_2d.c | 80 ++++++++++++++++++++++---------------------------= ---- 1 file changed, 33 insertions(+), 47 deletions(-) diff --git a/hw/display/ati_2d.c b/hw/display/ati_2d.c index 2dbf53f039..c31142af6e 100644 --- a/hw/display/ati_2d.c +++ b/hw/display/ati_2d.c @@ -42,6 +42,8 @@ static int ati_bpp_from_datatype(ATIVGAState *s) } } =20 +#define DEFAULT_CNTL (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CN= TL) + void ati_2d_blt(ATIVGAState *s) { /* FIXME it is probably more complex than this and may need to be */ @@ -51,6 +53,22 @@ void ati_2d_blt(ATIVGAState *s) s->vga.vbe_start_addr, surface_data(ds), surface_stride(ds), surface_bits_per_pixel(ds), (s->regs.dp_mix & GMC_ROP3_MASK) >> 16); + int bpp =3D ati_bpp_from_datatype(s); + int dst_stride =3D DEFAULT_CNTL ? s->regs.dst_pitch : s->regs.default_= pitch; + uint8_t *dst_bits =3D s->vga.vram_ptr + (DEFAULT_CNTL ? + s->regs.dst_offset : s->regs.default_offset); + + if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { + dst_bits +=3D s->regs.crtc_offset & 0x07ffffff; + dst_stride *=3D bpp; + } + uint8_t *end =3D s->vga.vram_ptr + s->vga.vram_size; + if (dst_bits >=3D end || + dst_bits + s->regs.dst_x + (s->regs.dst_y + s->regs.dst_height) * + dst_stride >=3D end) { + qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n"); + return; + } DPRINTF("%d %d %d, %d %d %d, (%d,%d) -> (%d,%d) %dx%d\n", s->regs.src_offset, s->regs.dst_offset, s->regs.default_offset, s->regs.src_pitch, s->regs.dst_pitch, s->regs.default_pitch, @@ -59,41 +77,28 @@ void ati_2d_blt(ATIVGAState *s) switch (s->regs.dp_mix & GMC_ROP3_MASK) { case ROP3_SRCCOPY: { - uint8_t *src_bits, *dst_bits, *end; - int src_stride, dst_stride, bpp =3D ati_bpp_from_datatype(s); - src_bits =3D s->vga.vram_ptr + - (s->regs.dp_gui_master_cntl & GMC_SRC_PITCH_OFFSET_CNTL= ? - s->regs.src_offset : s->regs.default_offset); - dst_bits =3D s->vga.vram_ptr + - (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CNTL= ? - s->regs.dst_offset : s->regs.default_offset); - src_stride =3D (s->regs.dp_gui_master_cntl & GMC_SRC_PITCH_OFFSET_= CNTL ? - s->regs.src_pitch : s->regs.default_pitch); - dst_stride =3D (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_= CNTL ? - s->regs.dst_pitch : s->regs.default_pitch); + int src_stride =3D DEFAULT_CNTL ? + s->regs.src_pitch : s->regs.default_pitch; + uint8_t *src_bits =3D s->vga.vram_ptr + (DEFAULT_CNTL ? + s->regs.src_offset : s->regs.default_offset); =20 if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { src_bits +=3D s->regs.crtc_offset & 0x07ffffff; - dst_bits +=3D s->regs.crtc_offset & 0x07ffffff; src_stride *=3D bpp; - dst_stride *=3D bpp; } + if (src_bits >=3D end || + src_bits + s->regs.src_x + (s->regs.src_y + s->regs.dst_height= ) * + src_stride >=3D end) { + qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n"); + return; + } + src_stride /=3D sizeof(uint32_t); dst_stride /=3D sizeof(uint32_t); - DPRINTF("pixman_blt(%p, %p, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d= )\n", src_bits, dst_bits, src_stride, dst_stride, bpp, bpp, s->regs.src_x, s->regs.src_y, s->regs.dst_x, s->regs.dst_y, s->regs.dst_width, s->regs.dst_height); - end =3D s->vga.vram_ptr + s->vga.vram_size; - if (src_bits >=3D end || dst_bits >=3D end || - src_bits + s->regs.src_x + (s->regs.src_y + s->regs.dst_height= ) * - src_stride * sizeof(uint32_t) >=3D end || - dst_bits + s->regs.dst_x + (s->regs.dst_y + s->regs.dst_height= ) * - dst_stride * sizeof(uint32_t) >=3D end) { - qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n"); - return; - } pixman_blt((uint32_t *)src_bits, (uint32_t *)dst_bits, src_stride, dst_stride, bpp, bpp, s->regs.src_x, s->regs.src_y, @@ -115,20 +120,7 @@ void ati_2d_blt(ATIVGAState *s) case ROP3_BLACKNESS: case ROP3_WHITENESS: { - uint8_t *dst_bits, *end; - int dst_stride, bpp =3D ati_bpp_from_datatype(s); uint32_t filler =3D 0; - dst_bits =3D s->vga.vram_ptr + - (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CNTL= ? - s->regs.dst_offset : s->regs.default_offset); - dst_stride =3D (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_= CNTL ? - s->regs.dst_pitch : s->regs.default_pitch); - - if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { - dst_bits +=3D s->regs.crtc_offset & 0x07ffffff; - dst_stride *=3D bpp; - } - dst_stride /=3D sizeof(uint32_t); =20 switch (s->regs.dp_mix & GMC_ROP3_MASK) { case ROP3_PATCOPY: @@ -144,22 +136,16 @@ void ati_2d_blt(ATIVGAState *s) break; } =20 + dst_stride /=3D sizeof(uint32_t); DPRINTF("pixman_fill(%p, %d, %d, %d, %d, %d, %d, %x)\n", dst_bits, dst_stride, bpp, s->regs.dst_x, s->regs.dst_y, s->regs.dst_width, s->regs.dst_height, filler); - end =3D s->vga.vram_ptr + s->vga.vram_size; - if (dst_bits >=3D end || - dst_bits + s->regs.dst_x + (s->regs.dst_y + s->regs.dst_height= ) * - dst_stride * sizeof(uint32_t) >=3D end) { - qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n"); - return; - } pixman_fill((uint32_t *)dst_bits, dst_stride, bpp, - s->regs.dst_x, s->regs.dst_y, - s->regs.dst_width, s->regs.dst_height, - filler); + s->regs.dst_x, s->regs.dst_y, + s->regs.dst_width, s->regs.dst_height, + filler); if (dst_bits >=3D s->vga.vram_ptr + s->vga.vbe_start_addr && dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr + s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset= ) { --=20 2.13.7