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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=matheus.bernardino@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1775673755798154100 Content-Type: text/plain; charset="utf-8" Add HVX IEEE floating-point min/max instructions: - vfmin_hf, vfmin_sf: IEEE floating-point minimum - vfmax_hf, vfmax_sf: IEEE floating-point maximum - vmax_hf, vmax_sf: qfloat IEEE maximum - vmin_hf, vmin_sf: qfloat IEEE minimum The Hexagon qfloat variants are similar to the IEEE-754 ones, but they handle NaN slightly differently. See comment on hvx_ieee_fp.h Signed-off-by: Matheus Tavares Bernardino Reviewed-by: Taylor Simpson --- target/hexagon/mmvec/hvx_ieee_fp.h | 6 +++ target/hexagon/attribs_def.h.inc | 2 + target/hexagon/mmvec/hvx_ieee_fp.c | 49 ++++++++++++++++++++ target/hexagon/hex_common.py | 1 + target/hexagon/imported/mmvec/encode_ext.def | 10 ++++ target/hexagon/imported/mmvec/ext.idef | 36 +++++++++++++- 6 files changed, 103 insertions(+), 1 deletion(-) diff --git a/target/hexagon/mmvec/hvx_ieee_fp.h b/target/hexagon/mmvec/hvx_= ieee_fp.h index 75008deb3b..ed8e4f2da9 100644 --- a/target/hexagon/mmvec/hvx_ieee_fp.h +++ b/target/hexagon/mmvec/hvx_ieee_fp.h @@ -15,4 +15,10 @@ float32 fp_mult_sf_hf(float16 a1, float16 a2, float_stat= us *fp_status); float32 fp_vdmpy(float16 a1, float16 a2, float16 a3, float16 a4, float_status *fp_status); =20 +/* Qfloat min/max treat +NaN as greater than +INF and -NaN as smaller than= -INF */ +uint32_t qf_max_sf(uint32_t a1, uint32_t a2, float_status *fp_status); +uint32_t qf_min_sf(uint32_t a1, uint32_t a2, float_status *fp_status); +uint16_t qf_max_hf(uint16_t a1, uint16_t a2, float_status *fp_status); +uint16_t qf_min_hf(uint16_t a1, uint16_t a2, float_status *fp_status); + #endif diff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.= h.inc index d3c4bf6301..2d0fc7e9c0 100644 --- a/target/hexagon/attribs_def.h.inc +++ b/target/hexagon/attribs_def.h.inc @@ -81,6 +81,7 @@ DEF_ATTRIB(CVI_SCATTER, "CVI Scatter operation", "", "") DEF_ATTRIB(CVI_SCATTER_RELEASE, "CVI Store Release for scatter", "", "") DEF_ATTRIB(CVI_TMP_DST, "CVI instruction that doesn't write a register", "= ", "") DEF_ATTRIB(CVI_SLOT23, "Can execute in slot 2 or slot 3 (HVX)", "", "") +DEF_ATTRIB(CVI_VA_2SRC, "Execs on multimedia vector engine; requires two s= rcs", "", "") =20 DEF_ATTRIB(VTCM_ALLBANK_ACCESS, "Allocates in all VTCM schedulers.", "", "= ") =20 @@ -179,6 +180,7 @@ DEF_ATTRIB(HVX_IEEE_FP_ACC, "HVX IEEE FP accumulate ins= truction", "", "") DEF_ATTRIB(HVX_IEEE_FP_OUT_16, "HVX IEEE FP 16-bit output", "", "") DEF_ATTRIB(HVX_IEEE_FP_OUT_32, "HVX IEEE FP 32-bit output", "", "") DEF_ATTRIB(CVI_VX_NO_TMP_LD, "HVX multiply without tmp load", "", "") +DEF_ATTRIB(HVX_FLT, "This a floating point HVX instruction.", "", "") =20 /* Keep this as the last attribute: */ DEF_ATTRIB(ZZ_LASTATTRIB, "Last attribute in the file", "", "") diff --git a/target/hexagon/mmvec/hvx_ieee_fp.c b/target/hexagon/mmvec/hvx_= ieee_fp.c index 3367226998..868c0c5b18 100644 --- a/target/hexagon/mmvec/hvx_ieee_fp.c +++ b/target/hexagon/mmvec/hvx_ieee_fp.c @@ -19,3 +19,52 @@ float32 fp_vdmpy(float16 a1, float16 a2, float16 a3, flo= at16 a4, return float32_add(fp_mult_sf_hf(a1, a3, fp_status), fp_mult_sf_hf(a2, a4, fp_status), fp_status); } + +#define float32_is_pos_nan(X) (float32_is_any_nan(X) && !float32_is_neg(X)) +#define float32_is_neg_nan(X) (float32_is_any_nan(X) && float32_is_neg(X)) +#define float16_is_pos_nan(X) (float16_is_any_nan(X) && !float16_is_neg(X)) +#define float16_is_neg_nan(X) (float16_is_any_nan(X) && float16_is_neg(X)) + +float32 qf_max_sf(float32 a1, float32 a2, float_status *fp_status) +{ + if (float32_is_pos_nan(a1) || float32_is_neg_nan(a2)) { + return a1; + } + if (float32_is_pos_nan(a2) || float32_is_neg_nan(a1)) { + return a2; + } + return float32_max(a1, a2, fp_status); +} + +float32 qf_min_sf(float32 a1, float32 a2, float_status *fp_status) +{ + if (float32_is_pos_nan(a1) || float32_is_neg_nan(a2)) { + return a2; + } + if (float32_is_pos_nan(a2) || float32_is_neg_nan(a1)) { + return a1; + } + return float32_min(a1, a2, fp_status); +} + +float16 qf_max_hf(float16 a1, float16 a2, float_status *fp_status) +{ + if (float16_is_pos_nan(a1) || float16_is_neg_nan(a2)) { + return a1; + } + if (float16_is_pos_nan(a2) || float16_is_neg_nan(a1)) { + return a2; + } + return float16_max(a1, a2, fp_status); +} + +float16 qf_min_hf(float16 a1, float16 a2, float_status *fp_status) +{ + if (float16_is_pos_nan(a1) || float16_is_neg_nan(a2)) { + return a2; + } + if (float16_is_pos_nan(a2) || float16_is_neg_nan(a1)) { + return a1; + } + return float16_min(a1, a2, fp_status); +} diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py index 9e8bcfdcf0..c81dd5b836 100755 --- a/target/hexagon/hex_common.py +++ b/target/hexagon/hex_common.py @@ -216,6 +216,7 @@ def need_env(tag): "A_CVI_GATHER" in attribdict[tag] or "A_CVI_SCATTER" in attribdict[tag] or "A_HVX_IEEE_FP" in attribdict[tag] or + "A_HVX_FLT" in attribdict[tag] or "A_IMPLICIT_WRITES_USR" in attribdict[tag]) =20 =20 diff --git a/target/hexagon/imported/mmvec/encode_ext.def b/target/hexagon/= imported/mmvec/encode_ext.def index 4ce87d09fd..d7f50db778 100644 --- a/target/hexagon/imported/mmvec/encode_ext.def +++ b/target/hexagon/imported/mmvec/encode_ext.def @@ -823,4 +823,14 @@ DEF_ENC(V6_vsub_sf_hf,"00011111100vvvvvPP1uuuuu101dddd= d") DEF_ENC(V6_vadd_hf_hf,"00011111101vvvvvPP1uuuuu111ddddd") DEF_ENC(V6_vsub_hf_hf,"00011111011vvvvvPP1uuuuu000ddddd") =20 +/* IEEE FP min/max instructions */ +DEF_ENC(V6_vfmin_hf,"00011100011vvvvvPP1uuuuu000ddddd") +DEF_ENC(V6_vfmin_sf,"00011100011vvvvvPP1uuuuu001ddddd") +DEF_ENC(V6_vfmax_hf,"00011100011vvvvvPP1uuuuu010ddddd") +DEF_ENC(V6_vfmax_sf,"00011100011vvvvvPP1uuuuu011ddddd") +DEF_ENC(V6_vmax_sf,"00011111110vvvvvPP1uuuuu001ddddd") +DEF_ENC(V6_vmin_sf,"00011111110vvvvvPP1uuuuu010ddddd") +DEF_ENC(V6_vmax_hf,"00011111110vvvvvPP1uuuuu011ddddd") +DEF_ENC(V6_vmin_hf,"00011111110vvvvvPP1uuuuu100ddddd") + #endif /* NO MMVEC */ diff --git a/target/hexagon/imported/mmvec/ext.idef b/target/hexagon/import= ed/mmvec/ext.idef index 14df8e4790..0e9cace203 100644 --- a/target/hexagon/imported/mmvec/ext.idef +++ b/target/hexagon/imported/mmvec/ext.idef @@ -43,7 +43,9 @@ EXTINSN(V6_##TAG, SYNTAX, ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA), \ DESCR, DO_FOR_EACH_CODE(WIDTH, CODE)) =20 - +#define ITERATOR_INSN_ANY_SLOT_2SRC(WIDTH,TAG,SYNTAX,DESCR,CODE) \ +EXTINSN(V6_##TAG, SYNTAX, ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC= ,A_HVX_FLT), \ +DESCR, DO_FOR_EACH_CODE(WIDTH, CODE)) =20 #define ITERATOR_INSN2_ANY_SLOT(WIDTH,TAG,SYNTAX,SYNTAX2,DESCR,CODE) \ ITERATOR_INSN_ANY_SLOT(WIDTH,TAG,SYNTAX2,DESCR,CODE) @@ -3000,6 +3002,38 @@ ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vsub_sf_hf, VddV.v[1].sf[i] =3D float32_sub(f16_to_f32(VuV.hf[2*i+1]), f16_to_f32(VvV.hf[2*i+1]), &env->hvx_fp_= status)) =20 +#define ITERATOR_INSN_IEEE_FP_16_32_LATE(WIDTH,TAG,SYNTAX,DESCR,CODE) \ +EXTINSN(V6_##TAG, SYNTAX, \ + ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX,A_HVX_IEEE_FP_OUT= _16,A_HVX_IEEE_FP_OUT_32), \ + DESCR, DO_FOR_EACH_CODE(WIDTH, CODE)) + +/* IEEE FP min/max instructions */ +ITERATOR_INSN_IEEE_FP_16_32_LATE(16, vfmin_hf, "Vd32.hf=3Dvfmin(Vu32.hf,Vv= 32.hf)", \ + "Vector IEEE min: hf", VdV.hf[i] =3D float16_min(VuV.hf[i], VvV.hf[i]= , \ + &env->hvx_fp_status)) +ITERATOR_INSN_IEEE_FP_16_32_LATE(32, vfmin_sf, "Vd32.sf=3Dvfmin(Vu32.sf,Vv= 32.sf)", \ + "Vector IEEE min: sf", VdV.sf[i] =3D float32_min(VuV.sf[i], VvV.sf[i]= , \ + &env->hvx_fp_status)) +ITERATOR_INSN_IEEE_FP_16_32_LATE(16, vfmax_hf, "Vd32.hf=3Dvfmax(Vu32.hf,V= v32.hf)", \ + "Vector IEEE max: hf", VdV.hf[i] =3D float16_max(VuV.hf[i], VvV.hf[i],= \ + &env->hvx_fp_status)) +ITERATOR_INSN_IEEE_FP_16_32_LATE(32, vfmax_sf, "Vd32.sf=3Dvfmax(Vu32.sf,V= v32.sf)", \ + "Vector IEEE max: sf", VdV.sf[i] =3D float32_max(VuV.sf[i], VvV.sf[i],= \ + &env->hvx_fp_status)) + +ITERATOR_INSN_ANY_SLOT_2SRC(32,vmax_sf,"Vd32.sf=3Dvmax(Vu32.sf,Vv32.sf)", \ + "Vector max of sf input", VdV.sf[i] =3D qf_max_sf(VuV.sf[i], VvV.sf[i]= , \ + &env->hvx_fp_status)) +ITERATOR_INSN_ANY_SLOT_2SRC(32,vmin_sf,"Vd32.sf=3Dvmin(Vu32.sf,Vv32.sf)", \ + "Vector min of sf input", VdV.sf[i] =3D qf_min_sf(VuV.sf[i], VvV.sf[i]= , \ + &env->hvx_fp_status)) +ITERATOR_INSN_ANY_SLOT_2SRC(16,vmax_hf,"Vd32.hf=3Dvmax(Vu32.hf,Vv32.hf)", \ + "Vector max of hf input", VdV.hf[i] =3D qf_max_hf(VuV.hf[i], VvV.hf[i]= , \ + &env->hvx_fp_status)) +ITERATOR_INSN_ANY_SLOT_2SRC(16,vmin_hf,"Vd32.hf=3Dvmin(Vu32.hf,Vv32.hf)", \ + "Vector min of hf input", VdV.hf[i] =3D qf_min_hf(VuV.hf[i], VvV.hf[i]= , \ + &env->hvx_fp_status)) + /*************************************************************************= ***** DEBUG Vector/Register Printing *************************************************************************= *****/ --=20 2.37.2