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Fri, 13 Dec 2019 12:48:37 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576237736; h=from:from:sender:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:list-id:list-help: list-unsubscribe:list-subscribe:list-post; bh=9leloGkX8nEcsan2jOivAguKzaHtt3p0mvE/pu7hUio=; b=VnADn1Q5nGLAU1CTYZVk4WqCLD6X1clSvgstzNKtbhzodT4doFAC1FPFHR8HiDySgTVJHg Y41HH99LG3clImGc0uVnmR8SvLzXxOhVvuGlolgLaZHKUStI02RrVtT4uIBcfS9MnZQp+x AnrNIMZTdneAJ/EBcyhuIDk/4BbdUac= From: Jiri Denemark To: libvir-list@redhat.com Date: Fri, 13 Dec 2019 12:48:32 +0100 Message-Id: <57eacd090d25c5669cf3dbb1044ae879e3a77854.1576236620.git.jdenemar@redhat.com> In-Reply-To: References: MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-loop: libvir-list@redhat.com Subject: [libvirt] [PATCH 1/2] cpu_map: Add TAA_NO bit for IA32_ARCH_CAPABILITIES MSR X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-MC-Unique: IUS0p0oCPpOfKqmkbVpWHA-1 X-Mimecast-Spam-Score: 0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @redhat.com) Content-Type: text/plain; charset="utf-8" CVE-2019-11135 CPUs with TAA_NO bit of IA32_ARCH_CAPABILITIES MSR set to 1 are not vulnerable to TSX Asynchronous Abort and passing this bit to a guest may avoid unnecessary mitigations. Signed-off-by: Jiri Denemark Reviewed-by: J=C3=A1n Tomko --- src/cpu_map/x86_features.xml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/cpu_map/x86_features.xml b/src/cpu_map/x86_features.xml index 2bed1e0372..d1180ed26d 100644 --- a/src/cpu_map/x86_features.xml +++ b/src/cpu_map/x86_features.xml @@ -502,4 +502,7 @@ + + + --=20 2.24.1 -- libvir-list mailing list libvir-list@redhat.com https://www.redhat.com/mailman/listinfo/libvir-list From nobody Sun May 5 11:05:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 205.139.110.61 as permitted sender) client-ip=205.139.110.61; envelope-from=libvir-list-bounces@redhat.com; helo=us-smtp-delivery-1.mimecast.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of redhat.com designates 205.139.110.61 as permitted sender) smtp.mailfrom=libvir-list-bounces@redhat.com; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; 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Fri, 13 Dec 2019 06:48:41 -0500 Received: by smtp.corp.redhat.com (Postfix) id B752160148; Fri, 13 Dec 2019 11:48:41 +0000 (UTC) Received: from orkuz.int.mamuti.net (ovpn-204-182.brq.redhat.com [10.40.204.182]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 89100601A2 for ; Fri, 13 Dec 2019 11:48:39 +0000 (UTC) Received: by orkuz.int.mamuti.net (Postfix, from userid 500) id 6918A2A8855; Fri, 13 Dec 2019 12:48:37 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1576237733; h=from:from:sender:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:list-id:list-help: list-unsubscribe:list-subscribe:list-post; bh=VgSmtnX319o+SCVKajd58T/5KDDw3KuJ9s5BhbpqePE=; b=F3yhb12AO2skLoMRi9l9sAVSKXcfAxNQGieddWaCFaoHcYDcbP5R71NVYroAxdNVp0Z+vE GVOXnOfvK8BI0HLYZuaesejs5hAwCXJ9qTWcCPD/nwK/wPu/sIQczVx+uISogGkhVxB5nt jIIBnJZIQGNiBUgSXHQmdMFam92U10A= From: Jiri Denemark To: libvir-list@redhat.com Date: Fri, 13 Dec 2019 12:48:33 +0100 Message-Id: In-Reply-To: References: MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-loop: libvir-list@redhat.com Subject: [libvirt] [PATCH 2/2] cpu_map: Add TSX_CTRL bit for IA32_ARCH_CAPABILITIES MSR X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: E01O0Fc5MqKRn6i3qxMxZw-1 X-Mimecast-Spam-Score: 0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @redhat.com) Content-Type: text/plain; charset="utf-8" CVE-2019-11135 When TSX_CTRL bit of IA32_ARCH_CAPABILITIES MSR is set to 1, the CPU supports IA32_TSX_CTRL MSR which can be used to disable and/or mask TSX. Signed-off-by: Jiri Denemark Reviewed-by: J=C3=A1n Tomko --- src/cpu_map/x86_features.xml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/cpu_map/x86_features.xml b/src/cpu_map/x86_features.xml index d1180ed26d..b42b490160 100644 --- a/src/cpu_map/x86_features.xml +++ b/src/cpu_map/x86_features.xml @@ -502,6 +502,9 @@ + + + --=20 2.24.1 -- libvir-list mailing list libvir-list@redhat.com https://www.redhat.com/mailman/listinfo/libvir-list