From nobody Fri Apr 26 14:24:01 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of redhat.com designates 209.132.183.24 as permitted sender) client-ip=209.132.183.24; envelope-from=libvir-list-bounces@redhat.com; helo=mx3-phx2.redhat.com; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of redhat.com designates 209.132.183.24 as permitted sender) smtp.mailfrom=libvir-list-bounces@redhat.com; Return-Path: Received: from mx3-phx2.redhat.com (mx3-phx2.redhat.com [209.132.183.24]) by mx.zohomail.com with SMTPS id 148725394994619.47225040338867; Thu, 16 Feb 2017 06:05:49 -0800 (PST) Received: from lists01.pubmisc.prod.ext.phx2.redhat.com (lists01.pubmisc.prod.ext.phx2.redhat.com [10.5.19.33]) by mx3-phx2.redhat.com (8.13.8/8.13.8) with ESMTP id v1GE2RHt011621; Thu, 16 Feb 2017 09:02:27 -0500 Received: from int-mx14.intmail.prod.int.phx2.redhat.com (int-mx14.intmail.prod.int.phx2.redhat.com [10.5.11.27]) by lists01.pubmisc.prod.ext.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id v1GE2MrB002098 for ; Thu, 16 Feb 2017 09:02:22 -0500 Received: from virval.usersys.redhat.com (dhcp129-92.brq.redhat.com [10.34.129.92]) by int-mx14.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id v1GE2KX7009369 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO) for ; Thu, 16 Feb 2017 09:02:21 -0500 Received: by virval.usersys.redhat.com (Postfix, from userid 500) id 821DE103B14; Thu, 16 Feb 2017 15:02:20 +0100 (CET) From: Jiri Denemark To: libvir-list@redhat.com Date: Thu, 16 Feb 2017 15:02:18 +0100 Message-Id: <7362199883135b1a69ba2155e9a82c55ddc0f8b4.1487253597.git.jdenemar@redhat.com> In-Reply-To: References: In-Reply-To: References: Mail-Followup-To: libvir-list@redhat.com X-Scanned-By: MIMEDefang 2.68 on 10.5.11.27 X-loop: libvir-list@redhat.com Subject: [libvirt] [PATCH 1/2] cpu_x86: Disable TSX on broken models X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" All Intel Haswell processors (except Xeon E7 v3 with stepping >=3D 4) have TSX disabled by microcode update. As not all CPUs are guaranteed to be patched with microcode updates we need to explicitly disable TSX on affected CPUs to avoid its accidental usage. https://bugzilla.redhat.com/show_bug.cgi?id=3D1406791 Signed-off-by: Jiri Denemark --- src/cpu/cpu_x86.c | 72 ++++++++++++++++++= ++-- .../x86_64-cpuid-Core-i5-4670T-guest.xml | 2 +- .../x86_64-cpuid-Core-i5-4670T-host.xml | 2 +- .../x86_64-cpuid-Core-i5-4670T-json.xml | 2 +- 4 files changed, 70 insertions(+), 8 deletions(-) diff --git a/src/cpu/cpu_x86.c b/src/cpu/cpu_x86.c index b3bccd176..bcf50cb9e 100644 --- a/src/cpu/cpu_x86.c +++ b/src/cpu/cpu_x86.c @@ -547,6 +547,26 @@ x86MakeSignature(unsigned int family, } =20 =20 +static void +x86DataToSignatureFull(const virCPUx86Data *data, + unsigned int *family, + unsigned int *model, + unsigned int *stepping) +{ + virCPUx86CPUID leaf1 =3D { .eax_in =3D 0x1 }; + virCPUx86CPUID *cpuid; + + *family =3D *model =3D *stepping =3D 0; + + if (!(cpuid =3D x86DataCpuid(data, &leaf1))) + return; + + *family =3D ((cpuid->eax >> 20) & 0xff) + ((cpuid->eax >> 8) & 0xf); + *model =3D ((cpuid->eax >> 12) & 0xf0) + ((cpuid->eax >> 4) & 0xf); + *stepping =3D cpuid->eax & 0xf; +} + + /* Mask out irrelevant bits (R and Step) from processor signature. */ #define SIGNATURE_MASK 0x0fff3ff0 =20 @@ -1784,9 +1804,44 @@ x86DecodeUseCandidate(virCPUx86ModelPtr current, } =20 =20 +/** + * Drop broken TSX features. + */ +static void +x86DataFilterTSX(virCPUx86Data *data, + virCPUx86VendorPtr vendor, + virCPUx86MapPtr map) +{ + unsigned int family; + unsigned int model; + unsigned int stepping; + + if (!vendor || STRNEQ(vendor->name, "Intel")) + return; + + x86DataToSignatureFull(data, &family, &model, &stepping); + + if (family =3D=3D 6 && + ((model =3D=3D 63 && stepping < 4) || + model =3D=3D 60 || + model =3D=3D 69 || + model =3D=3D 70)) { + virCPUx86FeaturePtr feature; + + VIR_DEBUG("Dropping broken TSX"); + + if ((feature =3D x86FeatureFind(map, "hle"))) + x86DataSubtract(data, &feature->data); + + if ((feature =3D x86FeatureFind(map, "rtm"))) + x86DataSubtract(data, &feature->data); + } +} + + static int x86Decode(virCPUDefPtr cpu, - const virCPUx86Data *data, + const virCPUx86Data *cpuData, const char **models, unsigned int nmodels, const char *preferred, @@ -1798,6 +1853,7 @@ x86Decode(virCPUDefPtr cpu, virCPUDefPtr cpuCandidate; virCPUx86ModelPtr model =3D NULL; virCPUDefPtr cpuModel =3D NULL; + virCPUx86Data data =3D VIR_CPU_X86_DATA_INIT; virCPUx86Data copy =3D VIR_CPU_X86_DATA_INIT; virCPUx86Data features =3D VIR_CPU_X86_DATA_INIT; virCPUx86VendorPtr vendor; @@ -1808,11 +1864,16 @@ x86Decode(virCPUDefPtr cpu, virCheckFlags(VIR_CONNECT_BASELINE_CPU_EXPAND_FEATURES | VIR_CONNECT_BASELINE_CPU_MIGRATABLE, -1); =20 - if (!data || !(map =3D virCPUx86GetMap())) + if (!cpuData || x86DataCopy(&data, cpuData) < 0) return -1; =20 - vendor =3D x86DataToVendor(data, map); - signature =3D x86DataToSignature(data); + if (!(map =3D virCPUx86GetMap())) + goto cleanup; + + vendor =3D x86DataToVendor(&data, map); + signature =3D x86DataToSignature(&data); + + x86DataFilterTSX(&data, vendor, map); =20 /* Walk through the CPU models in reverse order to check newest * models first. @@ -1847,7 +1908,7 @@ x86Decode(virCPUDefPtr cpu, continue; } =20 - if (!(cpuCandidate =3D x86DataToCPU(data, candidate, map))) + if (!(cpuCandidate =3D x86DataToCPU(&data, candidate, map))) goto cleanup; cpuCandidate->type =3D cpu->type; =20 @@ -1912,6 +1973,7 @@ x86Decode(virCPUDefPtr cpu, =20 cleanup: virCPUDefFree(cpuModel); + virCPUx86DataClear(&data); virCPUx86DataClear(©); virCPUx86DataClear(&features); return ret; diff --git a/tests/cputestdata/x86_64-cpuid-Core-i5-4670T-guest.xml b/tests= /cputestdata/x86_64-cpuid-Core-i5-4670T-guest.xml index 9c9399562..70d13282b 100644 --- a/tests/cputestdata/x86_64-cpuid-Core-i5-4670T-guest.xml +++ b/tests/cputestdata/x86_64-cpuid-Core-i5-4670T-guest.xml @@ -1,6 +1,6 @@ x86_64 - Haswell + Haswell-noTSX Intel diff --git a/tests/cputestdata/x86_64-cpuid-Core-i5-4670T-host.xml b/tests/= cputestdata/x86_64-cpuid-Core-i5-4670T-host.xml index b9f95ad87..d1d0bc716 100644 --- a/tests/cputestdata/x86_64-cpuid-Core-i5-4670T-host.xml +++ b/tests/cputestdata/x86_64-cpuid-Core-i5-4670T-host.xml @@ -1,6 +1,6 @@ x86_64 - Haswell + Haswell-noTSX Intel diff --git a/tests/cputestdata/x86_64-cpuid-Core-i5-4670T-json.xml b/tests/= cputestdata/x86_64-cpuid-Core-i5-4670T-json.xml index cf23f59d7..8d3a0b618 100644 --- a/tests/cputestdata/x86_64-cpuid-Core-i5-4670T-json.xml +++ b/tests/cputestdata/x86_64-cpuid-Core-i5-4670T-json.xml @@ -1,6 +1,6 @@ x86_64 - Haswell + Haswell-noTSX Intel --=20 2.11.1 -- libvir-list mailing list libvir-list@redhat.com https://www.redhat.com/mailman/listinfo/libvir-list From nobody Fri Apr 26 14:24:01 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of redhat.com designates 209.132.183.25 as permitted sender) client-ip=209.132.183.25; envelope-from=libvir-list-bounces@redhat.com; helo=mx4-phx2.redhat.com; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of redhat.com designates 209.132.183.25 as permitted sender) smtp.mailfrom=libvir-list-bounces@redhat.com; Return-Path: Received: from mx4-phx2.redhat.com (mx4-phx2.redhat.com [209.132.183.25]) by mx.zohomail.com with SMTPS id 1487254035333956.4766967283713; Thu, 16 Feb 2017 06:07:15 -0800 (PST) Received: from lists01.pubmisc.prod.ext.phx2.redhat.com (lists01.pubmisc.prod.ext.phx2.redhat.com [10.5.19.33]) by mx4-phx2.redhat.com (8.13.8/8.13.8) with ESMTP id v1GE2SFr018853; Thu, 16 Feb 2017 09:02:29 -0500 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) by lists01.pubmisc.prod.ext.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id v1GE2M7N002097 for ; Thu, 16 Feb 2017 09:02:22 -0500 Received: from virval.usersys.redhat.com (dhcp129-92.brq.redhat.com [10.34.129.92]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id v1GE2Kgm023434 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO) for ; Thu, 16 Feb 2017 09:02:21 -0500 Received: by virval.usersys.redhat.com (Postfix, from userid 500) id 83C0D10506F; Thu, 16 Feb 2017 15:02:20 +0100 (CET) From: Jiri Denemark To: libvir-list@redhat.com Date: Thu, 16 Feb 2017 15:02:19 +0100 Message-Id: In-Reply-To: References: In-Reply-To: References: Mail-Followup-To: libvir-list@redhat.com X-Scanned-By: MIMEDefang 2.68 on 10.5.11.23 X-loop: libvir-list@redhat.com Subject: [libvirt] [PATCH 2/2] cputest: Add CPUID data for Haswell with TSX X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" All existing Haswell CPUID data were gathered from CPUs with broken TSX. Let's add new data for Haswell with correct TSX implementation. Signed-off-by: Jiri Denemark --- tests/cputest.c | 1 + .../x86_64-cpuid-Xeon-E7-8890-guest.xml | 32 +++++++++++++++++++ .../cputestdata/x86_64-cpuid-Xeon-E7-8890-host.xml | 32 +++++++++++++++++++ tests/cputestdata/x86_64-cpuid-Xeon-E7-8890.xml | 37 ++++++++++++++++++= ++++ 4 files changed, 102 insertions(+) create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E7-8890-guest.xml create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E7-8890-host.xml create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E7-8890.xml diff --git a/tests/cputest.c b/tests/cputest.c index b7dd95d84..685aca152 100644 --- a/tests/cputest.c +++ b/tests/cputest.c @@ -842,6 +842,7 @@ mymain(void) DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-E5-2630", true); DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-E5-2650", true); DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-E7-4820", true); + DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-E7-8890", false); DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-W3520", true); DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-X5460", false); =20 diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E7-8890-guest.xml b/tests/= cputestdata/x86_64-cpuid-Xeon-E7-8890-guest.xml new file mode 100644 index 000000000..c62e36a3a --- /dev/null +++ b/tests/cputestdata/x86_64-cpuid-Xeon-E7-8890-guest.xml @@ -0,0 +1,32 @@ + + x86_64 + Haswell + Intel + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E7-8890-host.xml b/tests/c= putestdata/x86_64-cpuid-Xeon-E7-8890-host.xml new file mode 100644 index 000000000..e90598ec6 --- /dev/null +++ b/tests/cputestdata/x86_64-cpuid-Xeon-E7-8890-host.xml @@ -0,0 +1,32 @@ + + x86_64 + Haswell + Intel + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E7-8890.xml b/tests/cputes= tdata/x86_64-cpuid-Xeon-E7-8890.xml new file mode 100644 index 000000000..ccdb79219 --- /dev/null +++ b/tests/cputestdata/x86_64-cpuid-Xeon-E7-8890.xml @@ -0,0 +1,37 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + --=20 2.11.1 -- libvir-list mailing list libvir-list@redhat.com https://www.redhat.com/mailman/listinfo/libvir-list