From nobody Fri May 17 13:54:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 170.10.129.124 as permitted sender) client-ip=170.10.129.124; envelope-from=libvir-list-bounces@redhat.com; helo=us-smtp-delivery-124.mimecast.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of redhat.com designates 170.10.129.124 as permitted sender) smtp.mailfrom=libvir-list-bounces@redhat.com; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1659529462; cv=none; d=zohomail.com; s=zohoarc; b=b5T5kLTJPz64UgEXjWApBXFpTW4QRInty8WENmlj3fVFo4kaeag/thqbxA+uKNzLDFNbQm3/2pUZUq+P2UFbwy7vAoQtTUcuBqJOZlpuzaRb+ZhYq/srdFWxK57a5BJq6sCMULMYQHnITa9m4MxXevCH+HnhuuE2TQv75Uj0yi0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1659529462; h=Content-Type:Content-Transfer-Encoding:Date:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:To; bh=uDBn1ujIUABCy6uU8botLAbTEg1jKktXZdPrdALJMnU=; b=MeDv6NZ22sGn7YKmusv+5K3AfM+CM0XeDHTQ33M2eYFsYyYDco8YS/dAYcSm84aUS2DU4ePfCSdx9d3We3ER+pjvtMWVySW9dtfGqOx1jdm2zvRNxjb/GKQvz3o8rvjri/tJIbW5g+n+F7lU3BAtCscYg/4t2kNQa5VXX1N6Wdc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of redhat.com designates 170.10.129.124 as permitted sender) smtp.mailfrom=libvir-list-bounces@redhat.com; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by mx.zohomail.com with SMTPS id 1659529462123452.91353380245937; Wed, 3 Aug 2022 05:24:22 -0700 (PDT) Received: from mimecast-mx02.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-31-Y2Ma8QhwPJ-9uK23C-cKwQ-1; Wed, 03 Aug 2022 08:24:18 -0400 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 6C3252801777; Wed, 3 Aug 2022 12:24:15 +0000 (UTC) Received: from mm-prod-listman-01.mail-001.prod.us-east-1.aws.redhat.com (unknown [10.30.29.100]) by smtp.corp.redhat.com (Postfix) with ESMTP id E4668403164; Wed, 3 Aug 2022 12:24:12 +0000 (UTC) Received: from mm-prod-listman-01.mail-001.prod.us-east-1.aws.redhat.com (localhost [IPv6:::1]) by mm-prod-listman-01.mail-001.prod.us-east-1.aws.redhat.com (Postfix) with ESMTP id 99FE51946A50; Wed, 3 Aug 2022 12:24:12 +0000 (UTC) Received: from smtp.corp.redhat.com (int-mx09.intmail.prod.int.rdu2.redhat.com [10.11.54.9]) by mm-prod-listman-01.mail-001.prod.us-east-1.aws.redhat.com (Postfix) with ESMTP id D064A1946A4E for ; Wed, 3 Aug 2022 12:24:10 +0000 (UTC) Received: by smtp.corp.redhat.com (Postfix) id B1B3B492CA2; Wed, 3 Aug 2022 12:24:10 +0000 (UTC) Received: from maggie.redhat.com (unknown [10.43.2.88]) by smtp.corp.redhat.com (Postfix) with ESMTP id 5D462492C3B for ; Wed, 3 Aug 2022 12:24:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1659529461; h=from:from:sender:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding:list-id:list-help: list-unsubscribe:list-subscribe:list-post; bh=uDBn1ujIUABCy6uU8botLAbTEg1jKktXZdPrdALJMnU=; b=HST2JrYS5/+A1eYq6iNR2eUTNVi4Mr2FaoAfh3shL13DoBfKW00bGUbwRKQe+OAN1COJ+8 GAqHT7VPshizn6jdIWVffRUSZJbcPKPEGqAko6vfAxRkHQqtsrVcVzetHLU6WmxvYwvdxW frERcJu9Mr75l4BTi7QjdtSMziKueXQ= X-MC-Unique: Y2Ma8QhwPJ-9uK23C-cKwQ-1 X-Original-To: libvir-list@listman.corp.redhat.com From: Michal Privoznik To: libvir-list@redhat.com Subject: [PATCH] qemu: Move CPU validation out of PostParse Date: Wed, 3 Aug 2022 14:24:08 +0200 Message-Id: MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.85 on 10.11.54.9 X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libvir-list-bounces@redhat.com Sender: "libvir-list" X-Scanned-By: MIMEDefang 2.85 on 10.11.54.10 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1659529462912100001 Content-Type: text/plain; charset="utf-8"; x-default="true" The qemuDomainDefCPUPostParse() does a bit more than filling in missing info. It also validates CPU cache configuration. Move that code into qemuValidateDomainDefCpu() where the code fits better. And since I need to fix indentation of existing code in qemuValidateDomainDefCpu(), I'm taking this opportunity and move error messages onto single line. Interestingly, this uncovers a bug we have in sc_prohibit_diagnostic_without_format syntax-check rule, because previously a virReportError() with a message spawned over three lines was not caught but not it is. But trying to understand that regex is a job for another time. Signed-off-by: Michal Privoznik Reviewed-by: Erik Skultety --- src/qemu/qemu_domain.c | 56 ----------------- src/qemu/qemu_validate.c | 129 +++++++++++++++++++++++++++------------ 2 files changed, 89 insertions(+), 96 deletions(-) diff --git a/src/qemu/qemu_domain.c b/src/qemu/qemu_domain.c index a53c25f36e..61a7297599 100644 --- a/src/qemu/qemu_domain.c +++ b/src/qemu/qemu_domain.c @@ -4373,62 +4373,6 @@ qemuDomainDefCPUPostParse(virDomainDef *def, if (!def->cpu) return 0; =20 - if (def->cpu->cache) { - virCPUCacheDef *cache =3D def->cpu->cache; - - if (!ARCH_IS_X86(def->os.arch)) { - virReportError(VIR_ERR_CONFIG_UNSUPPORTED, - _("CPU cache specification is not supported " - "for '%s' architecture"), - virArchToString(def->os.arch)); - return -1; - } - - switch (cache->mode) { - case VIR_CPU_CACHE_MODE_EMULATE: - if (cache->level !=3D 3) { - virReportError(VIR_ERR_CONFIG_UNSUPPORTED, - _("CPU cache mode '%s' can only be used wit= h " - "level=3D'3'"), - virCPUCacheModeTypeToString(cache->mode)); - return -1; - } - break; - - case VIR_CPU_CACHE_MODE_PASSTHROUGH: - if (def->cpu->mode !=3D VIR_CPU_MODE_HOST_PASSTHROUGH && - def->cpu->mode !=3D VIR_CPU_MODE_MAXIMUM) { - virReportError(VIR_ERR_CONFIG_UNSUPPORTED, - _("CPU cache mode '%s' can only be used wit= h " - "'%s' / '%s' CPUs"), - virCPUCacheModeTypeToString(cache->mode), - virCPUModeTypeToString(VIR_CPU_MODE_HOST_PA= SSTHROUGH), - virCPUModeTypeToString(VIR_CPU_MODE_MAXIMUM= )); - return -1; - } - - if (cache->level !=3D -1) { - virReportError(VIR_ERR_CONFIG_UNSUPPORTED, - _("unsupported CPU cache level for mode '%s= '"), - virCPUCacheModeTypeToString(cache->mode)); - return -1; - } - break; - - case VIR_CPU_CACHE_MODE_DISABLE: - if (cache->level !=3D -1) { - virReportError(VIR_ERR_CONFIG_UNSUPPORTED, - _("unsupported CPU cache level for mode '%s= '"), - virCPUCacheModeTypeToString(cache->mode)); - return -1; - } - break; - - case VIR_CPU_CACHE_MODE_LAST: - break; - } - } - for (i =3D 0; i < def->cpu->nfeatures; i++) { virCPUFeatureDef *feature =3D &def->cpu->features[i]; =20 diff --git a/src/qemu/qemu_validate.c b/src/qemu/qemu_validate.c index 48bd40db9f..7fa899e411 100644 --- a/src/qemu/qemu_validate.c +++ b/src/qemu/qemu_validate.c @@ -332,52 +332,101 @@ qemuValidateDomainDefCpu(virQEMUDriver *driver, if (!cpu) return 0; =20 - if (!cpu->model && cpu->mode =3D=3D VIR_CPU_MODE_CUSTOM) - return 0; - - switch ((virCPUMode) cpu->mode) { - case VIR_CPU_MODE_HOST_PASSTHROUGH: - if (def->os.arch =3D=3D VIR_ARCH_ARMV7L && - driver->hostarch =3D=3D VIR_ARCH_AARCH64) { - if (!virQEMUCapsGet(qemuCaps, QEMU_CAPS_CPU_AARCH64_OFF)) { + if (def->cpu->cache) { + virCPUCacheDef *cache =3D def->cpu->cache; + + if (!ARCH_IS_X86(def->os.arch)) { + virReportError(VIR_ERR_CONFIG_UNSUPPORTED, + _("CPU cache specification is not supported for= '%s' architecture"), + virArchToString(def->os.arch)); + return -1; + } + + switch (cache->mode) { + case VIR_CPU_CACHE_MODE_EMULATE: + if (cache->level !=3D 3) { virReportError(VIR_ERR_CONFIG_UNSUPPORTED, - _("QEMU binary does not support CPU " - "host-passthrough for armv7l on " - "aarch64 host")); + _("CPU cache mode '%s' can only be used wit= h level=3D'3'"), + virCPUCacheModeTypeToString(cache->mode)); return -1; } - } + break; =20 - if (cpu->migratable && - cpu->migratable !=3D VIR_TRISTATE_SWITCH_OFF && - !virQEMUCapsGet(qemuCaps, QEMU_CAPS_CPU_MIGRATABLE)) { - virReportError(VIR_ERR_CONFIG_UNSUPPORTED, "%s", - _("Migratable attribute for host-passthrough " - "CPU is not supported by this QEMU binary")); - return -1; - } - break; - - case VIR_CPU_MODE_HOST_MODEL: - /* qemu_command.c will error out if cpu->mode is HOST_MODEL for - * every arch but PPC64. However, we can't move this validation - * here because non-PPC64 archs will translate HOST_MODEL to - * something else during domain start, changing cpu->mode to - * CUSTOM. - */ - break; - - case VIR_CPU_MODE_MAXIMUM: - if (!virQEMUCapsGet(qemuCaps, QEMU_CAPS_CPU_MAX)) { - virReportError(VIR_ERR_CONFIG_UNSUPPORTED, "%s", - _("maximum CPU is not supported by QEMU binary"= )); - return -1; + case VIR_CPU_CACHE_MODE_PASSTHROUGH: + if (def->cpu->mode !=3D VIR_CPU_MODE_HOST_PASSTHROUGH && + def->cpu->mode !=3D VIR_CPU_MODE_MAXIMUM) { + virReportError(VIR_ERR_CONFIG_UNSUPPORTED, + _("CPU cache mode '%s' can only be used wit= h '%s' / '%s' CPUs"), + virCPUCacheModeTypeToString(cache->mode), + virCPUModeTypeToString(VIR_CPU_MODE_HOST_PA= SSTHROUGH), + virCPUModeTypeToString(VIR_CPU_MODE_MAXIMUM= )); + return -1; + } + + if (cache->level !=3D -1) { + virReportError(VIR_ERR_CONFIG_UNSUPPORTED, + _("unsupported CPU cache level for mode '%s= '"), + virCPUCacheModeTypeToString(cache->mode)); + return -1; + } + break; + + case VIR_CPU_CACHE_MODE_DISABLE: + if (cache->level !=3D -1) { + virReportError(VIR_ERR_CONFIG_UNSUPPORTED, + _("unsupported CPU cache level for mode '%s= '"), + virCPUCacheModeTypeToString(cache->mode)); + return -1; + } + break; + + case VIR_CPU_CACHE_MODE_LAST: + break; } - break; + } + + if (cpu->model || cpu->mode !=3D VIR_CPU_MODE_CUSTOM) { + switch ((virCPUMode) cpu->mode) { + case VIR_CPU_MODE_HOST_PASSTHROUGH: + if (def->os.arch =3D=3D VIR_ARCH_ARMV7L && + driver->hostarch =3D=3D VIR_ARCH_AARCH64) { + if (!virQEMUCapsGet(qemuCaps, QEMU_CAPS_CPU_AARCH64_OFF)) { + virReportError(VIR_ERR_CONFIG_UNSUPPORTED, "%s", + _("QEMU binary does not support CPU hos= t-passthrough for armv7l on aarch64 host")); + return -1; + } + } =20 - case VIR_CPU_MODE_CUSTOM: - case VIR_CPU_MODE_LAST: - break; + if (cpu->migratable && + cpu->migratable !=3D VIR_TRISTATE_SWITCH_OFF && + !virQEMUCapsGet(qemuCaps, QEMU_CAPS_CPU_MIGRATABLE)) { + virReportError(VIR_ERR_CONFIG_UNSUPPORTED, "%s", + _("Migratable attribute for host-passthroug= h CPU is not supported by this QEMU binary")); + return -1; + } + break; + + case VIR_CPU_MODE_HOST_MODEL: + /* qemu_command.c will error out if cpu->mode is HOST_MODEL for + * every arch but PPC64. However, we can't move this validation + * here because non-PPC64 archs will translate HOST_MODEL to + * something else during domain start, changing cpu->mode to + * CUSTOM. + */ + break; + + case VIR_CPU_MODE_MAXIMUM: + if (!virQEMUCapsGet(qemuCaps, QEMU_CAPS_CPU_MAX)) { + virReportError(VIR_ERR_CONFIG_UNSUPPORTED, "%s", + _("maximum CPU is not supported by QEMU bin= ary")); + return -1; + } + break; + + case VIR_CPU_MODE_CUSTOM: + case VIR_CPU_MODE_LAST: + break; + } } =20 return 0; --=20 2.35.1