The RISC-V vector register length is only relevant for RISC-V
guest CPUs. Reject <vlen> if configured for any other
architecture.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
---
 src/qemu/qemu_validate.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/src/qemu/qemu_validate.c b/src/qemu/qemu_validate.c
index 439d4b1916..86ace2a8f6 100644
--- a/src/qemu/qemu_validate.c
+++ b/src/qemu/qemu_validate.c
@@ -451,6 +451,15 @@ qemuValidateDomainDefCpu(virQEMUDriver *driver,
         }
     }
 
+    if (cpu->vlen) {
+        if (!ARCH_IS_RISCV(def->os.arch)) {
+            virReportError(VIR_ERR_CONFIG_UNSUPPORTED,
+                           _("CPU vector length specification is not supported for '%1$s' architecture"),
+                           virArchToString(def->os.arch));
+            return -1;
+        }
+    }
+
     if (cpu->model || cpu->mode != VIR_CPU_MODE_CUSTOM) {
         switch ((virCPUMode) cpu->mode) {
         case VIR_CPU_MODE_HOST_PASSTHROUGH:
-- 
2.53.0