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Tsirkin" , Igor Mammedov , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Thomas Huth Cc: qemu-devel@nongnu.org, devel@lists.libvirt.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Richard Henderson , Sergio Lopez , Gerd Hoffmann , Peter Maydell , Laurent Vivier , Jiaxun Yang , Yi Liu , Eduardo Habkost , Alistair Francis , Daniel Henrique Barboza , Marcelo Tosatti , Weiwei Li , Amit Shah , Xiaoyao Li , Yanan Wang , Helge Deller , Palmer Dabbelt , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Ani Sinha , Fabiano Rosas , Liu Zhiwei , =?UTF-8?q?Cl=C3=A9ment=20Mathieu--Drif?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Huacai Chen , Jason Wang , Mark Cave-Ayland , BALATON Zoltan , Peter Krempa , Jiri Denemark , Zhao Liu Subject: [PATCH v5 23/28] target/i386/cpu: Remove CPUX86State::full_cpuid_auto_level field Date: Wed, 3 Dec 2025 00:28:30 +0800 Message-Id: <20251202162835.3227894-24-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251202162835.3227894-1-zhao1.liu@intel.com> References: <20251202162835.3227894-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.7; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1764691800512019200 From: Philippe Mathieu-Daud=C3=A9 The CPUX86State::full_cpuid_auto_level boolean was only disabled for the pc-q35-2.7 and pc-i440fx-2.7 machines, which got removed. Being now always %true, we can remove it and simplify x86_cpu_expand_features(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Zhao Liu Signed-off-by: Zhao Liu --- Note, although libvirt still uses this property in its test cases, it was confirmed this property is not exposed to user directly [*]. [*]: https://lore.kernel.org/qemu-devel/aDmphSY1MSxu7L9R@orkuz.int.mamuti.n= et/ --- target/i386/cpu.c | 111 ++++++++++++++++++++++------------------------ target/i386/cpu.h | 3 -- 2 files changed, 54 insertions(+), 60 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 641777578637..72c69ba81c1b 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -9019,69 +9019,67 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **e= rrp) =20 /* CPUID[EAX=3D7,ECX=3D0].EBX always increased level automatically: */ x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); - if (cpu->full_cpuid_auto_level) { - x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); - x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); - x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); - x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); - x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); - x86_cpu_adjust_feat_level(cpu, FEAT_7_1_ECX); - x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX); - x86_cpu_adjust_feat_level(cpu, FEAT_7_2_EDX); - x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); - x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); - x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); - x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); - x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); - x86_cpu_adjust_feat_level(cpu, FEAT_SVM); - x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); - - /* Intel Processor Trace requires CPUID[0x14] */ - if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { - if (cpu->intel_pt_auto_level) { - x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); - } else if (cpu->env.cpuid_min_level < 0x14) { - mark_unavailable_features(cpu, FEAT_7_0_EBX, - CPUID_7_0_EBX_INTEL_PT, - "Intel PT need CPUID leaf 0x14, please set by \"-cpu .= ..,intel-pt=3Don,min-level=3D0x14\""); - } + x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); + x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); + x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); + x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); + x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); + x86_cpu_adjust_feat_level(cpu, FEAT_7_1_ECX); + x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX); + x86_cpu_adjust_feat_level(cpu, FEAT_7_2_EDX); + x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); + x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); + x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); + x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); + x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); + x86_cpu_adjust_feat_level(cpu, FEAT_SVM); + x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); + + /* Intel Processor Trace requires CPUID[0x14] */ + if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { + if (cpu->intel_pt_auto_level) { + x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); + } else if (cpu->env.cpuid_min_level < 0x14) { + mark_unavailable_features(cpu, FEAT_7_0_EBX, + CPUID_7_0_EBX_INTEL_PT, + "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,i= ntel-pt=3Don,min-level=3D0x14\""); } + } =20 - /* - * Intel CPU topology with multi-dies support requires CPUID[0x1F]. - * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should de= tect - * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unl= ess - * cpu->vendor_cpuid_only has been unset for compatibility with ol= der - * machine types. - */ - if (x86_has_cpuid_0x1f(cpu) && - (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { - x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); - } + /* + * Intel CPU topology with multi-dies support requires CPUID[0x1F]. + * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect + * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless + * cpu->vendor_cpuid_only has been unset for compatibility with older + * machine types. + */ + if (x86_has_cpuid_0x1f(cpu) && + (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { + x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); + } =20 - /* Advanced Vector Extensions 10 (AVX10) requires CPUID[0x24] */ - if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { - x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x24); - } + /* Advanced Vector Extensions 10 (AVX10) requires CPUID[0x24] */ + if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { + x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x24); + } =20 - /* SVM requires CPUID[0x8000000A] */ - if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { - x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); - } + /* SVM requires CPUID[0x8000000A] */ + if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { + x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); + } =20 - /* SEV requires CPUID[0x8000001F] */ - if (sev_enabled()) { - x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); - } + /* SEV requires CPUID[0x8000001F] */ + if (sev_enabled()) { + x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); + } =20 - if (env->features[FEAT_8000_0021_EAX]) { - x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021); - } + if (env->features[FEAT_8000_0021_EAX]) { + x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021); + } =20 - /* SGX requires CPUID[0x12] for EPC enumeration */ - if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { - x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); - } + /* SGX requires CPUID[0x12] for EPC enumeration */ + if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { + x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); } =20 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set = */ @@ -10010,7 +10008,6 @@ static const Property x86_cpu_properties[] =3D { DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), DEFINE_PROP_UINT8("avx10-version", X86CPU, env.avx10_version, 0), DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), - DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_leve= l, true), DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, tru= e), diff --git a/target/i386/cpu.h b/target/i386/cpu.h index cee1f692a1c3..8c3eb86fa0c7 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2292,9 +2292,6 @@ struct ArchCPU { /* Force to enable cpuid 0x1f */ bool force_cpuid_0x1f; =20 - /* Enable auto level-increase for all CPUID leaves */ - bool full_cpuid_auto_level; - /* * Compatibility bits for old machine types (PC machine v6.0 and older= ). * Only advertise CPUID leaves defined by the vendor. --=20 2.34.1