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Tsirkin" , Igor Mammedov , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Thomas Huth Cc: qemu-devel@nongnu.org, devel@lists.libvirt.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Richard Henderson , Sergio Lopez , Gerd Hoffmann , Peter Maydell , Laurent Vivier , Jiaxun Yang , Yi Liu , Eduardo Habkost , Alistair Francis , Daniel Henrique Barboza , Marcelo Tosatti , Weiwei Li , Amit Shah , Xiaoyao Li , Yanan Wang , Helge Deller , Palmer Dabbelt , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Ani Sinha , Fabiano Rosas , Liu Zhiwei , =?UTF-8?q?Cl=C3=A9ment=20Mathieu--Drif?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Huacai Chen , Jason Wang , Mark Cave-Ayland , BALATON Zoltan , Peter Krempa , Jiri Denemark , Zhao Liu Subject: [PATCH v5 12/28] hw/nvram/fw_cfg: Rename fw_cfg_init_mem_wide() -> fw_cfg_init_mem_dma() Date: Wed, 3 Dec 2025 00:28:19 +0800 Message-Id: <20251202162835.3227894-13-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251202162835.3227894-1-zhao1.liu@intel.com> References: <20251202162835.3227894-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.7; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1764691676632019200 From: Philippe Mathieu-Daud=C3=A9 "wide" in fw_cfg_init_mem_wide() means "DMA support". Rename for clarity. Suggested-by: Zhao Liu Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Xiaoyao Li Reviewed-by: Zhao Liu Reviewed-by: Igor Mammedov Signed-off-by: Zhao Liu --- Changes since v4: * Fix a missing case in hw/loongarch/fw_cfg.c. --- hw/arm/virt.c | 2 +- hw/loongarch/fw_cfg.c | 4 ++-- hw/nvram/fw_cfg.c | 6 +++--- hw/riscv/virt.c | 4 ++-- include/hw/nvram/fw_cfg.h | 6 +++--- 5 files changed, 11 insertions(+), 11 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 25fb2bab5680..23d88e2fd014 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1412,7 +1412,7 @@ static FWCfgState *create_fw_cfg(const VirtMachineSta= te *vms, AddressSpace *as) FWCfgState *fw_cfg; char *nodename; =20 - fw_cfg =3D fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); + fw_cfg =3D fw_cfg_init_mem_dma(base + 8, base, 8, base + 16, as); fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); =20 nodename =3D g_strdup_printf("/fw-cfg@%" PRIx64, base); diff --git a/hw/loongarch/fw_cfg.c b/hw/loongarch/fw_cfg.c index 493563669e5b..d2a79efbf767 100644 --- a/hw/loongarch/fw_cfg.c +++ b/hw/loongarch/fw_cfg.c @@ -23,8 +23,8 @@ FWCfgState *virt_fw_cfg_init(ram_addr_t ram_size, Machine= State *ms) int max_cpus =3D ms->smp.max_cpus; int smp_cpus =3D ms->smp.cpus; =20 - fw_cfg =3D fw_cfg_init_mem_wide(VIRT_FWCFG_BASE + 8, VIRT_FWCFG_BASE, = 8, - VIRT_FWCFG_BASE + 16, &address_space_mem= ory); + fw_cfg =3D fw_cfg_init_mem_dma(VIRT_FWCFG_BASE + 8, VIRT_FWCFG_BASE, 8, + VIRT_FWCFG_BASE + 16, &address_space_memo= ry); fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c index c65deeb7c382..3f0d337eb9c5 100644 --- a/hw/nvram/fw_cfg.c +++ b/hw/nvram/fw_cfg.c @@ -1088,9 +1088,9 @@ static FWCfgState *fw_cfg_init_mem_internal(hwaddr ct= l_addr, return s; } =20 -FWCfgState *fw_cfg_init_mem_wide(hwaddr ctl_addr, - hwaddr data_addr, uint32_t data_width, - hwaddr dma_addr, AddressSpace *dma_as) +FWCfgState *fw_cfg_init_mem_dma(hwaddr ctl_addr, + hwaddr data_addr, uint32_t data_width, + hwaddr dma_addr, AddressSpace *dma_as) { assert(dma_addr && dma_as); return fw_cfg_init_mem_internal(ctl_addr, data_addr, data_width, diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 17909206c7ef..bfbb28f5bd26 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1274,8 +1274,8 @@ static FWCfgState *create_fw_cfg(const MachineState *= ms, hwaddr base) { FWCfgState *fw_cfg; =20 - fw_cfg =3D fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, - &address_space_memory); + fw_cfg =3D fw_cfg_init_mem_dma(base + 8, base, 8, base + 16, + &address_space_memory); fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); =20 return fw_cfg; diff --git a/include/hw/nvram/fw_cfg.h b/include/hw/nvram/fw_cfg.h index d5161a794362..c4c49886754c 100644 --- a/include/hw/nvram/fw_cfg.h +++ b/include/hw/nvram/fw_cfg.h @@ -309,9 +309,9 @@ FWCfgState *fw_cfg_init_io_dma(uint32_t iobase, uint32_= t dma_iobase, AddressSpace *dma_as); FWCfgState *fw_cfg_init_mem_nodma(hwaddr ctl_addr, hwaddr data_addr, unsigned data_width); -FWCfgState *fw_cfg_init_mem_wide(hwaddr ctl_addr, - hwaddr data_addr, uint32_t data_width, - hwaddr dma_addr, AddressSpace *dma_as); +FWCfgState *fw_cfg_init_mem_dma(hwaddr ctl_addr, + hwaddr data_addr, uint32_t data_width, + hwaddr dma_addr, AddressSpace *dma_as); =20 FWCfgState *fw_cfg_find(void); bool fw_cfg_dma_enabled(void *opaque); --=20 2.34.1