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b=eZ+C683dldYH/QhFY8TZCyy38wfRuz1aCRrm4OcmhBtoMdOiDBNYTu1F3jxemr8Rp hX6IDSkXYf2qPDUrB+9XwVeSNKok6+c1UycDK24I2mMx+0yZgzuZomKYYotxp18jxL tz9/qgIPBW9PzOrsVZf6o/DchwQhJcqDlE51S415wBHlUZKnAx/+OflC0bFFTpNGir MKVh4m1XZiLVacgtj6j7dVpBs6JgnzpA4lAZUC8mKDMF6wU9WtmsdEeUgfEexIAc06 GJkxj7J0mvLFO2kEUa1VKg+IcW+oMNj5eY+V2FeEH9X06cQ+8YiSAEL9SLsO0kCFRp A0c6PrVs3Clx5313/gHpV7N5+ZbcxHUYU9Jbcbw7pcRZLvPTbHmzcfYM2izdBR7733 jXjjDFbaAESj3krSEc0nBzqX4S3YVwu3QEGydzPAkoS/QI158n/o9fbGg0vbL8KGDE 7kIb1ciStqlWFbq2LipK4gkijBL8Wp+OfNbmNjRoDs2sGOMTt8FIWEQ1YXbtzlpDri waw09zoaGtMavRogloOpQvk3SQpjkVAYdT6zCRgx7S2t4cOjrmq820VNt7Vb8UG46e 8PSx77RAmeVcx2dLRISROcVMlVCyCkZaGP4bAsog2+UJbuj1MHE8sGpDYXDm6SX4iL evms07oZGJTB8llJr3bLpHG4= To: devel@lists.libvirt.org Subject: [PATCH 1/3] cpu_map: fix sync script to extract correctly vmx-* features Date: Mon, 24 Nov 2025 14:40:29 +0100 Message-ID: <20251124134031.58469-2-hector.cao@canonical.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20251124134031.58469-1-hector.cao@canonical.com> References: <20251124134031.58469-1-hector.cao@canonical.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-ID-Hash: OF2ARWH7JZCD27XPCGRKQMOBSFBAD5ZM X-Message-ID-Hash: OF2ARWH7JZCD27XPCGRKQMOBSFBAD5ZM X-MailFrom: hector.cao@canonical.com X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; loop; banned-address; header-match-devel.lists.libvirt.org-0; emergency; member-moderation; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header X-Mailman-Version: 3.3.10 Precedence: list List-Id: Development discussions about the libvirt library & tools Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: From: Hector Cao via Devel Reply-To: Hector Cao X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1763991938377019200 Content-Type: text/plain; charset="utf-8" The src/cpu_map/x86_features.xml file contains the definition of all x86 CPU features, these definitions specify how we can decode the feature support fom the CPUID or MSR values. The helper script sync_qemu_features_i386.py builds the x86_features.xml file from QEMU source code to be in sync with supported features in QEMU. This helper script parses QEMU target/i386/cpu.c file looking for CPU feature definitions and convert them into x86_features.xml contents. This is the resulting definition for the vmx-intr-exit feature encoded in the MSR 0x48d. EAX holds the 32 lower bits of the MSRE 64-bits value and should not be used to detect the VMX-* features. Indeed, VMX-* bit position should be parsed from QEMU source code in the 32 higher bits of the corresponding MSR value. This commit fixes this issue by using the 32 higher bits (EDX) to represent VMX-* features. --- src/cpu_map/sync_qemu_features_i386.py | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/src/cpu_map/sync_qemu_features_i386.py b/src/cpu_map/sync_qemu= _features_i386.py index b658b864f2..ed65d9966a 100755 --- a/src/cpu_map/sync_qemu_features_i386.py +++ b/src/cpu_map/sync_qemu_features_i386.py @@ -1,6 +1,7 @@ #!/usr/bin/env python3 =20 import argparse +import enum import os import re =20 @@ -201,6 +202,19 @@ def add_feature_cpuid(eax, ecx, reg, bit, name): =20 _FEATURES["cpuid"][eax][ecx][reg][bit] =3D name =20 +class VmxMsr(enum.Enum): + MSR_IA32_VMX_PROCBASED_CTLS2 =3D 0x0000048b + MSR_IA32_VMX_TRUE_PINBASED_CTLS =3D 0x0000048d + MSR_IA32_VMX_TRUE_PROCBASED_CTLS =3D 0x0000048e + MSR_IA32_VMX_TRUE_ENTRY_CTLS =3D 0x00000490 + MSR_IA32_VMX_TRUE_EXIT_CTLS =3D 0x0000048f + +def is_vmx_msr(msr): + try: + VmxMsr(msr) + return True + except ValueError: + return False =20 # add new msr feature bit def add_feature_msr(msr, bit, name): @@ -213,6 +227,11 @@ def add_feature_msr(msr, bit, name): if msr not in _FEATURES["msr"]: _FEATURES["msr"][msr] =3D dict() =20 + # VMX-* features are specified in the 32 higher bits + # of the MSR value + if is_vmx_msr(msr): + bit +=3D 32 + _FEATURES["msr"][msr][bit] =3D name =20 =20 --=20 2.45.2