From nobody Sun Oct 5 01:50:07 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.libvirt.org designates 8.43.85.245 as permitted sender) client-ip=8.43.85.245; envelope-from=devel-bounces@lists.libvirt.org; helo=lists.libvirt.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of lists.libvirt.org designates 8.43.85.245 as permitted sender) smtp.mailfrom=devel-bounces@lists.libvirt.org; arc=fail (Bad Signature); dmarc=pass(p=reject dis=none) header.from=lists.libvirt.org Return-Path: Received: from lists.libvirt.org (lists.libvirt.org [8.43.85.245]) by mx.zohomail.com with SMTPS id 1759364863987560.2830172150669; Wed, 1 Oct 2025 17:27:43 -0700 (PDT) Received: by lists.libvirt.org (Postfix, from userid 993) id DC657440CB; Wed, 1 Oct 2025 20:27:42 -0400 (EDT) Received: from [172.19.199.14] (lists.libvirt.org [8.43.85.245]) by lists.libvirt.org (Postfix) with ESMTP id 262B0441FA; Wed, 1 Oct 2025 20:25:30 -0400 (EDT) Received: by lists.libvirt.org (Postfix, from userid 993) id 1861641A52; Wed, 1 Oct 2025 20:24:06 -0400 (EDT) Received: from CY7PR03CU001.outbound.protection.outlook.com (mail-westcentralusazon11010008.outbound.protection.outlook.com [40.93.198.8]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (3072 bits) server-digest SHA256) (No client certificate requested) by lists.libvirt.org (Postfix) with ESMTPS id B41AD41B06 for ; Wed, 1 Oct 2025 20:24:04 -0400 (EDT) Received: from PH7PR12MB6834.namprd12.prod.outlook.com (2603:10b6:510:1b4::18) by DM4PR12MB6232.namprd12.prod.outlook.com (2603:10b6:8:a5::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9160.17; Thu, 2 Oct 2025 00:24:00 +0000 Received: from PH7PR12MB6834.namprd12.prod.outlook.com ([fe80::f432:162b:b94e:d2cb]) by PH7PR12MB6834.namprd12.prod.outlook.com ([fe80::f432:162b:b94e:d2cb%6]) with mapi id 15.20.9160.015; Thu, 2 Oct 2025 00:24:00 +0000 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on lists.libvirt.org X-Spam-Level: X-Spam-Status: No, score=-3.1 required=5.0 tests=ARC_SIGNED,ARC_VALID, DKIM_INVALID,DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED,SPF_PASS autolearn=unavailable autolearn_force=no version=4.0.1 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=oM0DYja63/jwcG8c3ELgeXQSq2+ovy8KpkNSYrfXPbXEzTqtzMeP3A4TP5LixiOU2RHhhMHzd6epbrEz9FbIoFRu494rchgW0BvBfmFL5aam62CzvtiuqBK122zA/CsNweobuz3aGGkHumGMpWHE3T4wimMsYrMDgBAg4inSqd3je6bToopKnGH4V1zEaE4Suz/Rn/sv11/sp3JA6B+X5S0hZkic5xfbx9wmuJJIJ7QjsQTrcGnEzhsBd0r6zl6xnIWepxSeeHKqO+sEy2C1GYpbO7DsNfO6AZd86HZchRd0440oEVmashwmGMpa1AWzkXgS6P69rUJW7zWfHa+iNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=pcH/sLMzFkc6DMRq8Z90U08Oy1Jg/IV8RpAU8U7MzEI=; b=lH7SY6DX2V5Qyqja3lzc1xfC+zzJ4SWJJg26tcc6FJCXB+AWBzVCeyvZi/uLbTHmvmgiQuM4lnGIMkERpNK1FLBy/Ar1OYpfnN/WkbpFttVq1aDS0edSijeo0190v8rpy+P79stS01sOzwJUF8aJ2HTVyIQU8h5hTwV1MkO04grzOBGuSg9VvbzI7Ge/CIZgchRBglUhm3qRo0dcIv3RQPiXntGsJa34EehfHyiV262COmbX8W1r2f9ul9sWUyesT+AEkn4aipE3LVNqHgjhCr9mfVHS3ES1DyBCg80eWOr12ysvoZFZiUO2q3IYZKpEEnkciXzhwwyTQeOBd11ZIw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=pcH/sLMzFkc6DMRq8Z90U08Oy1Jg/IV8RpAU8U7MzEI=; b=dQ6FaUqTbOUPevk828j5HB4CxNeXQX0dgoj2rrYMOLkKiQP/cTLEcWwru1TuxEShgxKZWa+/ZeyTw5QzBbtyf0lD0q5e9SOJTanHxHnFh94lE3PtZsXZhZP3fZ4KZ4tia7wSEdhlQSUqSVKm0iSeb63p7AC5dbBj/M0JU2vIbL/hBKgg5GjLymgNgIE8B2sFcPS4/+cV/BeR++DGHhdyVrUw7/mMKzyEhx1m9eATEfHUukDbVWo+V5PhZwYbFhJUEFcX4iYJPSlgxYKYzdEafWW8jW3kz9DcVCj0Y9MiaOfw46OBZrK9G2KS4WhsQnWnZFjldnhsswipU9vtU6CXYg== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; To: devel@lists.libvirt.org Subject: [PATCH v2 1/3] qemu: add IOMMU model smmuv3Dev Date: Wed, 1 Oct 2025 17:23:46 -0700 Message-ID: <20251002002348.1536936-2-nathanc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251002002348.1536936-1-nathanc@nvidia.com> References: <20251002002348.1536936-1-nathanc@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SJ0PR05CA0037.namprd05.prod.outlook.com (2603:10b6:a03:33f::12) To PH7PR12MB6834.namprd12.prod.outlook.com (2603:10b6:510:1b4::18) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH7PR12MB6834:EE_|DM4PR12MB6232:EE_ X-MS-Office365-Filtering-Correlation-Id: e64e3c4a-04b3-4d06-fe24-08de0149fbea X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?0fF0lLDLqXFCeSWgLSI64zDlPz+gsE4GaqSgzVJ0FemWHzI75AqBdsOQc0vA?= =?us-ascii?Q?X1hLCP/Mu+CnXS4ZWTQSZlSePIfIrWDm2nXcf9GmHOquITDu4R/6NHB77TAI?= =?us-ascii?Q?Ebhor2bQ20pjFKSVi3ki5HaOP0gBUrcj3u18hX+jmw9q6IEGrzQ1/yXZjBt0?= =?us-ascii?Q?C0cHoYyFj5F9cBuyV38ddeaP/pt22yv523bf5p0SV30y8KpTMua03rwqihaD?= =?us-ascii?Q?PQJ7aNtMwJlmOjWSIVSoVg9Y8H7DKEU/11ybi4Yf0t0WsaV3Em4N0Z2ti8L3?= =?us-ascii?Q?Y1zWn+QMZEJ6bQvqmaCFINTaPb4LqK8GmenpVSCiWsXNLdiNbHTnZPbtaeHC?= =?us-ascii?Q?dnq7arO+aHtc/B7NFKCrSRAL4AOuIHYe3FDoiBnDpXk14HNuEBwnNiW0J/Cn?= =?us-ascii?Q?EUBe4thXa1R5VPynSxjtOEG/lDKnLZF6BA7MeqWU6VctbAQhy9R6vSJHwq2E?= =?us-ascii?Q?L3UMpBL0ixE68n1lpv/gw/ZVa16u9BtejsLVKVX4MoCwKl+hOvt09VJvdfW5?= =?us-ascii?Q?8y1LZA0NLCCpxwuPPrUDJiZl+O7wDOKOxNrVtS+RCcQyGcB3A4v2UVGwPNAC?= =?us-ascii?Q?4yY3pW3CEzUDRW0+bwt1rQda6lwr7IYuNXbpW8VSNwOXzh5+swUWCFbvu/tQ?= =?us-ascii?Q?8q8lplcIb9CirGp4kFoi/Anm4r2V9eZYgJiA925S2vBW53X5vHgAF65UguJO?= =?us-ascii?Q?N1AA8XClvVmGbETE5xUaFXKrrzHIEf6RMYvzEg9DEtodEb3UrjARE4dqN4VU?= =?us-ascii?Q?YsuUxkOqK6ezlR2PkaxQ6HdawVrnMzFmoj4Fy4p6eLWcbYXyYur9rXhyJ+4J?= =?us-ascii?Q?x7Vv19B2q/pZ/y7AXyC73yWSgZJH2+aMgdQsynPSGWRW+h44M01jjdIpkMqQ?= =?us-ascii?Q?G3ctmCZfuRtGd2hJ/oaLzlnk2VS1Dn3BrotNR0R4uDLZHdqPLRPFQ8TJa3xC?= =?us-ascii?Q?U/1ZmQO0ath9q4j9SXWZmn5DjERbhHm9UJz7U0jVSe8pdKydXLo8i/TtaEWW?= =?us-ascii?Q?QW5Dokj6Fmqr5cndL/KJZ6GOZBhSmyGreud6NdRWvjlLhDH8bhBSLECJOQJZ?= =?us-ascii?Q?3n3YTPhFQGVMMEZCJJztCSKExdG1aKfo/kES/uUKUfnNnif165W4JjIQvJKj?= =?us-ascii?Q?vHNFxoz0Ls01pYB9FvU8L7dCODe6i/WuUZYiqX3JzDD42556ml1hxJgmX2Nk?= =?us-ascii?Q?CiR9v5Y4hcL3ZfgVlxh7vjd7d8LXcAlhtUoGHbicYcjqIa2j2d3vHR85ddgb?= =?us-ascii?Q?HYFzLLFRji8+UZDYWzGN4CA5OiyQruE45b6+BrKpErqrsbnvuTgV3vGUbOTB?= =?us-ascii?Q?q7cNE5q832zpL5YRr5UpyMREx/66pYRRc0PsumgWQWnFEVfKPX7aez+82Ilh?= =?us-ascii?Q?GBuQs0bE4M/jzlUKvg30uQvxMIFjPDdjFF/EUEMI+TIQEFzxl8zxU9uLMTN3?= =?us-ascii?Q?GacELFJavbn4S4lBypOP2n5jYHRHGvnI?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PH7PR12MB6834.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(366016)(376014);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?I8r5AgZgLmL2fG6r0U1IwaY7kERji5a9jymB1TrHHJOyv2pjfft55pIl8LiM?= =?us-ascii?Q?rHievLabrgjIcFVyL/ulMJjc8RRyi/F9WA4MfzsopdECXkaok7kOSvHS0EFe?= =?us-ascii?Q?23kJkJdhz5wLLdWwrWFWBYs4BHmxvYyzjVktmMv38zIYH1sRTW8SDKGtQlWv?= =?us-ascii?Q?bykInMhMc+fOCCuTm7OFC4ReAxgz0pruX0o/wa1kTitu+ELAdLW4iaUCYtpy?= =?us-ascii?Q?TYIRgeV1tB5em1LiDBQB1bW4ZsE8md55tYN2C/U1eypGygJZ6LO15v/97zPm?= =?us-ascii?Q?7omLuzSCwIZpR16luW8H30AcMrFCdMi0xNaMxeVwl7EBHFx7Yrze/lOaZCVR?= =?us-ascii?Q?EVtjMoLZXKOmZAxb2dmVTZ1Q4LX6e/v9iP9QIbfiPavr2239DB5gtkOQcKZj?= =?us-ascii?Q?t0Be69t5UbCUyVqWQX98hBf0wWKPojejhDRzX02VNKKFrSQg2LshtljBtwJ6?= =?us-ascii?Q?FDspPloVdGpqtAKtZSIdTvmsZd0ChjJETdx5CDtOd27JhDdAU5XNPh3SdoVR?= =?us-ascii?Q?B2rGV2d0ZK2+pdAjSZdFizdvzVrvrpJ1S3su5ZsJOS++ZrHGiuGVLUAMZtut?= =?us-ascii?Q?M2SzDx5I9GQm/L0cf5L6SsZALIDlB7u/aOybTJAVVVlTygS/paK3RBUW3EKs?= =?us-ascii?Q?e0aGMehrvMYAAuBxeYstxkTTi5Rjf6l956jQtvLvsCEDJIFfPgimU90AprUR?= =?us-ascii?Q?BObk57lzJ69sKf0u6QJZQg2J/++dGBazeerH4lEi9byqhWel5Z+KriBly+Ho?= =?us-ascii?Q?UFPXKM4avdTZwHvjiAotTY6Z4CSBDp0LOHFDO0WLLmzr1ESPHAwWEzYW6XDA?= =?us-ascii?Q?pfj8hiWwrffGEebsStZ0khssCUBR8sj5w3t4fWYooR5eSCTNcNfIaY7kMgr7?= =?us-ascii?Q?OqLMne53d+A3tN48LruPc+hYNeYx67Tbes2oZ9a0Qwufz6erAcVGTptjukoF?= =?us-ascii?Q?qCE8SlpNRIIPvwQaHT4L+yweNKVO4GlHEZsoPB9X9OAwiIiZv3XWmR54eh4f?= =?us-ascii?Q?byYpiCeOLSsiVpGuD3sjLOVmX4eHFUGYEJH3dkmc3V4jqIvDqeNP1YNUGcFh?= =?us-ascii?Q?Nl2F7HTOkN0r7zGPK6bQBnYKEGbxG/j31c4k8ujmjEMcikYRLhRQXOaPlekv?= =?us-ascii?Q?Vs/R1jJpcbfnQfEUzMF56LGEsxuc3oscr+9OuphYyDBOX8Tsv8gqEabK+qov?= =?us-ascii?Q?0H0ACphrNs0c5JuMN1hRVMDY4ltClxPeqla6FBBD+iS+AJqZDRsQVtV/kEbZ?= =?us-ascii?Q?pjK13ihLWudeM7+QUKrPKnNJc4223a+OaslHFsLgb/r0B67m9OaMNy9QKVOz?= =?us-ascii?Q?vKhh/52s7P0MrFuFh4kddbSsdUrPMwFV1B8onviWlzyU01hKLjEUR7TXejsZ?= =?us-ascii?Q?qP4Qrwc8Y0Lz5sOYufyJ+v6j324aJupM9/ZqdPgylb13covJChv6aWJlEJQi?= =?us-ascii?Q?GV96Dj/STb0QgSWaY4OLTpw3UvB+acLTp3O9t0B5c5O7v7IX0rrnitXgHKHd?= =?us-ascii?Q?Y5mBzT9NJxP3i86OOFGAZNQTh+94eti8VXWfoF5Q8Xk93tBi4GD1wxMos4t2?= =?us-ascii?Q?FIe7o9i53ubJTDhVmoWi6qTOFVNLEJLDGUFQVB5U?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: e64e3c4a-04b3-4d06-fe24-08de0149fbea X-MS-Exchange-CrossTenant-AuthSource: PH7PR12MB6834.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Oct 2025 00:24:00.5444 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: phb9bqefYakOKkDkinN2yAU/hagVYBhvAL0KnVYygUxw2ic+IRWdxofLY6ko2ALmeeSJLChNJ/igMkaDqpcZtw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6232 Message-ID-Hash: TBWNV62QNRSCYZO7ZAFI25YC3PBOVRNJ X-Message-ID-Hash: TBWNV62QNRSCYZO7ZAFI25YC3PBOVRNJ X-MailFrom: nathanc@nvidia.com X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; loop; banned-address; header-match-devel.lists.libvirt.org-0; emergency; member-moderation; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header CC: shameerali.kolothum.thodi@huawei.com, nicolinc@nvidia.com, nathanc@nvidia.com, mochs@nvidia.com X-Mailman-Version: 3.3.10 Precedence: list List-Id: Development discussions about the libvirt library & tools Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: From: Nathan Chen via Devel Reply-To: Nathan Chen X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1759364865986116600 Content-Type: text/plain; charset="utf-8" Introduce support for "smmuv3Dev" IOMMU model and its "parentIdx" driver attribute. The "parentIdx" attribute indicates the index of the controller that a smmuv3Dev IOMMU device is attached to. Signed-off-by: Nathan Chen --- docs/formatdomain.rst | 9 +++- src/conf/domain_conf.c | 17 ++++++++ src/conf/domain_conf.h | 2 + src/conf/domain_validate.c | 26 +++++++++-- src/conf/schemas/domaincommon.rng | 6 +++ src/qemu/qemu_command.c | 72 +++++++++++++++++++++++++++++-- src/qemu/qemu_domain_address.c | 2 + src/qemu/qemu_validate.c | 16 +++++++ 8 files changed, 141 insertions(+), 9 deletions(-) diff --git a/docs/formatdomain.rst b/docs/formatdomain.rst index f50dce477f..6a62291600 100644 --- a/docs/formatdomain.rst +++ b/docs/formatdomain.rst @@ -9161,8 +9161,9 @@ Example: ``model`` Supported values are ``intel`` (for Q35 guests) ``smmuv3`` (:since:`since 5.5.0`, for ARM virt guests), ``virtio`` - (:since:`since 8.3.0`, for Q35 and ARM virt guests) and - ``amd`` (:since:`since 11.5.0`). + (:since:`since 8.3.0`, for Q35 and ARM virt guests), + ``amd`` (:since:`since 11.5.0`), and ``smmuv3Dev`` (for + ARM virt guests). =20 ``driver`` The ``driver`` subelement can be used to configure additional options, = some @@ -9212,6 +9213,10 @@ Example: Enable x2APIC mode. Useful for higher number of guest CPUs. :since:`Since 11.5.0` (QEMU/KVM and ``amd`` model only) =20 + ``parentIdx`` + The ``parentIdx`` attribute notes the index of the controller that an + IOMMU device is attached to. (QEMU/KVM and ``smmuv3Dev`` model only) + The ``virtio`` IOMMU devices can further have ``address`` element as descr= ibed in `Device addresses`_ (address has to by type of ``pci``). =20 diff --git a/src/conf/domain_conf.c b/src/conf/domain_conf.c index 281846dfbe..6d1adb831d 100644 --- a/src/conf/domain_conf.c +++ b/src/conf/domain_conf.c @@ -1353,6 +1353,7 @@ VIR_ENUM_IMPL(virDomainIOMMUModel, "smmuv3", "virtio", "amd", + "smmuv3Dev", ); =20 VIR_ENUM_IMPL(virDomainVsockModel, @@ -2813,6 +2814,8 @@ virDomainIOMMUDefNew(void) =20 iommu =3D g_new0(virDomainIOMMUDef, 1); =20 + iommu->parent_idx =3D -1; + return g_steal_pointer(&iommu); } =20 @@ -14439,6 +14442,10 @@ virDomainIOMMUDefParseXML(virDomainXMLOption *xmlo= pt, if (virXMLPropTristateSwitch(driver, "passthrough", VIR_XML_PROP_N= ONE, &iommu->pt) < 0) return NULL; + + if (virXMLPropInt(driver, "parentIdx", 10, VIR_XML_PROP_NONE, + &iommu->parent_idx, -1) < 0) + return NULL; } =20 if (virDomainDeviceInfoParseXML(xmlopt, node, ctxt, @@ -22092,6 +22099,12 @@ virDomainIOMMUDefCheckABIStability(virDomainIOMMUD= ef *src, dst->aw_bits, src->aw_bits); return false; } + if (src->parent_idx !=3D dst->parent_idx) { + virReportError(VIR_ERR_CONFIG_UNSUPPORTED, + _("Target domain IOMMU device parent_idx value '%1$= d' does not match source '%2$d'"), + dst->parent_idx, src->parent_idx); + return false; + } if (src->dma_translation !=3D dst->dma_translation) { virReportError(VIR_ERR_CONFIG_UNSUPPORTED, _("Target domain IOMMU device dma translation '%1$s= ' does not match source '%2$s'"), @@ -28409,6 +28422,10 @@ virDomainIOMMUDefFormat(virBuffer *buf, virBufferAsprintf(&driverAttrBuf, " xtsup=3D'%s'", virTristateSwitchTypeToString(iommu->xtsup)); } + if (iommu->parent_idx >=3D 0) { + virBufferAsprintf(&driverAttrBuf, " parentIdx=3D'%d'", + iommu->parent_idx); + } =20 virXMLFormatElement(&childBuf, "driver", &driverAttrBuf, NULL); =20 diff --git a/src/conf/domain_conf.h b/src/conf/domain_conf.h index 39807b5fe3..1d0c94a00a 100644 --- a/src/conf/domain_conf.h +++ b/src/conf/domain_conf.h @@ -3039,6 +3039,7 @@ typedef enum { VIR_DOMAIN_IOMMU_MODEL_SMMUV3, VIR_DOMAIN_IOMMU_MODEL_VIRTIO, VIR_DOMAIN_IOMMU_MODEL_AMD, + VIR_DOMAIN_IOMMU_MODEL_SMMUV3_DEV, =20 VIR_DOMAIN_IOMMU_MODEL_LAST } virDomainIOMMUModel; @@ -3050,6 +3051,7 @@ struct _virDomainIOMMUDef { virTristateSwitch eim; virTristateSwitch iotlb; unsigned int aw_bits; + int parent_idx; virDomainDeviceInfo info; virTristateSwitch dma_translation; virTristateSwitch xtsup; diff --git a/src/conf/domain_validate.c b/src/conf/domain_validate.c index 93a2bc9b01..8a599fdbc6 100644 --- a/src/conf/domain_validate.c +++ b/src/conf/domain_validate.c @@ -3108,7 +3108,8 @@ virDomainIOMMUDefValidate(const virDomainIOMMUDef *io= mmu) iommu->eim !=3D VIR_TRISTATE_SWITCH_ABSENT || iommu->iotlb !=3D VIR_TRISTATE_SWITCH_ABSENT || iommu->aw_bits !=3D 0 || - iommu->dma_translation !=3D VIR_TRISTATE_SWITCH_ABSENT) { + iommu->dma_translation !=3D VIR_TRISTATE_SWITCH_ABSENT || + iommu->parent_idx !=3D -1) { virReportError(VIR_ERR_XML_ERROR, _("iommu model '%1$s' doesn't support additiona= l attributes"), virDomainIOMMUModelTypeToString(iommu->model)); @@ -3120,7 +3121,8 @@ virDomainIOMMUDefValidate(const virDomainIOMMUDef *io= mmu) if (iommu->caching_mode !=3D VIR_TRISTATE_SWITCH_ABSENT || iommu->eim !=3D VIR_TRISTATE_SWITCH_ABSENT || iommu->aw_bits !=3D 0 || - iommu->dma_translation !=3D VIR_TRISTATE_SWITCH_ABSENT) { + iommu->dma_translation !=3D VIR_TRISTATE_SWITCH_ABSENT || + iommu->parent_idx !=3D -1) { virReportError(VIR_ERR_XML_ERROR, _("iommu model '%1$s' doesn't support some addi= tional attributes"), virDomainIOMMUModelTypeToString(iommu->model)); @@ -3130,7 +3132,24 @@ virDomainIOMMUDefValidate(const virDomainIOMMUDef *i= ommu) =20 case VIR_DOMAIN_IOMMU_MODEL_INTEL: if (iommu->pt !=3D VIR_TRISTATE_SWITCH_ABSENT || - iommu->xtsup !=3D VIR_TRISTATE_SWITCH_ABSENT) { + iommu->xtsup !=3D VIR_TRISTATE_SWITCH_ABSENT || + iommu->parent_idx !=3D -1) { + virReportError(VIR_ERR_XML_ERROR, + _("iommu model '%1$s' doesn't support some addi= tional attributes"), + virDomainIOMMUModelTypeToString(iommu->model)); + return -1; + } + break; + + case VIR_DOMAIN_IOMMU_MODEL_SMMUV3_DEV: + if (iommu->intremap !=3D VIR_TRISTATE_SWITCH_ABSENT || + iommu->caching_mode !=3D VIR_TRISTATE_SWITCH_ABSENT || + iommu->eim !=3D VIR_TRISTATE_SWITCH_ABSENT || + iommu->iotlb !=3D VIR_TRISTATE_SWITCH_ABSENT || + iommu->aw_bits !=3D 0 || + iommu->dma_translation !=3D VIR_TRISTATE_SWITCH_ABSENT || + iommu->xtsup !=3D VIR_TRISTATE_SWITCH_ABSENT || + iommu->pt !=3D VIR_TRISTATE_SWITCH_ABSENT) { virReportError(VIR_ERR_XML_ERROR, _("iommu model '%1$s' doesn't support some addi= tional attributes"), virDomainIOMMUModelTypeToString(iommu->model)); @@ -3155,6 +3174,7 @@ virDomainIOMMUDefValidate(const virDomainIOMMUDef *io= mmu) =20 case VIR_DOMAIN_IOMMU_MODEL_VIRTIO: case VIR_DOMAIN_IOMMU_MODEL_AMD: + case VIR_DOMAIN_IOMMU_MODEL_SMMUV3_DEV: case VIR_DOMAIN_IOMMU_MODEL_LAST: break; } diff --git a/src/conf/schemas/domaincommon.rng b/src/conf/schemas/domaincom= mon.rng index b9230a35b4..26880b6db2 100644 --- a/src/conf/schemas/domaincommon.rng +++ b/src/conf/schemas/domaincommon.rng @@ -6266,6 +6266,7 @@ smmuv3 virtio amd + smmuv3Dev @@ -6311,6 +6312,11 @@ + + + + + diff --git a/src/qemu/qemu_command.c b/src/qemu/qemu_command.c index 031f09b7a5..e789e8cf2c 100644 --- a/src/qemu/qemu_command.c +++ b/src/qemu/qemu_command.c @@ -6294,6 +6294,62 @@ qemuBuildBootCommandLine(virCommand *cmd, } =20 =20 +static virJSONValue * +qemuBuildPCISmmuv3DevDevProps(const virDomainDef *def, + const virDomainIOMMUDef *iommu) +{ + g_autoptr(virJSONValue) props =3D NULL; + g_autofree char *bus =3D NULL; + size_t i; + bool contIsPHB =3D false; + + for (i =3D 0; i < def->ncontrollers; i++) { + virDomainControllerDef *cont =3D def->controllers[i]; + if (cont->idx =3D=3D iommu->parent_idx) { + if (cont->type =3D=3D VIR_DOMAIN_CONTROLLER_TYPE_PCI) { + const char *alias =3D cont->info.alias; + contIsPHB =3D virDomainControllerIsPSeriesPHB(cont); + + if (!alias) + return NULL; + + if (virDomainDeviceAliasIsUserAlias(alias)) { + if (cont->model =3D=3D VIR_DOMAIN_CONTROLLER_MODEL_PCI= _ROOT && + iommu->parent_idx <=3D 0) { + if (qemuDomainSupportsPCIMultibus(def)) + bus =3D g_strdup("pci.0"); + else + bus =3D g_strdup("pci"); + } else if (cont->model =3D=3D VIR_DOMAIN_CONTROLLER_MO= DEL_PCIE_ROOT) { + bus =3D g_strdup("pcie.0"); + } + } else { + bus =3D g_strdup(alias); + } + break; + } + } + } + + if (!bus) + return NULL; + + if (contIsPHB && iommu->parent_idx > 0) { + char *temp_bus =3D g_strdup_printf("%s.0", bus); + g_free(bus); + bus =3D temp_bus; + } + + if (virJSONValueObjectAdd(&props, + "s:driver", "arm-smmuv3", + "s:primary-bus", bus, + NULL) < 0) + return NULL; + + return g_steal_pointer(&props); +} + + static int qemuBuildIOMMUCommandLine(virCommand *cmd, const virDomainDef *def, @@ -6342,7 +6398,6 @@ qemuBuildIOMMUCommandLine(virCommand *cmd, return 0; =20 case VIR_DOMAIN_IOMMU_MODEL_SMMUV3: - /* There is no -device for SMMUv3, so nothing to be done here */ return 0; =20 case VIR_DOMAIN_IOMMU_MODEL_AMD: @@ -6373,6 +6428,14 @@ qemuBuildIOMMUCommandLine(virCommand *cmd, =20 return 0; =20 + case VIR_DOMAIN_IOMMU_MODEL_SMMUV3_DEV: + if (!(props =3D qemuBuildPCISmmuv3DevDevProps(def, iommu))) + return -1; + if (qemuBuildDeviceCommandlineFromJSON(cmd, props, def, qemuCaps) = < 0) + return -1; + + return 0; + case VIR_DOMAIN_IOMMU_MODEL_LAST: default: virReportEnumRangeError(virDomainIOMMUModel, iommu->model); @@ -7206,6 +7269,7 @@ qemuBuildMachineCommandLine(virCommand *cmd, case VIR_DOMAIN_IOMMU_MODEL_INTEL: case VIR_DOMAIN_IOMMU_MODEL_VIRTIO: case VIR_DOMAIN_IOMMU_MODEL_AMD: + case VIR_DOMAIN_IOMMU_MODEL_SMMUV3_DEV: /* These IOMMUs are formatted in qemuBuildIOMMUCommandLine */ break; =20 @@ -10860,15 +10924,15 @@ qemuBuildCommandLine(virDomainObj *vm, if (qemuBuildBootCommandLine(cmd, def) < 0) return NULL; =20 - if (qemuBuildIOMMUCommandLine(cmd, def, qemuCaps) < 0) - return NULL; - if (qemuBuildGlobalControllerCommandLine(cmd, def) < 0) return NULL; =20 if (qemuBuildControllersCommandLine(cmd, def, qemuCaps) < 0) return NULL; =20 + if (qemuBuildIOMMUCommandLine(cmd, def, qemuCaps) < 0) + return NULL; + if (qemuBuildMemoryDeviceCommandLine(cmd, cfg, def, priv) < 0) return NULL; =20 diff --git a/src/qemu/qemu_domain_address.c b/src/qemu/qemu_domain_address.c index 96a9ca9b14..06bf4fab32 100644 --- a/src/qemu/qemu_domain_address.c +++ b/src/qemu/qemu_domain_address.c @@ -952,6 +952,7 @@ qemuDomainDeviceCalculatePCIConnectFlags(virDomainDevic= eDef *dev, =20 case VIR_DOMAIN_IOMMU_MODEL_INTEL: case VIR_DOMAIN_IOMMU_MODEL_SMMUV3: + case VIR_DOMAIN_IOMMU_MODEL_SMMUV3_DEV: case VIR_DOMAIN_IOMMU_MODEL_LAST: /* These are not PCI devices */ return 0; @@ -2378,6 +2379,7 @@ qemuDomainAssignDevicePCISlots(virDomainDef *def, =20 case VIR_DOMAIN_IOMMU_MODEL_INTEL: case VIR_DOMAIN_IOMMU_MODEL_SMMUV3: + case VIR_DOMAIN_IOMMU_MODEL_SMMUV3_DEV: case VIR_DOMAIN_IOMMU_MODEL_LAST: /* These are not PCI devices */ break; diff --git a/src/qemu/qemu_validate.c b/src/qemu/qemu_validate.c index c7ecb467a3..aac004c544 100644 --- a/src/qemu/qemu_validate.c +++ b/src/qemu/qemu_validate.c @@ -5414,6 +5414,22 @@ qemuValidateDomainDeviceDefIOMMU(const virDomainIOMM= UDef *iommu, } break; =20 + case VIR_DOMAIN_IOMMU_MODEL_SMMUV3_DEV: + if (!qemuDomainIsARMVirt(def)) { + virReportError(VIR_ERR_CONFIG_UNSUPPORTED, + _("IOMMU device: '%1$s' is only supported with = ARM Virt machines"), + virDomainIOMMUModelTypeToString(iommu->model)); + return -1; + } + // TODO: Check for pluggable device SMMUv3 qemu capability + if (!virQEMUCapsGet(qemuCaps, QEMU_CAPS_MACHINE_VIRT_IOMMU)) { + virReportError(VIR_ERR_CONFIG_UNSUPPORTED, + _("IOMMU device: '%1$s' is not supported with t= his QEMU binary"), + virDomainIOMMUModelTypeToString(iommu->model)); + return -1; + } + break; + case VIR_DOMAIN_IOMMU_MODEL_LAST: default: virReportEnumRangeError(virDomainIOMMUModel, iommu->model); --=20 2.43.0