From nobody Sun Oct 5 01:49:27 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.libvirt.org designates 8.43.85.245 as permitted sender) client-ip=8.43.85.245; envelope-from=devel-bounces@lists.libvirt.org; helo=lists.libvirt.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of lists.libvirt.org designates 8.43.85.245 as permitted sender) smtp.mailfrom=devel-bounces@lists.libvirt.org; arc=fail (Bad Signature); dmarc=pass(p=reject dis=none) header.from=lists.libvirt.org Return-Path: Received: from lists.libvirt.org (lists.libvirt.org [8.43.85.245]) by mx.zohomail.com with SMTPS id 1758590631851401.99605980297986; Mon, 22 Sep 2025 18:23:51 -0700 (PDT) Received: by lists.libvirt.org (Postfix, from userid 993) id BDB2E41B9B; Mon, 22 Sep 2025 21:23:50 -0400 (EDT) Received: from [172.19.199.10] (lists.libvirt.org [8.43.85.245]) by lists.libvirt.org (Postfix) with ESMTP id 68EAA43EAE; Mon, 22 Sep 2025 21:16:58 -0400 (EDT) Received: by lists.libvirt.org (Postfix, from userid 993) id 56AE8419D7; Mon, 22 Sep 2025 21:16:36 -0400 (EDT) Received: from SN4PR0501CU005.outbound.protection.outlook.com (mail-southcentralusazon11011038.outbound.protection.outlook.com [40.93.194.38]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (3072 bits) server-digest SHA256) (No client certificate requested) by lists.libvirt.org (Postfix) with ESMTPS id 040A741A29 for ; Mon, 22 Sep 2025 21:16:12 -0400 (EDT) Received: from PH7PR12MB6834.namprd12.prod.outlook.com (2603:10b6:510:1b4::18) by SJ2PR12MB7917.namprd12.prod.outlook.com (2603:10b6:a03:4c7::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9137.16; Tue, 23 Sep 2025 01:16:04 +0000 Received: from PH7PR12MB6834.namprd12.prod.outlook.com ([fe80::f432:162b:b94e:d2cb]) by PH7PR12MB6834.namprd12.prod.outlook.com ([fe80::f432:162b:b94e:d2cb%6]) with mapi id 15.20.9137.018; Tue, 23 Sep 2025 01:16:04 +0000 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on lists.libvirt.org X-Spam-Level: X-Spam-Status: No, score=-3.1 required=5.0 tests=ARC_SIGNED,ARC_VALID, DKIM_INVALID,DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED,SPF_PASS autolearn=unavailable autolearn_force=no version=4.0.1 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=BEPtCvY9x6x3SCt3ZbmdZJzHFEiGmNZ8W/0+lC9vZvrE2jvbXeWGUdP9Liwi3xfVDFLjdil3uWeqNYJn0Lvf386vo7ZDRtDEeuhvzW91JHIqrXCYkOUOPwukxMUAPaNsmC57jgYPVBnBGdmfpBLQixI8ZwbA/JkBu0gMuyYtiMVyKcwosPacA8Pk22i+W0hXo9hWbnjyBk94+quv9ta4Xs3d4yfnAxs6GehlgEdJcvpdvaz9VknJw/2I0p05o+9m7uSnpEelFVF1D06Rn7wBvbfwe2SgqxnL8udZLA9cqFb1HIDmop+M4eHBCBC+9jQQ3C7eH4NUUGVProJIBFtU5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=hITjc9oQ8s6U/Qs1HwS8uk37gSTjQjMd10UIOQkNzbU=; b=usXEWiD4ALm9LOOSAqRFzSmyR3HYbxolnQt5l6QhdZOqEGqsGifuazclWnzPlWeJ3fqxB9JCrZ9lT6fQ50QLRT3aoM7i3dYk3rVoe4VIrKMuzhdG5+JAR37CssUGJbjhAnJlXnRcqmEnO0Uq8SbGqd3VXcsqh5KYn3oUWPO4Et5Il3fwzfo6XxMBF/ctN51T8iUFhNvHPdrCqEULAVnIZ5gXNrDzInL39a0iEsppuE0LOCPPT5QN+FZfQsB3AHxG5dE8+k3wq+quKGvnnX+qrOIH68UZnID1jVPGbFitklWLtHM71hKHg/ASw0R3ikQvbJLPQlcmSOgTVvVTxB2OrQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=hITjc9oQ8s6U/Qs1HwS8uk37gSTjQjMd10UIOQkNzbU=; b=qk3DjtRdU10OKzGkn9SZLwLMN1YwoUQufujw2T/5QUzGGI4HMg8IxYSU0UlwaVxcQd4FFQ2Yo+8Qgj8UmqadK0AD4QyjAOlZQWKnd/FvFU0kOUHaBKARPdi21yhPjwa16sYf8Wp3f572AazlOdBxRybBGsM+5eNlFOx2o77V9NSpof0tij/dLB3EXh91d9jVGCbm07oWGiLPQhSB5VAj713+StGd0ettos1CG/D5aOptRgQHOyJWF+aEeGIdzIJMsgsvcnFAxaZyhUTXeCIhoFpkdA0FTljvTvHf8Fvv/qNjeGKAbevelaye/fS2yjvh1zQZBsfc+ue1iEONAqxqmg== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; To: devel@lists.libvirt.org Subject: [RFC PATCH 1/7] qemu: add IOMMU model smmuv3Dev Date: Mon, 22 Sep 2025 18:15:54 -0700 Message-ID: <20250923011600.3229388-2-nathanc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250923011600.3229388-1-nathanc@nvidia.com> References: <20250923011600.3229388-1-nathanc@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BY5PR20CA0009.namprd20.prod.outlook.com (2603:10b6:a03:1f4::22) To PH7PR12MB6834.namprd12.prod.outlook.com (2603:10b6:510:1b4::18) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH7PR12MB6834:EE_|SJ2PR12MB7917:EE_ X-MS-Office365-Filtering-Correlation-Id: ed512050-01ab-4e2b-f7d0-08ddfa3ec455 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|366016|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?YtG6n9+CpB4Bs0gJlOOAJ2vt4MylZI+OS5r/5HLrl5HbuVwK4sTXAhVKmgq5?= =?us-ascii?Q?dhvooptYYcFO2r1izydRrYTfWjhar8El1TJr5rLTtA8fVc8OAEJa5heEOesj?= =?us-ascii?Q?0ma36thEkRszbAjevd6yGBC4KMgo2EOl2X/qp1l+KH8Urjth9K3Q16nhOZRg?= =?us-ascii?Q?Qq++87u7UGB5BOC4/tYnlo7XgKCuuRb7nJgt1moCJjnUlJWsUd/kJkCLOAZq?= =?us-ascii?Q?RQRypYv22VPo79mCBXmcFeNG6DTr3Wkq1aaeF207BGKd4RqM23i1Al13yeaI?= =?us-ascii?Q?9U4FaK3WIF8sdseXJL6vJ+pZ+pgsGwFcO21Fge4GAkcT/IPv9+GxmTitPQEb?= =?us-ascii?Q?oCOrRIlcdMcPwRDLDNCwyxrUVaE4kJ9s1PXF5cwEbzmTJF7hnogwhzCWDBDA?= =?us-ascii?Q?4Be1KbzZNV/COV5+z+SEr/TxPOpLg6vIfNDppoPwMcumSL/5ynms4PHjG/Qc?= =?us-ascii?Q?xAPtosMWqS1BrKPKK9tA684z0KL79hesY6nwsfWCQEnjVSF5GWZ6l2U5hmpn?= =?us-ascii?Q?GiuDkj1qpiBv9v3yV5QvaTaNAu6FIYLDojWCBOyFdlV0MvIL9mf5FRpEQT2k?= =?us-ascii?Q?H7l1u5psQyMMehW+YfCkuW6SCe9dBHe9PXlPUXaWrVlYTsgz1oMVb7HSMkpx?= =?us-ascii?Q?a+tZQzilqsXm+qLt7mOuWCdz2Y6kRYojYsdw33yX+ZflFjLxaR/6IpoQD4gB?= =?us-ascii?Q?c9RhTa02KClDU2zbHeD9hTQW+HMRPd/DxmJQ4XddL6vs7T3FxtleWl8UTbUx?= =?us-ascii?Q?S/rSV+BQnqogbgpP1oDVBF5Nqcy/KeAZe29ZVgdfhOMHv1R/lkZvHaMFdgLh?= =?us-ascii?Q?pvGZeMi+7lZAMxez5brOOtXxuTTqpVSeRfvSQnuoYWzgi01X3jB6AP56XUxT?= =?us-ascii?Q?DX7cYersMbScQIk0+JYnlpGsVOiFlfm8pkOSHy4+YDGK1wFf3I9rEwsjkRzC?= =?us-ascii?Q?CiQTkDMYk2uEGlPY2uvkOa1iq3WUL6+rv58l8wnkhGnlKyoZhkjM8VdYSfMe?= =?us-ascii?Q?AZ3ZmnOpXVYAflFPUUB5mRKt5JXfQv8ayN/3pvOYPAj0UZrQhH6cAaikUhId?= =?us-ascii?Q?6yMRY9yni3b/lUTAxWEzl0FJCkcQkoLicrOplTJobSghuTY5FcK3wjeQsUDa?= =?us-ascii?Q?AUS5XdCgMCxsBhF8pwu8kSNbRPcwp8xWoXRv5f0wW+ugYQsGf5GX5t/BeDwY?= =?us-ascii?Q?Dp63adm4s9AVPw5hPNJn09D6wfXKl77t4AkcXxgePjXVpz6HpM1kPp5GPa3V?= =?us-ascii?Q?oFtcUsjESkmbKprYo715msjZC5nzjIZ4U5prqmt5HbXIJy8rddhJgquBbwzY?= =?us-ascii?Q?bUnqr1ARzR6nNkxcVb364k9LkP2odnaz7shf+S5b0edFArQ782bn2RFMhApq?= =?us-ascii?Q?etfp2hy2cE6XTaRGMRyhFrpJrW0KgRtc5ouTkn6VSvhrGpawBr+XVt9oWmle?= =?us-ascii?Q?AXM9YF2ulSo=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PH7PR12MB6834.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(366016)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?H8O5c96wyJyB4HGjaLN4+b+HdezTwpSg60Q19XyvQmOUqzqA/r4VGGIr9KPz?= =?us-ascii?Q?5qNizbZjI30UYn0W0TKKiNFJX/gLbgfxhMugUFRfCIbnCu1hxeqjVmH/59o5?= =?us-ascii?Q?SsDGK0EQ99A3sRNPvMId18gcxQ/OF0s8ho4YZSFNJCQoI4DXSqRcwrWF6uRu?= =?us-ascii?Q?p9/crMafwjAVNiDEOvnOkdsCsr7VPY1dNOA7lULi/1iLzRkQlBEbwUFwhw6B?= =?us-ascii?Q?qimCCpSB85wbSuHYP0256uLAJofvEG7qpteGi7XgciiSmub69VH5ND7oaDqj?= =?us-ascii?Q?DQGS+TFiwFU/WulWM/dFxfDNoY3Ke9xPt3LmoU085tj16NZgOTNWq1fDIJj6?= =?us-ascii?Q?dujbW42+NSJi3V4A59g6otQs3PQqzKpiftEfrWqoIX9Xw7CpZyMTP1u/eiRY?= =?us-ascii?Q?mU+jW1U/f6vy+wl6FW9bo4KH6uqq1/5//CXX1vTr/Cp5X6/CPG3S4MPdCz1N?= =?us-ascii?Q?q2ze4hf8jqRdq6HDyokrsR9E5NdPj5bpMUtfA/liL1GGYRiwvbU15booJPZh?= =?us-ascii?Q?AItZymL5XiLkdO6MaAh8u2EsxfknrF4FkdtpXtcMUFKTse5zWVS6OlI2VXgU?= =?us-ascii?Q?w9/meYhIt3YL2h/Fq44x/u4aRaL46sMfxqtuLx3ZxWaFofW7WKWDbODJcKz6?= =?us-ascii?Q?ISz7tSJYcAXRN3ksnm1pw7Go5S5eLadQS+Lwpl/n+lmkaQrThQ5FVEP21KNC?= =?us-ascii?Q?sm2SV+FRs+RCnWESY58IfKxW+Dunzrb/NnTsgCg+pIBDbOKr1Shv5Qjl2Vpu?= =?us-ascii?Q?C7tCPMWxtsuM/a22J1+pv2jMRAGq/WdkydymbQgY00Xa1aSA6ssKbYq6lnUC?= =?us-ascii?Q?pKivYnDG9CCAyijByhelsnYWbMx0uEiw2rjTMKNeFCScUH+QgiDVxG6z9k1a?= =?us-ascii?Q?2OLlu28slPhWkJ+fwPKXwfvT9b10XAv1gayMlIuOpufJMv5kysyZRNcOxgpn?= =?us-ascii?Q?xaA31giK/TGM4yit1b+zUEER4kGFWwlx/mUFg9cme0R85ybhPyYd08+Oat2b?= =?us-ascii?Q?3f1KrQu64K3JrkKh9ofwBdjt50oxmYwn01MKG9N5qKb5lMJ79ZU8LcocCKN9?= =?us-ascii?Q?7pg8wM43pLSvUsK9qIZwrJ0au2odFumlCMkPvrDbI5pjx3xZVMLHIx6yS7B3?= =?us-ascii?Q?KW4CvPKdUqwOZPa2/JE3OgO15cUgEsBkY9no/yN1Lej9gZJTKY5QACENlJs7?= =?us-ascii?Q?mALiy4V5afTSEKom6jDNirRQ3YpNt1Ksk5nvQGGQksw6voi9JaNcoTTEIy/y?= =?us-ascii?Q?+2VJ8fmTYgSZdDi1BXh8dUKnzcMSmneA6IRZV4Vjo3P5uPcX+yF4KIA8KTjR?= =?us-ascii?Q?pBNKsUI5SOtzK23cHwRGdVjxajYADUQU3iFGOIp6RsTcwQln707MG4iZJ1Qd?= =?us-ascii?Q?t01z9eBNG9I6PNjGe4413/bt/i4t50HxaddU24BsIxY26XMHLaJE/0Wl2frH?= =?us-ascii?Q?rkzBi5Xhp4vPghV9zP+Gusw6T272lTpXYjH1Yngp9MDDNsze5tRdWMNM66+6?= =?us-ascii?Q?buAHaM3AOnAVYor35fOZFUzDEJRfRIeNnYYbaH/BRykyBxBO58JlGPN6z88g?= =?us-ascii?Q?IZPShb1uOSlYvKVmP+eOM8SjGJrgSxfv5o/EFZVC?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: ed512050-01ab-4e2b-f7d0-08ddfa3ec455 X-MS-Exchange-CrossTenant-AuthSource: PH7PR12MB6834.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2025 01:16:04.6982 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 6aFkgu8hFTZE4oiqxG8QVpthtZhuAL4wGkhtwPCD+vO4+JMjhXPyDx1jFEIDGbEixD/H2CRrMBa/Tbb5wI7PyQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB7917 Message-ID-Hash: OOAFLBQDC4ICNFWJQJ3GUDJ5M3SGK7TU X-Message-ID-Hash: OOAFLBQDC4ICNFWJQJ3GUDJ5M3SGK7TU X-MailFrom: nathanc@nvidia.com X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; loop; banned-address; header-match-devel.lists.libvirt.org-0; emergency; member-moderation; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header CC: shameerali.kolothum.thodi@huawei.com, nicolinc@nvidia.com, nathanc@nvidia.com, mochs@nvidia.com X-Mailman-Version: 3.3.10 Precedence: list List-Id: Development discussions about the libvirt library & tools Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: From: Nathan Chen via Devel Reply-To: Nathan Chen X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1758590633909116600 Content-Type: text/plain; charset="utf-8" Introduce support for "smmuv3Dev" IOMMU model and "parentIdx" and "accel" IOMMU device attributes. The former indicates the index of the controller that a smmuv3Dev IOMMU device is attached to, while the latter indicates whether hardware accelerated SMMUv3 support is to be enabled. Signed-off-by: Nathan Chen --- docs/formatdomain.rst | 13 +++++- src/conf/domain_conf.c | 35 +++++++++++++++ src/conf/domain_conf.h | 3 ++ src/conf/domain_validate.c | 26 +++++++++-- src/conf/schemas/domaincommon.rng | 11 +++++ src/qemu/qemu_command.c | 73 +++++++++++++++++++++++++++++-- src/qemu/qemu_domain_address.c | 2 + src/qemu/qemu_validate.c | 16 +++++++ 8 files changed, 170 insertions(+), 9 deletions(-) diff --git a/docs/formatdomain.rst b/docs/formatdomain.rst index f50dce477f..2f1e06ba0e 100644 --- a/docs/formatdomain.rst +++ b/docs/formatdomain.rst @@ -9161,8 +9161,17 @@ Example: ``model`` Supported values are ``intel`` (for Q35 guests) ``smmuv3`` (:since:`since 5.5.0`, for ARM virt guests), ``virtio`` - (:since:`since 8.3.0`, for Q35 and ARM virt guests) and - ``amd`` (:since:`since 11.5.0`). + (:since:`since 8.3.0`, for Q35 and ARM virt guests), + ``amd`` (:since:`since 11.5.0`), and ``smmuv3Dev`` (for + ARM virt guests). + +``parentIdx`` + The ``parentIdx`` attribute notes the index of the controller that a + smmuv3Dev IOMMU device is attached to. + +``accel`` + The ``accel`` attribute with possible values ``on`` and ``off`` can be = used + to enable hardware acceleration support for smmuv3Dev IOMMU devices. =20 ``driver`` The ``driver`` subelement can be used to configure additional options, = some diff --git a/src/conf/domain_conf.c b/src/conf/domain_conf.c index 281846dfbe..42b2a5c74f 100644 --- a/src/conf/domain_conf.c +++ b/src/conf/domain_conf.c @@ -1353,6 +1353,7 @@ VIR_ENUM_IMPL(virDomainIOMMUModel, "smmuv3", "virtio", "amd", + "smmuv3Dev", ); =20 VIR_ENUM_IMPL(virDomainVsockModel, @@ -2813,6 +2814,8 @@ virDomainIOMMUDefNew(void) =20 iommu =3D g_new0(virDomainIOMMUDef, 1); =20 + iommu->parent_idx =3D -1; + return g_steal_pointer(&iommu); } =20 @@ -14407,6 +14410,14 @@ virDomainIOMMUDefParseXML(virDomainXMLOption *xmlo= pt, VIR_XML_PROP_REQUIRED, &iommu->model) < 0) return NULL; =20 + if (virXMLPropInt(node, "parentIdx", 10, VIR_XML_PROP_NONE, + &iommu->parent_idx, -1) < 0) + return NULL; + + if (virXMLPropTristateSwitch(node, "accel", VIR_XML_PROP_NONE, + &iommu->accel) < 0) + return NULL; + if ((driver =3D virXPathNode("./driver", ctxt))) { if (virXMLPropTristateSwitch(driver, "intremap", VIR_XML_PROP_NONE, &iommu->intremap) < 0) @@ -22092,6 +22103,18 @@ virDomainIOMMUDefCheckABIStability(virDomainIOMMUD= ef *src, dst->aw_bits, src->aw_bits); return false; } + if (src->parent_idx !=3D dst->parent_idx) { + virReportError(VIR_ERR_CONFIG_UNSUPPORTED, + _("Target domain IOMMU device parent_idx value '%1$= d' does not match source '%2$d'"), + dst->parent_idx, src->parent_idx); + return false; + } + if (src->accel !=3D dst->accel) { + virReportError(VIR_ERR_CONFIG_UNSUPPORTED, + _("Target domain IOMMU device accel value '%1$d' do= es not match source '%2$d'"), + dst->accel, src->accel); + return false; + } if (src->dma_translation !=3D dst->dma_translation) { virReportError(VIR_ERR_CONFIG_UNSUPPORTED, _("Target domain IOMMU device dma translation '%1$s= ' does not match source '%2$s'"), @@ -28417,6 +28440,18 @@ virDomainIOMMUDefFormat(virBuffer *buf, virBufferAsprintf(&attrBuf, " model=3D'%s'", virDomainIOMMUModelTypeToString(iommu->model)); =20 + if (iommu->parent_idx >=3D 0 && iommu->model =3D=3D VIR_DOMAIN_IOMMU_M= ODEL_SMMUV3_DEV) { + virBufferAsprintf(&attrBuf, " parentIdx=3D'%d'", + iommu->parent_idx); + } + + if (iommu->model =3D=3D VIR_DOMAIN_IOMMU_MODEL_SMMUV3_DEV) { + if (iommu->accel !=3D VIR_TRISTATE_SWITCH_ABSENT) { + virBufferAsprintf(&attrBuf, " accel=3D'%s'", + virTristateSwitchTypeToString(iommu->accel)); + } + } + virXMLFormatElement(buf, "iommu", &attrBuf, &childBuf); } =20 diff --git a/src/conf/domain_conf.h b/src/conf/domain_conf.h index 39807b5fe3..c4541589d3 100644 --- a/src/conf/domain_conf.h +++ b/src/conf/domain_conf.h @@ -3039,6 +3039,7 @@ typedef enum { VIR_DOMAIN_IOMMU_MODEL_SMMUV3, VIR_DOMAIN_IOMMU_MODEL_VIRTIO, VIR_DOMAIN_IOMMU_MODEL_AMD, + VIR_DOMAIN_IOMMU_MODEL_SMMUV3_DEV, =20 VIR_DOMAIN_IOMMU_MODEL_LAST } virDomainIOMMUModel; @@ -3050,10 +3051,12 @@ struct _virDomainIOMMUDef { virTristateSwitch eim; virTristateSwitch iotlb; unsigned int aw_bits; + int parent_idx; virDomainDeviceInfo info; virTristateSwitch dma_translation; virTristateSwitch xtsup; virTristateSwitch pt; + virTristateSwitch accel; }; =20 typedef enum { diff --git a/src/conf/domain_validate.c b/src/conf/domain_validate.c index 93a2bc9b01..ba12ea706d 100644 --- a/src/conf/domain_validate.c +++ b/src/conf/domain_validate.c @@ -3108,7 +3108,8 @@ virDomainIOMMUDefValidate(const virDomainIOMMUDef *io= mmu) iommu->eim !=3D VIR_TRISTATE_SWITCH_ABSENT || iommu->iotlb !=3D VIR_TRISTATE_SWITCH_ABSENT || iommu->aw_bits !=3D 0 || - iommu->dma_translation !=3D VIR_TRISTATE_SWITCH_ABSENT) { + iommu->dma_translation !=3D VIR_TRISTATE_SWITCH_ABSENT || + iommu->accel !=3D VIR_TRISTATE_SWITCH_ABSENT) { virReportError(VIR_ERR_XML_ERROR, _("iommu model '%1$s' doesn't support additiona= l attributes"), virDomainIOMMUModelTypeToString(iommu->model)); @@ -3120,7 +3121,8 @@ virDomainIOMMUDefValidate(const virDomainIOMMUDef *io= mmu) if (iommu->caching_mode !=3D VIR_TRISTATE_SWITCH_ABSENT || iommu->eim !=3D VIR_TRISTATE_SWITCH_ABSENT || iommu->aw_bits !=3D 0 || - iommu->dma_translation !=3D VIR_TRISTATE_SWITCH_ABSENT) { + iommu->dma_translation !=3D VIR_TRISTATE_SWITCH_ABSENT || + iommu->accel !=3D VIR_TRISTATE_SWITCH_ABSENT) { virReportError(VIR_ERR_XML_ERROR, _("iommu model '%1$s' doesn't support some addi= tional attributes"), virDomainIOMMUModelTypeToString(iommu->model)); @@ -3130,7 +3132,24 @@ virDomainIOMMUDefValidate(const virDomainIOMMUDef *i= ommu) =20 case VIR_DOMAIN_IOMMU_MODEL_INTEL: if (iommu->pt !=3D VIR_TRISTATE_SWITCH_ABSENT || - iommu->xtsup !=3D VIR_TRISTATE_SWITCH_ABSENT) { + iommu->xtsup !=3D VIR_TRISTATE_SWITCH_ABSENT || + iommu->accel !=3D VIR_TRISTATE_SWITCH_ABSENT) { + virReportError(VIR_ERR_XML_ERROR, + _("iommu model '%1$s' doesn't support some addi= tional attributes"), + virDomainIOMMUModelTypeToString(iommu->model)); + return -1; + } + break; + + case VIR_DOMAIN_IOMMU_MODEL_SMMUV3_DEV: + if (iommu->intremap !=3D VIR_TRISTATE_SWITCH_ABSENT || + iommu->caching_mode !=3D VIR_TRISTATE_SWITCH_ABSENT || + iommu->eim !=3D VIR_TRISTATE_SWITCH_ABSENT || + iommu->iotlb !=3D VIR_TRISTATE_SWITCH_ABSENT || + iommu->aw_bits !=3D 0 || + iommu->dma_translation !=3D VIR_TRISTATE_SWITCH_ABSENT || + iommu->xtsup !=3D VIR_TRISTATE_SWITCH_ABSENT || + iommu->pt !=3D VIR_TRISTATE_SWITCH_ABSENT) { virReportError(VIR_ERR_XML_ERROR, _("iommu model '%1$s' doesn't support some addi= tional attributes"), virDomainIOMMUModelTypeToString(iommu->model)); @@ -3155,6 +3174,7 @@ virDomainIOMMUDefValidate(const virDomainIOMMUDef *io= mmu) =20 case VIR_DOMAIN_IOMMU_MODEL_VIRTIO: case VIR_DOMAIN_IOMMU_MODEL_AMD: + case VIR_DOMAIN_IOMMU_MODEL_SMMUV3_DEV: case VIR_DOMAIN_IOMMU_MODEL_LAST: break; } diff --git a/src/conf/schemas/domaincommon.rng b/src/conf/schemas/domaincom= mon.rng index b9230a35b4..1aaa1a3180 100644 --- a/src/conf/schemas/domaincommon.rng +++ b/src/conf/schemas/domaincommon.rng @@ -6266,8 +6266,19 @@ smmuv3 virtio amd + smmuv3Dev + + + + + + + + + + diff --git a/src/qemu/qemu_command.c b/src/qemu/qemu_command.c index 031f09b7a5..53088f8d8f 100644 --- a/src/qemu/qemu_command.c +++ b/src/qemu/qemu_command.c @@ -6294,6 +6294,63 @@ qemuBuildBootCommandLine(virCommand *cmd, } =20 =20 +static virJSONValue * +qemuBuildPCISmmuv3DevDevProps(const virDomainDef *def, + const virDomainIOMMUDef *iommu) +{ + g_autoptr(virJSONValue) props =3D NULL; + g_autofree char *bus =3D NULL; + size_t i; + bool contIsPHB =3D false; + + for (i =3D 0; i < def->ncontrollers; i++) { + virDomainControllerDef *cont =3D def->controllers[i]; + if (cont->idx =3D=3D iommu->parent_idx) { + if (cont->type =3D=3D VIR_DOMAIN_CONTROLLER_TYPE_PCI) { + const char *alias =3D cont->info.alias; + contIsPHB =3D virDomainControllerIsPSeriesPHB(cont); + + if (!alias) + return NULL; + + if (virDomainDeviceAliasIsUserAlias(alias)) { + if (cont->model =3D=3D VIR_DOMAIN_CONTROLLER_MODEL_PCI= _ROOT && + iommu->parent_idx <=3D 0) { + if (qemuDomainSupportsPCIMultibus(def)) + bus =3D g_strdup("pci.0"); + else + bus =3D g_strdup("pci"); + } else if (cont->model =3D=3D VIR_DOMAIN_CONTROLLER_MO= DEL_PCIE_ROOT) { + bus =3D g_strdup("pcie.0"); + } + } else { + bus =3D g_strdup(alias); + } + break; + } + } + } + + if (!bus) + return NULL; + + if (contIsPHB && iommu->parent_idx > 0) { + char *temp_bus =3D g_strdup_printf("%s.0", bus); + g_free(bus); + bus =3D temp_bus; + } + + if (virJSONValueObjectAdd(&props, + "s:driver", "arm-smmuv3", + "s:primary-bus", bus, + "b:accel", (iommu->accel =3D=3D VIR_TRISTATE= _SWITCH_ON), + NULL) < 0) + return NULL; + + return g_steal_pointer(&props); +} + + static int qemuBuildIOMMUCommandLine(virCommand *cmd, const virDomainDef *def, @@ -6342,7 +6399,6 @@ qemuBuildIOMMUCommandLine(virCommand *cmd, return 0; =20 case VIR_DOMAIN_IOMMU_MODEL_SMMUV3: - /* There is no -device for SMMUv3, so nothing to be done here */ return 0; =20 case VIR_DOMAIN_IOMMU_MODEL_AMD: @@ -6373,6 +6429,14 @@ qemuBuildIOMMUCommandLine(virCommand *cmd, =20 return 0; =20 + case VIR_DOMAIN_IOMMU_MODEL_SMMUV3_DEV: + if (!(props =3D qemuBuildPCISmmuv3DevDevProps(def, iommu))) + return -1; + if (qemuBuildDeviceCommandlineFromJSON(cmd, props, def, qemuCaps) = < 0) + return -1; + + return 0; + case VIR_DOMAIN_IOMMU_MODEL_LAST: default: virReportEnumRangeError(virDomainIOMMUModel, iommu->model); @@ -7206,6 +7270,7 @@ qemuBuildMachineCommandLine(virCommand *cmd, case VIR_DOMAIN_IOMMU_MODEL_INTEL: case VIR_DOMAIN_IOMMU_MODEL_VIRTIO: case VIR_DOMAIN_IOMMU_MODEL_AMD: + case VIR_DOMAIN_IOMMU_MODEL_SMMUV3_DEV: /* These IOMMUs are formatted in qemuBuildIOMMUCommandLine */ break; =20 @@ -10860,15 +10925,15 @@ qemuBuildCommandLine(virDomainObj *vm, if (qemuBuildBootCommandLine(cmd, def) < 0) return NULL; =20 - if (qemuBuildIOMMUCommandLine(cmd, def, qemuCaps) < 0) - return NULL; - if (qemuBuildGlobalControllerCommandLine(cmd, def) < 0) return NULL; =20 if (qemuBuildControllersCommandLine(cmd, def, qemuCaps) < 0) return NULL; =20 + if (qemuBuildIOMMUCommandLine(cmd, def, qemuCaps) < 0) + return NULL; + if (qemuBuildMemoryDeviceCommandLine(cmd, cfg, def, priv) < 0) return NULL; =20 diff --git a/src/qemu/qemu_domain_address.c b/src/qemu/qemu_domain_address.c index 96a9ca9b14..06bf4fab32 100644 --- a/src/qemu/qemu_domain_address.c +++ b/src/qemu/qemu_domain_address.c @@ -952,6 +952,7 @@ qemuDomainDeviceCalculatePCIConnectFlags(virDomainDevic= eDef *dev, =20 case VIR_DOMAIN_IOMMU_MODEL_INTEL: case VIR_DOMAIN_IOMMU_MODEL_SMMUV3: + case VIR_DOMAIN_IOMMU_MODEL_SMMUV3_DEV: case VIR_DOMAIN_IOMMU_MODEL_LAST: /* These are not PCI devices */ return 0; @@ -2378,6 +2379,7 @@ qemuDomainAssignDevicePCISlots(virDomainDef *def, =20 case VIR_DOMAIN_IOMMU_MODEL_INTEL: case VIR_DOMAIN_IOMMU_MODEL_SMMUV3: + case VIR_DOMAIN_IOMMU_MODEL_SMMUV3_DEV: case VIR_DOMAIN_IOMMU_MODEL_LAST: /* These are not PCI devices */ break; diff --git a/src/qemu/qemu_validate.c b/src/qemu/qemu_validate.c index c7ecb467a3..aac004c544 100644 --- a/src/qemu/qemu_validate.c +++ b/src/qemu/qemu_validate.c @@ -5414,6 +5414,22 @@ qemuValidateDomainDeviceDefIOMMU(const virDomainIOMM= UDef *iommu, } break; =20 + case VIR_DOMAIN_IOMMU_MODEL_SMMUV3_DEV: + if (!qemuDomainIsARMVirt(def)) { + virReportError(VIR_ERR_CONFIG_UNSUPPORTED, + _("IOMMU device: '%1$s' is only supported with = ARM Virt machines"), + virDomainIOMMUModelTypeToString(iommu->model)); + return -1; + } + // TODO: Check for pluggable device SMMUv3 qemu capability + if (!virQEMUCapsGet(qemuCaps, QEMU_CAPS_MACHINE_VIRT_IOMMU)) { + virReportError(VIR_ERR_CONFIG_UNSUPPORTED, + _("IOMMU device: '%1$s' is not supported with t= his QEMU binary"), + virDomainIOMMUModelTypeToString(iommu->model)); + return -1; + } + break; + case VIR_DOMAIN_IOMMU_MODEL_LAST: default: virReportEnumRangeError(virDomainIOMMUModel, iommu->model); --=20 2.43.0