From nobody Mon Sep 8 02:34:22 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1756699747; cv=none; d=zohomail.com; s=zohoarc; b=ba7FHVkqb1CCGVUJ1/XySXt7qaRKyrCJFierIxmsyyEmUfXEXCsfCOa7KHil+EAGWpC4ZwLH9PoP3ZeqbF7rVJ278k065QJGWcBp5gQE8AweMqeK7JxB+sq3INucRLK+GTUqxMw2MhD2H10YfWUNbDjHblTjdLvT9Q8AkANZa3U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756699747; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=dAme40QxEBl0L/plI0zi2T1faPqNyqiHMl8/Klam+lc=; b=dGYd0YL5lkCXQ02j0X6YNYQIg0YgTFVxVtRFR0xwGJU+fpEi0s+CwbxbqFYCwRqLHRtgcV365QlF1VKvOt6KRDjXA4FCBXPhc+dhu9dXK1uT6cT3NJdrlZPco2sCOME8ZJQ3ClXXLUO6wF4mONz5fxdXR/fegw786dJ/8Xx3z/M= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756699747427114.58125169856032; Sun, 31 Aug 2025 21:09:07 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1usvqR-0002o4-CO; Mon, 01 Sep 2025 00:08:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1usvqK-0002nE-Ji; Mon, 01 Sep 2025 00:08:33 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1usvqI-000862-JK; Mon, 01 Sep 2025 00:08:32 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Mon, 1 Sep 2025 12:08:09 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Mon, 1 Sep 2025 12:08:09 +0800 To: "reviewer:Incompatible changes" , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:All patches CC here" , "open list:ASPEED BMCs" CC: , , Subject: [PATCH v1 4/4] docs/specs/aspeed-intc: Remove GIC 128 - 136 Date: Mon, 1 Sep 2025 12:08:07 +0800 Message-ID: <20250901040808.1454742-5-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250901040808.1454742-1-jamin_lin@aspeedtech.com> References: <20250901040808.1454742-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1756699749083116600 Content-Type: text/plain; charset="utf-8" The GIC interrupts 128 - 136 were only used by the AST2700 A0 SoC. Since the AST2700 A0 has been deprecated, these interrupt definitions are no longer needed. This commit removes them to clean up the codebase. Signed-off-by: Jamin Lin --- docs/specs/aspeed-intc.rst | 93 +++++++++++--------------------------- 1 file changed, 26 insertions(+), 67 deletions(-) diff --git a/docs/specs/aspeed-intc.rst b/docs/specs/aspeed-intc.rst index 9cefd7f37f..c0a4b4d150 100644 --- a/docs/specs/aspeed-intc.rst +++ b/docs/specs/aspeed-intc.rst @@ -47,18 +47,7 @@ Bit GIC 9 201 =3D=3D=3D=3D =3D=3D=3D=3D =20 -AST2700 A0 ----------- -It has only one INTC controller, and currently, only GIC 128-136 is suppor= ted. -To support both AST2700 A1 and AST2700 A0, there are 10 OR gates in the IN= TC, -with gates 1 to 9 supporting GIC 128-136. - -Design for GICINT 132 ---------------------- -The orgate has interrupt sources ranging from 0 to 31, with its output pin -connected to INTC. The output pin is then connected to GIC 132. - -Block Diagram of GICINT 196 for AST2700 A1 and GICINT 132 for AST2700 A0 +Block Diagram of GICINT 196 for AST2700 A1 ------------------------------------------------------------------------ =20 .. code-block:: @@ -68,69 +57,39 @@ Block Diagram of GICINT 196 for AST2700 A1 and GICINT 1= 32 for AST2700 A0 | To GICINT196 = | | = | | ETH1 |-----------| |-------------------------= -| |--------------| | - | -------->|0 | | INTCIO = | | orgates[0] | | + | ------->|0 | | INTCIO = | | orgates[0] | | | ETH2 | 4| orgates[0]------>|inpin[0]-------->outpin[0= ]|------->| 0 | | - | -------->|1 5| orgates[1]------>|inpin[1]-------->outpin[1= ]|------->| 1 | | + | ------->|1 5| orgates[1]------>|inpin[1]-------->outpin[1= ]|------->| 1 | | | ETH3 | 6| orgates[2]------>|inpin[2]-------->outpin[2= ]|------->| 2 | | - | -------->|2 19| orgates[3]------>|inpin[3]-------->outpin[3= ]|------->| 3 OR[0:9] |-----| | + | ------->|2 19| orgates[3]------>|inpin[3]-------->outpin[3= ]|------->| 3 OR[0:9] |-----| | | UART0 | 20|-->orgates[4]------>|inpin[4]-------->outpin[4= ]|------->| 4 | | | - | -------->|7 21| orgates[5]------>|inpin[5]-------->outpin[5= ]|------->| 5 | | | + | ------->|7 21| orgates[5]------>|inpin[5]-------->outpin[5= ]|------->| 5 | | | | UART1 | 22| orgates[6]------>|inpin[6]-------->outpin[6= ]|------->| 6 | | | - | -------->|8 23| orgates[7]------>|inpin[7]-------->outpin[7= ]|------->| 7 | | | + | ------->|8 23| orgates[7]------>|inpin[7]-------->outpin[7= ]|------->| 7 | | | | UART2 | 24| orgates[8]------>|inpin[8]-------->outpin[8= ]|------->| 8 | | | - | -------->|9 25| orgates[9]------>|inpin[9]-------->outpin[9= ]|------->| 9 | | | + | ------->|9 25| orgates[9]------>|inpin[9]-------->outpin[9= ]|------->| 9 | | | | UART3 | 26| |-------------------------= -| |--------------| | | - | ---------|10 27| = | | + | ------->|10 27| = | | | UART5 | 28| = | | - | -------->|11 29| = | | + | ------->|11 29| = | | | UART6 | | = | | - | -------->|12 30| |----------------------------------------= -------------------------------| | + | ------->|12 30| |----------------------------------------= -------------------------------| | | UART7 | 31| | = | - | -------->|13 | | = | - | UART8 | OR[0:31] | | |-----------------------= -------| |----------| | - | -------->|14 | | | INTC = | | GIC | | - | UART9 | | | |inpin[0:0]--------->out= pin[0] |---------->|192 | | - | -------->|15 | | |inpin[0:1]--------->out= pin[1] |---------->|193 | | - | UART10 | | | |inpin[0:2]--------->out= pin[2] |---------->|194 | | - | -------->|16 | | |inpin[0:3]--------->out= pin[3] |---------->|195 | | - | UART11 | | |--------------> |inpin[0:4]--------->out= pin[4] |---------->|196 | | - | -------->|17 | |inpin[0:5]--------->out= pin[5] |---------->|197 | | - | UART12 | | |inpin[0:6]--------->out= pin[6] |---------->|198 | | - | -------->|18 | |inpin[0:7]--------->out= pin[7] |---------->|199 | | - | |-----------| |inpin[0:8]--------->out= pin[8] |---------->|200 | | - | |inpin[0:9]--------->out= pin[9] |---------->|201 | | - |----------------------------------------------------------------------= ---------------------------------| - |----------------------------------------------------------------------= ---------------------------------| - | ETH1 |-----------| orgates[1]------->|inpin[1]----------->out= pin[10]|---------->|128 | | - | -------->|0 | orgates[2]------->|inpin[2]----------->out= pin[11]|---------->|129 | | - | ETH2 | 4| orgates[3]------->|inpin[3]----------->out= pin[12]|---------->|130 | | - | -------->|1 5| orgates[4]------->|inpin[4]----------->out= pin[13]|---------->|131 | | - | ETH3 | 6|---->orgates[5]------->|inpin[5]----------->out= pin[14]|---------->|132 | | - | -------->|2 19| orgates[6]------->|inpin[6]----------->out= pin[15]|---------->|133 | | - | UART0 | 20| orgates[7]------->|inpin[7]----------->out= pin[16]|---------->|134 | | - | -------->|7 21| orgates[8]------->|inpin[8]----------->out= pin[17]|---------->|135 | | - | UART1 | 22| orgates[9]------->|inpin[9]----------->out= pin[18]|---------->|136 | | - | -------->|8 23| |-----------------------= -------| |----------| | - | UART2 | 24| = | - | -------->|9 25| AST2700 A0 Design = | - | UART3 | 26| = | - | -------->|10 27| = | - | UART5 | 28| = | - | -------->|11 29| GICINT132 = | - | UART6 | | = | - | -------->|12 30| = | - | UART7 | 31| = | - | -------->|13 | = | - | UART8 | OR[0:31] | = | - | -------->|14 | = | - | UART9 | | = | - | -------->|15 | = | - | UART10 | | = | - | -------->|16 | = | - | UART11 | | = | - | -------->|17 | = | - | UART12 | | = | - | -------->|18 | = | - | |-----------| = | + | ------->|13 | | = | + | UART8 | OR[0:31] | | |-----------------------= ------| |----------| | + | ------->|14 | | | INTC = | | GIC | | + | UART9 | | | |inpin[0:0]--------->out= pin[0]|--------->|192 | | + | ------->|15 | | |inpin[0:1]--------->out= pin[1]|--------->|193 | | + | UART10 | | | |inpin[0:2]--------->out= pin[2]|--------->|194 | | + | ------->|16 | | |inpin[0:3]--------->out= pin[3]|--------->|195 | | + | UART11 | | |--------------> |inpin[0:4]--------->out= pin[4]|--------->|196 | | + | ------->|17 | |inpin[0:5]--------->out= pin[5]|--------->|197 | | + | UART12 | | |inpin[0:6]--------->out= pin[6]|--------->|198 | | + | ------->|18 | |inpin[0:7]--------->out= pin[7]|--------->|199 | | + | |-----------| |inpin[0:8]--------->out= pin[8]|--------->|200 | | + | |inpin[0:9]--------->out= pin[9]|--------->|201 | | + | |-----------------------= ------| |----------| | + | = | | = | |----------------------------------------------------------------------= ---------------------------------| + --=20 2.43.0