From nobody Mon Sep 8 02:39:38 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1756700618; cv=none; d=zohomail.com; s=zohoarc; b=TGhuQInJRT2yVkFDVpexrgzBKJ5KJTGy1JQActF12seIU1ZpDAUROqCY2nwQgOUaS7NGqUfOw+cmdVE1RcDHxknIxd3IsekJmPdqbTEVdGRScl80mTOXFug3gmSgMmuM/Ry/kpYEloo0mRwoNhpvvRnIIpYXcKDY17PSIQwNSys= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756700618; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=KUHH3odOBnlIJz4uzoSNvfL6ylV+Tdi51Z/NSwqBdpE=; b=GEVlI5qukrrqanpWiFe82eEAXmFJyDQoahkkJClm3jj4GdYvbkalcdiVb7OcGgoDRVRFOJ172mwIgldO+H332nCVgtuRdG4fXWs801ibEUaWSvF62pB/oI2uka/mdjOhW/yUCdiFd6qh1zCXGSRJrP+UqmWFFGdkmbPnwZdsXUM= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756700618975490.6829188420098; Sun, 31 Aug 2025 21:23:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1usw3n-0006gk-TK; Mon, 01 Sep 2025 00:22:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1usvqE-0002mJ-7V; Mon, 01 Sep 2025 00:08:26 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1usvqC-000862-Hv; Mon, 01 Sep 2025 00:08:25 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Mon, 1 Sep 2025 12:08:09 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Mon, 1 Sep 2025 12:08:09 +0800 To: "reviewer:Incompatible changes" , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:All patches CC here" , "open list:ASPEED BMCs" CC: , , Subject: [PATCH v1 2/4] hw/arm/aspeed_ast27x0: Remove ast2700-a0 SOC Date: Mon, 1 Sep 2025 12:08:05 +0800 Message-ID: <20250901040808.1454742-3-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250901040808.1454742-1-jamin_lin@aspeedtech.com> References: <20250901040808.1454742-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1756700619941116600 Content-Type: text/plain; charset="utf-8" The ast2700-a1 SOC represented the first revision of the AST2700 and was intended as an early engineering sample rather than a production platform. A newer revision, A1, is now supported, and the ast2700-a1 SOC should replace the older A0 version. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast27x0.c | 81 ----------------------------------------- 1 file changed, 81 deletions(-) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 6aa3841b69..2e47e2f860 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -89,54 +89,6 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D { #define AST2700_MAX_IRQ 256 =20 /* Shared Peripheral Interrupt values below are offset by -32 from datashe= et */ -static const int aspeed_soc_ast2700a0_irqmap[] =3D { - [ASPEED_DEV_SDMC] =3D 0, - [ASPEED_DEV_HACE] =3D 4, - [ASPEED_DEV_XDMA] =3D 5, - [ASPEED_DEV_UART4] =3D 8, - [ASPEED_DEV_SCU] =3D 12, - [ASPEED_DEV_RTC] =3D 13, - [ASPEED_DEV_EMMC] =3D 15, - [ASPEED_DEV_TIMER1] =3D 16, - [ASPEED_DEV_TIMER2] =3D 17, - [ASPEED_DEV_TIMER3] =3D 18, - [ASPEED_DEV_TIMER4] =3D 19, - [ASPEED_DEV_TIMER5] =3D 20, - [ASPEED_DEV_TIMER6] =3D 21, - [ASPEED_DEV_TIMER7] =3D 22, - [ASPEED_DEV_TIMER8] =3D 23, - [ASPEED_DEV_DP] =3D 28, - [ASPEED_DEV_EHCI1] =3D 33, - [ASPEED_DEV_EHCI2] =3D 37, - [ASPEED_DEV_LPC] =3D 128, - [ASPEED_DEV_IBT] =3D 128, - [ASPEED_DEV_KCS] =3D 128, - [ASPEED_DEV_ADC] =3D 130, - [ASPEED_DEV_GPIO] =3D 130, - [ASPEED_DEV_I2C] =3D 130, - [ASPEED_DEV_FMC] =3D 131, - [ASPEED_DEV_WDT] =3D 131, - [ASPEED_DEV_PWM] =3D 131, - [ASPEED_DEV_I3C] =3D 131, - [ASPEED_DEV_UART0] =3D 132, - [ASPEED_DEV_UART1] =3D 132, - [ASPEED_DEV_UART2] =3D 132, - [ASPEED_DEV_UART3] =3D 132, - [ASPEED_DEV_UART5] =3D 132, - [ASPEED_DEV_UART6] =3D 132, - [ASPEED_DEV_UART7] =3D 132, - [ASPEED_DEV_UART8] =3D 132, - [ASPEED_DEV_UART9] =3D 132, - [ASPEED_DEV_UART10] =3D 132, - [ASPEED_DEV_UART11] =3D 132, - [ASPEED_DEV_UART12] =3D 132, - [ASPEED_DEV_ETH1] =3D 132, - [ASPEED_DEV_ETH2] =3D 132, - [ASPEED_DEV_ETH3] =3D 132, - [ASPEED_DEV_PECI] =3D 133, - [ASPEED_DEV_SDHCI] =3D 133, -}; - static const int aspeed_soc_ast2700a1_irqmap[] =3D { [ASPEED_DEV_SDMC] =3D 0, [ASPEED_DEV_HACE] =3D 4, @@ -958,34 +910,6 @@ static void aspeed_soc_ast2700_realize(DeviceState *de= v, Error **errp) AST2700_SOC_IOMEM_SIZE); } =20 -static void aspeed_soc_ast2700a0_class_init(ObjectClass *oc, const void *d= ata) -{ - static const char * const valid_cpu_types[] =3D { - ARM_CPU_TYPE_NAME("cortex-a35"), - NULL - }; - DeviceClass *dc =3D DEVICE_CLASS(oc); - AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(oc); - - /* Reason: The Aspeed SoC can only be instantiated from a board */ - dc->user_creatable =3D false; - dc->realize =3D aspeed_soc_ast2700_realize; - - sc->valid_cpu_types =3D valid_cpu_types; - sc->silicon_rev =3D AST2700_A0_SILICON_REV; - sc->sram_size =3D 0x20000; - sc->spis_num =3D 3; - sc->ehcis_num =3D 2; - sc->wdts_num =3D 8; - sc->macs_num =3D 1; - sc->uarts_num =3D 13; - sc->num_cpus =3D 4; - sc->uarts_base =3D ASPEED_DEV_UART0; - sc->irqmap =3D aspeed_soc_ast2700a0_irqmap; - sc->memmap =3D aspeed_soc_ast2700_memmap; - sc->get_irq =3D aspeed_soc_ast2700_get_irq; -} - static void aspeed_soc_ast2700a1_class_init(ObjectClass *oc, const void *d= ata) { static const char * const valid_cpu_types[] =3D { @@ -1020,11 +944,6 @@ static const TypeInfo aspeed_soc_ast27x0_types[] =3D { .parent =3D TYPE_ASPEED_SOC, .instance_size =3D sizeof(Aspeed27x0SoCState), .abstract =3D true, - }, { - .name =3D "ast2700-a0", - .parent =3D TYPE_ASPEED27X0_SOC, - .instance_init =3D aspeed_soc_ast2700_init, - .class_init =3D aspeed_soc_ast2700a0_class_init, }, { .name =3D "ast2700-a1", --=20 2.43.0