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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Jiaxun Yang Reviewed-by: J=C3=A1n Tomko Reviewed-by: Richard Henderson --- MAINTAINERS | 1 - docs/about/deprecated.rst | 12 -- docs/about/removed-features.rst | 5 + docs/system/target-mips.rst | 11 -- configs/devices/mips-softmmu/common.mak | 1 - hw/mips/mipssim.c | 249 ------------------------ hw/mips/Kconfig | 7 - hw/mips/meson.build | 1 - 8 files changed, 5 insertions(+), 282 deletions(-) delete mode 100644 hw/mips/mipssim.c diff --git a/MAINTAINERS b/MAINTAINERS index 8f074e43712..6a2d3aa43bf 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1414,7 +1414,6 @@ F: tests/functional/mips*/test_tuxrun.py Mipssim R: Aleksandar Rikalo S: Orphan -F: hw/mips/mipssim.c F: hw/net/mipsnet.c =20 Fuloong 2E diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index d50645a0711..1b1e3f16337 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -323,18 +323,6 @@ and serves as the initial engineering sample rather th= an a production version. A newer revision, A1, is now supported, and the ``ast2700a1-evb`` should replace the older A0 version. =20 -Mips ``mipssim`` machine (since 10.0) -''''''''''''''''''''''''''''''''''''' - -Linux dropped support for this virtual machine type in kernel v3.7, and -there does not seem to be anybody around who is still using this board -in QEMU: Most former MIPS-related people are working on other architectures -in their everyday job nowadays, and we are also not aware of anybody still -using old binaries with this board (i.e. there is also no binary available -online to check that this board did not completely bitrot yet). It is -recommended to use another MIPS machine for future MIPS code development -instead. - RISC-V default machine option (since 10.0) '''''''''''''''''''''''''''''''''''''''''' =20 diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.= rst index d7c2113fc3e..2a277fac047 100644 --- a/docs/about/removed-features.rst +++ b/docs/about/removed-features.rst @@ -1099,6 +1099,11 @@ were added for little endian CPUs. Big endian suppor= t was never tested and likely never worked. Starting with QEMU v10.1, the machines are now only available as little-endian machines. =20 +Mips ``mipssim`` machine (removed in 10.2) +'''''''''''''''''''''''''''''''''''''''''' + +Linux dropped support for this virtual machine type in kernel v3.7, and +there was also no binary available online to use with that board. =20 linux-user mode CPUs -------------------- diff --git a/docs/system/target-mips.rst b/docs/system/target-mips.rst index 9028c3b304d..2a152e13380 100644 --- a/docs/system/target-mips.rst +++ b/docs/system/target-mips.rst @@ -12,8 +12,6 @@ machine types are emulated: =20 - An ACER Pica \"pica61\". This machine needs the 64-bit emulator. =20 -- MIPS emulator pseudo board \"mipssim\" - - A MIPS Magnum R4000 machine \"magnum\". This machine needs the 64-bit emulator. =20 @@ -80,15 +78,6 @@ The Loongson-3 virtual platform emulation supports: =20 - Both KVM and TCG supported =20 -The mipssim pseudo board emulation provides an environment similar to -what the proprietary MIPS emulator uses for running Linux. It supports: - -- A range of MIPS CPUs, default is the 24Kf - -- PC style serial port - -- MIPSnet network emulation - .. include:: cpu-models-mips.rst.inc =20 .. _nanoMIPS-System-emulator: diff --git a/configs/devices/mips-softmmu/common.mak b/configs/devices/mips= -softmmu/common.mak index b50107feafe..cdeae7ce450 100644 --- a/configs/devices/mips-softmmu/common.mak +++ b/configs/devices/mips-softmmu/common.mak @@ -6,4 +6,3 @@ =20 # Boards are selected by default, uncomment to keep out of the build. # CONFIG_MALTA=3Dn -# CONFIG_MIPSSIM=3Dn diff --git a/hw/mips/mipssim.c b/hw/mips/mipssim.c deleted file mode 100644 index e843307b9b6..00000000000 --- a/hw/mips/mipssim.c +++ /dev/null @@ -1,249 +0,0 @@ -/* - * QEMU/mipssim emulation - * - * Emulates a very simple machine model similar to the one used by the - * proprietary MIPS emulator. - * - * Copyright (c) 2007 Thiemo Seufer - * - * Permission is hereby granted, free of charge, to any person obtaining a= copy - * of this software and associated documentation files (the "Software"), t= o deal - * in the Software without restriction, including without limitation the r= ights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included= in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN - * THE SOFTWARE. - */ - -#include "qemu/osdep.h" -#include "qapi/error.h" -#include "qemu/datadir.h" -#include "system/address-spaces.h" -#include "hw/clock.h" -#include "hw/mips/mips.h" -#include "hw/char/serial-mm.h" -#include "net/net.h" -#include "system/system.h" -#include "hw/boards.h" -#include "hw/loader.h" -#include "elf.h" -#include "hw/sysbus.h" -#include "hw/qdev-properties.h" -#include "qemu/error-report.h" -#include "system/qtest.h" -#include "system/reset.h" -#include "cpu.h" - -#define BIOS_SIZE (4 * MiB) - -static struct _loaderparams { - int ram_size; - const char *kernel_filename; - const char *kernel_cmdline; - const char *initrd_filename; -} loaderparams; - -typedef struct ResetData { - MIPSCPU *cpu; - uint64_t vector; -} ResetData; - -static uint64_t load_kernel(void) -{ - uint64_t entry, kernel_high, initrd_size; - long kernel_size; - ram_addr_t initrd_offset; - - kernel_size =3D load_elf(loaderparams.kernel_filename, NULL, - cpu_mips_kseg0_to_phys, NULL, - &entry, NULL, - &kernel_high, NULL, - TARGET_BIG_ENDIAN ? ELFDATA2MSB : ELFDATA2LSB, - EM_MIPS, 1, 0); - if (kernel_size < 0) { - error_report("could not load kernel '%s': %s", - loaderparams.kernel_filename, - load_elf_strerror(kernel_size)); - exit(1); - } - - /* load initrd */ - initrd_size =3D 0; - initrd_offset =3D 0; - if (loaderparams.initrd_filename) { - initrd_size =3D get_image_size(loaderparams.initrd_filename); - if (initrd_size > 0) { - initrd_offset =3D ROUND_UP(kernel_high, INITRD_PAGE_SIZE); - if (initrd_offset + initrd_size > loaderparams.ram_size) { - error_report("memory too small for initial ram disk '%s'", - loaderparams.initrd_filename); - exit(1); - } - initrd_size =3D load_image_targphys(loaderparams.initrd_filena= me, - initrd_offset, loaderparams.ram_size - initrd_offset); - } - if (initrd_size =3D=3D (target_ulong) -1) { - error_report("could not load initial ram disk '%s'", - loaderparams.initrd_filename); - exit(1); - } - } - return entry; -} - -static void main_cpu_reset(void *opaque) -{ - ResetData *s =3D (ResetData *)opaque; - CPUMIPSState *env =3D &s->cpu->env; - - cpu_reset(CPU(s->cpu)); - env->active_tc.PC =3D s->vector & ~(target_ulong)1; - if (s->vector & 1) { - env->hflags |=3D MIPS_HFLAG_M16; - } -} - -static void mipsnet_init(int base, qemu_irq irq) -{ - DeviceState *dev; - SysBusDevice *s; - - dev =3D qemu_create_nic_device("mipsnet", true, NULL); - if (!dev) { - return; - } - - s =3D SYS_BUS_DEVICE(dev); - sysbus_realize_and_unref(s, &error_fatal); - sysbus_connect_irq(s, 0, irq); - memory_region_add_subregion(get_system_io(), - base, - sysbus_mmio_get_region(s, 0)); -} - -static void -mips_mipssim_init(MachineState *machine) -{ - const char *kernel_filename =3D machine->kernel_filename; - const char *kernel_cmdline =3D machine->kernel_cmdline; - const char *initrd_filename =3D machine->initrd_filename; - const char *bios_name =3D TARGET_BIG_ENDIAN ? "mips_bios.bin" - : "mipsel_bios.bin"; - char *filename; - MemoryRegion *address_space_mem =3D get_system_memory(); - MemoryRegion *isa =3D g_new(MemoryRegion, 1); - MemoryRegion *bios =3D g_new(MemoryRegion, 1); - Clock *cpuclk; - MIPSCPU *cpu; - CPUMIPSState *env; - ResetData *reset_info; - int bios_size; - - cpuclk =3D clock_new(OBJECT(machine), "cpu-refclk"); -#ifdef TARGET_MIPS64 - clock_set_hz(cpuclk, 6000000); /* 6 MHz */ -#else - clock_set_hz(cpuclk, 12000000); /* 12 MHz */ -#endif - - /* Init CPUs. */ - cpu =3D mips_cpu_create_with_clock(machine->cpu_type, cpuclk, - TARGET_BIG_ENDIAN); - env =3D &cpu->env; - - reset_info =3D g_new0(ResetData, 1); - reset_info->cpu =3D cpu; - reset_info->vector =3D env->active_tc.PC; - qemu_register_reset(main_cpu_reset, reset_info); - - /* Allocate RAM. */ - memory_region_init_rom(bios, NULL, "mips_mipssim.bios", BIOS_SIZE, - &error_fatal); - - memory_region_add_subregion(address_space_mem, 0, machine->ram); - - /* Map the BIOS / boot exception handler. */ - memory_region_add_subregion(address_space_mem, 0x1fc00000LL, bios); - /* Load a BIOS / boot exception handler image. */ - filename =3D qemu_find_file(QEMU_FILE_TYPE_BIOS, - machine->firmware ?: bios_name); - if (filename) { - bios_size =3D load_image_targphys(filename, 0x1fc00000LL, BIOS_SIZ= E); - g_free(filename); - } else { - bios_size =3D -1; - } - if ((bios_size < 0 || bios_size > BIOS_SIZE) && - machine->firmware && !qtest_enabled()) { - /* Bail out if we have neither a kernel image nor boot vector code= . */ - error_report("Could not load MIPS bios '%s'", machine->firmware); - exit(1); - } else { - /* We have a boot vector start address. */ - env->active_tc.PC =3D (target_long)(int32_t)0xbfc00000; - } - - if (kernel_filename) { - loaderparams.ram_size =3D machine->ram_size; - loaderparams.kernel_filename =3D kernel_filename; - loaderparams.kernel_cmdline =3D kernel_cmdline; - loaderparams.initrd_filename =3D initrd_filename; - reset_info->vector =3D load_kernel(); - } - - /* Init CPU internal devices. */ - cpu_mips_irq_init_cpu(cpu); - cpu_mips_clock_init(cpu); - - /* - * Register 64 KB of ISA IO space at 0x1fd00000. But without interrup= ts - * (except for the hardcoded serial port interrupt) -device cannot wor= k, - * so do not expose the ISA bus to the user. - */ - memory_region_init_alias(isa, NULL, "isa_mmio", - get_system_io(), 0, 0x00010000); - memory_region_add_subregion(get_system_memory(), 0x1fd00000, isa); - - /* - * A single 16450 sits at offset 0x3f8. It is attached to - * MIPS CPU INT2, which is interrupt 4. - */ - if (serial_hd(0)) { - DeviceState *dev =3D qdev_new(TYPE_SERIAL_MM); - - qdev_prop_set_chr(dev, "chardev", serial_hd(0)); - qdev_prop_set_uint8(dev, "regshift", 0); - qdev_prop_set_uint8(dev, "endianness", DEVICE_LITTLE_ENDIAN); - sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, env->irq[4]); - memory_region_add_subregion(get_system_io(), 0x3f8, - sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); - } - - /* MIPSnet uses the MIPS CPU INT0, which is interrupt 2. */ - mipsnet_init(0x4200, env->irq[2]); -} - -static void mips_mipssim_machine_init(MachineClass *mc) -{ - mc->desc =3D "MIPS MIPSsim platform"; - mc->init =3D mips_mipssim_init; -#ifdef TARGET_MIPS64 - mc->default_cpu_type =3D MIPS_CPU_TYPE_NAME("5Kf"); -#else - mc->default_cpu_type =3D MIPS_CPU_TYPE_NAME("24Kf"); -#endif - mc->default_ram_id =3D "mips_mipssim.ram"; -} - -DEFINE_MACHINE("mipssim", mips_mipssim_machine_init) diff --git a/hw/mips/Kconfig b/hw/mips/Kconfig index f84fffcd323..b59cb2f1114 100644 --- a/hw/mips/Kconfig +++ b/hw/mips/Kconfig @@ -13,13 +13,6 @@ config MALTA select SERIAL_MM select SMBUS_EEPROM =20 -config MIPSSIM - bool - default y - depends on MIPS - select SERIAL_MM - select MIPSNET - config JAZZ bool default y diff --git a/hw/mips/meson.build b/hw/mips/meson.build index 31dbd2bf4d9..390f0fd7f9d 100644 --- a/hw/mips/meson.build +++ b/hw/mips/meson.build @@ -8,7 +8,6 @@ mips_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('cps.c'= )) =20 if 'CONFIG_TCG' in config_all_accel mips_ss.add(when: 'CONFIG_JAZZ', if_true: files('jazz.c')) -mips_ss.add(when: 'CONFIG_MIPSSIM', if_true: files('mipssim.c')) mips_ss.add(when: 'CONFIG_FULOONG', if_true: files('fuloong2e.c')) mips_ss.add(when: 'CONFIG_MIPS_BOSTON', if_true: files('boston.c')) endif --=20 2.51.0 From nobody Mon Sep 8 03:36:52 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.libvirt.org designates 8.43.85.245 as permitted sender) client-ip=8.43.85.245; envelope-from=devel-bounces@lists.libvirt.org; helo=lists.libvirt.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.libvirt.org designates 8.43.85.245 as permitted sender) smtp.mailfrom=devel-bounces@lists.libvirt.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756392131; cv=none; d=zohomail.com; s=zohoarc; b=JnKOZK4Zkwi8ziA5tk/3XtcIDCUnUdSFH0AcQ+7HlgVBqMj1Wq8GbeUyVBAwiyFeJQyrhUsI8tzDHHohXM9GeAQkiI+SM7CxRkBhknP1hoz9lThJtHA4avzO0G8eVqreL88/eYW4XUBcnVbQ69l6jbFWKOeMHegrKirLbS5iHE8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756392131; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Owner:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=s1kz5AIExByLWtCTCBKM3lTyxgVVh7J2ReArYeuqvwk=; b=b+HlqAidkvOzZT6MiPeHU1Pkcg7bCC+OX33jj1T/vmVfFXtpKqclONhriMghFgAsF2JGSxbDBLPRmMRg8yamu2YJpHlaeUhKMpRlPdwXdtAExlnz1VeASN3XwFrn50zSv5ruld81FtC+yF8UpFG2cJJAaYrYI12kUy876WaNmPk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.libvirt.org designates 8.43.85.245 as permitted sender) smtp.mailfrom=devel-bounces@lists.libvirt.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.libvirt.org (lists.libvirt.org [8.43.85.245]) by mx.zohomail.com with SMTPS id 175639213131647.35770478522545; Thu, 28 Aug 2025 07:42:11 -0700 (PDT) Received: by lists.libvirt.org (Postfix, from userid 993) id 45CD2440D1; Thu, 28 Aug 2025 10:42:08 -0400 (EDT) Received: from [172.19.199.3] (lists.libvirt.org [8.43.85.245]) by lists.libvirt.org (Postfix) with ESMTP id D239544113; Thu, 28 Aug 2025 10:39:04 -0400 (EDT) Received: by lists.libvirt.org (Postfix, from userid 993) id 4D93F44036; Thu, 28 Aug 2025 10:38:55 -0400 (EDT) Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (3072 bits) server-digest SHA256) (No client certificate requested) by lists.libvirt.org (Postfix) with ESMTPS id 580E0440D7 for ; Thu, 28 Aug 2025 10:38:14 -0400 (EDT) Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-45b7c01a708so2513585e9.3 for ; Thu, 28 Aug 2025 07:38:14 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Remove as now dead code. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Jiaxun Yang Reviewed-by: J=C3=A1n Tomko Reviewed-by: Richard Henderson --- MAINTAINERS | 5 - hw/net/mipsnet.c | 297 -------------------------------------------- hw/net/Kconfig | 3 - hw/net/meson.build | 1 - hw/net/trace-events | 7 -- 5 files changed, 313 deletions(-) delete mode 100644 hw/net/mipsnet.c diff --git a/MAINTAINERS b/MAINTAINERS index 6a2d3aa43bf..e293dfdb20d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1411,11 +1411,6 @@ F: include/hw/southbridge/piix.h F: tests/functional/mips*/test_malta.py F: tests/functional/mips*/test_tuxrun.py =20 -Mipssim -R: Aleksandar Rikalo -S: Orphan -F: hw/net/mipsnet.c - Fuloong 2E M: Huacai Chen M: Philippe Mathieu-Daud=C3=A9 diff --git a/hw/net/mipsnet.c b/hw/net/mipsnet.c deleted file mode 100644 index 583aa1c7de6..00000000000 --- a/hw/net/mipsnet.c +++ /dev/null @@ -1,297 +0,0 @@ -#include "qemu/osdep.h" -#include "hw/irq.h" -#include "hw/qdev-properties.h" -#include "net/net.h" -#include "qemu/module.h" -#include "trace.h" -#include "hw/sysbus.h" -#include "migration/vmstate.h" -#include "qom/object.h" - -/* MIPSnet register offsets */ - -#define MIPSNET_DEV_ID 0x00 -#define MIPSNET_BUSY 0x08 -#define MIPSNET_RX_DATA_COUNT 0x0c -#define MIPSNET_TX_DATA_COUNT 0x10 -#define MIPSNET_INT_CTL 0x14 -# define MIPSNET_INTCTL_TXDONE 0x00000001 -# define MIPSNET_INTCTL_RXDONE 0x00000002 -# define MIPSNET_INTCTL_TESTBIT 0x80000000 -#define MIPSNET_INTERRUPT_INFO 0x18 -#define MIPSNET_RX_DATA_BUFFER 0x1c -#define MIPSNET_TX_DATA_BUFFER 0x20 - -#define MAX_ETH_FRAME_SIZE 1514 - -#define TYPE_MIPS_NET "mipsnet" -OBJECT_DECLARE_SIMPLE_TYPE(MIPSnetState, MIPS_NET) - -struct MIPSnetState { - SysBusDevice parent_obj; - - uint32_t busy; - uint32_t rx_count; - uint32_t rx_read; - uint32_t tx_count; - uint32_t tx_written; - uint32_t intctl; - uint8_t rx_buffer[MAX_ETH_FRAME_SIZE]; - uint8_t tx_buffer[MAX_ETH_FRAME_SIZE]; - MemoryRegion io; - qemu_irq irq; - NICState *nic; - NICConf conf; -}; - -static void mipsnet_reset(MIPSnetState *s) -{ - s->busy =3D 1; - s->rx_count =3D 0; - s->rx_read =3D 0; - s->tx_count =3D 0; - s->tx_written =3D 0; - s->intctl =3D 0; - memset(s->rx_buffer, 0, MAX_ETH_FRAME_SIZE); - memset(s->tx_buffer, 0, MAX_ETH_FRAME_SIZE); -} - -static void mipsnet_update_irq(MIPSnetState *s) -{ - int isr =3D !!s->intctl; - trace_mipsnet_irq(isr, s->intctl); - qemu_set_irq(s->irq, isr); -} - -static int mipsnet_buffer_full(MIPSnetState *s) -{ - if (s->rx_count >=3D MAX_ETH_FRAME_SIZE) { - return 1; - } - return 0; -} - -static int mipsnet_can_receive(NetClientState *nc) -{ - MIPSnetState *s =3D qemu_get_nic_opaque(nc); - - if (s->busy) { - return 0; - } - return !mipsnet_buffer_full(s); -} - -static ssize_t mipsnet_receive(NetClientState *nc, - const uint8_t *buf, size_t size) -{ - MIPSnetState *s =3D qemu_get_nic_opaque(nc); - - trace_mipsnet_receive(size); - if (!mipsnet_can_receive(nc)) { - return 0; - } - - if (size >=3D sizeof(s->rx_buffer)) { - return 0; - } - s->busy =3D 1; - - /* Just accept everything. */ - - /* Write packet data. */ - memcpy(s->rx_buffer, buf, size); - - s->rx_count =3D size; - s->rx_read =3D 0; - - /* Now we can signal we have received something. */ - s->intctl |=3D MIPSNET_INTCTL_RXDONE; - mipsnet_update_irq(s); - - return size; -} - -static uint64_t mipsnet_ioport_read(void *opaque, hwaddr addr, - unsigned int size) -{ - MIPSnetState *s =3D opaque; - int ret =3D 0; - - addr &=3D 0x3f; - switch (addr) { - case MIPSNET_DEV_ID: - ret =3D be32_to_cpu(0x4d495053); /* MIPS */ - break; - case MIPSNET_DEV_ID + 4: - ret =3D be32_to_cpu(0x4e455430); /* NET0 */ - break; - case MIPSNET_BUSY: - ret =3D s->busy; - break; - case MIPSNET_RX_DATA_COUNT: - ret =3D s->rx_count; - break; - case MIPSNET_TX_DATA_COUNT: - ret =3D s->tx_count; - break; - case MIPSNET_INT_CTL: - ret =3D s->intctl; - s->intctl &=3D ~MIPSNET_INTCTL_TESTBIT; - break; - case MIPSNET_INTERRUPT_INFO: - /* XXX: This seems to be a per-VPE interrupt number. */ - ret =3D 0; - break; - case MIPSNET_RX_DATA_BUFFER: - if (s->rx_count) { - s->rx_count--; - ret =3D s->rx_buffer[s->rx_read++]; - if (mipsnet_can_receive(s->nic->ncs)) { - qemu_flush_queued_packets(qemu_get_queue(s->nic)); - } - } - break; - /* Reads as zero. */ - case MIPSNET_TX_DATA_BUFFER: - default: - break; - } - trace_mipsnet_read(addr, ret); - return ret; -} - -static void mipsnet_ioport_write(void *opaque, hwaddr addr, - uint64_t val, unsigned int size) -{ - MIPSnetState *s =3D opaque; - - addr &=3D 0x3f; - trace_mipsnet_write(addr, val); - switch (addr) { - case MIPSNET_TX_DATA_COUNT: - s->tx_count =3D (val <=3D MAX_ETH_FRAME_SIZE) ? val : 0; - s->tx_written =3D 0; - break; - case MIPSNET_INT_CTL: - if (val & MIPSNET_INTCTL_TXDONE) { - s->intctl &=3D ~MIPSNET_INTCTL_TXDONE; - } else if (val & MIPSNET_INTCTL_RXDONE) { - s->intctl &=3D ~MIPSNET_INTCTL_RXDONE; - } else if (val & MIPSNET_INTCTL_TESTBIT) { - mipsnet_reset(s); - s->intctl |=3D MIPSNET_INTCTL_TESTBIT; - } else if (!val) { - /* ACK testbit interrupt, flag was cleared on read. */ - } - s->busy =3D !!s->intctl; - mipsnet_update_irq(s); - if (mipsnet_can_receive(s->nic->ncs)) { - qemu_flush_queued_packets(qemu_get_queue(s->nic)); - } - break; - case MIPSNET_TX_DATA_BUFFER: - s->tx_buffer[s->tx_written++] =3D val; - if ((s->tx_written >=3D MAX_ETH_FRAME_SIZE) - || (s->tx_written =3D=3D s->tx_count)) { - /* Send buffer. */ - trace_mipsnet_send(s->tx_written); - qemu_send_packet(qemu_get_queue(s->nic), - s->tx_buffer, s->tx_written); - s->tx_count =3D s->tx_written =3D 0; - s->intctl |=3D MIPSNET_INTCTL_TXDONE; - s->busy =3D 1; - mipsnet_update_irq(s); - } - break; - /* Read-only registers */ - case MIPSNET_DEV_ID: - case MIPSNET_BUSY: - case MIPSNET_RX_DATA_COUNT: - case MIPSNET_INTERRUPT_INFO: - case MIPSNET_RX_DATA_BUFFER: - default: - break; - } -} - -static const VMStateDescription vmstate_mipsnet =3D { - .name =3D "mipsnet", - .version_id =3D 0, - .minimum_version_id =3D 0, - .fields =3D (const VMStateField[]) { - VMSTATE_UINT32(busy, MIPSnetState), - VMSTATE_UINT32(rx_count, MIPSnetState), - VMSTATE_UINT32(rx_read, MIPSnetState), - VMSTATE_UINT32(tx_count, MIPSnetState), - VMSTATE_UINT32(tx_written, MIPSnetState), - VMSTATE_UINT32(intctl, MIPSnetState), - VMSTATE_BUFFER(rx_buffer, MIPSnetState), - VMSTATE_BUFFER(tx_buffer, MIPSnetState), - VMSTATE_END_OF_LIST() - } -}; - -static NetClientInfo net_mipsnet_info =3D { - .type =3D NET_CLIENT_DRIVER_NIC, - .size =3D sizeof(NICState), - .receive =3D mipsnet_receive, -}; - -static const MemoryRegionOps mipsnet_ioport_ops =3D { - .read =3D mipsnet_ioport_read, - .write =3D mipsnet_ioport_write, - .impl.min_access_size =3D 1, - .impl.max_access_size =3D 4, -}; - -static void mipsnet_realize(DeviceState *dev, Error **errp) -{ - SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); - MIPSnetState *s =3D MIPS_NET(dev); - - memory_region_init_io(&s->io, OBJECT(dev), &mipsnet_ioport_ops, s, - "mipsnet-io", 36); - sysbus_init_mmio(sbd, &s->io); - sysbus_init_irq(sbd, &s->irq); - - s->nic =3D qemu_new_nic(&net_mipsnet_info, &s->conf, - object_get_typename(OBJECT(dev)), dev->id, - &dev->mem_reentrancy_guard, s); - qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); -} - -static void mipsnet_sysbus_reset(DeviceState *dev) -{ - MIPSnetState *s =3D MIPS_NET(dev); - mipsnet_reset(s); -} - -static const Property mipsnet_properties[] =3D { - DEFINE_NIC_PROPERTIES(MIPSnetState, conf), -}; - -static void mipsnet_class_init(ObjectClass *klass, const void *data) -{ - DeviceClass *dc =3D DEVICE_CLASS(klass); - - dc->realize =3D mipsnet_realize; - set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); - dc->desc =3D "MIPS Simulator network device"; - device_class_set_legacy_reset(dc, mipsnet_sysbus_reset); - dc->vmsd =3D &vmstate_mipsnet; - device_class_set_props(dc, mipsnet_properties); -} - -static const TypeInfo mipsnet_info =3D { - .name =3D TYPE_MIPS_NET, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(MIPSnetState), - .class_init =3D mipsnet_class_init, -}; - -static void mipsnet_register_types(void) -{ - type_register_static(&mipsnet_info); -} - -type_init(mipsnet_register_types) diff --git a/hw/net/Kconfig b/hw/net/Kconfig index 7f80218d10f..2b513d68958 100644 --- a/hw/net/Kconfig +++ b/hw/net/Kconfig @@ -82,9 +82,6 @@ config OPENCORES_ETH config XGMAC bool =20 -config MIPSNET - bool - config ALLWINNER_EMAC bool =20 diff --git a/hw/net/meson.build b/hw/net/meson.build index e6759e26ca6..913eaedbc52 100644 --- a/hw/net/meson.build +++ b/hw/net/meson.build @@ -23,7 +23,6 @@ system_ss.add(when: 'CONFIG_LAN9118_PHY', if_true: files(= 'lan9118_phy.c')) system_ss.add(when: 'CONFIG_NE2000_ISA', if_true: files('ne2000-isa.c')) system_ss.add(when: 'CONFIG_OPENCORES_ETH', if_true: files('opencores_eth.= c')) system_ss.add(when: 'CONFIG_XGMAC', if_true: files('xgmac.c')) -system_ss.add(when: 'CONFIG_MIPSNET', if_true: files('mipsnet.c')) system_ss.add(when: 'CONFIG_XILINX_AXI', if_true: files('xilinx_axienet.c'= )) system_ss.add(when: 'CONFIG_ALLWINNER_EMAC', if_true: files('allwinner_ema= c.c')) system_ss.add(when: 'CONFIG_ALLWINNER_SUN8I_EMAC', if_true: files('allwinn= er-sun8i-emac.c')) diff --git a/hw/net/trace-events b/hw/net/trace-events index 72b69c4a8bb..e82d7490c33 100644 --- a/hw/net/trace-events +++ b/hw/net/trace-events @@ -20,13 +20,6 @@ lan9118_phy_reset(void) "" lance_mem_readw(uint64_t addr, uint32_t ret) "addr=3D0x%"PRIx64"val=3D0x%0= 4x" lance_mem_writew(uint64_t addr, uint32_t val) "addr=3D0x%"PRIx64"val=3D0x%= 04x" =20 -# mipsnet.c -mipsnet_send(uint32_t size) "sending len=3D%u" -mipsnet_receive(uint32_t size) "receiving len=3D%u" -mipsnet_read(uint64_t addr, uint32_t val) "read addr=3D0x%" PRIx64 " val= =3D0x%x" -mipsnet_write(uint64_t addr, uint64_t val) "write addr=3D0x%" PRIx64 " val= =3D0x%" PRIx64 -mipsnet_irq(uint32_t isr, uint32_t intctl) "set irq to %d (0x%02x)" - # ne2000.c ne2000_read(uint64_t addr, uint64_t val) "read addr=3D0x%" PRIx64 " val=3D= 0x%" PRIx64 ne2000_write(uint64_t addr, uint64_t val) "write addr=3D0x%" PRIx64 " val= =3D0x%" PRIx64 --=20 2.51.0