From nobody Sun Dec 14 12:17:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.libvirt.org designates 8.43.85.245 as permitted sender) client-ip=8.43.85.245; envelope-from=devel-bounces@lists.libvirt.org; helo=lists.libvirt.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@intel.com; spf=pass (zohomail.com: domain of lists.libvirt.org designates 8.43.85.245 as permitted sender) smtp.mailfrom=devel-bounces@lists.libvirt.org; dmarc=fail(p=none dis=none) header.from=intel.com Return-Path: Received: from lists.libvirt.org (lists.libvirt.org [8.43.85.245]) by mx.zohomail.com with SMTPS id 1751264819316550.1353777878253; Sun, 29 Jun 2025 23:26:59 -0700 (PDT) Received: by lists.libvirt.org (Postfix, from userid 996) id 6658D1441; Mon, 30 Jun 2025 02:26:58 -0400 (EDT) Received: from lists.libvirt.org (localhost [IPv6:::1]) by lists.libvirt.org (Postfix) with ESMTP id 5B6A11532; Mon, 30 Jun 2025 02:22:34 -0400 (EDT) Received: by lists.libvirt.org (Postfix, from userid 996) id 5CEB313A1; Mon, 30 Jun 2025 02:22:29 -0400 (EDT) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.libvirt.org (Postfix) with ESMTPS id B85CC13A1 for ; Mon, 30 Jun 2025 02:22:05 -0400 (EDT) Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jun 2025 23:22:05 -0700 Received: from spr-s2600bt.bj.intel.com ([10.240.192.127]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jun 2025 23:22:03 -0700 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on lists.libvirt.org X-Spam-Level: X-Spam-Status: No, score=-3.1 required=5.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED, RCVD_IN_VALIDITY_RPBL_BLOCKED,RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_NONE autolearn=unavailable autolearn_force=no version=3.4.4 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1751264526; x=1782800526; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cmATkZ55MqAus8gjChdVdwBMVAiUjNy4h2zNTSaqRQI=; b=DTwi1OYot9tWj7s53EVwti/mVF/EdBN0AsYIRM7NPzzWg1R3uxZOx5jj /r2c/sSDGtIj9jj+PB2xUw5nIEtQrJqwpMYt9PaQyyLElNiSk/pif684p 4evjxwlWg0Umjvo6djzH4l70YwqXAyA1C3xOFMOCMpWhjWIHuzM2c3S0e NQsVdTpqEnuyKDixz1jmVJ0i/BczBSJlwvbwNtjkGOBkOADWUcg9xiXw/ ibQIf+xIijEhiYNZpJmfB2MNmMhRJB/T2mt46/mN9mvx09AtAasXVxsxF 0hf75UNVekvmS/0VAEAaJUsHagrJ4/wSeUetdGzDU3u/fYLK32OhJ7yj2 g==; X-CSE-ConnectionGUID: LmwkvxROSCaa7/QppgH2bw== X-CSE-MsgGUID: yfiuUhHeSouPHPHCFgCIeA== X-IronPort-AV: E=McAfee;i="6800,10657,11479"; a="70912538" X-IronPort-AV: E=Sophos;i="6.16,277,1744095600"; d="scan'208";a="70912538" X-CSE-ConnectionGUID: niYzgtsSSpGSRDcFvm2ZEA== X-CSE-MsgGUID: C33z1DPmRAyH36azcuqecQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,277,1744095600"; d="scan'208";a="153549355" From: Zhenzhong Duan To: devel@lists.libvirt.org Subject: [PATCH v3 11/21] qemu: Force special parameters enabled for TDX guest Date: Mon, 30 Jun 2025 14:17:22 +0800 Message-Id: <20250630061732.303374-12-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250630061732.303374-1-zhenzhong.duan@intel.com> References: <20250630061732.303374-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-ID-Hash: 2SW3A35W3T7AUM2VSLJYQQYOFDSJZX4M X-Message-ID-Hash: 2SW3A35W3T7AUM2VSLJYQQYOFDSJZX4M X-MailFrom: zhenzhong.duan@intel.com X-Mailman-Rule-Hits: nonmember-moderation X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-config-1; header-match-config-2; header-match-config-3; header-match-devel.lists.libvirt.org-0 CC: phrdina@redhat.com, pkrempa@redhat.com, jjongsma@redhat.com, jsuchane@redhat.com, chenyi.qiang@intel.com, isaku.yamahata@intel.com, xiaoyao.li@intel.com, chao.p.peng@intel.com, Zhenzhong Duan X-Mailman-Version: 3.2.2 Precedence: list List-Id: Development discussions about the libvirt library & tools Archived-At: List-Archive: List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1751264820592116600 Content-Type: text/plain; charset="utf-8" TDX guest requires some special parameters to boot, currently: "kernel_irqchip=3Dsplit" "pmu!=3Don" "smm!=3Don" "-bios" If not specified explicitly, QEMU should configure this option implicitly when start a TDX guest. Signed-off-by: Zhenzhong Duan Reviewed-by: Daniel P. Berrang=C3=A9 --- src/qemu/qemu_validate.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/src/qemu/qemu_validate.c b/src/qemu/qemu_validate.c index ef9f326a9b..adba3e4a89 100644 --- a/src/qemu/qemu_validate.c +++ b/src/qemu/qemu_validate.c @@ -1425,6 +1425,38 @@ qemuValidateDomainDef(const virDomainDef *def, _("Only bit0(debug) and bit28(sept-ve-disab= le) are supported intel TDX launch security policy")); return -1; } + if (def->features[VIR_DOMAIN_FEATURE_IOAPIC] =3D=3D VIR_DOMAIN= _IOAPIC_KVM) { + virReportError(VIR_ERR_CONFIG_UNSUPPORTED, "%s", + _("Intel TDX launch security needs split ke= rnel irqchip")); + return -1; + } + /* Current KVM doesn't support PMU for TD guest. It returns + * error if TD is created with PMU bit being set in attributes. + * By default, QEMU disable PMU for TD guest. + */ + if (def->features[VIR_DOMAIN_FEATURE_PMU] =3D=3D VIR_TRISTATE_= SWITCH_ON) { + virReportError(VIR_ERR_CONFIG_UNSUPPORTED, "%s", + _("Intel TDX launch security is not support= ed with PMU enabled")); + return -1; + } + /* TDX doesn't support SMM and VMM cannot emulate SMM for TDX = VMs + * because VMM cannot manipulate TDX VM's memory. + * By default, QEMU disable SMM for TD guest. + */ + if (def->features[VIR_DOMAIN_FEATURE_SMM] =3D=3D VIR_TRISTATE_= SWITCH_ON) { + virReportError(VIR_ERR_CONFIG_UNSUPPORTED, "%s", + _("Intel TDX launch security is not support= ed with SMM enabled")); + return -1; + } + /* TDVF(OVMF) needs to run at private memory for TD guest. TDX= cannot + * support pflash device since it doesn't support read-only pr= ivate memory. + * Thus load TDVF(OVMF) with -bios option for TDs. + */ + if (def->os.loader && def->os.loader->type =3D=3D VIR_DOMAIN_L= OADER_TYPE_PFLASH) { + virReportError(VIR_ERR_CONFIG_UNSUPPORTED, "%s", + _("Intel TDX launch security is not support= ed with pflash loader")); + return -1; + } break; case VIR_DOMAIN_LAUNCH_SECURITY_NONE: case VIR_DOMAIN_LAUNCH_SECURITY_LAST: --=20 2.34.1