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no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-config-1; header-match-config-2; header-match-config-3; header-match-devel.lists.libvirt.org-0 CC: Jason Wang , Paolo Bonzini , Richard Henderson , devel@lists.libvirt.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , "Edgar E. Iglesias" , Thomas Huth , qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Peter Maydell , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= X-Mailman-Version: 3.2.2 Precedence: list List-Id: Development discussions about the libvirt library & tools Archived-At: List-Archive: List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1731081036131116600 Content-Type: text/plain; charset="utf-8" Consider the CPU ENDI bit, swap instructions when the CPU endianness doesn't match the binary one. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/microblaze/cpu.h | 7 +++++++ target/microblaze/translate.c | 5 +++-- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 3e5a3e5c60..6d540713eb 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -412,6 +412,13 @@ void mb_tcg_init(void); /* Ensure there is no overlap between the two masks. */ QEMU_BUILD_BUG_ON(MSR_TB_MASK & IFLAGS_TB_MASK); =20 +static inline bool mb_cpu_is_big_endian(CPUState *cs) +{ + MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); + + return !cpu->cfg.endi; +} + static inline void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) { diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 0b466db694..5595ae4fad 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -709,7 +709,7 @@ static void record_unaligned_ess(DisasContext *dc, int = rd, =20 static inline MemOp mo_endian(DisasContext *dc) { - return MO_TE; + return dc->cfg->endi ? MO_LE : MO_BE; } =20 static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop, @@ -1646,7 +1646,8 @@ static void mb_tr_translate_insn(DisasContextBase *dc= b, CPUState *cs) =20 dc->tb_flags_to_set =3D 0; =20 - ir =3D translator_ldl(cpu_env(cs), &dc->base, dc->base.pc_next); + ir =3D translator_ldl_swap(cpu_env(cs), &dc->base, dc->base.pc_next, + mb_cpu_is_big_endian(cs) !=3D TARGET_BIG_ENDI= AN); if (!decode(dc, ir)) { trap_illegal(dc, true); } --=20 2.45.2