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Iglesias" , qemu-arm@nongnu.org, Peter Maydell , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 09/16] hw/ssi/xilinx_spips: Make device endianness configurable Date: Thu, 7 Nov 2024 01:22:15 +0000 Message-ID: <20241107012223.94337-10-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241107012223.94337-1-philmd@linaro.org> References: <20241107012223.94337-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1730942746982116600 Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN. Add the "little-endian" property to select the device endianness, defaulting to little endian. Set the proper endianness on the single machine using the device. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/ssi/xilinx_spips.h | 1 + hw/arm/xilinx_zynq.c | 1 + hw/ssi/xilinx_spips.c | 46 ++++++++++++++++++++++++++--------- 3 files changed, 36 insertions(+), 12 deletions(-) diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h index 7a754bf67a..451c3758b3 100644 --- a/include/hw/ssi/xilinx_spips.h +++ b/include/hw/ssi/xilinx_spips.h @@ -101,6 +101,7 @@ typedef struct XilinxQSPIPS XilinxQSPIPS; struct XlnxZynqMPQSPIPS { XilinxQSPIPS parent_obj; =20 + bool little_endian_model; StreamSink *dma; int gqspi_irqline; =20 diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index fde4d946b7..bcc0022c17 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -142,6 +142,7 @@ static inline int zynq_init_spi_flashes(uint32_t base_a= ddr, qemu_irq irq, int num_ss =3D is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES; =20 dev =3D qdev_new(is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi"); + qdev_prop_set_bit(dev, "little-endian", true); qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1); qdev_prop_set_uint8(dev, "num-ss-bits", num_ss); qdev_prop_set_uint8(dev, "num-busses", num_busses); diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index aeb462c3ce..5c6f0dd079 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -1251,17 +1251,32 @@ static MemTxResult lqspi_write(void *opaque, hwaddr= offset, uint64_t value, return MEMTX_ERROR; } =20 -static const MemoryRegionOps lqspi_ops =3D { - .read_with_attrs =3D lqspi_read, - .write_with_attrs =3D lqspi_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, - .impl =3D { - .min_access_size =3D 4, - .max_access_size =3D 4, +static const MemoryRegionOps lqspi_ops[2] =3D { + { + .read_with_attrs =3D lqspi_read, + .write_with_attrs =3D lqspi_write, + .endianness =3D DEVICE_BIG_ENDIAN, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4 + }, }, - .valid =3D { - .min_access_size =3D 1, - .max_access_size =3D 4 + { + .read_with_attrs =3D lqspi_read, + .write_with_attrs =3D lqspi_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + }, } }; =20 @@ -1325,8 +1340,9 @@ static void xilinx_qspips_realize(DeviceState *dev, E= rror **errp) s->num_txrx_bytes =3D 4; =20 xilinx_spips_realize(dev, errp); - memory_region_init_io(&s->mmlqspi, OBJECT(s), &lqspi_ops, s, "lqspi", - (1 << LQSPI_ADDRESS_BITS) * 2); + memory_region_init_io(&s->mmlqspi, OBJECT(s), + &lqspi_ops[s->little_endian_model], + s, "lqspi", (1 << LQSPI_ADDRESS_BITS) * 2); sysbus_init_mmio(sbd, &s->mmlqspi); =20 q->lqspi_cached_addr =3D ~0ULL; @@ -1432,12 +1448,18 @@ static Property xilinx_spips_properties[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +static Property xilinx_qspips_properties[] =3D { + DEFINE_PROP_BOOL("little-endian", XilinxQSPIPS, little_endian_model, t= rue), + DEFINE_PROP_END_OF_LIST(), +}; + static void xilinx_qspips_class_init(ObjectClass *klass, void * data) { DeviceClass *dc =3D DEVICE_CLASS(klass); XilinxSPIPSClass *xsc =3D XILINX_SPIPS_CLASS(klass); =20 dc->realize =3D xilinx_qspips_realize; + device_class_set_props(dc, xilinx_qspips_properties); xsc->reg_ops =3D &qspips_ops; xsc->reg_size =3D XLNX_SPIPS_R_MAX * 4; xsc->rx_fifo_size =3D RXFF_A_Q; --=20 2.45.2