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[88.29.160.86]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-381c113e528sm16313895f8f.78.2024.11.05.05.05.45 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 05 Nov 2024 05:05:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1730811948; x=1731416748; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UmQHqWTaQOMkWHXP0Jn/QpgcUfCH1B37UiHSpX6N2KA=; b=s5HPSlAwC2nA+to5RFYRJHwjdxqCcpkRZTt+rMvMVhefAgAA6uPMsU/1ILGUOCMtUL Sk4japgXgFTaW4BRSox/gTdrBSrXrn0iM3pFSrkrYlUjMLqk6VBjfFr2cX3ChPGLCDNk Uu2mUHdtrZvQhmshMSqJLQO9GMDHXwHbIdTR/EI9kQiN8x6bL+xHF7w5GuyQvvaOjAMw 9Llwloovy8KhI7Fu8Ub71BH5Z/nmNllEZFjKvlliuLRePn0HwqrvKLLwup2Ck3FvlMhx 2W8/o6fVYisL6Olt0uz0GYBxPmvmi4hR8aTaJV0YhTp6FURjybGWvW//u9Vi20Advcyq A54Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730811948; x=1731416748; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UmQHqWTaQOMkWHXP0Jn/QpgcUfCH1B37UiHSpX6N2KA=; b=W+CI1cfOBAyJXx5aw2ol/3jsyBlMcv6lh1RTKsT5IM9WG1OfMTQCfR5lT+szdQtHtY ykwKPhmxmUvQbNT++qRoqK5wacDaLGrTQWcmQKzb+cDKI90V0F6cydg52zijRHYnP9lN nKCfo24NanGSrz8iON8xmPGrlLXyUuXzr692RYL5MZPE59Z3D+9bQiHD4OMtZ+3NLq+b xR4NpfhaznWZRW63yHcA3nbQrybpzY7IvgcxdJLzlrnxGIOCqbkUiImXt3uH6gBEKpAF q2BnfU9MZhzjwi/4n2Cz4DQB1qpfb68/7tOdw/hLAHXrGs5GaCECQagpYDVdpiMMAas6 5izA== X-Gm-Message-State: AOJu0YyWsSJtuFrPyD7Qh5Nm22iPLNQmHpWgSBqUswmgQqT5PRR6PnSO XSgYSj5kbKSR+pObMMOoLSgMYw6olC14evhmoluKjsOXJM/3KJ0ExreD9AJoBsQBkLR4in7+EyS Lov4= X-Google-Smtp-Source: AGHT+IF9LFFphDUgWLEt7s3C/xmfz8xwqCoBamUp4pLN6Hxf/UouJKv/9GK36kiEoganAkopqGhI5g== X-Received: by 2002:a05:6512:10d1:b0:539:f10b:ff93 with SMTP id 2adb3069b0e04-53d65df7cb4mr6726958e87.27.1730811948119; Tue, 05 Nov 2024 05:05:48 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Anton Johansson Cc: "Edgar E. Iglesias" , Peter Maydell , Alistair Francis , Thomas Huth , qemu-arm@nongnu.org, devel@lists.libvirt.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , Jason Wang , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 07/19] hw/microblaze: Restrict MemoryRegionOps are implemented as 32-bit Date: Tue, 5 Nov 2024 14:04:19 +0100 Message-ID: <20241105130431.22564-8-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241105130431.22564-1-philmd@linaro.org> References: <20241105130431.22564-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::12a; envelope-from=philmd@linaro.org; helo=mail-lf1-x12a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1730811975926116600 All these MemoryRegionOps read() and write() handlers are implemented expecting 32-bit accesses. Clarify that setting .impl.min/max_access_size fields. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Anton Johansson --- hw/char/xilinx_uartlite.c | 4 ++++ hw/intc/xilinx_intc.c | 4 ++++ hw/net/xilinx_ethlite.c | 4 ++++ hw/timer/xilinx_timer.c | 4 ++++ 4 files changed, 16 insertions(+) diff --git a/hw/char/xilinx_uartlite.c b/hw/char/xilinx_uartlite.c index a69ad769cc4..892efe81fee 100644 --- a/hw/char/xilinx_uartlite.c +++ b/hw/char/xilinx_uartlite.c @@ -170,6 +170,10 @@ static const MemoryRegionOps uart_ops =3D { .read =3D uart_read, .write =3D uart_write, .endianness =3D DEVICE_NATIVE_ENDIAN, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, .valid =3D { .min_access_size =3D 1, .max_access_size =3D 4, diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c index 2b8246f6206..1762b34564e 100644 --- a/hw/intc/xilinx_intc.c +++ b/hw/intc/xilinx_intc.c @@ -144,6 +144,10 @@ static const MemoryRegionOps pic_ops =3D { .read =3D pic_read, .write =3D pic_write, .endianness =3D DEVICE_NATIVE_ENDIAN, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index 11eb53c4d60..ede7c172748 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -170,6 +170,10 @@ static const MemoryRegionOps eth_ops =3D { .read =3D eth_read, .write =3D eth_write, .endianness =3D DEVICE_NATIVE_ENDIAN, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c index 0822345779c..28ac95edea1 100644 --- a/hw/timer/xilinx_timer.c +++ b/hw/timer/xilinx_timer.c @@ -193,6 +193,10 @@ static const MemoryRegionOps timer_ops =3D { .read =3D timer_read, .write =3D timer_write, .endianness =3D DEVICE_NATIVE_ENDIAN, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, --=20 2.45.2