From nobody Thu Nov 21 17:09:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1730812099; cv=none; d=zohomail.com; s=zohoarc; b=O9g4hZdQhuAO0oJXdtEnwDdCK7UdHluCvRucaJNTZnwH6Cr+poOVpy8YYjgfFjXAKg0TXMWjihF0N8BB114JFwxFxrs0Ozc2thPiT9OQyyY9ZNh467ieUkV2mqB/xEVBQQtqYMHQ3nWCsMLgkeQQ+pN3qno4Ky3nNXw20lLeRys= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1730812099; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=2HA1iYoQhge6HN2CHRy7t3YqB3wWBO4DLLl9qjbY1CM=; b=g0zqbifTHFjdarXFsxtu9oJyF6gjdQDqBE01nfr3y52OGKpbVo1BOuyRcVSiHDR24zE93F1OgAiT5yFs+KkzSPUl6intaI8EE7Y1wjHgdo+ITmW7MPrD3QwITZDOHJbU0IBm7yq+clCGmx214Lt4gqqjflKGr1LoARhiE2BJp1s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1730812098939745.7244869045616; Tue, 5 Nov 2024 05:08:18 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t8JGy-0006Om-B4; Tue, 05 Nov 2024 08:07:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t8JGk-00064L-LF for qemu-devel@nongnu.org; Tue, 05 Nov 2024 08:06:50 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1t8JGh-0002ec-Mw for qemu-devel@nongnu.org; Tue, 05 Nov 2024 08:06:50 -0500 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-37d4ac91d97so4578004f8f.2 for ; Tue, 05 Nov 2024 05:06:47 -0800 (PST) Received: from localhost.localdomain (86.red-88-29-160.dynamicip.rima-tde.net. [88.29.160.86]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-381c10d4d1fsm16076930f8f.38.2024.11.05.05.06.42 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 05 Nov 2024 05:06:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1730812006; x=1731416806; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2HA1iYoQhge6HN2CHRy7t3YqB3wWBO4DLLl9qjbY1CM=; b=Lpo9L8RkA4YYSK/qvcTHeX06Up0oGGU189jK6IG9s3BkMb+IThDvaeAjn5RfdLUGKN f2VXhFE3fVZDYu3IYU5QqAojUS70baIaahc/IwwM1lfS807lC84wBEDmLI33X9unujm/ Fg1oihOaT6YkHb2nIlvv+VTfB6xWvylHbwrJyFJZTGE4jZ4bNyIjcSdDy/qKIYllDOj4 yq8W/rkUeLt3mD49yXVnJl2g5Gs/L2H/LzKz0eyOLBdM7/yLgBW3KiF3yTfWlBWRzpNe qqaIFNWhwOMJ52/tHePpYvBPTllS6X4kB3xl8lCovgNFN0KGIwboagxCANvq/kZ9cRxc gpiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730812006; x=1731416806; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2HA1iYoQhge6HN2CHRy7t3YqB3wWBO4DLLl9qjbY1CM=; b=BB0v0nfLoJrpBTuzP9eH5aZQWckwK/inN/TgPjZSreUZiVA9kldvzMstODpdzcffac 7D7BiTrkOS+XOl0mBgMLRBH99+IrWgybzoEqDYnYxMDJnXNmbh8k02yCjIdXNWnC4Opz ZDQD/GwptjTQcrXMauotDSgIoZWlWA03lRz5IY+u2puJfzAfBfY83j8HMxTbEl6xcGfu jTzAX4tfuYiv0/7X30nXcNBs6lwbBAF1SPtvVVPbC46LXAAyVUmE3FoJLIz6VVriqDfI /ZI/vscVK+uRF3l5rA1om8nxLeu3z7pKIaDB+YK0WCW1F1qKPiWvLYaw0LSzoCLzGdO6 1LpQ== X-Gm-Message-State: AOJu0YxidGYEAKlYlTsPqRrw7t28VQe0kISJWhLFzF36QRrRpes+hjfY /vegvHVhH4HU6Yx43CkMxkq6/q3fA677DM2nPRxylD6BQCgxjXmiGyD6wl26HWawi4yGPTkQRkm vS0M= X-Google-Smtp-Source: AGHT+IHFlOyH7jLqLmVJWiSq5ZAd02Ui4PVZS15kFWcQDOeKoizvayG3iUaxo7TlK8hsaSPPS+Hcow== X-Received: by 2002:a05:6000:1a8c:b0:37d:5042:c8de with SMTP id ffacd0b85a97d-381c7a5d4eemr16315520f8f.22.1730812005816; Tue, 05 Nov 2024 05:06:45 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Anton Johansson Cc: "Edgar E. Iglesias" , Peter Maydell , Alistair Francis , Thomas Huth , qemu-arm@nongnu.org, devel@lists.libvirt.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , Jason Wang , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 13/19] target/microblaze: Explode MO_TExx -> MO_TE | MO_xx Date: Tue, 5 Nov 2024 14:04:25 +0100 Message-ID: <20241105130431.22564-14-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241105130431.22564-1-philmd@linaro.org> References: <20241105130431.22564-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1730812101672116600 Extract the implicit MO_TE definition in order to replace it by runtime variable in the next commit. Mechanical change using: $ for n in UW UL UQ UO SW SL SQ; do \ sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \ $(git grep -l MO_TE$n target/microblaze); \ done Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/microblaze/translate.c | 36 +++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 4beaf69e76a..4c25b1e4383 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -779,13 +779,13 @@ static bool trans_lbui(DisasContext *dc, arg_typeb *a= rg) static bool trans_lhu(DisasContext *dc, arg_typea *arg) { TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); } =20 static bool trans_lhur(DisasContext *dc, arg_typea *arg) { TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, true); + return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true); } =20 static bool trans_lhuea(DisasContext *dc, arg_typea *arg) @@ -797,26 +797,26 @@ static bool trans_lhuea(DisasContext *dc, arg_typea *= arg) return true; #else TCGv addr =3D compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false); + return do_load(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false); #endif } =20 static bool trans_lhui(DisasContext *dc, arg_typeb *arg) { TCGv addr =3D compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false); } =20 static bool trans_lw(DisasContext *dc, arg_typea *arg) { TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); } =20 static bool trans_lwr(DisasContext *dc, arg_typea *arg) { TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, true); + return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true); } =20 static bool trans_lwea(DisasContext *dc, arg_typea *arg) @@ -828,14 +828,14 @@ static bool trans_lwea(DisasContext *dc, arg_typea *a= rg) return true; #else TCGv addr =3D compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_load(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false); + return do_load(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false); #endif } =20 static bool trans_lwi(DisasContext *dc, arg_typeb *arg) { TCGv addr =3D compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); + return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false); } =20 static bool trans_lwx(DisasContext *dc, arg_typea *arg) @@ -845,7 +845,7 @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg) /* lwx does not throw unaligned access errors, so force alignment */ tcg_gen_andi_tl(addr, addr, ~3); =20 - tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TEUL); + tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TE | MO_UL); tcg_gen_mov_tl(cpu_res_addr, addr); =20 if (arg->rd) { @@ -929,13 +929,13 @@ static bool trans_sbi(DisasContext *dc, arg_typeb *ar= g) static bool trans_sh(DisasContext *dc, arg_typea *arg) { TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); + return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false= ); } =20 static bool trans_shr(DisasContext *dc, arg_typea *arg) { TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, true); + return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true); } =20 static bool trans_shea(DisasContext *dc, arg_typea *arg) @@ -947,26 +947,26 @@ static bool trans_shea(DisasContext *dc, arg_typea *a= rg) return true; #else TCGv addr =3D compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false); + return do_store(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false= ); #endif } =20 static bool trans_shi(DisasContext *dc, arg_typeb *arg) { TCGv addr =3D compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); + return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false= ); } =20 static bool trans_sw(DisasContext *dc, arg_typea *arg) { TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); + return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false= ); } =20 static bool trans_swr(DisasContext *dc, arg_typea *arg) { TCGv addr =3D compute_ldst_addr_typea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, true); + return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true); } =20 static bool trans_swea(DisasContext *dc, arg_typea *arg) @@ -978,14 +978,14 @@ static bool trans_swea(DisasContext *dc, arg_typea *a= rg) return true; #else TCGv addr =3D compute_ldst_addr_ea(dc, arg->ra, arg->rb); - return do_store(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false); + return do_store(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false= ); #endif } =20 static bool trans_swi(DisasContext *dc, arg_typeb *arg) { TCGv addr =3D compute_ldst_addr_typeb(dc, arg->ra, arg->imm); - return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); + return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false= ); } =20 static bool trans_swx(DisasContext *dc, arg_typea *arg) @@ -1014,7 +1014,7 @@ static bool trans_swx(DisasContext *dc, arg_typea *ar= g) =20 tcg_gen_atomic_cmpxchg_i32(tval, cpu_res_addr, cpu_res_val, reg_for_write(dc, arg->rd), - dc->mem_index, MO_TEUL); + dc->mem_index, MO_TE | MO_UL); =20 tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_fail); =20 --=20 2.45.2