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Thu, 27 Apr 2023 14:04:17 -0700 (PDT) From: Daniel Henrique Barboza To: libvir-list@redhat.com Subject: [PATCH 1/1] cpu_riscv64.c: add update() implementation Date: Thu, 27 Apr 2023 18:04:10 -0300 Message-Id: <20230427210410.247849-2-dbarboza@ventanamicro.com> In-Reply-To: <20230427210410.247849-1-dbarboza@ventanamicro.com> References: <20230427210410.247849-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 3.1 on 10.11.54.3 X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dbarboza@ventanamicro.com Errors-To: libvir-list-bounces@redhat.com Sender: "libvir-list" X-Scanned-By: MIMEDefang 3.1 on 10.11.54.8 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: ventanamicro.com Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1682629507062100001 Content-Type: text/plain; charset="utf-8"; x-default="true" At this moment it is not possible to launch a 'riscv64' domain of type 'qemu' (i.e. TCG) and machine 'virt' in a x86 host: $ sudo ./run tools/virsh start riscv-virt1 error: Failed to start domain 'riscv-virt1' error: this function is not supported by the connection driver: cannot update guest CPU for riscv64 architecture A guest CPU definition will be added if absent by qemuDomainSetDefaultCPU(): rv64 This def will then be updated in qemuProcessUpdateGuestCPU(), which calls virCPUUpdate(). The error above is being thrown by this function because the current RISC-V driver does not have an 'update' API implemented. There is no particular reason to not support TCG RISC-V guests in x86 or any other host arch, so let's add an 'update' API to the RISC-V driver. The code was copied from virCPUarmUpdate() from the ARM driver since it's a good enough implementation to get us started. Signed-off-by: Daniel Henrique Barboza --- src/cpu/cpu_riscv64.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/src/cpu/cpu_riscv64.c b/src/cpu/cpu_riscv64.c index c44bdeb291..9796f8c967 100644 --- a/src/cpu/cpu_riscv64.c +++ b/src/cpu/cpu_riscv64.c @@ -46,6 +46,32 @@ virCPURiscv64ValidateFeatures(virCPUDef *cpu G_GNUC_UNUS= ED) } =20 =20 +static int +virCPUriscvUpdate(virCPUDef *guest, + const virCPUDef *host, + bool relative) +{ + g_autoptr(virCPUDef) updated =3D virCPUDefCopyWithoutModel(guest); + + if (!relative || guest->mode !=3D VIR_CPU_MODE_HOST_MODEL) + return 0; + + if (!host) { + virReportError(VIR_ERR_CONFIG_UNSUPPORTED, "%s", + _("unknown host CPU model")); + return -1; + } + + updated->mode =3D VIR_CPU_MODE_CUSTOM; + virCPUDefCopyModel(updated, host, true); + + virCPUDefStealModel(guest, updated, false); + guest->mode =3D VIR_CPU_MODE_CUSTOM; + guest->match =3D VIR_CPU_MATCH_EXACT; + + return 0; +} + struct cpuArchDriver cpuDriverRiscv64 =3D { .name =3D "riscv64", .arch =3D archs, @@ -54,6 +80,6 @@ struct cpuArchDriver cpuDriverRiscv64 =3D { .decode =3D NULL, .encode =3D NULL, .baseline =3D NULL, - .update =3D NULL, + .update =3D virCPUriscvUpdate, .validateFeatures =3D virCPURiscv64ValidateFeatures, }; --=20 2.40.0