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Fri, 18 Mar 2022 16:40:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1647621641; h=from:from:sender:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:list-id:list-help: list-unsubscribe:list-subscribe:list-post; bh=QQ4BMv+3OEmm8n23eF1Fg1DgWPwcNm7HW3VQnRmMFZc=; b=ZVeSZScPjEcGF10JtagpuiRbrTM/GNV9uOigr0I9Av8S98eMsLgD2QfVzlGITzCZWk7S8U ZnOdZFR1Ac4xZreyb7CeP4tMnq8FTgPGZh/qRSSHwYp1GSOiUEYWaDLSFUsRITjY4ko+a4 BsnybRlqk8b5ToqlF1PgHSFzo8178R4= X-MC-Unique: Hmzm1L2pO0WKliLT8W5DQw-1 X-Original-To: libvir-list@listman.corp.redhat.com From: Andrea Bolognani To: libvir-list@redhat.com Subject: [libvirt PATCH v2 02/17] conf: Introduce VIR_PCI_CONNECT_INTEGRATED Date: Fri, 18 Mar 2022 17:40:13 +0100 Message-Id: <20220318164028.1185357-3-abologna@redhat.com> In-Reply-To: <20220318164028.1185357-1-abologna@redhat.com> References: <20220318164028.1185357-1-abologna@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.85 on 10.11.54.7 X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libvir-list-bounces@redhat.com Sender: "libvir-list" X-Scanned-By: MIMEDefang 2.85 on 10.11.54.8 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1647621643445100003 This new flag can be used to convince the PCI address assignment algorithm to place a device directly on the root bus. It will be used to implement support for virtio-iommu, which needs to be an integrated device in order to work correctly. Signed-off-by: Andrea Bolognani Reviewed-by: J=C3=A1n Tomko --- src/conf/domain_addr.c | 17 +++++++++++++++++ src/conf/domain_addr.h | 26 +++++++++++++++----------- 2 files changed, 32 insertions(+), 11 deletions(-) diff --git a/src/conf/domain_addr.c b/src/conf/domain_addr.c index 49ca775a52..1173143635 100644 --- a/src/conf/domain_addr.c +++ b/src/conf/domain_addr.c @@ -303,6 +303,23 @@ virDomainPCIAddressFlagsCompatible(virPCIDeviceAddress= *addr, virErrorNumber errType =3D (fromConfig ? VIR_ERR_XML_ERROR : VIR_ERR_INTERNAL_ERROR= ); =20 + if (devFlags & VIR_PCI_CONNECT_INTEGRATED) { + if (addr->bus =3D=3D 0) { + /* pcie-root doesn't usually allow endpoint devices to be + * plugged directly into it, but for integrated devices + * that's exactly what we want */ + busFlags |=3D VIR_PCI_CONNECT_AUTOASSIGN; + } else { + if (reportError) { + virReportError(errType, + _("The device at PCI address %s needs to be= " + "an integrated device (bus=3D0)"), + addrStr); + } + return false; + } + } + if (fromConfig) { /* If the requested connection was manually specified in * config, allow a PCI device to connect to a PCIe slot, or diff --git a/src/conf/domain_addr.h b/src/conf/domain_addr.h index 814b556024..1772ea7088 100644 --- a/src/conf/domain_addr.h +++ b/src/conf/domain_addr.h @@ -35,24 +35,28 @@ typedef enum { VIR_PCI_CONNECT_AUTOASSIGN =3D 1 << 0, /* okay to autoassign a device = to this controller */ VIR_PCI_CONNECT_HOTPLUGGABLE =3D 1 << 1, /* is hotplug needed/supporte= d */ =20 + /* Set for devices that can only work as integrated devices (directly + * connected to pci.0 or pcie.0, with no additional buses in between) = */ + VIR_PCI_CONNECT_INTEGRATED =3D 1 << 2, + /* set for devices that can share a single slot in auto-assignment * (by assigning one device to each of the 8 functions on the slot) */ - VIR_PCI_CONNECT_AGGREGATE_SLOT =3D 1 << 2, + VIR_PCI_CONNECT_AGGREGATE_SLOT =3D 1 << 3, =20 /* kinds of devices as a bitmap so they can be combined (some PCI * controllers permit connecting multiple types of devices) */ - VIR_PCI_CONNECT_TYPE_PCI_DEVICE =3D 1 << 3, - VIR_PCI_CONNECT_TYPE_PCIE_DEVICE =3D 1 << 4, - VIR_PCI_CONNECT_TYPE_PCIE_ROOT_PORT =3D 1 << 5, - VIR_PCI_CONNECT_TYPE_PCIE_SWITCH_UPSTREAM_PORT =3D 1 << 6, - VIR_PCI_CONNECT_TYPE_PCIE_SWITCH_DOWNSTREAM_PORT =3D 1 << 7, - VIR_PCI_CONNECT_TYPE_DMI_TO_PCI_BRIDGE =3D 1 << 8, - VIR_PCI_CONNECT_TYPE_PCI_EXPANDER_BUS =3D 1 << 9, - VIR_PCI_CONNECT_TYPE_PCIE_EXPANDER_BUS =3D 1 << 10, - VIR_PCI_CONNECT_TYPE_PCI_BRIDGE =3D 1 << 11, - VIR_PCI_CONNECT_TYPE_PCIE_TO_PCI_BRIDGE =3D 1 << 12, + VIR_PCI_CONNECT_TYPE_PCI_DEVICE =3D 1 << 4, + VIR_PCI_CONNECT_TYPE_PCIE_DEVICE =3D 1 << 5, + VIR_PCI_CONNECT_TYPE_PCIE_ROOT_PORT =3D 1 << 6, + VIR_PCI_CONNECT_TYPE_PCIE_SWITCH_UPSTREAM_PORT =3D 1 << 7, + VIR_PCI_CONNECT_TYPE_PCIE_SWITCH_DOWNSTREAM_PORT =3D 1 << 8, + VIR_PCI_CONNECT_TYPE_DMI_TO_PCI_BRIDGE =3D 1 << 9, + VIR_PCI_CONNECT_TYPE_PCI_EXPANDER_BUS =3D 1 << 10, + VIR_PCI_CONNECT_TYPE_PCIE_EXPANDER_BUS =3D 1 << 11, + VIR_PCI_CONNECT_TYPE_PCI_BRIDGE =3D 1 << 12, + VIR_PCI_CONNECT_TYPE_PCIE_TO_PCI_BRIDGE =3D 1 << 13, } virDomainPCIConnectFlags; =20 /* a combination of all bits that describe the type of connections --=20 2.35.1