From nobody Mon Feb 9 07:05:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 170.10.133.124 as permitted sender) client-ip=170.10.133.124; envelope-from=libvir-list-bounces@redhat.com; helo=us-smtp-delivery-124.mimecast.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of redhat.com designates 170.10.133.124 as permitted sender) smtp.mailfrom=libvir-list-bounces@redhat.com; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1635870414; cv=none; d=zohomail.com; s=zohoarc; b=O3qd5GFM7V3B+S6rK2WXaIiGxmvfbgp+aWSWGad8M1602POmGXd+XvuCiV5Zn4QuS4ayROBNKMx9v8k9leKt4fhLQQ6nTVPCWdb0vJutOymV+0dZ8avu0MFkc8k8NgrWyLU9PmP/iD4MhuQ1CZZRWLRmGH0ikO5AvngZW0CZ528= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1635870414; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=tsi2My5XXdeCuf7g7TOXfBruTMn20sP+YMYltNBg7pc=; b=meb20B0U73iAZ/IjaX5j4IjpIKkuAjGOkcfq3ejcv90ze8DDzRMiRABaXhYSJi5QgXMasxLd8SlgMcZ3zA5JcEj34W93Kwq8hPWUrrUX6F6V+EeGrCuqbR6IlPvN/a9t6VYK55ZMJgwxe4m/VQq8drcmLXgVIqw2f7IoJyPIIu4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of redhat.com designates 170.10.133.124 as permitted sender) smtp.mailfrom=libvir-list-bounces@redhat.com; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by mx.zohomail.com with SMTPS id 163587041471262.66330331646088; Tue, 2 Nov 2021 09:26:54 -0700 (PDT) Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-244-BRwslPfXMCuWYOHnFIZKxg-1; Tue, 02 Nov 2021 12:26:49 -0400 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id EBF54806690; Tue, 2 Nov 2021 16:26:42 +0000 (UTC) Received: from colo-mx.corp.redhat.com (colo-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.20]) by smtp.corp.redhat.com (Postfix) with ESMTPS id CBFEC5DF35; Tue, 2 Nov 2021 16:26:42 +0000 (UTC) Received: from lists01.pubmisc.prod.ext.phx2.redhat.com (lists01.pubmisc.prod.ext.phx2.redhat.com [10.5.19.33]) by colo-mx.corp.redhat.com (Postfix) with ESMTP id A0323180BAD1; Tue, 2 Nov 2021 16:26:42 +0000 (UTC) Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) by lists01.pubmisc.prod.ext.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id 1A2GQR5a005397 for ; Tue, 2 Nov 2021 12:26:27 -0400 Received: by smtp.corp.redhat.com (Postfix) id AF6871972D; Tue, 2 Nov 2021 16:26:27 +0000 (UTC) Received: from sirius.home.kraxel.org (unknown [10.39.194.99]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 883C619C59; Tue, 2 Nov 2021 16:26:25 +0000 (UTC) Received: by sirius.home.kraxel.org (Postfix, from userid 1000) id B19A31801AB5; Tue, 2 Nov 2021 17:26:19 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1635870413; h=from:from:sender:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:list-id:list-help: list-unsubscribe:list-subscribe:list-post; bh=tsi2My5XXdeCuf7g7TOXfBruTMn20sP+YMYltNBg7pc=; b=Fx9rsgaKyLX6fMe+tSLlYBFko8Z3yPOl5NqPb7R/CFDrreBicE+DJ87eoKH+RNtFOhOe45 9a6oaI+E60IiDIoQis34PL8ocpMKlaZbDJFr3Ag39KhbOZ9wMJvXEWklq/PH5dr1E7+uE4 MGfxMarxeMuY8d86OkUkDGvPrgHqFp4= X-MC-Unique: BRwslPfXMCuWYOHnFIZKxg-1 From: Gerd Hoffmann To: qemu-devel@nongnu.org Subject: [PULL 03/10] microvm: add device tree support. Date: Tue, 2 Nov 2021 17:26:12 +0100 Message-Id: <20211102162619.2760593-4-kraxel@redhat.com> In-Reply-To: <20211102162619.2760593-1-kraxel@redhat.com> References: <20211102162619.2760593-1-kraxel@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-loop: libvir-list@redhat.com Cc: Thomas Huth , Eduardo Habkost , Sergio Lopez , "Michael S. Tsirkin" , libvir-list@redhat.com, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Wainer dos Santos Moschetta , Willian Rampazzo , Gerd Hoffmann , Marcel Apfelbaum , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1635870417151100005 Content-Type: text/plain; charset="utf-8" Allows edk2 detect virtio-mmio devices and pcie ecam. See comment in hw/i386/microvm-dt.c for more details. Signed-off-by: Gerd Hoffmann Reviewed-by: Sergio Lopez Message-Id: <20211014193617.2475578-1-kraxel@redhat.com> --- hw/i386/microvm-dt.h | 8 + include/hw/i386/microvm.h | 4 + hw/i386/microvm-dt.c | 341 +++++++++++++++++++++++++++++ hw/i386/microvm.c | 2 + .gitlab-ci.d/buildtest.yml | 1 - configs/targets/i386-softmmu.mak | 1 + configs/targets/x86_64-softmmu.mak | 1 + hw/i386/meson.build | 2 +- 8 files changed, 358 insertions(+), 2 deletions(-) create mode 100644 hw/i386/microvm-dt.h create mode 100644 hw/i386/microvm-dt.c diff --git a/hw/i386/microvm-dt.h b/hw/i386/microvm-dt.h new file mode 100644 index 000000000000..77c79cbdd9fb --- /dev/null +++ b/hw/i386/microvm-dt.h @@ -0,0 +1,8 @@ +#ifndef HW_I386_MICROVM_DT_H +#define HW_I386_MICROVM_DT_H + +#include "hw/i386/microvm.h" + +void dt_setup_microvm(MicrovmMachineState *mms); + +#endif diff --git a/include/hw/i386/microvm.h b/include/hw/i386/microvm.h index f25f8374413f..4d9c732d4b2b 100644 --- a/include/hw/i386/microvm.h +++ b/include/hw/i386/microvm.h @@ -104,6 +104,10 @@ struct MicrovmMachineState { Notifier machine_done; Notifier powerdown_req; struct GPEXConfig gpex; + + /* device tree */ + void *fdt; + uint32_t ioapic_phandle[2]; }; =20 #define TYPE_MICROVM_MACHINE MACHINE_TYPE_NAME("microvm") diff --git a/hw/i386/microvm-dt.c b/hw/i386/microvm-dt.c new file mode 100644 index 000000000000..875ba9196394 --- /dev/null +++ b/hw/i386/microvm-dt.c @@ -0,0 +1,341 @@ +/* + * microvm device tree support + * + * This generates an device tree for microvm and exports it via fw_cfg + * as "etc/fdt" to the firmware (edk2 specifically). + * + * The use case is to allow edk2 find the pcie ecam and the virtio + * devices, without adding an ACPI parser, reusing the fdt parser + * which is needed anyway for the arm platform. + * + * Note 1: The device tree is incomplete. CPUs and memory is missing + * for example, those can be detected using other fw_cfg files. + * Also pci ecam irq routing is not there, edk2 doesn't use + * interrupts. + * + * Note 2: This is for firmware only. OSes should use the more + * complete ACPI tables for hardware discovery. + * + * ---------------------------------------------------------------------- + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ +#include "qemu/osdep.h" +#include "qemu/cutils.h" +#include "sysemu/device_tree.h" +#include "hw/char/serial.h" +#include "hw/i386/fw_cfg.h" +#include "hw/rtc/mc146818rtc.h" +#include "hw/sysbus.h" +#include "hw/virtio/virtio-mmio.h" +#include "hw/usb/xhci.h" + +#include "microvm-dt.h" + +static bool debug; + +static void dt_add_microvm_irq(MicrovmMachineState *mms, + const char *nodename, uint32_t irq) +{ + int index =3D 0; + + if (irq >=3D IO_APIC_SECONDARY_IRQBASE) { + irq -=3D IO_APIC_SECONDARY_IRQBASE; + index++; + } + + qemu_fdt_setprop_cell(mms->fdt, nodename, "interrupt-parent", + mms->ioapic_phandle[index]); + qemu_fdt_setprop_cells(mms->fdt, nodename, "interrupts", irq, 0); +} + +static void dt_add_virtio(MicrovmMachineState *mms, VirtIOMMIOProxy *mmio) +{ + SysBusDevice *dev =3D SYS_BUS_DEVICE(mmio); + VirtioBusState *mmio_virtio_bus =3D &mmio->bus; + BusState *mmio_bus =3D &mmio_virtio_bus->parent_obj; + char *nodename; + + if (QTAILQ_EMPTY(&mmio_bus->children)) { + return; + } + + hwaddr base =3D dev->mmio[0].addr; + hwaddr size =3D 512; + unsigned index =3D (base - VIRTIO_MMIO_BASE) / size; + uint32_t irq =3D mms->virtio_irq_base + index; + + nodename =3D g_strdup_printf("/virtio_mmio@%" PRIx64, base); + qemu_fdt_add_subnode(mms->fdt, nodename); + qemu_fdt_setprop_string(mms->fdt, nodename, "compatible", "virtio,mmio= "); + qemu_fdt_setprop_sized_cells(mms->fdt, nodename, "reg", 2, base, 2, si= ze); + qemu_fdt_setprop(mms->fdt, nodename, "dma-coherent", NULL, 0); + dt_add_microvm_irq(mms, nodename, irq); + g_free(nodename); +} + +static void dt_add_xhci(MicrovmMachineState *mms) +{ + const char compat[] =3D "generic-xhci"; + uint32_t irq =3D MICROVM_XHCI_IRQ; + hwaddr base =3D MICROVM_XHCI_BASE; + hwaddr size =3D XHCI_LEN_REGS; + char *nodename; + + nodename =3D g_strdup_printf("/usb@%" PRIx64, base); + qemu_fdt_add_subnode(mms->fdt, nodename); + qemu_fdt_setprop(mms->fdt, nodename, "compatible", compat, sizeof(comp= at)); + qemu_fdt_setprop_sized_cells(mms->fdt, nodename, "reg", 2, base, 2, si= ze); + qemu_fdt_setprop(mms->fdt, nodename, "dma-coherent", NULL, 0); + dt_add_microvm_irq(mms, nodename, irq); + g_free(nodename); +} + +static void dt_add_pcie(MicrovmMachineState *mms) +{ + hwaddr base =3D PCIE_MMIO_BASE; + int nr_pcie_buses; + char *nodename; + + nodename =3D g_strdup_printf("/pcie@%" PRIx64, base); + qemu_fdt_add_subnode(mms->fdt, nodename); + qemu_fdt_setprop_string(mms->fdt, nodename, + "compatible", "pci-host-ecam-generic"); + qemu_fdt_setprop_string(mms->fdt, nodename, "device_type", "pci"); + qemu_fdt_setprop_cell(mms->fdt, nodename, "#address-cells", 3); + qemu_fdt_setprop_cell(mms->fdt, nodename, "#size-cells", 2); + qemu_fdt_setprop_cell(mms->fdt, nodename, "linux,pci-domain", 0); + qemu_fdt_setprop(mms->fdt, nodename, "dma-coherent", NULL, 0); + + qemu_fdt_setprop_sized_cells(mms->fdt, nodename, "reg", + 2, PCIE_ECAM_BASE, 2, PCIE_ECAM_SIZE); + if (mms->gpex.mmio64.size) { + qemu_fdt_setprop_sized_cells(mms->fdt, nodename, "ranges", + + 1, FDT_PCI_RANGE_MMIO, + 2, mms->gpex.mmio32.base, + 2, mms->gpex.mmio32.base, + 2, mms->gpex.mmio32.size, + + 1, FDT_PCI_RANGE_MMIO_64BIT, + 2, mms->gpex.mmio64.base, + 2, mms->gpex.mmio64.base, + 2, mms->gpex.mmio64.size); + } else { + qemu_fdt_setprop_sized_cells(mms->fdt, nodename, "ranges", + + 1, FDT_PCI_RANGE_MMIO, + 2, mms->gpex.mmio32.base, + 2, mms->gpex.mmio32.base, + 2, mms->gpex.mmio32.size); + } + + nr_pcie_buses =3D PCIE_ECAM_SIZE / PCIE_MMCFG_SIZE_MIN; + qemu_fdt_setprop_cells(mms->fdt, nodename, "bus-range", 0, + nr_pcie_buses - 1); +} + +static void dt_add_ioapic(MicrovmMachineState *mms, SysBusDevice *dev) +{ + hwaddr base =3D dev->mmio[0].addr; + char *nodename; + uint32_t ph; + int index; + + switch (base) { + case IO_APIC_DEFAULT_ADDRESS: + index =3D 0; + break; + case IO_APIC_SECONDARY_ADDRESS: + index =3D 1; + break; + default: + fprintf(stderr, "unknown ioapic @ %" PRIx64 "\n", base); + return; + } + + nodename =3D g_strdup_printf("/ioapic%d@%" PRIx64, index + 1, base); + qemu_fdt_add_subnode(mms->fdt, nodename); + qemu_fdt_setprop_string(mms->fdt, nodename, + "compatible", "intel,ce4100-ioapic"); + qemu_fdt_setprop(mms->fdt, nodename, "interrupt-controller", NULL, 0); + qemu_fdt_setprop_cell(mms->fdt, nodename, "#interrupt-cells", 0x2); + qemu_fdt_setprop_cell(mms->fdt, nodename, "#address-cells", 0x2); + qemu_fdt_setprop_sized_cells(mms->fdt, nodename, "reg", + 2, base, 2, 0x1000); + + ph =3D qemu_fdt_alloc_phandle(mms->fdt); + qemu_fdt_setprop_cell(mms->fdt, nodename, "phandle", ph); + qemu_fdt_setprop_cell(mms->fdt, nodename, "linux,phandle", ph); + mms->ioapic_phandle[index] =3D ph; + + g_free(nodename); +} + +static void dt_add_isa_serial(MicrovmMachineState *mms, ISADevice *dev) +{ + const char compat[] =3D "ns16550"; + uint32_t irq =3D object_property_get_int(OBJECT(dev), "irq", NULL); + hwaddr base =3D object_property_get_int(OBJECT(dev), "iobase", NULL); + hwaddr size =3D 8; + char *nodename; + + nodename =3D g_strdup_printf("/serial@%" PRIx64, base); + qemu_fdt_add_subnode(mms->fdt, nodename); + qemu_fdt_setprop(mms->fdt, nodename, "compatible", compat, sizeof(comp= at)); + qemu_fdt_setprop_sized_cells(mms->fdt, nodename, "reg", 2, base, 2, si= ze); + dt_add_microvm_irq(mms, nodename, irq); + + if (base =3D=3D 0x3f8 /* com1 */) { + qemu_fdt_setprop_string(mms->fdt, "/chosen", "stdout-path", nodena= me); + } + + g_free(nodename); +} + +static void dt_add_isa_rtc(MicrovmMachineState *mms, ISADevice *dev) +{ + const char compat[] =3D "motorola,mc146818"; + uint32_t irq =3D RTC_ISA_IRQ; + hwaddr base =3D RTC_ISA_BASE; + hwaddr size =3D 8; + char *nodename; + + nodename =3D g_strdup_printf("/rtc@%" PRIx64, base); + qemu_fdt_add_subnode(mms->fdt, nodename); + qemu_fdt_setprop(mms->fdt, nodename, "compatible", compat, sizeof(comp= at)); + qemu_fdt_setprop_sized_cells(mms->fdt, nodename, "reg", 2, base, 2, si= ze); + dt_add_microvm_irq(mms, nodename, irq); + g_free(nodename); +} + +static void dt_setup_isa_bus(MicrovmMachineState *mms, DeviceState *bridge) +{ + BusState *bus =3D qdev_get_child_bus(bridge, "isa.0"); + BusChild *kid; + Object *obj; + + QTAILQ_FOREACH(kid, &bus->children, sibling) { + DeviceState *dev =3D kid->child; + + /* serial */ + obj =3D object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL); + if (obj) { + dt_add_isa_serial(mms, ISA_DEVICE(obj)); + continue; + } + + /* rtc */ + obj =3D object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC); + if (obj) { + dt_add_isa_rtc(mms, ISA_DEVICE(obj)); + continue; + } + + if (debug) { + fprintf(stderr, "%s: unhandled: %s\n", __func__, + object_get_typename(OBJECT(dev))); + } + } +} + +static void dt_setup_sys_bus(MicrovmMachineState *mms) +{ + BusState *bus; + BusChild *kid; + Object *obj; + + /* sysbus devices */ + bus =3D sysbus_get_default(); + QTAILQ_FOREACH(kid, &bus->children, sibling) { + DeviceState *dev =3D kid->child; + + /* ioapic */ + obj =3D object_dynamic_cast(OBJECT(dev), TYPE_IOAPIC); + if (obj) { + dt_add_ioapic(mms, SYS_BUS_DEVICE(obj)); + continue; + } + } + + QTAILQ_FOREACH(kid, &bus->children, sibling) { + DeviceState *dev =3D kid->child; + + /* virtio */ + obj =3D object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MMIO); + if (obj) { + dt_add_virtio(mms, VIRTIO_MMIO(obj)); + continue; + } + + /* xhci */ + obj =3D object_dynamic_cast(OBJECT(dev), TYPE_XHCI_SYSBUS); + if (obj) { + dt_add_xhci(mms); + continue; + } + + /* pcie */ + obj =3D object_dynamic_cast(OBJECT(dev), TYPE_GPEX_HOST); + if (obj) { + dt_add_pcie(mms); + continue; + } + + /* isa */ + obj =3D object_dynamic_cast(OBJECT(dev), "isabus-bridge"); + if (obj) { + dt_setup_isa_bus(mms, DEVICE(obj)); + continue; + } + + if (debug) { + obj =3D object_dynamic_cast(OBJECT(dev), TYPE_IOAPIC); + if (obj) { + /* ioapic already added in first pass */ + continue; + } + fprintf(stderr, "%s: unhandled: %s\n", __func__, + object_get_typename(OBJECT(dev))); + } + } +} + +void dt_setup_microvm(MicrovmMachineState *mms) +{ + X86MachineState *x86ms =3D X86_MACHINE(mms); + int size =3D 0; + + mms->fdt =3D create_device_tree(&size); + + /* root node */ + qemu_fdt_setprop_string(mms->fdt, "/", "compatible", "linux,microvm"); + qemu_fdt_setprop_cell(mms->fdt, "/", "#address-cells", 0x2); + qemu_fdt_setprop_cell(mms->fdt, "/", "#size-cells", 0x2); + + qemu_fdt_add_subnode(mms->fdt, "/chosen"); + dt_setup_sys_bus(mms); + + /* add to fw_cfg */ + fprintf(stderr, "%s: add etc/fdt to fw_cfg\n", __func__); + fw_cfg_add_file(x86ms->fw_cfg, "etc/fdt", mms->fdt, size); + + if (debug) { + fprintf(stderr, "%s: writing microvm.fdt\n", __func__); + g_file_set_contents("microvm.fdt", mms->fdt, size, NULL); + int ret =3D system("dtc -I dtb -O dts microvm.fdt"); + if (ret !=3D 0) { + fprintf(stderr, "%s: oops, dtc not installed?\n", __func__); + } + } +} diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c index f257ec5a0bc1..8d6ebea3414d 100644 --- a/hw/i386/microvm.c +++ b/hw/i386/microvm.c @@ -28,6 +28,7 @@ #include "sysemu/reset.h" #include "sysemu/runstate.h" #include "acpi-microvm.h" +#include "microvm-dt.h" =20 #include "hw/loader.h" #include "hw/irq.h" @@ -626,6 +627,7 @@ static void microvm_machine_done(Notifier *notifier, vo= id *data) machine_done); =20 acpi_setup_microvm(mms); + dt_setup_microvm(mms); } =20 static void microvm_powerdown_req(Notifier *notifier, void *data) diff --git a/.gitlab-ci.d/buildtest.yml b/.gitlab-ci.d/buildtest.yml index 5c378e35f91f..6c1301e91287 100644 --- a/.gitlab-ci.d/buildtest.yml +++ b/.gitlab-ci.d/buildtest.yml @@ -575,7 +575,6 @@ build-without-default-features: CONFIGURE_ARGS: --without-default-features --disable-capstone - --disable-fdt --disable-pie --disable-qom-cast-debug --disable-slirp diff --git a/configs/targets/i386-softmmu.mak b/configs/targets/i386-softmm= u.mak index 5babf71895db..6b3c99fc86c5 100644 --- a/configs/targets/i386-softmmu.mak +++ b/configs/targets/i386-softmmu.mak @@ -1,3 +1,4 @@ TARGET_ARCH=3Di386 TARGET_SUPPORTS_MTTCG=3Dy +TARGET_NEED_FDT=3Dy TARGET_XML_FILES=3D gdb-xml/i386-32bit.xml diff --git a/configs/targets/x86_64-softmmu.mak b/configs/targets/x86_64-so= ftmmu.mak index 75e42bc84047..197817c94346 100644 --- a/configs/targets/x86_64-softmmu.mak +++ b/configs/targets/x86_64-softmmu.mak @@ -1,4 +1,5 @@ TARGET_ARCH=3Dx86_64 TARGET_BASE_ARCH=3Di386 TARGET_SUPPORTS_MTTCG=3Dy +TARGET_NEED_FDT=3Dy TARGET_XML_FILES=3D gdb-xml/i386-64bit.xml diff --git a/hw/i386/meson.build b/hw/i386/meson.build index c502965219d6..213e2e82b3d7 100644 --- a/hw/i386/meson.build +++ b/hw/i386/meson.build @@ -11,7 +11,7 @@ i386_ss.add(when: 'CONFIG_X86_IOMMU', if_true: files('x86= -iommu.c'), if_false: files('x86-iommu-stub.c')) i386_ss.add(when: 'CONFIG_AMD_IOMMU', if_true: files('amd_iommu.c')) i386_ss.add(when: 'CONFIG_I440FX', if_true: files('pc_piix.c')) -i386_ss.add(when: 'CONFIG_MICROVM', if_true: files('microvm.c', 'acpi-micr= ovm.c')) +i386_ss.add(when: 'CONFIG_MICROVM', if_true: files('microvm.c', 'acpi-micr= ovm.c', 'microvm-dt.c')) i386_ss.add(when: 'CONFIG_Q35', if_true: files('pc_q35.c')) i386_ss.add(when: 'CONFIG_VMMOUSE', if_true: files('vmmouse.c')) i386_ss.add(when: 'CONFIG_VMPORT', if_true: files('vmport.c')) --=20 2.31.1