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Mon, 16 Aug 2021 23:25:17 -0400 Received: from dggemv703-chm.china.huawei.com (unknown [172.30.72.56]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4GpbxY14n7zYkg3; Tue, 17 Aug 2021 11:24:49 +0800 (CST) Received: from dggpemm000001.china.huawei.com (7.185.36.245) by dggemv703-chm.china.huawei.com (10.3.19.46) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Tue, 17 Aug 2021 11:25:11 +0800 Received: from huawei.com (10.174.186.236) by dggpemm000001.china.huawei.com (7.185.36.245) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Tue, 17 Aug 2021 11:25:10 +0800 From: Yifei Jiang To: , Subject: [PATCH RFC v6 09/12] target/riscv: Add host cpu type Date: Tue, 17 Aug 2021 11:24:44 +0800 Message-ID: <20210817032447.2055-10-jiangyifei@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20210817032447.2055-1-jiangyifei@huawei.com> References: <20210817032447.2055-1-jiangyifei@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.186.236] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm000001.china.huawei.com (7.185.36.245) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" 'host' type cpu is set isa to RV32 or RV64 simply, more isa info will obtain from KVM in kvm_arch_init_vcpu() Signed-off-by: Yifei Jiang Signed-off-by: Mingwang Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 15 +++++++++++++++ target/riscv/cpu.h | 1 + 2 files changed, 16 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2251784f7b..976e71c4c7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -260,6 +260,18 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) } #endif =20 +#if defined(CONFIG_KVM) +static void riscv_host_cpu_init(Object *obj) +{ + CPURISCVState *env =3D &RISCV_CPU(obj)->env; +#if defined(TARGET_RISCV32) + set_misa(env, RV32); +#elif defined(TARGET_RISCV64) + set_misa(env, RV64); +#endif +} +#endif + static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) { ObjectClass *oc; @@ -792,6 +804,9 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .class_init =3D riscv_cpu_class_init, }, DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), +#if defined(CONFIG_KVM) + DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), +#endif #if defined(TARGET_RISCV32) DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 3d3bdc2816..720cb688bb 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -44,6 +44,7 @@ #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") +#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") =20 #if defined(TARGET_RISCV32) # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 --=20 2.19.1