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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id s20sm8990109wmj.46.2021.01.07.14.22.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:23:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fW0mwAJFoILMKm9wYoK9XOOf/CSaqeng2a0yxdXuwlk=; b=AH6CvUU40CZjmLEhU77ijgxJ0hPcSMVJ2GzOlTsKVCyXCFn5YpBwssc/U0Qs/dA6hn G0d9aoDgsdMQhvNtJj+FOu1D6AoghLx7jVtVuZrB3juWVTd/6kOmcUQlTsoVh8QCwF8/ dK9th7CfpxglazqSCFZEEGkjpywpTrx5RlstQS5rsnMWHGN9VwYfJHutIBLLyU4g1gVN XLNCObf8hgaAVGAsdzAKclkUfGIUc80m3ZOe2pMrJ6+Idto37dbwYx7qd1okKyi8EXNv UKxvhPOXw+lyHe2I+u9lYHLl7HNcCZpvhT995xNTOOryONIvDtZ4aTEFrBCVbnTuG9kn e5pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=fW0mwAJFoILMKm9wYoK9XOOf/CSaqeng2a0yxdXuwlk=; b=sjF4B4uWXIHoa48osrxUfESt5W7wvBtlgyrId4BaFuN051Oe56OPfASea5+zfHVYfn pXgBUMleyqJzCcluyxowM14lWWw9h8vjgWJ2zdzQ1gXFlVp58+Y0wjsFO5OKOMqBJxya ojyEz9JGk2K29UZh/OjlumXly16x2x7T2W9VKaD6okegRzxNL1wqz5Eut7ThR01Jormj C5iBk3BxXV2FFJzJvlYcw2m5WmKw92tgxlT7k0ZzEircljp1GmQHZYzDwOblHeXN+T5n JJAOI2msctATagDYYPHhicpd7Nw9UK5DHBRM7flWf0Luw7smfOcAsrntqeK3fSSzUfH2 41Aw== X-Gm-Message-State: AOAM533pW4tLL0AxjwOb1ZwztNDE1yyr3BLAbccRUQV7Vna3zLfA+yzq A1Y93qjMNy2Mm19GBdiDO9I= X-Google-Smtp-Source: ABdhPJxClHvusZYqPYf/w2zXO0+Cg3NpWMcgUHjWirXKV2TwoH7uxBpXmD1ODQrmjp71U9B2+y3JdQ== X-Received: by 2002:adf:80ae:: with SMTP id 43mr705077wrl.50.1610058180999; Thu, 07 Jan 2021 14:23:00 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: libvir-list@redhat.com, Paolo Bonzini , Laurent Vivier , kvm@vger.kernel.org, Jiaxun Yang , Aurelien Jarno , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Paul Burton , Richard Henderson Subject: [PULL 01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA Date: Thu, 7 Jan 2021 23:21:48 +0100 Message-Id: <20210107222253.20382-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The MIPS3 and MIPS32/64 ISA use different definitions for the CP0 Config0 register. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201201132817.2863301-2-f4bug@amsat.org> --- target/mips/cpu.h | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 4cbc31c3e8d..0086f95ea2a 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -828,7 +828,7 @@ struct CPUMIPSState { #define CP0EBase_WG 11 target_ulong CP0_CMGCRBase; /* - * CP0 Register 16 + * CP0 Register 16 (after Release 1) */ int32_t CP0_Config0; #define CP0C0_M 31 @@ -845,6 +845,14 @@ struct CPUMIPSState { #define CP0C0_VI 3 #define CP0C0_K0 0 /* 2..0 */ #define CP0C0_AR_LENGTH 3 +/* + * CP0 Register 16 (before Release 1) + */ +#define CP0C0_Impl 16 /* 24..16 */ +#define CP0C0_IC 9 /* 11..9 */ +#define CP0C0_DC 6 /* 8..6 */ +#define CP0C0_IB 5 +#define CP0C0_DB 4 int32_t CP0_Config1; #define CP0C1_M 31 #define CP0C1_MMU 25 /* 30..25 */ --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.50 as permitted sender) client-ip=209.85.128.50; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f50.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1610058188; cv=none; d=zohomail.com; s=zohoarc; b=PjZ16A71ie2gohdv1ImJF50AKsba3pyElj9KjamkFQWB4upWkcTyc+uK4CNYoFnLmX0rWsiUAkPNJe3RJ1Hwl8plr05ulRszcRw1wqh59vfCc8wdMSYczbOh353itqcxahwWx9r/jn/o/fvE87d5pjqBRYaiM84nro6bN9hX+F4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610058188; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+5gxhXnPVS+EmwiIP+LC6CRqrj3N73XVIMAHkwrkkuk=; b=HltkmeCL8Hbq2K39/XsITbx9eoUlOcscUG5jAI+4QfAkgpXUqzjEIiD4TIJ+7MIrXf29tPbeEMyGHeCxS1KhAf9/yHFOgYHtY/Ros/2C4/gd+gbCDiQCfw5juI4Flr8ubgFCfM0F+OuX/VLKaJO90qUDskeWars+dW5oxtbXoDw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) by mx.zohomail.com with SMTPS id 1610058188370589.2701752323642; Thu, 7 Jan 2021 14:23:08 -0800 (PST) Received: by mail-wm1-f50.google.com with SMTP id y23so6835164wmi.1 for ; Thu, 07 Jan 2021 14:23:07 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (241.red-88-10-103.dynamicip.rima-tde.net. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201201132817.2863301-3-f4bug@amsat.org> --- target/mips/translate_init.c.inc | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.= c.inc index f72fee3b40a..cac3d241831 100644 --- a/target/mips/translate_init.c.inc +++ b/target/mips/translate_init.c.inc @@ -495,7 +495,8 @@ const mips_def_t mips_defs[] =3D .name =3D "R4000", .CP0_PRid =3D 0x00000400, /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency= . */ - .CP0_Config0 =3D (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0= C0_K0), + .CP0_Config0 =3D (2 << CP0C0_Impl) | (1 << CP0C0_IC) | (1 << CP0C0= _DC) | + (2 << CP0C0_K0), /* Note: Config1 is only used internally, the R4000 has only Confi= g0. */ .CP0_Config1 =3D (1 << CP0C1_FP) | (47 << CP0C1_MMU), .CP0_LLAddr_rw_bitmask =3D 0xFFFFFFFF, @@ -516,7 +517,8 @@ const mips_def_t mips_defs[] =3D .name =3D "VR5432", .CP0_PRid =3D 0x00005400, /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency= . */ - .CP0_Config0 =3D (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0= C0_K0), + .CP0_Config0 =3D (2 << CP0C0_Impl) | (1 << CP0C0_IC) | (1 << CP0C0= _DC) | + (2 << CP0C0_K0), .CP0_Config1 =3D (1 << CP0C1_FP) | (47 << CP0C1_MMU), .CP0_LLAddr_rw_bitmask =3D 0xFFFFFFFFL, .CP0_LLAddr_shift =3D 4, @@ -766,8 +768,8 @@ const mips_def_t mips_defs[] =3D .name =3D "Loongson-2E", .CP0_PRid =3D 0x6302, /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */ - .CP0_Config0 =3D (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | - (0x1<<5) | (0x1<<4) | (0x1<<1), + .CP0_Config0 =3D (3 << CP0C0_Impl) | (4 << CP0C0_IC) | (4 << CP0C0= _DC) | + (1 << CP0C0_IB) | (1 << CP0C0_DB) | (0x2 << CP0C0_K= 0), /* Note: Config1 is only used internally, Loongson-2E has only Config0. */ .CP0_Config1 =3D (1 << CP0C1_FP) | (47 << CP0C1_MMU), @@ -786,8 +788,8 @@ const mips_def_t mips_defs[] =3D .name =3D "Loongson-2F", .CP0_PRid =3D 0x6303, /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */ - .CP0_Config0 =3D (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | - (0x1<<5) | (0x1<<4) | (0x1<<1), + .CP0_Config0 =3D (3 << CP0C0_Impl) | (4 << CP0C0_IC) | (4 << CP0C0= _DC) | + (1 << CP0C0_IB) | (1 << CP0C0_DB) | (0x2 << CP0C0_K= 0), /* Note: Config1 is only used internally, Loongson-2F has only Config0. */ .CP0_Config1 =3D (1 << CP0C1_FP) | (47 << CP0C1_MMU), --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.46 as permitted sender) client-ip=209.85.128.46; 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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id q15sm9893608wrw.75.2021.01.07.14.23.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:23:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qWarhXBRCCKl1ib6yNLPWYWSvngUVzs/930y/X1kaDM=; b=OuM8zCGuNKENPmA4AeOPBdxZtVqMeY6L/Qv81iOjsTaLsVhNTiF50IuicWsO8xsyU6 o0YnigsuBrsraQeRizxBsomHfdxZIkbwBoywYTxdXLmqXJ5LlsBkfCJAzthQm4hhH681 pMnR00hnz1Vk57j5SO61N7SoMInJ12z1LYEw1qAKQLvAOLeh+6B8UifHppiM09sgyr+6 IouSehCrBqmUXzGLX8iNu1dqgmKYWfxhb6FDOLK63NnBD25BeS8taeITL6RNsNl6kU+J nteWfI+rNhmXMDJUF+V7/x92LZyffEXHgdvcmn9w3dvTNFRrcOXzq5uNVBAAGeaoDmon 6eTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=qWarhXBRCCKl1ib6yNLPWYWSvngUVzs/930y/X1kaDM=; b=nL7VB/qhLGVfh1C9vpyLO8dhHbzpDFVLxaGVjb7QYUQ2dHSCFXrY2lMG1DvhE8ueT6 pnWfDNBcRXMfW8r9j63B12b5WOyhPyQgIi+WMypbu4ivCNH7+WhXaCMihxzDlV7eRDx2 XaxBkq/v5hHl5/8pdU3xz4yo6OaPoMz/LMVIBnkzYPj+mLnA3Hg1cZQGQJ3acIsoQ8UN L5q/QLxKpIc0Dkh1LpwaWlUr74lSJ2gdbIUsuZXSGa2beiySOTmIpG9wR2THiFHnJZrQ Hm57+rv1wDRBEjeGyYmCZYsdF5lPCTWzE5WCU0YZ74Tuk5ugUW1fLW1Y7ZQB9jjTTRxn 0eWA== X-Gm-Message-State: AOAM533RWfPa97A1wcf8TbxmhiovpfgbJCLlUgL9hJVWwVb3i9VuMObn 0auF2rwnCyY1sCOtePfsxIg= X-Google-Smtp-Source: ABdhPJwXEJY641mvWZFlqGlSPn78NAiXwQ5lcO0KUEHFx1ZWxt8dNXQxbxwgVbBtDlkQiI8jfm1hCA== X-Received: by 2002:a1c:6283:: with SMTP id w125mr480401wmb.155.1610058191505; Thu, 07 Jan 2021 14:23:11 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: libvir-list@redhat.com, Paolo Bonzini , Laurent Vivier , kvm@vger.kernel.org, Jiaxun Yang , Aurelien Jarno , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Paul Burton Subject: [PULL 03/66] target/mips/addr: Add translation helpers for KSEG1 Date: Thu, 7 Jan 2021 23:21:50 +0100 Message-Id: <20210107222253.20382-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) From: Jiaxun Yang It's useful for bootloader to do I/O operations. Signed-off-by: Jiaxun Yang Tested-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Huacai Chen Message-Id: <20201215064507.30148-3-jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/cpu.h | 2 ++ target/mips/addr.c | 10 ++++++++++ 2 files changed, 12 insertions(+) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 0086f95ea2a..0c2d397e4a9 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1312,6 +1312,8 @@ uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_= t addr); uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr); =20 uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr); +uint64_t cpu_mips_kseg1_to_phys(void *opaque, uint64_t addr); +uint64_t cpu_mips_phys_to_kseg1(void *opaque, uint64_t addr); bool mips_um_ksegs_enabled(void); void mips_um_ksegs_enable(void); =20 diff --git a/target/mips/addr.c b/target/mips/addr.c index 27a6036c451..86f1c129c9f 100644 --- a/target/mips/addr.c +++ b/target/mips/addr.c @@ -40,6 +40,16 @@ uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uin= t64_t addr) return addr | 0x40000000ll; } =20 +uint64_t cpu_mips_kseg1_to_phys(void *opaque, uint64_t addr) +{ + return addr & 0x1fffffffll; +} + +uint64_t cpu_mips_phys_to_kseg1(void *opaque, uint64_t addr) +{ + return (addr & 0x1fffffffll) | 0xffffffffa0000000ll; +} + bool mips_um_ksegs_enabled(void) { return mips_um_ksegs; --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.46 as permitted sender) client-ip=209.85.128.46; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f46.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.46 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1610058198; cv=none; d=zohomail.com; s=zohoarc; b=cEnSRyqQlDVsWPQBWiz2Cvb8pNwl5/uQkEa/0NRMQbeHzAvolOXhgiTBhBwzC/NdaIOZetO/W+v7xm7Xc5ybgc08JVfN+t+QBcXgZHjAzO9vNHzRtM/UqHa/U34xGLUTDb7WcRAX1QKtSSusaXCaorHvfGp9j/bzYck2LmUfP/A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610058198; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=i4p93KWwozcpUdxQORlradD/IWu48glCvPCZu/J+OhM=; b=B+bXiX6ynwPHcK4f9ghBiHwaICNY3psO+gqqow+T8asahd1/o/RkyLeezx7mAbskNAf8qPzXJrMnMo6dpoNXo4huf+xJbi27+Zg/FVJznRHTPfRM/eT21UMnzCiI3t2TnRM5Mdu7LtdG+srYBRM0Xdl3l02QMqB4giAPjsCXJ2k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.46 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) by mx.zohomail.com with SMTPS id 1610058198762272.57712558230594; Thu, 7 Jan 2021 14:23:18 -0800 (PST) Received: by mail-wm1-f46.google.com with SMTP id v14so6362529wml.1 for ; Thu, 07 Jan 2021 14:23:18 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (241.red-88-10-103.dynamicip.rima-tde.net. [88.10.103.241]) by smtp.gmail.com with ESMTPSA id y7sm9861567wmb.37.2021.01.07.14.23.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:23:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=i4p93KWwozcpUdxQORlradD/IWu48glCvPCZu/J+OhM=; b=Czkxpi82pJCD7JSf0mA7kHhcxneqK0d6Fsds+0JbSzuPtZWV1yh1M5oXFGZ+w0JNuW cyc5o4bORJxj++VlibljEoacu8ytM3nu/1NQbW3IgS/bOzz1y9DfQt+sKqMpCMHFyH7R L9Yw4OgAR6qcwJ82fnwL7IIdbY8GsFKenrAsXAREMdk5h1j94jq1mNQbh/U8E/o5uYKK wjx9K4+FV2DA7gTfJD1gevkY8UEbaQdtJ7hR7mAwRcis19ywwvO2BOHPJJdYa/gtmkom gCe6QknW3HDOAqJmSv7I6pxVUett3/FbWSncVR8NTYiJW6QHnM0MEPER2H1PsEUn30Vz vHsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=i4p93KWwozcpUdxQORlradD/IWu48glCvPCZu/J+OhM=; b=UQ81r0QHICNaRkMbuNzPT5T1y6PNsUFHJvphju6hbQVV0MNufguogSdpLl+dMPFq/A s7GMmjioVW0OkbUqL8afpsuFXfgPEvCb1hAFlrEOEf3wcXhcNddQ7vorWciGYTiAbPom 1r+1jpypdiVJlq7mw6QE4vNMEPM45w3bJimLBXy12mKxddGuz76EKpRL2MJyTCTUiojt gZMdsufC6EVF8x8j7u3bPRBjrIEWYSwqaAphjkYO9eW2gaaqMg/rr0QRdgyeBvC3s0Z5 74ssd2NYnaH3loznHvVWZKWN/jXhHHkhEvb6pUHHjdQeFfEU646A06QPiGteUm1zCEUi Ox0g== X-Gm-Message-State: AOAM531+ivNTfHSURUDsuajSOSjM/U0NMt8yVS1jKIjIE0YxwKqbsl7P 8CjreF/UPrKUKnvY0fEtV3rhu8wAyAY= X-Google-Smtp-Source: ABdhPJw42/Tbgd5nDkMN32lGkO4V59KXfV71HMhGiFKrMKuVn2Z9xZTeKIOwm/xUy/9bCNTfy7TeRQ== X-Received: by 2002:a1c:234d:: with SMTP id j74mr532053wmj.18.1610058196986; Thu, 07 Jan 2021 14:23:16 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: libvir-list@redhat.com, Paolo Bonzini , Laurent Vivier , kvm@vger.kernel.org, Jiaxun Yang , Aurelien Jarno , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Paul Burton , Richard Henderson Subject: [PULL 04/66] target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment Date: Thu, 7 Jan 2021 23:21:51 +0100 Message-Id: <20210107222253.20382-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Remove a comment added 12 years ago but never used (commit b6d96beda3a: "Use temporary registers for the MIPS FPU emulation"). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20210104221154.3127610-2-f4bug@amsat.org> --- target/mips/mips-defs.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index ed6a7a9e545..555e165fb01 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -1,12 +1,6 @@ #ifndef QEMU_MIPS_DEFS_H #define QEMU_MIPS_DEFS_H =20 -/* - * If we want to use host float regs... - * - * #define USE_HOST_FLOAT_REGS - */ - /* Real pages are variable size... */ #define MIPS_TLB_MAX 128 =20 --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) client-ip=216.205.24.124; envelope-from=libvir-list-bounces@redhat.com; helo=us-smtp-delivery-124.mimecast.com; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) smtp.mailfrom=libvir-list-bounces@redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1610058220; cv=none; d=zohomail.com; s=zohoarc; b=Avw29O1CmoIKZvkDKKnxq4G0QR+8lLKbmMsnLN5s6rchJ5Q5So+RH7FzZqGX9T2q909Ek4u3v6tDtCpkV6eT8raW7Y9WBReT1gjsL0cba1M6Iwnl5TJ88bnttrhBoGxhZD9+6uxMYLzhDTsW2n9J1tyq4lYixF9cQ+XPd5S+mOw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610058220; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=nLKJKOTk7XMRzOC+u/WBz+w7tk2M4QOBGegMa8D7C0U=; b=DrzbMN3tbq/9l5MBSd302b5cY1kIG0CnjZng9UAGd+3xO6hAz2K5Y731MYhE4xie3Md+3zpFUJ2G0am1fltbYgpTQki/vii+2zh3AYGlzwxbaI/c50AK9SeSG1+2BeB+s1bbXjKlaPW2O1e0nVkbYsNdreGOVbL5ecJ4bSe4IVY= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) smtp.mailfrom=libvir-list-bounces@redhat.com Return-Path: Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [216.205.24.124]) by mx.zohomail.com with SMTPS id 1610058220423612.7653230268849; Thu, 7 Jan 2021 14:23:40 -0800 (PST) Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-523-6HRcuq5iOteaRV9HMLn4MA-1; Thu, 07 Jan 2021 17:23:36 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id F3C1A803620; Thu, 7 Jan 2021 22:23:30 +0000 (UTC) Received: from colo-mx.corp.redhat.com (colo-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.21]) by smtp.corp.redhat.com (Postfix) with ESMTPS id D1A7C62693; Thu, 7 Jan 2021 22:23:30 +0000 (UTC) Received: from lists01.pubmisc.prod.ext.phx2.redhat.com (lists01.pubmisc.prod.ext.phx2.redhat.com [10.5.19.33]) by colo-mx.corp.redhat.com (Postfix) with ESMTP id 52E744E590; Thu, 7 Jan 2021 22:23:30 +0000 (UTC) Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.rdu2.redhat.com [10.11.54.4]) by lists01.pubmisc.prod.ext.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id 107MNSYt028680 for ; Thu, 7 Jan 2021 17:23:28 -0500 Received: by smtp.corp.redhat.com (Postfix) id 88D8D2026D11; Thu, 7 Jan 2021 22:23:28 +0000 (UTC) Received: from mimecast-mx02.redhat.com (mimecast04.extmail.prod.ext.rdu2.redhat.com [10.11.55.20]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 8406B2026D46 for ; Thu, 7 Jan 2021 22:23:28 +0000 (UTC) Received: from us-smtp-1.mimecast.com (us-smtp-delivery-1.mimecast.com [207.211.31.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 703C4101A560 for ; Thu, 7 Jan 2021 22:23:28 +0000 (UTC) Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-7-89HEBhQMP8uqgxn3fiamSg-1; Thu, 07 Jan 2021 17:23:23 -0500 Received: by mail-wr1-f43.google.com with SMTP id y17so7092145wrr.10; Thu, 07 Jan 2021 14:23:23 -0800 (PST) Received: from x1w.redhat.com (241.red-88-10-103.dynamicip.rima-tde.net. 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Thu, 07 Jan 2021 14:23:22 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 05/66] target/mips/mips-defs: Reorder CPU_MIPS5 definition Date: Thu, 7 Jan 2021 23:21:52 +0100 Message-Id: <20210107222253.20382-6-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.78 on 10.11.54.4 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Move CPU_MIPS5 after CPU_MIPS4 :) Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210104221154.3127610-3-f4bug@amsat.org> --- target/mips/mips-defs.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 555e165fb01..48544ba73b4 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -65,13 +65,12 @@ #define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2) #define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3) #define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4) +#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5) #define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX) #define CPU_R5900 (CPU_MIPS3 | INSN_R5900) #define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E) #define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI) =20 -#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5) - /* MIPS Technologies "Release 1" */ #define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32) #define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64) --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 63.128.21.124 as permitted sender) client-ip=63.128.21.124; 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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id c7sm11506623wro.16.2021.01.07.14.23.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:23:26 -0800 (PST) X-MC-Unique: tBW3KxGVOFCfjnLJc32YuQ-1 X-MC-Unique: vz3CwCrTOtiLZ-kwbqUfnA-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=CCcScCerij69CQ6oZxOAaSELOgitQBqHQwR1Q8IbG/E=; b=fQJ6YBby51FHEb9oeqCgNT5O6hO3Rm0dGiGMs4C7hLxuiIJ4d6mz0c/E9JBIKecn1e uzbX7w/gcU0g8IHutC4bttt9AXQMm9BKzR9KowA15A2UfJ5ZRzRVSrM8YM4uyoc/hVbL 8Ag+dk7BspekfHkgmJT6AvUnswWB/2Q5F14136ZkZwr89VqW00T0gwW6V0lUVg8e13R9 gQ5nUebM/8W7xIyHsvg5gtOMemonUTjFD8xWLtYYTN6k6RDLTKpEglY46e8qEUkUPcCf c34Md4au2Cyfd0KnrhlqC6XJpqTTV3uRj7oGEHcOYDDjJOuqSIhFZ5U0F2iKhukKph0b d8EQ== X-Gm-Message-State: AOAM5320PNx+OBr2eQ50KoKJCuMA9xkjEUapdKZZ9GSburT45cN4OO8N WJsyAmExUeZ+zYSFquIHaVg= X-Google-Smtp-Source: ABdhPJy/gw9y0iLygnNYCRbNVdeUgo3SJN/NH5crn6wIfiA04NxP/S7hfoDf86Rn9ZrhmLpdiaeK+g== X-Received: by 2002:a7b:cb4f:: with SMTP id v15mr489712wmj.123.1610058207316; Thu, 07 Jan 2021 14:23:27 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 06/66] target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1 Date: Thu, 7 Jan 2021 23:21:53 +0100 Message-Id: <20210107222253.20382-7-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.78 on 10.11.54.4 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable 'CPU_MIPS32' and 'CPU_MIPS64' definitions concern CPUs implementing the "Release 1" ISA. Rename it with the 'R1' suffix, as the other CPU definitions do. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20210104221154.3127610-4-f4bug@amsat.org> --- target/mips/mips-defs.h | 8 ++++---- target/mips/translate_init.c.inc | 14 +++++++------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 48544ba73b4..1630ae20d59 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -72,12 +72,12 @@ #define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI) =20 /* MIPS Technologies "Release 1" */ -#define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32) -#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64) +#define CPU_MIPS32R1 (CPU_MIPS2 | ISA_MIPS32) +#define CPU_MIPS64R1 (CPU_MIPS5 | CPU_MIPS32R1 | ISA_MIPS64) =20 /* MIPS Technologies "Release 2" */ -#define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) -#define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2) +#define CPU_MIPS32R2 (CPU_MIPS32R1 | ISA_MIPS32R2) +#define CPU_MIPS64R2 (CPU_MIPS64R1 | CPU_MIPS32R2 | ISA_MIPS64R2) =20 /* MIPS Technologies "Release 3" */ #define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3) diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.= c.inc index cac3d241831..0ba3cf18ef7 100644 --- a/target/mips/translate_init.c.inc +++ b/target/mips/translate_init.c.inc @@ -72,7 +72,7 @@ const mips_def_t mips_defs[] =3D .CP0_Status_rw_bitmask =3D 0x1278FF17, .SEGBITS =3D 32, .PABITS =3D 32, - .insn_flags =3D CPU_MIPS32, + .insn_flags =3D CPU_MIPS32R1, .mmu_type =3D MMU_TYPE_R4000, }, { @@ -94,7 +94,7 @@ const mips_def_t mips_defs[] =3D .CP0_Status_rw_bitmask =3D 0x1258FF17, .SEGBITS =3D 32, .PABITS =3D 32, - .insn_flags =3D CPU_MIPS32 | ASE_MIPS16, + .insn_flags =3D CPU_MIPS32R1 | ASE_MIPS16, .mmu_type =3D MMU_TYPE_FMT, }, { @@ -114,7 +114,7 @@ const mips_def_t mips_defs[] =3D .CP0_Status_rw_bitmask =3D 0x1278FF17, .SEGBITS =3D 32, .PABITS =3D 32, - .insn_flags =3D CPU_MIPS32, + .insn_flags =3D CPU_MIPS32R1, .mmu_type =3D MMU_TYPE_R4000, }, { @@ -134,7 +134,7 @@ const mips_def_t mips_defs[] =3D .CP0_Status_rw_bitmask =3D 0x1258FF17, .SEGBITS =3D 32, .PABITS =3D 32, - .insn_flags =3D CPU_MIPS32 | ASE_MIPS16, + .insn_flags =3D CPU_MIPS32R1 | ASE_MIPS16, .mmu_type =3D MMU_TYPE_FMT, }, { @@ -552,7 +552,7 @@ const mips_def_t mips_defs[] =3D .CP0_Status_rw_bitmask =3D 0x12F8FFFF, .SEGBITS =3D 42, .PABITS =3D 36, - .insn_flags =3D CPU_MIPS64, + .insn_flags =3D CPU_MIPS64R1, .mmu_type =3D MMU_TYPE_R4000, }, { @@ -578,7 +578,7 @@ const mips_def_t mips_defs[] =3D .CP1_fcr31_rw_bitmask =3D 0xFF83FFFF, .SEGBITS =3D 42, .PABITS =3D 36, - .insn_flags =3D CPU_MIPS64, + .insn_flags =3D CPU_MIPS64R1, .mmu_type =3D MMU_TYPE_R4000, }, { @@ -607,7 +607,7 @@ const mips_def_t mips_defs[] =3D .CP1_fcr31_rw_bitmask =3D 0xFF83FFFF, .SEGBITS =3D 40, .PABITS =3D 36, - .insn_flags =3D CPU_MIPS64 | ASE_MIPS3D, + .insn_flags =3D CPU_MIPS64R1 | ASE_MIPS3D, .mmu_type =3D MMU_TYPE_R4000, }, { --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.50 as permitted sender) client-ip=209.85.128.50; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f50.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1610058214; cv=none; d=zohomail.com; s=zohoarc; b=nBzbB+nMVCZ91RpbweSZ6rbJZfxZKsONwM8Rgl5cpqhSYLDcYZWLx+1Ug2x6iG8Y8JzSYs/e1mxn9yT/tfjhYGUfVvP2jRfJ2ft6GJlXgo91H59SGXk0iLkNLfDVFr72jS3rvzbtK6eXioqqtIe+GYOkD9KoHMGmYuOSnIht/Bw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610058214; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=3Ch2a+v0V9pkwP2v4j689PWjNoR3rWExCE6zEXoddgE=; b=mK1vBS00DDT8CqRUlQtwNluZ33YD//DPtb4vQmrIa60M7icu8c+SkM3n/z6TaAl8OZryje83T35jozDEy1E9b7LK0P/d+/kYqtrxEAry9Re3n7/iCB2X7YWzdRcjkwWYJcEcQVqW2R17QK/uOCZABiGaiFMW0PMQJ9RmfK8sqYY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) by mx.zohomail.com with SMTPS id 1610058214262401.3033402400637; Thu, 7 Jan 2021 14:23:34 -0800 (PST) Received: by mail-wm1-f50.google.com with SMTP id c133so6348028wme.4 for ; Thu, 07 Jan 2021 14:23:33 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (241.red-88-10-103.dynamicip.rima-tde.net. [88.10.103.241]) by smtp.gmail.com with ESMTPSA id h3sm9671549wmm.4.2021.01.07.14.23.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:23:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3Ch2a+v0V9pkwP2v4j689PWjNoR3rWExCE6zEXoddgE=; b=F57d2OKfrrp3wKUvNPdjKLIL1JjNbvqvSnUIGGYAFlnUEwYJnSrIJsmBM3RopRak9i ls8Hc9/z/VQpZL94Dgnuyez4a+4GmKVJ62vwUqMEXw1LqLFfAnKx55tyLiO+x6i6DKlE I0v9utPtcgZ8vGF/WVznVUUdeCoFsO1n67keu/29bZzyZxHHiX4COkED1sqeGQ5J+Rue fnz389ZQnM28/Y/Kexe39hHI8ybzDH8A3IrPf4WghREr8/W7OGaCfc7hgc7dOzvInRDF UsU6w7c3BBPtLA+fqNYIJKRDRbKhtE8ErP0MIJocmoo9Meg5sLsXnXF1VF4Uqu2Kg36R zsnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=3Ch2a+v0V9pkwP2v4j689PWjNoR3rWExCE6zEXoddgE=; b=RvFKXpoodm0tcD8HTnv4flCEDGM1zWpsQr20EiJSciJhrEM2YnwHsEPfmiRfK1RM/0 L2jN4n7zirGHgRyWQTUCoUOhI2HVgFaiH3tg2ZGaH88YDER/cqVHUPCkQ7rWZ75HFfzQ XsNM1yzK0gyAWFNOqHh6kYiTF6rsyEnKvEI2wOn8qsUld6zu2mOI77hIrGjyg3IPMiyM 1WqAmtCbS9K4gsbXO5pOEOJtxuOMvTSf3E4FiwF9L88pwqQ/J1vm0pF0LVveiYRrNqmJ sliNl4DGLPs+mbyCLjFdc9+lGDZ3371mRzjM2jJ29mIrqIUjDUg2rSULJ/bOs8fKtDUW S9MQ== X-Gm-Message-State: AOAM531Hg1Qy+PrA2lfvEyz3zRirkAN7eqJxbRZf6FCod0TyNo3YPYc7 HK9ATVo7Vc/sQTrsbzB8kzs= X-Google-Smtp-Source: ABdhPJzdXdIKcSBucUT3pYndkmoS5x60aKLlSZfLFhp/WfE/w7yrlfWqPpWEEiHMXDU748QZYuCVww== X-Received: by 2002:a1c:9692:: with SMTP id y140mr528197wmd.128.1610058212530; Thu, 07 Jan 2021 14:23:32 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: libvir-list@redhat.com, Paolo Bonzini , Laurent Vivier , kvm@vger.kernel.org, Jiaxun Yang , Aurelien Jarno , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Paul Burton , Richard Henderson Subject: [PULL 07/66] target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit() Date: Thu, 7 Jan 2021 23:21:54 +0100 Message-Id: <20210107222253.20382-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) MIPS 64-bit ISA is introduced with MIPS3. Introduce the CPU_MIPS64 definition aliased to the MIPS3 ISA, and the cpu_type_is_64bit() method to check if a CPU supports this ISA (thus is 64-bit). Suggested-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20210104221154.3127610-5-f4bug@amsat.org> --- target/mips/cpu.h | 5 +++++ target/mips/mips-defs.h | 4 +++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 0c2d397e4a9..9c45744c5c1 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1305,6 +1305,11 @@ static inline bool ase_mt_available(CPUMIPSState *en= v) return env->CP0_Config3 & (1 << CP0C3_MT); } =20 +static inline bool cpu_type_is_64bit(const char *cpu_type) +{ + return cpu_type_supports_isa(cpu_type, CPU_MIPS64); +} + void cpu_set_exception_base(int vp_index, target_ulong address); =20 /* addr.c */ diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 1630ae20d59..89a9a4dda31 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -13,7 +13,7 @@ */ #define ISA_MIPS1 0x0000000000000001ULL #define ISA_MIPS2 0x0000000000000002ULL -#define ISA_MIPS3 0x0000000000000004ULL +#define ISA_MIPS3 0x0000000000000004ULL /* 64-bit */ #define ISA_MIPS4 0x0000000000000008ULL #define ISA_MIPS5 0x0000000000000010ULL #define ISA_MIPS32 0x0000000000000020ULL @@ -71,6 +71,8 @@ #define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E) #define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI) =20 +#define CPU_MIPS64 (ISA_MIPS3) + /* MIPS Technologies "Release 1" */ #define CPU_MIPS32R1 (CPU_MIPS2 | ISA_MIPS32) #define CPU_MIPS64R1 (CPU_MIPS5 | CPU_MIPS32R1 | ISA_MIPS64) --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 63.128.21.124 as permitted sender) client-ip=63.128.21.124; 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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id o13sm11872381wrh.88.2021.01.07.14.23.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:23:37 -0800 (PST) X-MC-Unique: Bu8d98D3P8K-typDMeBkbw-1 X-MC-Unique: q7xnijFbNA2JNTauJOoM6A-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=3dEWbpDdPMdXRy3J2F2mLkOfTaazaI9EIz5mLCDLiyI=; b=L9LiYvFE0uCAppjde4XGW4z9M4+KpU0hGvkVilh2pyjWlhqIrmc61oV1FYulzSpD/b RoNqfsoGzhDz/fVDm6jGOptQvIfOCJZEfnfIVIHxlA4BZ3bmyE4dwJv/CutaWNmD2srz PghHqeqvGVF4621rckcm3XyGORrc1d+3meu5KDMHkt36jc0z0HIu/ulOMGEl90SKHX0p BaehAqB6GzOSlZNi90YceMd18FwH1EbwyhpH1IbdbQQ6cImypMetJqEDB75f7AKzCZrI SBZcjSqMsUIvnCeZmiXdlG+E3GURe5EVeufkzisNLt5L2WhpTLuPrL38p2jvXgntpxIK GTzw== X-Gm-Message-State: AOAM531QKiig2cgwy2HyNMP0hV0cLVNdSRrnpVCxh3ZBxUt8ND92J2uI DkJoxs2Uo6pTr4OXv3Dc9Bk= X-Google-Smtp-Source: ABdhPJxWBSZI/e+jPEoF1RloYNcT970YP2LcN6V5aQKKkXis7I1KbpzS65Ja/lqCJkM2rDokmSLgMg== X-Received: by 2002:adf:dd90:: with SMTP id x16mr645299wrl.85.1610058218031; Thu, 07 Jan 2021 14:23:38 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 08/66] hw/mips/boston: Check 64-bit support with cpu_type_is_64bit() Date: Thu, 7 Jan 2021 23:21:55 +0100 Message-Id: <20210107222253.20382-9-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.78 on 10.11.54.6 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Directly check if the CPU supports 64-bit with the recently added cpu_type_is_64bit() helper (inlined). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20210104221154.3127610-6-f4bug@amsat.org> --- hw/mips/boston.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/hw/mips/boston.c b/hw/mips/boston.c index c3b94c68e1b..467fbc1c8be 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -444,7 +444,6 @@ static void boston_mach_init(MachineState *machine) DriveInfo *hd[6]; Chardev *chr; int fw_size, fit_err; - bool is_64b; =20 if ((machine->ram_size % GiB) || (machine->ram_size > (2 * GiB))) { @@ -463,8 +462,6 @@ static void boston_mach_init(MachineState *machine) exit(1); } =20 - is_64b =3D cpu_type_supports_isa(machine->cpu_type, ISA_MIPS64); - object_initialize_child(OBJECT(machine), "cps", &s->cps, TYPE_MIPS_CPS= ); object_property_set_str(OBJECT(&s->cps), "cpu-type", machine->cpu_type, &error_fatal); @@ -545,7 +542,8 @@ static void boston_mach_init(MachineState *machine) } =20 gen_firmware(memory_region_get_ram_ptr(flash) + 0x7c00000, - s->kernel_entry, s->fdt_base, is_64b); + s->kernel_entry, s->fdt_base, + cpu_type_is_64bit(machine->cpu_type)); } else if (!qtest_enabled()) { error_report("Please provide either a -kernel or -bios argument"); exit(1); --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) client-ip=216.205.24.124; envelope-from=libvir-list-bounces@redhat.com; helo=us-smtp-delivery-124.mimecast.com; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) smtp.mailfrom=libvir-list-bounces@redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1610058245; cv=none; d=zohomail.com; s=zohoarc; b=VcM5XZdj8cpUk1ZeHRYyCPJ+7xniJiVZxoq0blPWOO3UpubY4drGnVhoenTBxhIjSA7n6U/RM9diIIopqhP9vGQBMerVBUM/Jd+WdW1DgF1oD37vOELZWQnoiOq01LwbF8LmtXSX5xIj4Dc1bfCPeOKt75l/f96lIH+TkF8+ZbE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610058245; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=JF+srhqzVhiG9h5YfjprayJ58NzAW66CVocxdnKYZak=; b=NcH+WQ8Ivr2m9vrPuv+W99VLYGtpN5TeCFTm9OlRg8QuoT1pT3f/zarq5DbpWj9xsXdWLRA/aMG1BNnij/ifLUY2BkPZi3ukUb3ZOrQgy82jQcPp49+iWmYj98791v263kWOzxBOnZ/02roRPPj1Vw0fd6iMvcfIIAOAYlGfFRo= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) smtp.mailfrom=libvir-list-bounces@redhat.com Return-Path: Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [216.205.24.124]) by mx.zohomail.com with SMTPS id 1610058245402792.7658557980822; Thu, 7 Jan 2021 14:24:05 -0800 (PST) Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-539-ilc4yFQBPTSAPkPBNFrJVA-1; Thu, 07 Jan 2021 17:24:01 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 4CBA3100C603; Thu, 7 Jan 2021 22:23:55 +0000 (UTC) Received: from colo-mx.corp.redhat.com (colo-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.20]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 29D8A62A22; Thu, 7 Jan 2021 22:23:55 +0000 (UTC) Received: from lists01.pubmisc.prod.ext.phx2.redhat.com (lists01.pubmisc.prod.ext.phx2.redhat.com [10.5.19.33]) by colo-mx.corp.redhat.com (Postfix) with ESMTP id E90741809CA3; Thu, 7 Jan 2021 22:23:54 +0000 (UTC) Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.rdu2.redhat.com [10.11.54.4]) by lists01.pubmisc.prod.ext.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id 107MNrJv028986 for ; Thu, 7 Jan 2021 17:23:53 -0500 Received: by smtp.corp.redhat.com (Postfix) id EFBDF2026D46; Thu, 7 Jan 2021 22:23:52 +0000 (UTC) Received: from mimecast-mx02.redhat.com (mimecast02.extmail.prod.ext.rdu2.redhat.com [10.11.55.18]) by smtp.corp.redhat.com (Postfix) with ESMTPS id E66812026D12 for ; Thu, 7 Jan 2021 22:23:48 +0000 (UTC) Received: from us-smtp-1.mimecast.com (us-smtp-1.mimecast.com [207.211.31.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 6A5DD8007D9 for ; Thu, 7 Jan 2021 22:23:48 +0000 (UTC) Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-393-8Hrww3jFMeeHNxkWT5cC0g-1; Thu, 07 Jan 2021 17:23:44 -0500 Received: by mail-wm1-f45.google.com with SMTP id 3so6817777wmg.4; Thu, 07 Jan 2021 14:23:44 -0800 (PST) Received: from x1w.redhat.com (241.red-88-10-103.dynamicip.rima-tde.net. [88.10.103.241]) by smtp.gmail.com with ESMTPSA id c6sm10834861wrh.7.2021.01.07.14.23.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:23:42 -0800 (PST) X-MC-Unique: ilc4yFQBPTSAPkPBNFrJVA-1 X-MC-Unique: 8Hrww3jFMeeHNxkWT5cC0g-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=JF+srhqzVhiG9h5YfjprayJ58NzAW66CVocxdnKYZak=; b=BeqX3YmA+p24iKlDzHlyXJ0KmufnGf6gQ8XuJp4UzXB6YcNn+jyvzEHakmC6KgIKRe 8t4O0IvGOI1YTJZCi8Gjiprh//Qr4Ts66GSNNIA+R2k2zJP8ITNNbAcLYcvl5HWHeidF Rf0OCzB25Y/eJqGs3FdX1Dda4G83SpVGMC2rn1lbfnqyhAuWiBEIQFv4Sb5QbjrQu+VP vql6KLRMgbxvd0LsSTgSCUfkq0vz7kJtX2DgG0DGDDnOLruhegPCKcazyYGFAx8ZUycm JZvLZQTjPQZCt7FV4sEsaKcDiIwN31IoPAO7nXcyerYLvcqAVNVKryPVILyvsWwYYwJ8 WkQQ== X-Gm-Message-State: AOAM533q6DRG+pS5lHjm/0/F/Hci2RzsHCCWt0GN574dhL8+eEaBlydA iNaEkLaYOGze/QjGZUrR0S8= X-Google-Smtp-Source: ABdhPJyqDIoi12kS/zEfaBOSjiMRo+zjIF9jiFqHqRZVWv01024Gv+Yl22rTTDgoM4CVyIbrMKG0xA== X-Received: by 2002:a1c:4904:: with SMTP id w4mr507415wma.140.1610058223270; Thu, 07 Jan 2021 14:23:43 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 09/66] target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1 Date: Thu, 7 Jan 2021 23:21:56 +0100 Message-Id: <20210107222253.20382-10-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.78 on 10.11.54.4 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Use the single ISA_MIPS32 definition to check if the Release 1 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R1 in few commits. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210104221154.3127610-7-f4bug@amsat.org> --- target/mips/mips-defs.h | 3 +-- target/mips/translate.c | 10 +++++----- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 89a9a4dda31..23ce8b8406f 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -18,7 +18,6 @@ #define ISA_MIPS5 0x0000000000000010ULL #define ISA_MIPS32 0x0000000000000020ULL #define ISA_MIPS32R2 0x0000000000000040ULL -#define ISA_MIPS64 0x0000000000000080ULL #define ISA_MIPS64R2 0x0000000000000100ULL #define ISA_MIPS32R3 0x0000000000000200ULL #define ISA_MIPS64R3 0x0000000000000400ULL @@ -75,7 +74,7 @@ =20 /* MIPS Technologies "Release 1" */ #define CPU_MIPS32R1 (CPU_MIPS2 | ISA_MIPS32) -#define CPU_MIPS64R1 (CPU_MIPS5 | CPU_MIPS32R1 | ISA_MIPS64) +#define CPU_MIPS64R1 (CPU_MIPS5 | CPU_MIPS32R1) =20 /* MIPS Technologies "Release 2" */ #define CPU_MIPS32R2 (CPU_MIPS32R1 | ISA_MIPS32R2) diff --git a/target/mips/translate.c b/target/mips/translate.c index 19933b7868c..172027f9d6e 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -8943,7 +8943,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) const char *register_name =3D "invalid"; =20 if (sel !=3D 0) { - check_insn(ctx, ISA_MIPS64); + check_insn(ctx, ISA_MIPS32); } =20 switch (reg) { @@ -9669,7 +9669,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) const char *register_name =3D "invalid"; =20 if (sel !=3D 0) { - check_insn(ctx, ISA_MIPS64); + check_insn(ctx, ISA_MIPS32); } =20 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { @@ -14907,12 +14907,12 @@ static int decode_mips16_opc(CPUMIPSState *env, D= isasContext *ctx) break; #if defined(TARGET_MIPS64) case RR_RY_CNVT_ZEW: - check_insn(ctx, ISA_MIPS64); + check_insn(ctx, ISA_MIPS32); check_mips_64(ctx); tcg_gen_ext32u_tl(cpu_gpr[rx], cpu_gpr[rx]); break; case RR_RY_CNVT_SEW: - check_insn(ctx, ISA_MIPS64); + check_insn(ctx, ISA_MIPS32); check_mips_64(ctx); tcg_gen_ext32s_tl(cpu_gpr[rx], cpu_gpr[rx]); break; @@ -27612,7 +27612,7 @@ static void decode_opc_special2_legacy(CPUMIPSState= *env, DisasContext *ctx) #if defined(TARGET_MIPS64) case OPC_DCLO: case OPC_DCLZ: - check_insn(ctx, ISA_MIPS64); + check_insn(ctx, ISA_MIPS32); check_mips_64(ctx); gen_cl(ctx, op1, rd, rs); break; --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) client-ip=216.205.24.124; envelope-from=libvir-list-bounces@redhat.com; helo=us-smtp-delivery-124.mimecast.com; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) smtp.mailfrom=libvir-list-bounces@redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1610058248; cv=none; d=zohomail.com; s=zohoarc; b=gUNSVHmApJEKGP0IjH1XIMgiTg9Xm2t7jk1n0sz47k/wskA98jSd4N7KoydM+r5qJQw/7Ctk88lHaDf4wp1Q2yAtc9o28+wLWlVDSyHYDqOrpoiCCG1kI/hnekpe7wcscZ9dbdwqfmnie6x3+za0w1k4oYE2FnNflTQx3tQDXog= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610058248; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id e15sm10531456wrx.86.2021.01.07.14.23.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:23:47 -0800 (PST) X-MC-Unique: 0JlDQgTkOm6I9zVdXie-Pw-1 X-MC-Unique: VQZZn5WNMYq7YtoUrKxo4g-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=RavFb6dHUeenzrSfS/Q/TJH5UznJIUfWdY3rLcA4ySo=; b=kewYlEP8lSzM211xG6IjETrSqxiODqkiOzmXMjOHe2i4mmCCvkl1nKOpAr6QSdmGiP 1eqNVVwhsVcefQF5KSpAJUXxs/HnpdmC5A0+5ZPTdnptN5ikKC/nZE9kXGmpBTLkCp8x Q8yYujhRyJTLOXFgsDiSlqR/V5NRnIc978qDt8ZXZNO2ySY0ftpl/L7sWWkp3N2Q2WBl MsgO7hs7589Nlr0I1C+BIYC+97KqrDVekmFLra1iUbwGQMxeKPlmLJSFC7etjtOZX2Df pZJJERbG2qWv/7SA1NwNZ8xdG1+BjuwM+0OnRoM4Dv8j1T3q6D/YIqV2MMoEDDKSh9Jz oUrQ== X-Gm-Message-State: AOAM533+FxDh5eYxJRjwF8WDdJaVNVxafPf4fbQpx0/dcmkREo9VFLfg ySTVhA50JG9ZTT5trT6G2lQ= X-Google-Smtp-Source: ABdhPJzUXXuSdtPR6ULt4R79zWpOOuF4QmJ5/Gvwe7kpCeGD2sb3/+U49oGXlw0Hv5NJhAtc0Km/iw== X-Received: by 2002:a1c:9ac6:: with SMTP id c189mr492866wme.137.1610058228349; Thu, 07 Jan 2021 14:23:48 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 10/66] target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2 Date: Thu, 7 Jan 2021 23:21:57 +0100 Message-Id: <20210107222253.20382-11-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Use the single ISA_MIPS32R2 definition to check if the Release 2 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R2 in few commits. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210104221154.3127610-8-f4bug@amsat.org> --- target/mips/mips-defs.h | 3 +-- linux-user/mips/cpu_loop.c | 1 - target/mips/translate.c | 4 ++-- 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 23ce8b8406f..b36b59c12d3 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -18,7 +18,6 @@ #define ISA_MIPS5 0x0000000000000010ULL #define ISA_MIPS32 0x0000000000000020ULL #define ISA_MIPS32R2 0x0000000000000040ULL -#define ISA_MIPS64R2 0x0000000000000100ULL #define ISA_MIPS32R3 0x0000000000000200ULL #define ISA_MIPS64R3 0x0000000000000400ULL #define ISA_MIPS32R5 0x0000000000000800ULL @@ -78,7 +77,7 @@ =20 /* MIPS Technologies "Release 2" */ #define CPU_MIPS32R2 (CPU_MIPS32R1 | ISA_MIPS32R2) -#define CPU_MIPS64R2 (CPU_MIPS64R1 | CPU_MIPS32R2 | ISA_MIPS64R2) +#define CPU_MIPS64R2 (CPU_MIPS64R1 | CPU_MIPS32R2) =20 /* MIPS Technologies "Release 3" */ #define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3) diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index cfe7ba5c47d..f0831379cc4 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -385,7 +385,6 @@ void target_cpu_copy_regs(CPUArchState *env, struct tar= get_pt_regs *regs) prog_req.fre &=3D interp_req.fre; =20 bool cpu_has_mips_r2_r6 =3D env->insn_flags & ISA_MIPS32R2 || - env->insn_flags & ISA_MIPS64R2 || env->insn_flags & ISA_MIPS32R6 || env->insn_flags & ISA_MIPS64R6; =20 diff --git a/target/mips/translate.c b/target/mips/translate.c index 172027f9d6e..9fc9dedf30d 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28621,7 +28621,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) case OPC_DINSM: case OPC_DINSU: case OPC_DINS: - check_insn(ctx, ISA_MIPS64R2); + check_insn(ctx, ISA_MIPS32R2); check_mips_64(ctx); gen_bitops(ctx, op1, rt, rs, sa, rd); break; @@ -28641,7 +28641,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) decode_opc_special3_r6(env, ctx); break; default: - check_insn(ctx, ISA_MIPS64R2); + check_insn(ctx, ISA_MIPS32R2); check_mips_64(ctx); op2 =3D MASK_DBSHFL(ctx->opcode); gen_bshfl(ctx, op2, rt, rd); --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 63.128.21.124 as permitted sender) client-ip=63.128.21.124; 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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id j9sm9990483wrm.14.2021.01.07.14.23.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:23:52 -0800 (PST) X-MC-Unique: rAaCkRvqMveSXhP6KxF1jQ-1 X-MC-Unique: aXlHywnZNVWgXtg83r5fZQ-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Sk0GjPOwaKw1OtxDzWJCyQVWdlOOm+hBJhH4fWESj5c=; b=sxSdd2RJ1046XV+FDvjzoy1UnRRGAp+agbWGUoN3anJPh469t1qQ8NgkHlvXqFbku+ xJb9NUzLSOsfqV5Bw5exWFeigoxM/qB0wawo0Wl9K+pcEzIeIlEZC5MByIw5aOvu8qmJ 2eDobGAkhptoghKkZa8GmtwfVXjxqmmClv6TZBe60jJ/Ja9U/Svr+YsO0ZyHKg530IzJ zp97DYb0lckqmUVqNAioG3CfsOzTGDQCHEMvOhVtt+7ijPukNWiWt/W8cAkmcZ2A5qNU re4zMyDCLwVR3Xb4jwNS54abO58qkqH2IRwXOGZDSozi0W/W/6ogUVzESD8IEpH+dnno tiFg== X-Gm-Message-State: AOAM531JharInFU5vjUUWNUHHl4rohl9Zzn2M8XZ2cVcV9M8pyA+ogBP GEngQru4kn1yuc7L8CDB46s= X-Google-Smtp-Source: ABdhPJxfMY/2VlzrtrNQv5zadl7d7OP9CwGcm/sT/2JQXSTpWmw1iz3t3qwI+FOR73I7mUwUdKKAgA== X-Received: by 2002:adf:e688:: with SMTP id r8mr687398wrm.20.1610058233425; Thu, 07 Jan 2021 14:23:53 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 11/66] target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3 Date: Thu, 7 Jan 2021 23:21:58 +0100 Message-Id: <20210107222253.20382-12-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Use the single ISA_MIPS32R3 definition to check if the Release 3 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R3 in few commits. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210104221154.3127610-9-f4bug@amsat.org> --- target/mips/mips-defs.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index b36b59c12d3..ccdde0b4a43 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -19,7 +19,6 @@ #define ISA_MIPS32 0x0000000000000020ULL #define ISA_MIPS32R2 0x0000000000000040ULL #define ISA_MIPS32R3 0x0000000000000200ULL -#define ISA_MIPS64R3 0x0000000000000400ULL #define ISA_MIPS32R5 0x0000000000000800ULL #define ISA_MIPS64R5 0x0000000000001000ULL #define ISA_MIPS32R6 0x0000000000002000ULL @@ -81,7 +80,7 @@ =20 /* MIPS Technologies "Release 3" */ #define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3) -#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3) +#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3) =20 /* MIPS Technologies "Release 5" */ #define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5) --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 63.128.21.124 as permitted sender) client-ip=63.128.21.124; envelope-from=libvir-list-bounces@redhat.com; helo=us-smtp-delivery-124.mimecast.com; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of redhat.com designates 63.128.21.124 as permitted sender) smtp.mailfrom=libvir-list-bounces@redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1610058261; cv=none; d=zohomail.com; s=zohoarc; b=Prf3OgP0Tq6iEXohI8rcs+sgivK5U/cM3ax8HTuV/6/EoMydewvPpBCnNwt/MTwMwef1KkeWESWoSiBk+ogHVRlbNSVmgg2d23XXaK6t8TY0dDJHh5QNJFDs1VH4+efEUynI0PmGDojJNYJQsQnRZ33hEPBTU8H8Eq9v6cre8EU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610058261; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=R9iTS/+Q/OL/iW6QRfMv5vZReuHwVb5bW5AGpFsloxk=; b=b90y6mV7iqttFs2nYl5OPvZPEjmPFUJwbxK1TUAjC6eBm2ol67155GXiuclZ/NI4zBKSE1SE0yyUJqAS7xvoWCaNAXIbuAOH3X77CUYSX2KcGeH6oI0U/Gq9hd56bm5uV9bLoGTnZxwqjWlxOA8vFNbqjtvC8UTCRGYe3l1z+7Y= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of redhat.com designates 63.128.21.124 as permitted sender) smtp.mailfrom=libvir-list-bounces@redhat.com Return-Path: Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [63.128.21.124]) by mx.zohomail.com with SMTPS id 1610058261171358.6767026147494; Thu, 7 Jan 2021 14:24:21 -0800 (PST) Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-112-d8m1lQU8NZ2mMrWF8fj0PQ-1; Thu, 07 Jan 2021 17:24:17 -0500 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 5D032107ACF6; Thu, 7 Jan 2021 22:24:11 +0000 (UTC) Received: from colo-mx.corp.redhat.com (colo-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.21]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 381CB1042A83; Thu, 7 Jan 2021 22:24:11 +0000 (UTC) Received: from lists01.pubmisc.prod.ext.phx2.redhat.com (lists01.pubmisc.prod.ext.phx2.redhat.com [10.5.19.33]) by colo-mx.corp.redhat.com (Postfix) with ESMTP id 02D2850032; Thu, 7 Jan 2021 22:24:11 +0000 (UTC) Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.rdu2.redhat.com [10.11.54.5]) by lists01.pubmisc.prod.ext.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id 107MO9Pw029171 for ; Thu, 7 Jan 2021 17:24:09 -0500 Received: by smtp.corp.redhat.com (Postfix) id 222A1D7B10; Thu, 7 Jan 2021 22:24:09 +0000 (UTC) Received: from mimecast-mx02.redhat.com (mimecast01.extmail.prod.ext.rdu2.redhat.com [10.11.55.17]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 1B529D7B1D for ; Thu, 7 Jan 2021 22:24:04 +0000 (UTC) Received: from us-smtp-1.mimecast.com (us-smtp-2.mimecast.com [205.139.110.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id B95E7858280 for ; Thu, 7 Jan 2021 22:24:04 +0000 (UTC) Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-586-I_M8m6K7MM-sUVssuG1lGA-1; Thu, 07 Jan 2021 17:24:00 -0500 Received: by mail-wr1-f48.google.com with SMTP id r3so7139269wrt.2; Thu, 07 Jan 2021 14:23:59 -0800 (PST) Received: from x1w.redhat.com (241.red-88-10-103.dynamicip.rima-tde.net. [88.10.103.241]) by smtp.gmail.com with ESMTPSA id c16sm10724308wrx.51.2021.01.07.14.23.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:23:57 -0800 (PST) X-MC-Unique: d8m1lQU8NZ2mMrWF8fj0PQ-1 X-MC-Unique: I_M8m6K7MM-sUVssuG1lGA-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=R9iTS/+Q/OL/iW6QRfMv5vZReuHwVb5bW5AGpFsloxk=; b=hLcXl59h/Isn56pm5Zre2e23xL/ciV1QH+ea3/lhHHLXuZ+nR/I2Y8dum4JlEd8pUV yneNCCCVnhSHtV1utXMtGA+TjROv3yH1gh797zGE+QbPcd7NuRjmf8259urT6tZUQb2O 58L5q3AJivhs+avuFb+12npkynrJZZHRMy/duGFeOHqZTKIjrpi2y45caocwCBQhtEl8 62xn1aeDZuSeTW/HiyVAvSIVfcTwx9dEdJSFw8WqqxJF/d+BbB3mMEnxuNcfCk4j+IAQ knASOSU+a4LZi3Id620GFfzrurOVfaT+oSRLjSh3M5CZgnyxwo5s+pLgUZIjiPRdxZQn QUGg== X-Gm-Message-State: AOAM533EMg3xC1ldEz8gjvxi1IcB2taxIKd5kUag0U5tPa74KTP3YPQ4 3FcOKP/o08R5skHSqKSwM9s= X-Google-Smtp-Source: ABdhPJy0sO863+4qLz2HdBGbQrXuLugI5GKgLWVCcPwhAv9Pa6qnXGqqntjW9U6RUL8K1L83XVKcEw== X-Received: by 2002:a5d:6a4c:: with SMTP id t12mr657799wrw.249.1610058238789; Thu, 07 Jan 2021 14:23:58 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 12/66] target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5 Date: Thu, 7 Jan 2021 23:21:59 +0100 Message-Id: <20210107222253.20382-13-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.79 on 10.11.54.5 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Use the single ISA_MIPS32R5 definition to check if the Release 5 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R5 in few commits. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210104221154.3127610-10-f4bug@amsat.org> --- target/mips/mips-defs.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index ccdde0b4a43..b71127ddd7c 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -20,7 +20,6 @@ #define ISA_MIPS32R2 0x0000000000000040ULL #define ISA_MIPS32R3 0x0000000000000200ULL #define ISA_MIPS32R5 0x0000000000000800ULL -#define ISA_MIPS64R5 0x0000000000001000ULL #define ISA_MIPS32R6 0x0000000000002000ULL #define ISA_MIPS64R6 0x0000000000004000ULL #define ISA_NANOMIPS32 0x0000000000008000ULL @@ -84,7 +83,7 @@ =20 /* MIPS Technologies "Release 5" */ #define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5) -#define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5 | ISA_MIPS64R5) +#define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5) =20 /* MIPS Technologies "Release 6" */ #define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6) --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) client-ip=216.205.24.124; envelope-from=libvir-list-bounces@redhat.com; helo=us-smtp-delivery-124.mimecast.com; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) smtp.mailfrom=libvir-list-bounces@redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1610058265; cv=none; d=zohomail.com; s=zohoarc; b=KAleGU9mzeiHSC328MWTdKbEHZWPDcahYNKQu7aSOm62tWFx4Du5VDJp2TZ71jhXXIK0wbVH0Xckx2Y9UjUW/5gCo4yLoNTmj2qz0tkI6/pQU5eYNVx3Q3BR+WBvoP2+V7R6eLvC3wBdngxDnCQO1RG93nZUg423eEviXEk/x64= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610058265; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qSV6cUIXNddxL4SLc4iJCGuI243MH3AVKaHvwWDIY1Q=; b=Iv+6bnv/jK+NmejUs9Ju+8CRYaXrrITdaiCRMrmaLXPGiGkG6rLPZCjMHwSRIJmbfZbRJ8Il8aod35uvRZ4/wXX7IP25XgeW8N6CJYbgpkF7Gr7RayvgaYG5hX096RLGu1kLIDTDdSFw+KL+S/z9WGw/DcR1Z3LS8c/Uwas8Z90= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) smtp.mailfrom=libvir-list-bounces@redhat.com Return-Path: Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [216.205.24.124]) by mx.zohomail.com with SMTPS id 1610058265415859.1359686745765; Thu, 7 Jan 2021 14:24:25 -0800 (PST) Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-35-CygAqEHiMDazGlpQsUxHLQ-1; Thu, 07 Jan 2021 17:24:21 -0500 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 243CF100C605; Thu, 7 Jan 2021 22:24:14 +0000 (UTC) Received: from colo-mx.corp.redhat.com (colo-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.20]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 0385919813; Thu, 7 Jan 2021 22:24:14 +0000 (UTC) Received: from lists01.pubmisc.prod.ext.phx2.redhat.com (lists01.pubmisc.prod.ext.phx2.redhat.com [10.5.19.33]) by colo-mx.corp.redhat.com (Postfix) with ESMTP id BE5861809CA3; Thu, 7 Jan 2021 22:24:13 +0000 (UTC) Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.rdu2.redhat.com [10.11.54.4]) by lists01.pubmisc.prod.ext.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id 107MOASZ029199 for ; Thu, 7 Jan 2021 17:24:10 -0500 Received: by smtp.corp.redhat.com (Postfix) id B27D92026D11; Thu, 7 Jan 2021 22:24:10 +0000 (UTC) Received: from mimecast-mx02.redhat.com (mimecast05.extmail.prod.ext.rdu2.redhat.com [10.11.55.21]) by smtp.corp.redhat.com (Postfix) with ESMTPS id ADE6B2026D46 for ; Thu, 7 Jan 2021 22:24:08 +0000 (UTC) Received: from us-smtp-1.mimecast.com (us-smtp-delivery-1.mimecast.com [207.211.31.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 6C95C8008A5 for ; Thu, 7 Jan 2021 22:24:08 +0000 (UTC) Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-351-fzynfOmaOGyRnxXa8JUdKg-1; Thu, 07 Jan 2021 17:24:05 -0500 Received: by mail-wr1-f44.google.com with SMTP id w5so7084806wrm.11; Thu, 07 Jan 2021 14:24:04 -0800 (PST) Received: from x1w.redhat.com (241.red-88-10-103.dynamicip.rima-tde.net. [88.10.103.241]) by smtp.gmail.com with ESMTPSA id c18sm12260023wmk.0.2021.01.07.14.24.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:24:03 -0800 (PST) X-MC-Unique: CygAqEHiMDazGlpQsUxHLQ-1 X-MC-Unique: fzynfOmaOGyRnxXa8JUdKg-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=qSV6cUIXNddxL4SLc4iJCGuI243MH3AVKaHvwWDIY1Q=; b=tEf15rG+bxKRsmNKrGKiLy50mXtA24ankmL1JznbFx+CQBNL7A4N9odstoQ8dts9K3 QeBIYF55fLj2oh5R3QqH2DG6OfTGMN1FtAZBp1ZS7dx5nbqj9gMlGaMmzjWVm2foAA93 TOtC0oNsk4ZaYQnYAeHjMHJvCcQuss4gVV0JINbZZxAd86SQ0GJf5NFtI3D+2D8hsPJU 3N0im90hSV61AJUDnZb1Tc8W2gsypajxFxBhxhVEQ7aKLklbXE+j393vTbiScWJpOgxo Klc3Ch3WxOGPthXfna6TaN2w5fvmQ4Y/NOmtSsX2qanbGcgBq/P9Q1IW2/Y2+1V+vbpk x/fA== X-Gm-Message-State: AOAM5336VrwWoVM36kM3bEsN2k8CwfnK7Ch0Ay7Bx2pPlnbEbJIwwhCg MAm7kv3Z+5HT0JpswQ4tu08= X-Google-Smtp-Source: ABdhPJyzuSYApH/LEUIk3VZce9bmGliTdDaDj8EIBV0nDYtvElZ7LTqhhA8lxJOM0epf3pu5FwmgUg== X-Received: by 2002:adf:ffc8:: with SMTP id x8mr688100wrs.158.1610058243946; Thu, 07 Jan 2021 14:24:03 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 13/66] target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6 Date: Thu, 7 Jan 2021 23:22:00 +0100 Message-Id: <20210107222253.20382-14-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.78 on 10.11.54.4 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Use the single ISA_MIPS32R6 definition to check if the Release 6 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R6 in few commits. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210104221154.3127610-11-f4bug@amsat.org> --- target/mips/internal.h | 2 +- target/mips/mips-defs.h | 3 +-- linux-user/mips/cpu_loop.c | 3 +-- target/mips/helper.c | 6 +++--- target/mips/translate.c | 2 +- 5 files changed, 7 insertions(+), 9 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index e4d2d9f44f9..3466725b761 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -354,7 +354,7 @@ static inline void compute_hflags(CPUMIPSState *env) } else if (((env->hflags & MIPS_HFLAG_KSU) =3D=3D MIPS_HFLAG_UM) && !(env->CP0_Status & (1 << CP0St_UX))) { env->hflags |=3D MIPS_HFLAG_AWRAP; - } else if (env->insn_flags & ISA_MIPS64R6) { + } else if (env->insn_flags & ISA_MIPS32R6) { /* Address wrapping for Supervisor and Kernel is specified in R6 */ if ((((env->hflags & MIPS_HFLAG_KSU) =3D=3D MIPS_HFLAG_SM) && !(env->CP0_Status & (1 << CP0St_SX))) || diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index b71127ddd7c..fea547508f0 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -21,7 +21,6 @@ #define ISA_MIPS32R3 0x0000000000000200ULL #define ISA_MIPS32R5 0x0000000000000800ULL #define ISA_MIPS32R6 0x0000000000002000ULL -#define ISA_MIPS64R6 0x0000000000004000ULL #define ISA_NANOMIPS32 0x0000000000008000ULL /* * bits 24-39: MIPS ASEs @@ -87,7 +86,7 @@ =20 /* MIPS Technologies "Release 6" */ #define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6) -#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6) +#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6) =20 /* Wave Computing: "nanoMIPS" */ #define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32) diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index f0831379cc4..e400166c583 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -385,8 +385,7 @@ void target_cpu_copy_regs(CPUArchState *env, struct tar= get_pt_regs *regs) prog_req.fre &=3D interp_req.fre; =20 bool cpu_has_mips_r2_r6 =3D env->insn_flags & ISA_MIPS32R2 || - env->insn_flags & ISA_MIPS32R6 || - env->insn_flags & ISA_MIPS64R6; + env->insn_flags & ISA_MIPS32R6; =20 if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) { env->CP0_Config5 |=3D (1 << CP0C5_FRE); diff --git a/target/mips/helper.c b/target/mips/helper.c index 87296fbad69..5b74815beb0 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -1145,7 +1145,7 @@ void mips_cpu_do_interrupt(CPUState *cs) enter_debug_mode: if (env->insn_flags & ISA_MIPS3) { env->hflags |=3D MIPS_HFLAG_64; - if (!(env->insn_flags & ISA_MIPS64R6) || + if (!(env->insn_flags & ISA_MIPS32R6) || env->CP0_Status & (1 << CP0St_KX)) { env->hflags &=3D ~MIPS_HFLAG_AWRAP; } @@ -1174,7 +1174,7 @@ void mips_cpu_do_interrupt(CPUState *cs) env->CP0_Status |=3D (1 << CP0St_ERL) | (1 << CP0St_BEV); if (env->insn_flags & ISA_MIPS3) { env->hflags |=3D MIPS_HFLAG_64; - if (!(env->insn_flags & ISA_MIPS64R6) || + if (!(env->insn_flags & ISA_MIPS32R6) || env->CP0_Status & (1 << CP0St_KX)) { env->hflags &=3D ~MIPS_HFLAG_AWRAP; } @@ -1360,7 +1360,7 @@ void mips_cpu_do_interrupt(CPUState *cs) env->CP0_Status |=3D (1 << CP0St_EXL); if (env->insn_flags & ISA_MIPS3) { env->hflags |=3D MIPS_HFLAG_64; - if (!(env->insn_flags & ISA_MIPS64R6) || + if (!(env->insn_flags & ISA_MIPS32R6) || env->CP0_Status & (1 << CP0St_KX)) { env->hflags &=3D ~MIPS_HFLAG_AWRAP; } diff --git a/target/mips/translate.c b/target/mips/translate.c index 9fc9dedf30d..fc93b9da8eb 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -31438,7 +31438,7 @@ static void mips_tr_init_disas_context(DisasContext= Base *dcbase, CPUState *cs) #else ctx->mem_idx =3D hflags_mmu_index(ctx->hflags); #endif - ctx->default_tcg_memop_mask =3D (ctx->insn_flags & (ISA_MIPS32R6 | ISA= _MIPS64R6 | + ctx->default_tcg_memop_mask =3D (ctx->insn_flags & (ISA_MIPS32R6 | INSN_LOONGSON3A)) ? MO_UNALN : MO_ALIGN; =20 LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx, --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.51 as permitted sender) client-ip=209.85.128.51; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f51.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1610058250; cv=none; d=zohomail.com; s=zohoarc; b=TjJDfm8R6dlpeMCOAvpY9KpVCY58ODIXERp7t4JDfuZraP3vjjVszHzpf7qc0V1qZMDYk78zvABixJ4UUZui7MnCKdDrYlJWNOujv5bAdYkqTQkorOnrlT5y802YBruJpGehTRodLxCP6HUCgPDD3Kx02MHvWaV9oshi1r27n58= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610058250; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lyrz/PhO4KF7gD9TiETRABWrYhrHwF0TOd6pyZtd8B4=; b=WP1byVfmS1qW04j2VfjCM47ATZ/1n0uYDMtEcSZ4TSyjP+561Gfsen7F/TA0rIIDEOtMoRfPs83z/0+a32P4WKxe2x6Np+xXukiBXAk4bQFBRKwsmdsOBGQRSVvmeiVCiXrRCeyR9nSQ+YDH6dtOKJcM/B75jc4SDgiA4IUdmqg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) by mx.zohomail.com with SMTPS id 1610058250929229.00265278190466; Thu, 7 Jan 2021 14:24:10 -0800 (PST) Received: by mail-wm1-f51.google.com with SMTP id 3so6818407wmg.4 for ; Thu, 07 Jan 2021 14:24:10 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (241.red-88-10-103.dynamicip.rima-tde.net. [88.10.103.241]) by smtp.gmail.com with ESMTPSA id x25sm9186197wmc.3.2021.01.07.14.24.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:24:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lyrz/PhO4KF7gD9TiETRABWrYhrHwF0TOd6pyZtd8B4=; b=sQ6N6WefI+pC37et7AQvNKqPmeZHt6XZFKQmnwsHv8LaWG/5fcjRKYNQhzeYW0+eA3 aajtada7+Gx/A27Awl6VL8x380j+VuZ+2GQHroqs+tYY8dCPm31+w1klsLJ7SWpVD7Fl KiE37Xsji1u3IP6rrkaRIOV7qKnr4JgnalFVNSqq4P5QA5NclmRWwihL1hiqb9k5ltIj u1BLS9kHQIEwSo0JgEFlrKDsvQCebe+SeE1G9lAQIWVwy8fnld4WBgvpcOLNAG63ZqHs EKiZrzP3xpuRrkXpDYeXJr0/0RP1Hubb5xHvhpmR/YZIlWBSglUQvN48BFMJ3XKoef8Z uBuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=lyrz/PhO4KF7gD9TiETRABWrYhrHwF0TOd6pyZtd8B4=; b=HoXMQlo7Ixj3xhOy58gUKOYRpx9bWEcUcWhVp/+TeDJ0Si+xzd97yH+dGJqN5+JiEY 6epXLQOSk6pxmUJyQ8DQMAv97DxwmN8VvBUYgCgqjA4Lk5Ow7jvCdb9i5OvDA8CH+t6+ m7Lz0ghtbaGsk2v0hHRdsJE+HraA3zEgP+NLDcQg/7Iptmc7730qBpmjHWgD9K3L926e hToa7PdIIwq9Lfo+0YTSSutzxJvkREq5NkSKYidHe7QJoEdE68EvBHvu4m45SARoqdvU TEsEetsAih870vTildcRsAuhPmVEDzbTFJTIdvrdlDqZQVJaznE8HzciUnGUQVGnarN/ sK6Q== X-Gm-Message-State: AOAM530HpMs9iUhMYzkaxOJFHt+2O3N8G5QnMHF8LfMECofP8qE7FuLo blCanRZS5B0eSkfZ7p2r0BkUAF/x4aI= X-Google-Smtp-Source: ABdhPJx2m9NGD8CwX3+QH+HzByCdi2UV+8vXuh4fZXwBIItQJi1frALwUcovpoTq6hhtRZJjFBfv9Q== X-Received: by 2002:a1c:df85:: with SMTP id w127mr527600wmg.166.1610058249087; Thu, 07 Jan 2021 14:24:09 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: libvir-list@redhat.com, Paolo Bonzini , Laurent Vivier , kvm@vger.kernel.org, Jiaxun Yang , Aurelien Jarno , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Paul Burton , Richard Henderson Subject: [PULL 14/66] target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1 Date: Thu, 7 Jan 2021 23:22:01 +0100 Message-Id: <20210107222253.20382-15-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The MIPS ISA release '1' is common to 32/64-bit CPUs. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210104221154.3127610-12-f4bug@amsat.org> --- target/mips/internal.h | 2 +- target/mips/mips-defs.h | 4 +-- target/mips/translate.c | 54 ++++++++++++++++++++--------------------- 3 files changed, 30 insertions(+), 30 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 3466725b761..94910f75a61 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -411,7 +411,7 @@ static inline void compute_hflags(CPUMIPSState *env) if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { env->hflags |=3D MIPS_HFLAG_COP1X; } - } else if (env->insn_flags & ISA_MIPS32) { + } else if (env->insn_flags & ISA_MIPS_R1) { if (env->hflags & MIPS_HFLAG_64) { env->hflags |=3D MIPS_HFLAG_COP1X; } diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index fea547508f0..a7048ffaffe 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -16,7 +16,7 @@ #define ISA_MIPS3 0x0000000000000004ULL /* 64-bit */ #define ISA_MIPS4 0x0000000000000008ULL #define ISA_MIPS5 0x0000000000000010ULL -#define ISA_MIPS32 0x0000000000000020ULL +#define ISA_MIPS_R1 0x0000000000000020ULL #define ISA_MIPS32R2 0x0000000000000040ULL #define ISA_MIPS32R3 0x0000000000000200ULL #define ISA_MIPS32R5 0x0000000000000800ULL @@ -69,7 +69,7 @@ #define CPU_MIPS64 (ISA_MIPS3) =20 /* MIPS Technologies "Release 1" */ -#define CPU_MIPS32R1 (CPU_MIPS2 | ISA_MIPS32) +#define CPU_MIPS32R1 (CPU_MIPS2 | ISA_MIPS_R1) #define CPU_MIPS64R1 (CPU_MIPS5 | CPU_MIPS32R1) =20 /* MIPS Technologies "Release 2" */ diff --git a/target/mips/translate.c b/target/mips/translate.c index fc93b9da8eb..a59fbd94bac 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7411,7 +7411,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) const char *register_name =3D "invalid"; =20 if (sel !=3D 0) { - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); } =20 switch (reg) { @@ -8179,7 +8179,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) const char *register_name =3D "invalid"; =20 if (sel !=3D 0) { - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); } =20 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { @@ -8943,7 +8943,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) const char *register_name =3D "invalid"; =20 if (sel !=3D 0) { - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); } =20 switch (reg) { @@ -9669,7 +9669,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) const char *register_name =3D "invalid"; =20 if (sel !=3D 0) { - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); } =20 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { @@ -11006,7 +11006,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext= *ctx, uint32_t opc, break; case OPC_DERET: opn =3D "deret"; - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { goto die; @@ -11021,7 +11021,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext= *ctx, uint32_t opc, break; case OPC_WAIT: opn =3D "wait"; - check_insn(ctx, ISA_MIPS3 | ISA_MIPS32); + check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1); if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { goto die; @@ -11056,7 +11056,7 @@ static void gen_compute_branch1(DisasContext *ctx, = uint32_t op, } =20 if (cc !=3D 0) { - check_insn(ctx, ISA_MIPS4 | ISA_MIPS32); + check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1); } =20 btarget =3D ctx->base.pc_next + 4 + offset; @@ -14425,7 +14425,7 @@ static int decode_extended_mips16_opc(CPUMIPSState = *env, DisasContext *ctx) gen_arith_imm(ctx, OPC_ADDIU, 29, 29, imm); break; case I8_SVRS: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); { int xsregs =3D (ctx->opcode >> 24) & 0x7; int aregs =3D (ctx->opcode >> 16) & 0xf; @@ -14675,7 +14675,7 @@ static int decode_mips16_opc(CPUMIPSState *env, Dis= asContext *ctx) ((int8_t)ctx->opcode) << 3); break; case I8_SVRS: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); { int do_ra =3D ctx->opcode & (1 << 6); int do_s0 =3D ctx->opcode & (1 << 5); @@ -14819,7 +14819,7 @@ static int decode_mips16_opc(CPUMIPSState *env, Dis= asContext *ctx) int ra =3D (ctx->opcode >> 5) & 0x1; =20 if (nd) { - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); } =20 if (link) { @@ -14840,7 +14840,7 @@ static int decode_mips16_opc(CPUMIPSState *env, Dis= asContext *ctx) * XXX: not clear which exception should be raised * when in debug mode... */ - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); generate_exception_end(ctx, EXCP_DBp); } break; @@ -14891,7 +14891,7 @@ static int decode_mips16_opc(CPUMIPSState *env, Dis= asContext *ctx) gen_HILO(ctx, OPC_MFHI, 0, rx); break; case RR_CNVT: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); switch (cnvt_op) { case RR_RY_CNVT_ZEB: tcg_gen_ext8u_tl(cpu_gpr[rx], cpu_gpr[rx]); @@ -14907,12 +14907,12 @@ static int decode_mips16_opc(CPUMIPSState *env, D= isasContext *ctx) break; #if defined(TARGET_MIPS64) case RR_RY_CNVT_ZEW: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); check_mips_64(ctx); tcg_gen_ext32u_tl(cpu_gpr[rx], cpu_gpr[rx]); break; case RR_RY_CNVT_SEW: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); check_mips_64(ctx); tcg_gen_ext32s_tl(cpu_gpr[rx], cpu_gpr[rx]); break; @@ -15831,7 +15831,7 @@ static void gen_pool16c_insn(DisasContext *ctx) * XXX: not clear which exception should be raised * when in debug mode... */ - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); generate_exception_end(ctx, EXCP_DBp); } break; @@ -16175,7 +16175,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasC= ontext *ctx, int rt, int rs) case CLZ: mips32_op =3D OPC_CLZ; do_cl: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); gen_cl(ctx, mips32_op, rt, rs); break; case RDHWR: @@ -16202,7 +16202,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasC= ontext *ctx, int rt, int rs) mips32_op =3D OPC_DIVU; goto do_div; do_div: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); gen_muldiv(ctx, mips32_op, 0, rs, rt); break; case MADD: @@ -16221,7 +16221,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasC= ontext *ctx, int rt, int rs) check_insn_opc_removed(ctx, ISA_MIPS32R6); mips32_op =3D OPC_MSUBU; do_mul: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); gen_muldiv(ctx, mips32_op, 0, rs, rt); break; default: @@ -16369,7 +16369,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasC= ontext *ctx, int rt, int rs) if (is_uhi(extract32(ctx->opcode, 16, 10))) { gen_helper_do_semihosting(cpu_env); } else { - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); if (ctx->hflags & MIPS_HFLAG_SBRI) { generate_exception_end(ctx, EXCP_RI); } else { @@ -24889,7 +24889,7 @@ static void decode_opc_special_legacy(CPUMIPSState = *env, DisasContext *ctx) switch (op1) { case OPC_MOVN: /* Conditional move */ case OPC_MOVZ: - check_insn(ctx, ISA_MIPS4 | ISA_MIPS32 | + check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1 | INSN_LOONGSON2E | INSN_LOONGSON2F); gen_cond_move(ctx, op1, rd, rs, rt); break; @@ -24902,7 +24902,7 @@ static void decode_opc_special_legacy(CPUMIPSState = *env, DisasContext *ctx) gen_HILO(ctx, op1, rd & 3, rs); break; case OPC_MOVCI: - check_insn(ctx, ISA_MIPS4 | ISA_MIPS32); + check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1); if (env->CP0_Config1 & (1 << CP0C1_FP)) { check_cp1_enabled(ctx); gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7, @@ -27577,7 +27577,7 @@ static void decode_opc_special2_legacy(CPUMIPSState= *env, DisasContext *ctx) case OPC_MADDU: case OPC_MSUB: case OPC_MSUBU: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); gen_muldiv(ctx, op1, rd & 3, rs, rt); break; case OPC_MUL: @@ -27594,7 +27594,7 @@ static void decode_opc_special2_legacy(CPUMIPSState= *env, DisasContext *ctx) break; case OPC_CLO: case OPC_CLZ: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); gen_cl(ctx, op1, rd, rs); break; case OPC_SDBBP: @@ -27605,14 +27605,14 @@ static void decode_opc_special2_legacy(CPUMIPSSta= te *env, DisasContext *ctx) * XXX: not clear which exception should be raised * when in debug mode... */ - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); generate_exception_end(ctx, EXCP_DBp); } break; #if defined(TARGET_MIPS64) case OPC_DCLO: case OPC_DCLZ: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); check_mips_64(ctx); gen_cl(ctx, op1, rd, rs); break; @@ -31025,7 +31025,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_CACHE: check_insn_opc_removed(ctx, ISA_MIPS32R6); check_cp0_enabled(ctx); - check_insn(ctx, ISA_MIPS3 | ISA_MIPS32); + check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1); if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { gen_cache_operation(ctx, rt, rs, imm); } @@ -31036,7 +31036,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) if (ctx->insn_flags & INSN_R5900) { /* Treat as NOP. */ } else { - check_insn(ctx, ISA_MIPS4 | ISA_MIPS32); + check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1); /* Treat as NOP. */ } break; --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.41 as permitted sender) client-ip=209.85.128.41; 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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id h184sm9757605wmh.23.2021.01.07.14.24.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:24:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PSq/MNApcem6+6+pS1q24pjrL0M72OS3waZH/uk8OxE=; b=LftUvc+VmPrjeZsJN4mvB3mnOJOA7VTCbhOO7Vi38GsmaXIS+8b7w2dq4m3F6pKJp8 QojMkIsss5Z2aBE9Z0rCSQmNlgaK/gwx6XvuFtzktzT21giJGZ/xI/iJnhFIn5x6KyvH IqweS6e5Dfh7Oy/UT8MuBqmhrfM1hTQ3WMlZN+kUGDfelPIxz5ljU386b/2pTnR4T3C2 RJ8jVaabFxVoJa3KSHmwV8mDsI+IpIQCByvUggsS4FZT2Ne6adahxGNFvs/04Lo4YDPD SgbGYDMsOdcwlX0FCPecnMRMY25Hm74OsoPNp0hKCFy9AU9/RfOE9OgTWsLUQGZtwe+k BTag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=PSq/MNApcem6+6+pS1q24pjrL0M72OS3waZH/uk8OxE=; b=OIcxHrgvVNXok3L885NMsnQSLE0Ycf5ZBitGNeWshlOsfTRxgZSKSUDm/svnW/CLgd 7XpEog65vt7+SNwWNvQWQFSUNXLq81HK+yJZzBU0VlGFFE/aK6ZY4MroD9eIBIkXPDFI jOnMno3iEH3OLVxjl3dMsGEUmjRCDF20dOoEeDkLc/0K+1VGCSpalM2kXujhyQneHAIa kle0/m16hEA6ZMH+oeMk9yzKMiGY2fIinU350GtBeBWV00Yemp1gPS07qoQ2sXhrznrF 2r5LIxo/1CZH24Zm/dwHVtwhMAPa4m+JFH7T97nBq2HX+WsQSVY8P4jx+oPLeRQ/WaeR j4mw== X-Gm-Message-State: AOAM533Q70HYw8bSLKSlskTllIf34dw3KuYemX++3cjCJgJaSk0QeOAp PqspaTfg8ljR0M+C+kaog1FA9+k/TVI= X-Google-Smtp-Source: ABdhPJxkdtu2+piHi8ggwZy0CKNAQ/DOAHJboo1RmGQh5DqoYYk/6XXz0rCaM32+EMiHGnVxKgyxCw== X-Received: by 2002:a1c:b78a:: with SMTP id h132mr490513wmf.141.1610058254155; Thu, 07 Jan 2021 14:24:14 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: libvir-list@redhat.com, Paolo Bonzini , Laurent Vivier , kvm@vger.kernel.org, Jiaxun Yang , Aurelien Jarno , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Paul Burton , Richard Henderson Subject: [PULL 15/66] target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2 Date: Thu, 7 Jan 2021 23:22:02 +0100 Message-Id: <20210107222253.20382-16-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The MIPS ISA release 2 is common to 32/64-bit CPUs. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210104221154.3127610-13-f4bug@amsat.org> --- target/mips/internal.h | 2 +- target/mips/mips-defs.h | 4 +- linux-user/mips/cpu_loop.c | 2 +- target/mips/cp0_timer.c | 4 +- target/mips/helper.c | 2 +- target/mips/translate.c | 138 ++++++++++++++++++------------------- 6 files changed, 76 insertions(+), 76 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 94910f75a61..23ae31ef989 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -407,7 +407,7 @@ static inline void compute_hflags(CPUMIPSState *env) } =20 } - if (env->insn_flags & ISA_MIPS32R2) { + if (env->insn_flags & ISA_MIPS_R2) { if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { env->hflags |=3D MIPS_HFLAG_COP1X; } diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index a7048ffaffe..d1eeb69dfd7 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -17,7 +17,7 @@ #define ISA_MIPS4 0x0000000000000008ULL #define ISA_MIPS5 0x0000000000000010ULL #define ISA_MIPS_R1 0x0000000000000020ULL -#define ISA_MIPS32R2 0x0000000000000040ULL +#define ISA_MIPS_R2 0x0000000000000040ULL #define ISA_MIPS32R3 0x0000000000000200ULL #define ISA_MIPS32R5 0x0000000000000800ULL #define ISA_MIPS32R6 0x0000000000002000ULL @@ -73,7 +73,7 @@ #define CPU_MIPS64R1 (CPU_MIPS5 | CPU_MIPS32R1) =20 /* MIPS Technologies "Release 2" */ -#define CPU_MIPS32R2 (CPU_MIPS32R1 | ISA_MIPS32R2) +#define CPU_MIPS32R2 (CPU_MIPS32R1 | ISA_MIPS_R2) #define CPU_MIPS64R2 (CPU_MIPS64R1 | CPU_MIPS32R2) =20 /* MIPS Technologies "Release 3" */ diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index e400166c583..748e1c664f1 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -384,7 +384,7 @@ void target_cpu_copy_regs(CPUArchState *env, struct tar= get_pt_regs *regs) prog_req.frdefault &=3D interp_req.frdefault; prog_req.fre &=3D interp_req.fre; =20 - bool cpu_has_mips_r2_r6 =3D env->insn_flags & ISA_MIPS32R2 || + bool cpu_has_mips_r2_r6 =3D env->insn_flags & ISA_MIPS_R2 || env->insn_flags & ISA_MIPS32R6; =20 if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) { diff --git a/target/mips/cp0_timer.c b/target/mips/cp0_timer.c index 5ec0d6249e9..70de95d338f 100644 --- a/target/mips/cp0_timer.c +++ b/target/mips/cp0_timer.c @@ -44,7 +44,7 @@ static void cpu_mips_timer_update(CPUMIPSState *env) static void cpu_mips_timer_expire(CPUMIPSState *env) { cpu_mips_timer_update(env); - if (env->insn_flags & ISA_MIPS32R2) { + if (env->insn_flags & ISA_MIPS_R2) { env->CP0_Cause |=3D 1 << CP0Ca_TI; } qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]); @@ -93,7 +93,7 @@ void cpu_mips_store_compare(CPUMIPSState *env, uint32_t v= alue) if (!(env->CP0_Cause & (1 << CP0Ca_DC))) { cpu_mips_timer_update(env); } - if (env->insn_flags & ISA_MIPS32R2) { + if (env->insn_flags & ISA_MIPS_R2) { env->CP0_Cause &=3D ~(1 << CP0Ca_TI); } qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]); diff --git a/target/mips/helper.c b/target/mips/helper.c index 5b74815beb0..98d6ecaa65e 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -431,7 +431,7 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulo= ng val) uint32_t old =3D env->CP0_Cause; int i; =20 - if (env->insn_flags & ISA_MIPS32R2) { + if (env->insn_flags & ISA_MIPS_R2) { mask |=3D 1 << CP0Ca_DC; } if (env->insn_flags & ISA_MIPS32R6) { diff --git a/target/mips/translate.c b/target/mips/translate.c index a59fbd94bac..9c71d306ee5 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7612,7 +7612,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) register_name =3D "PageMask"; break; case CP0_REG05__PAGEGRAIN: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain)); register_name =3D "PageGrain"; break; @@ -7660,27 +7660,27 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) register_name =3D "Wired"; break; case CP0_REG06__SRSCONF0: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0)); register_name =3D "SRSConf0"; break; case CP0_REG06__SRSCONF1: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1)); register_name =3D "SRSConf1"; break; case CP0_REG06__SRSCONF2: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2)); register_name =3D "SRSConf2"; break; case CP0_REG06__SRSCONF3: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3)); register_name =3D "SRSConf3"; break; case CP0_REG06__SRSCONF4: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4)); register_name =3D "SRSConf4"; break; @@ -7696,7 +7696,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REGISTER_07: switch (sel) { case CP0_REG07__HWRENA: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna)); register_name =3D "HWREna"; break; @@ -7791,17 +7791,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) register_name =3D "Status"; break; case CP0_REG12__INTCTL: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl)); register_name =3D "IntCtl"; break; case CP0_REG12__SRSCTL: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl)); register_name =3D "SRSCtl"; break; case CP0_REG12__SRSMAP: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); register_name =3D "SRSMap"; break; @@ -7837,13 +7837,13 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) register_name =3D "PRid"; break; case CP0_REG15__EBASE: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase)); tcg_gen_ext32s_tl(arg, arg); register_name =3D "EBase"; break; case CP0_REG15__CMGCRBASE: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); CP0_CHECK(ctx->cmgcr); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBa= se)); tcg_gen_ext32s_tl(arg, arg); @@ -8357,7 +8357,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) register_name =3D "PageMask"; break; case CP0_REG05__PAGEGRAIN: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_pagegrain(cpu_env, arg); register_name =3D "PageGrain"; ctx->base.is_jmp =3D DISAS_STOP; @@ -8403,27 +8403,27 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) register_name =3D "Wired"; break; case CP0_REG06__SRSCONF0: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsconf0(cpu_env, arg); register_name =3D "SRSConf0"; break; case CP0_REG06__SRSCONF1: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsconf1(cpu_env, arg); register_name =3D "SRSConf1"; break; case CP0_REG06__SRSCONF2: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsconf2(cpu_env, arg); register_name =3D "SRSConf2"; break; case CP0_REG06__SRSCONF3: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsconf3(cpu_env, arg); register_name =3D "SRSConf3"; break; case CP0_REG06__SRSCONF4: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsconf4(cpu_env, arg); register_name =3D "SRSConf4"; break; @@ -8439,7 +8439,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REGISTER_07: switch (sel) { case CP0_REG07__HWRENA: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_hwrena(cpu_env, arg); ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "HWREna"; @@ -8522,21 +8522,21 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) register_name =3D "Status"; break; case CP0_REG12__INTCTL: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_intctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "IntCtl"; break; case CP0_REG12__SRSCTL: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "SRSCtl"; break; case CP0_REG12__SRSMAP: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; @@ -8581,7 +8581,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) register_name =3D "PRid"; break; case CP0_REG15__EBASE: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_ebase(cpu_env, arg); register_name =3D "EBase"; break; @@ -9120,7 +9120,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) register_name =3D "PageMask"; break; case CP0_REG05__PAGEGRAIN: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain)); register_name =3D "PageGrain"; break; @@ -9165,27 +9165,27 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) register_name =3D "Wired"; break; case CP0_REG06__SRSCONF0: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0)); register_name =3D "SRSConf0"; break; case CP0_REG06__SRSCONF1: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1)); register_name =3D "SRSConf1"; break; case CP0_REG06__SRSCONF2: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2)); register_name =3D "SRSConf2"; break; case CP0_REG06__SRSCONF3: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3)); register_name =3D "SRSConf3"; break; case CP0_REG06__SRSCONF4: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4)); register_name =3D "SRSConf4"; break; @@ -9201,7 +9201,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case CP0_REGISTER_07: switch (sel) { case CP0_REG07__HWRENA: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna)); register_name =3D "HWREna"; break; @@ -9294,17 +9294,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) register_name =3D "Status"; break; case CP0_REG12__INTCTL: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl)); register_name =3D "IntCtl"; break; case CP0_REG12__SRSCTL: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl)); register_name =3D "SRSCtl"; break; case CP0_REG12__SRSMAP: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); register_name =3D "SRSMap"; break; @@ -9339,12 +9339,12 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) register_name =3D "PRid"; break; case CP0_REG15__EBASE: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase)); register_name =3D "EBase"; break; case CP0_REG15__CMGCRBASE: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); CP0_CHECK(ctx->cmgcr); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBa= se)); register_name =3D "CMGCRBase"; @@ -9847,7 +9847,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) register_name =3D "PageMask"; break; case CP0_REG05__PAGEGRAIN: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_pagegrain(cpu_env, arg); register_name =3D "PageGrain"; break; @@ -9892,27 +9892,27 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) register_name =3D "Wired"; break; case CP0_REG06__SRSCONF0: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsconf0(cpu_env, arg); register_name =3D "SRSConf0"; break; case CP0_REG06__SRSCONF1: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsconf1(cpu_env, arg); register_name =3D "SRSConf1"; break; case CP0_REG06__SRSCONF2: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsconf2(cpu_env, arg); register_name =3D "SRSConf2"; break; case CP0_REG06__SRSCONF3: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsconf3(cpu_env, arg); register_name =3D "SRSConf3"; break; case CP0_REG06__SRSCONF4: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsconf4(cpu_env, arg); register_name =3D "SRSConf4"; break; @@ -9928,7 +9928,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case CP0_REGISTER_07: switch (sel) { case CP0_REG07__HWRENA: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_hwrena(cpu_env, arg); ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "HWREna"; @@ -10015,21 +10015,21 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg= , int reg, int sel) register_name =3D "Status"; break; case CP0_REG12__INTCTL: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_intctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "IntCtl"; break; case CP0_REG12__SRSCTL: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "SRSCtl"; break; case CP0_REG12__SRSMAP: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; @@ -10074,7 +10074,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) register_name =3D "PRid"; break; case CP0_REG15__EBASE: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_ebase(cpu_env, arg); register_name =3D "EBase"; break; @@ -13453,7 +13453,7 @@ static void gen_rdhwr(DisasContext *ctx, int rt, in= t rd, int sel) * The Linux kernel will emulate rdhwr if it's not supported natively. * Therefore only check the ISA in system mode. */ - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); #endif t0 =3D tcg_temp_new(); =20 @@ -16269,12 +16269,12 @@ static void gen_pool32axf(CPUMIPSState *env, Disa= sContext *ctx, int rt, int rs) switch (minor) { case RDPGPR: check_cp0_enabled(ctx); - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_load_srsgpr(rs, rt); break; case WRPGPR: check_cp0_enabled(ctx); - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_store_srsgpr(rs, rt); break; default: @@ -24984,7 +24984,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) switch ((ctx->opcode >> 21) & 0x1f) { case 1: /* rotr is decoded as srl on non-R2 CPUs */ - if (ctx->insn_flags & ISA_MIPS32R2) { + if (ctx->insn_flags & ISA_MIPS_R2) { op1 =3D OPC_ROTR; } /* Fallthrough */ @@ -25010,7 +25010,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) switch ((ctx->opcode >> 6) & 0x1f) { case 1: /* rotrv is decoded as srlv on non-R2 CPUs */ - if (ctx->insn_flags & ISA_MIPS32R2) { + if (ctx->insn_flags & ISA_MIPS_R2) { op1 =3D OPC_ROTRV; } /* Fallthrough */ @@ -25083,7 +25083,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) switch ((ctx->opcode >> 21) & 0x1f) { case 1: /* drotr is decoded as dsrl on non-R2 CPUs */ - if (ctx->insn_flags & ISA_MIPS32R2) { + if (ctx->insn_flags & ISA_MIPS_R2) { op1 =3D OPC_DROTR; } /* Fallthrough */ @@ -25101,7 +25101,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) switch ((ctx->opcode >> 21) & 0x1f) { case 1: /* drotr32 is decoded as dsrl32 on non-R2 CPUs */ - if (ctx->insn_flags & ISA_MIPS32R2) { + if (ctx->insn_flags & ISA_MIPS_R2) { op1 =3D OPC_DROTR32; } /* Fallthrough */ @@ -25133,7 +25133,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) switch ((ctx->opcode >> 6) & 0x1f) { case 1: /* drotrv is decoded as dsrlv on non-R2 CPUs */ - if (ctx->insn_flags & ISA_MIPS32R2) { + if (ctx->insn_flags & ISA_MIPS_R2) { op1 =3D OPC_DROTRV; } /* Fallthrough */ @@ -28594,7 +28594,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) switch (op1) { case OPC_EXT: case OPC_INS: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_bitops(ctx, op1, rt, rs, sa, rd); break; case OPC_BSHFL: @@ -28609,7 +28609,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) decode_opc_special3_r6(env, ctx); break; default: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_bshfl(ctx, op2, rt, rd); break; } @@ -28621,7 +28621,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) case OPC_DINSM: case OPC_DINSU: case OPC_DINS: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); check_mips_64(ctx); gen_bitops(ctx, op1, rt, rs, sa, rd); break; @@ -28641,7 +28641,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) decode_opc_special3_r6(env, ctx); break; default: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); check_mips_64(ctx); op2 =3D MASK_DBSHFL(ctx->opcode); gen_bshfl(ctx, op2, rt, rd); @@ -30741,7 +30741,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) generate_exception_end(ctx, EXCP_RI); break; case OPC_SYNCI: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); /* * Break the TB to be able to sync copied instructions * immediately. @@ -30858,7 +30858,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) } break; case OPC_DI: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); save_cpu_state(ctx, 1); gen_helper_di(t0, cpu_env); gen_store_gpr(t0, rt); @@ -30869,7 +30869,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) ctx->base.is_jmp =3D DISAS_STOP; break; case OPC_EI: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); save_cpu_state(ctx, 1); gen_helper_ei(t0, cpu_env); gen_store_gpr(t0, rt); @@ -30890,11 +30890,11 @@ static void decode_opc(CPUMIPSState *env, DisasCo= ntext *ctx) #endif /* !CONFIG_USER_ONLY */ break; case OPC_RDPGPR: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_load_srsgpr(rt, rd); break; case OPC_WRPGPR: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_store_srsgpr(rt, rd); break; default: @@ -31056,7 +31056,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_MFHC1: case OPC_MTHC1: check_cp1_enabled(ctx); - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); /* fall through */ case OPC_MFC1: case OPC_CFC1: @@ -31250,21 +31250,21 @@ static void decode_opc(CPUMIPSState *env, DisasCo= ntext *ctx) switch (op1) { case OPC_LUXC1: case OPC_SUXC1: - check_insn(ctx, ISA_MIPS5 | ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS5 | ISA_MIPS_R2); /* Fallthrough */ case OPC_LWXC1: case OPC_LDXC1: case OPC_SWXC1: case OPC_SDXC1: - check_insn(ctx, ISA_MIPS4 | ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2); gen_flt3_ldst(ctx, op1, sa, rd, rs, rt); break; case OPC_PREFX: - check_insn(ctx, ISA_MIPS4 | ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2); /* Treat as NOP. */ break; case OPC_ALNV_PS: - check_insn(ctx, ISA_MIPS5 | ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS5 | ISA_MIPS_R2); /* Fallthrough */ case OPC_MADD_S: case OPC_MADD_D: @@ -31278,7 +31278,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_NMSUB_S: case OPC_NMSUB_D: case OPC_NMSUB_PS: - check_insn(ctx, ISA_MIPS4 | ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2); gen_flt3_arith(ctx, op1, sa, rs, rd, rt); break; default: --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) client-ip=209.85.221.48; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f48.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1610058260; cv=none; d=zohomail.com; s=zohoarc; b=OYYKB9ftcUnU/dzqrV5O7AUd2are3nqWubjvcDFXLYxwk2VwMzDNWaJoagcZ5zFRWi/4whDKKuc7vLOQFX6vI6H6USgdhLHJFXNCSNIJkrta3ED7sxQPUeG7mMfnKODqFIbQeTE2/qm6XDKhJ/lPhouz/jKVCgTIXrqG48E7ZgU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610058260; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; 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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id s205sm9587176wmf.46.2021.01.07.14.24.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:24:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=H9zOVt5mC6BKrn8/aJIajQg1rLT3CbXMbjoqCH1psww=; b=beBwsrVB1OdeBJyHJfBZqSSkiXc2Ue4xXXcXCdc0Jq1ATjpysiX0D7pLfbYYgs9p94 hzHmgbY8uphkM+OngIndbv618FCoFRiRQiGsaEbwCy8vo2/EblQvr/e876PpdWqGDr2P g0ZFsGLnVB0GURPU9O5ZweBRIQ97Tnuscuroddyz5MAR2HH4tb5vgbAWK+RLVWUihMJr FDiMccnI/iLbgv+VDCTgO1O47+aOCVltiBppBQn7Vx8qDI9vWTjpe/tXqqcvzAmj3maa pQQVd3VRhUjkIC13xujo2SqAmmnADXXIAquaq+TJ5wmyRWfdN+5A8b96KQ/eZv46wPUA a/FA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=H9zOVt5mC6BKrn8/aJIajQg1rLT3CbXMbjoqCH1psww=; b=bxRUVdxcG19AEjEgYE26qbjAbcJjo+ZDlX3SE0ayxhRbyYY4ATqXZF91QHyU/oQj0W QZddER7LQ9yH9YxOltiOwfLxq6Vpb4ZGU4BfM/eFMmlqzKOwa2Iqz+Cfkwh4H2d+sFMk pY8h6hGmBM7LOWL3C8ryRRKTyj9SbnQ17vhDH8ymGU4ybuqOtNB7ACSE/7DlfmY8zaxQ fIXJOtRQ8JpSdRwgM9f5GWtSeq1OxcqXfwqOBEodySM8D5VesD0J5/tsdqZ3/z6JiMpX hQDL9lJehGx6CBrhttnKMJJLAjpDl9U99i78USRv+FbbCbOr/FU/3pFS5MVxvnO8Jgmg NAQA== X-Gm-Message-State: AOAM5308GoUCRZJBfPFqlDUlROcO/oWgx2YoctnTDI1BeqgX1KNmCKJd N3puNYt4OftkItAQHMo+R1E= X-Google-Smtp-Source: ABdhPJzWKwcEhW2PD8mOSa2fKu6MVLKZYReyP+7sdgmKhxVPAKNtE8mLuWtkAEUYiNitLhmQDoaWQg== X-Received: by 2002:a05:6000:144f:: with SMTP id v15mr692233wrx.138.1610058259241; Thu, 07 Jan 2021 14:24:19 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: libvir-list@redhat.com, Paolo Bonzini , Laurent Vivier , kvm@vger.kernel.org, Jiaxun Yang , Aurelien Jarno , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Paul Burton , Richard Henderson Subject: [PULL 16/66] target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3 Date: Thu, 7 Jan 2021 23:22:03 +0100 Message-Id: <20210107222253.20382-17-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The MIPS ISA release 3 is common to 32/64-bit CPUs. To avoid holes in the insn_flags type, update the definition with the next available bit. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210104221154.3127610-14-f4bug@amsat.org> --- target/mips/mips-defs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index d1eeb69dfd7..12ff2b3280c 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -18,7 +18,7 @@ #define ISA_MIPS5 0x0000000000000010ULL #define ISA_MIPS_R1 0x0000000000000020ULL #define ISA_MIPS_R2 0x0000000000000040ULL -#define ISA_MIPS32R3 0x0000000000000200ULL +#define ISA_MIPS_R3 0x0000000000000080ULL #define ISA_MIPS32R5 0x0000000000000800ULL #define ISA_MIPS32R6 0x0000000000002000ULL #define ISA_NANOMIPS32 0x0000000000008000ULL @@ -77,7 +77,7 @@ #define CPU_MIPS64R2 (CPU_MIPS64R1 | CPU_MIPS32R2) =20 /* MIPS Technologies "Release 3" */ -#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3) +#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS_R3) #define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3) =20 /* MIPS Technologies "Release 5" */ --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) client-ip=209.85.221.44; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f44.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1610058266; cv=none; d=zohomail.com; s=zohoarc; b=N7a7ky4JyVsmyvO7JQdcsuRjnqYow8qIWv3oi2d2M59a2qB7Ua/51V0GuJbDo0XluW0FMOTfqRfi7s2BJE+LM9l7zJxoGcg5+BgVTE9coaJOTSbmm6Tx3pGv30+DQLDxuT721J4oGEehRlEJHICNyl+9axomWh7cqBh5AODAoTk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610058266; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8VbnptZXgmw1r+fJKrz2Q7we2TDNwx1PgIcbr0B8enM=; b=SYf3j8NrRJDHQJlPxlusWYkTPWxGgfEMQOmRqu5XI2csJKuvoWVmRtiA+WHHbU8eOxTzWgg3Il52a38YZerKfdYp2ZUFPd9F6uGpcUPk93Ihvyo0CuXMZPn4YISqu/XuTo6DIZX8E+WjhFhkmB64waIUm91NsftNUQaV4pmpVDw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) by mx.zohomail.com with SMTPS id 1610058266029722.2904421868138; Thu, 7 Jan 2021 14:24:26 -0800 (PST) Received: by mail-wr1-f44.google.com with SMTP id q18so7155056wrn.1 for ; Thu, 07 Jan 2021 14:24:25 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (241.red-88-10-103.dynamicip.rima-tde.net. [88.10.103.241]) by smtp.gmail.com with ESMTPSA id r82sm9930125wma.18.2021.01.07.14.24.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:24:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8VbnptZXgmw1r+fJKrz2Q7we2TDNwx1PgIcbr0B8enM=; b=vWEk798tkKQE/nbkyfZecpulRxQ1g9CZ1hflnEYJuTb9GxDtygEnCMLNsN3EucxS2q oCEDMtjH1rC4YAOr68TSV4itLsAji+Zc0MW+QwSHyoc1r8m8pIR0+iDNfbBuinMLuthC L/r1EuqQ6xuDF49Nuuu1rTL7wok0P2G4gufFVtMI9qfyzC0EwcPlxSHwO9T8R7Zo/Sut cw76yjxwPvXiKsRK5YZTKgI7pJ985o8lz80TN6O9zRYqGOV/eNvoW/etUkf+tEHIS/c4 l6tSZCk8bHtICw89nlSz3aVHHkv47SbEwIgcp/zdk6MOcOqLNaECMyN6WrLBLb2IhGDD d52Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=8VbnptZXgmw1r+fJKrz2Q7we2TDNwx1PgIcbr0B8enM=; b=pktHitzNsqHPk216s3n0e+gCloM/hx5K9xkYbowuKc0rdTaCgZaJBrtdBzbgmRNSIQ xOwVvgVleskQQQJBvdbGuScdxCxjfGFdhK6j0ObT2x27bVTRpbGH/nGMfqQ1KkaQ7x0S enbfS/CLpYRFWjfBkEPCcjppipWH+erL9Z417/+939Hdxi23t7+xhvrlb9Fxk1h2M1C7 o/9PLEhIE+23xYcMe1poEc71Ie/UxelTafqli3G2K2oQbLT0Yvt4pOZGEvNWLhMtNSk4 DpDKfRMECTc9JS2SzfBcM9jBz8j/dBVdRD8bRDJuAZ3S79hxFPq1ppawTsQng66rSBAX inzA== X-Gm-Message-State: AOAM533Dsrfv3Cfxs/NoxFoAjGK3G7X+wbP0/xgszLE2e2SI3yPRAw0n wnr2OYxgHnLOtaDHNHdXtP8= X-Google-Smtp-Source: ABdhPJwgPM2/a71z5sYYShgXCbd3btGleobgBn7VBL17CWaY0SuEJ2YpO/wDeSbt636lq2M1sKJG8g== X-Received: by 2002:a5d:6a88:: with SMTP id s8mr706468wru.118.1610058264312; Thu, 07 Jan 2021 14:24:24 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: libvir-list@redhat.com, Paolo Bonzini , Laurent Vivier , kvm@vger.kernel.org, Jiaxun Yang , Aurelien Jarno , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Paul Burton , Richard Henderson Subject: [PULL 17/66] target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5 Date: Thu, 7 Jan 2021 23:22:04 +0100 Message-Id: <20210107222253.20382-18-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The MIPS ISA release 5 is common to 32/64-bit CPUs. To avoid holes in the insn_flags type, update the definition with the next available bit. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210104221154.3127610-15-f4bug@amsat.org> --- target/mips/mips-defs.h | 4 ++-- target/mips/translate.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 12ff2b3280c..181f3715472 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -19,7 +19,7 @@ #define ISA_MIPS_R1 0x0000000000000020ULL #define ISA_MIPS_R2 0x0000000000000040ULL #define ISA_MIPS_R3 0x0000000000000080ULL -#define ISA_MIPS32R5 0x0000000000000800ULL +#define ISA_MIPS_R5 0x0000000000000100ULL #define ISA_MIPS32R6 0x0000000000002000ULL #define ISA_NANOMIPS32 0x0000000000008000ULL /* @@ -81,7 +81,7 @@ #define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3) =20 /* MIPS Technologies "Release 5" */ -#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5) +#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS_R5) #define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5) =20 /* MIPS Technologies "Release 6" */ diff --git a/target/mips/translate.c b/target/mips/translate.c index 9c71d306ee5..83fd6c473a5 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -10993,7 +10993,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext= *ctx, uint32_t opc, if (ctx->opcode & (1 << bit_shift)) { /* OPC_ERETNC */ opn =3D "eretnc"; - check_insn(ctx, ISA_MIPS32R5); + check_insn(ctx, ISA_MIPS_R5); gen_helper_eretnc(cpu_env); } else { /* OPC_ERET */ --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) client-ip=216.205.24.124; envelope-from=libvir-list-bounces@redhat.com; helo=us-smtp-delivery-124.mimecast.com; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) smtp.mailfrom=libvir-list-bounces@redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1610058290; cv=none; d=zohomail.com; s=zohoarc; b=Tvan92RcCxHmI8c/GNPEawvA9jQ7M4xA6vJNvGDUpqXx7pfcr2PzX0pDe3TwijxfjHXA51shPmKh/eTMit2d14MzJFn5YdxrZ2xK+lmLu9VKJOmwDUUJ6SWEWLWvI6LS/I3s1E8f8HPw7GDjJaUxq9XrvI42FQbLLJ3sw6/jCc8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610058290; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id m8sm10082986wmc.27.2021.01.07.14.24.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:24:29 -0800 (PST) X-MC-Unique: bXLqJWivNLSolLqj2H_eYA-1 X-MC-Unique: hq1JTeCeMv-F5Qb_Cdl1fA-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=+ROz8kLr0ajAbCB92YY9f25vBRbsoSaL9vHc2JZ+ss8=; b=FxVo72VoNCY/VBTIxsvACVMaxan2ih2LtqaOgJKYaa4slKzleJH1GEFbwVhmKpOB2j XySjP5qZZp4GNOE/hSn1eNeABCxv5AUCVYcaRDu2RUHdkKN7uY6+Tz1JIKyt4JRGzDRi DUWEIxwZYuMIDcp+BrVI1/BZuDoJ9g8BChkCZmQf+Z+YKwfDy1z8VatcEXdb3Wy8j0PI uYznU+CoCWt3TN8F5rY11Wv9amO3YkqYtLSkww0V5xWd4xRTUtHNzQWneN6LdV9SjP0a w9Nk5qv140iUBf7C7nZswF0UE4mtoGr6RnXus0BWskfJi5Ilq95DgSU640GCtfgfSCpy 1cEQ== X-Gm-Message-State: AOAM533DUxYp/P46CK/Xp9ToZ0fZMX2WLiF3STWly8XrKrPItHYKpX6w DrNAOrGYnXpmB0mQdt3DoTifC8yO634= X-Google-Smtp-Source: ABdhPJxwWscDAiHyLTrAjJD6T/GRX0C8xYRGrmQkZmOfM5+DX831TdHpamk/8zSO30HOdhSH3zKuRg== X-Received: by 2002:a1c:40d6:: with SMTP id n205mr544750wma.0.1610058270263; Thu, 07 Jan 2021 14:24:30 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 18/66] target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6 Date: Thu, 7 Jan 2021 23:22:05 +0100 Message-Id: <20210107222253.20382-19-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The MIPS ISA release 6 is common to 32/64-bit CPUs. To avoid holes in the insn_flags type, update the definition with the next available bit. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210104221154.3127610-16-f4bug@amsat.org> --- target/mips/internal.h | 4 +- target/mips/mips-defs.h | 4 +- linux-user/mips/cpu_loop.c | 2 +- target/mips/cp0_helper.c | 18 +- target/mips/cpu.c | 6 +- target/mips/fpu_helper.c | 4 +- target/mips/helper.c | 10 +- target/mips/translate.c | 426 ++++++++++++++++++------------------- 8 files changed, 237 insertions(+), 237 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 23ae31ef989..77a648bcf9c 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -354,7 +354,7 @@ static inline void compute_hflags(CPUMIPSState *env) } else if (((env->hflags & MIPS_HFLAG_KSU) =3D=3D MIPS_HFLAG_UM) && !(env->CP0_Status & (1 << CP0St_UX))) { env->hflags |=3D MIPS_HFLAG_AWRAP; - } else if (env->insn_flags & ISA_MIPS32R6) { + } else if (env->insn_flags & ISA_MIPS_R6) { /* Address wrapping for Supervisor and Kernel is specified in R6 */ if ((((env->hflags & MIPS_HFLAG_KSU) =3D=3D MIPS_HFLAG_SM) && !(env->CP0_Status & (1 << CP0St_SX))) || @@ -365,7 +365,7 @@ static inline void compute_hflags(CPUMIPSState *env) } #endif if (((env->CP0_Status & (1 << CP0St_CU0)) && - !(env->insn_flags & ISA_MIPS32R6)) || + !(env->insn_flags & ISA_MIPS_R6)) || !(env->hflags & MIPS_HFLAG_KSU)) { env->hflags |=3D MIPS_HFLAG_CP0; } diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 181f3715472..97866019a72 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -20,7 +20,7 @@ #define ISA_MIPS_R2 0x0000000000000040ULL #define ISA_MIPS_R3 0x0000000000000080ULL #define ISA_MIPS_R5 0x0000000000000100ULL -#define ISA_MIPS32R6 0x0000000000002000ULL +#define ISA_MIPS_R6 0x0000000000000200ULL #define ISA_NANOMIPS32 0x0000000000008000ULL /* * bits 24-39: MIPS ASEs @@ -85,7 +85,7 @@ #define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5) =20 /* MIPS Technologies "Release 6" */ -#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6) +#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS_R6) #define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6) =20 /* Wave Computing: "nanoMIPS" */ diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index 748e1c664f1..19947448a25 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -385,7 +385,7 @@ void target_cpu_copy_regs(CPUArchState *env, struct tar= get_pt_regs *regs) prog_req.fre &=3D interp_req.fre; =20 bool cpu_has_mips_r2_r6 =3D env->insn_flags & ISA_MIPS_R2 || - env->insn_flags & ISA_MIPS32R6; + env->insn_flags & ISA_MIPS_R6; =20 if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) { env->CP0_Config5 |=3D (1 << CP0C5_FRE); diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c index 36a92857bfb..aae2af6eccc 100644 --- a/target/mips/cp0_helper.c +++ b/target/mips/cp0_helper.c @@ -527,7 +527,7 @@ void helper_mtc0_index(CPUMIPSState *env, target_ulong = arg1) uint32_t index_p =3D env->CP0_Index & 0x80000000; uint32_t tlb_index =3D arg1 & 0x7fffffff; if (tlb_index < env->tlb->nb_tlb) { - if (env->insn_flags & ISA_MIPS32R6) { + if (env->insn_flags & ISA_MIPS_R6) { index_p |=3D arg1 & 0x80000000; } env->CP0_Index =3D index_p | tlb_index; @@ -960,7 +960,7 @@ void helper_mtc0_pwfield(CPUMIPSState *env, target_ulon= g arg1) uint32_t old_ptei =3D (env->CP0_PWField >> CP0PF_PTEI) & 0x3FULL; uint32_t new_ptei =3D (arg1 >> CP0PF_PTEI) & 0x3FULL; =20 - if ((env->insn_flags & ISA_MIPS32R6)) { + if ((env->insn_flags & ISA_MIPS_R6)) { if (((arg1 >> CP0PF_BDI) & 0x3FULL) < 12) { mask &=3D ~(0x3FULL << CP0PF_BDI); } @@ -980,7 +980,7 @@ void helper_mtc0_pwfield(CPUMIPSState *env, target_ulon= g arg1) env->CP0_PWField =3D arg1 & mask; =20 if ((new_ptei >=3D 32) || - ((env->insn_flags & ISA_MIPS32R6) && + ((env->insn_flags & ISA_MIPS_R6) && (new_ptei =3D=3D 0 || new_ptei =3D=3D 1))) { env->CP0_PWField =3D (env->CP0_PWField & ~0x3FULL) | (old_ptei << CP0PF_PTEI); @@ -990,7 +990,7 @@ void helper_mtc0_pwfield(CPUMIPSState *env, target_ulon= g arg1) uint32_t old_ptew =3D (env->CP0_PWField >> CP0PF_PTEW) & 0x3F; uint32_t new_ptew =3D (arg1 >> CP0PF_PTEW) & 0x3F; =20 - if ((env->insn_flags & ISA_MIPS32R6)) { + if ((env->insn_flags & ISA_MIPS_R6)) { if (((arg1 >> CP0PF_GDW) & 0x3F) < 12) { mask &=3D ~(0x3F << CP0PF_GDW); } @@ -1007,7 +1007,7 @@ void helper_mtc0_pwfield(CPUMIPSState *env, target_ul= ong arg1) env->CP0_PWField =3D arg1 & mask; =20 if ((new_ptew >=3D 32) || - ((env->insn_flags & ISA_MIPS32R6) && + ((env->insn_flags & ISA_MIPS_R6) && (new_ptew =3D=3D 0 || new_ptew =3D=3D 1))) { env->CP0_PWField =3D (env->CP0_PWField & ~0x3F) | (old_ptew << CP0PF_PTEW); @@ -1026,7 +1026,7 @@ void helper_mtc0_pwsize(CPUMIPSState *env, target_ulo= ng arg1) =20 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1) { - if (env->insn_flags & ISA_MIPS32R6) { + if (env->insn_flags & ISA_MIPS_R6) { if (arg1 < env->tlb->nb_tlb) { env->CP0_Wired =3D arg1; } @@ -1075,10 +1075,10 @@ void helper_mtc0_hwrena(CPUMIPSState *env, target_u= long arg1) uint32_t mask =3D 0x0000000F; =20 if ((env->CP0_Config1 & (1 << CP0C1_PC)) && - (env->insn_flags & ISA_MIPS32R6)) { + (env->insn_flags & ISA_MIPS_R6)) { mask |=3D (1 << 4); } - if (env->insn_flags & ISA_MIPS32R6) { + if (env->insn_flags & ISA_MIPS_R6) { mask |=3D (1 << 5); } if (env->CP0_Config3 & (1 << CP0C3_ULRI)) { @@ -1149,7 +1149,7 @@ void helper_mtc0_entryhi(CPUMIPSState *env, target_ul= ong arg1) =20 /* 1k pages not implemented */ #if defined(TARGET_MIPS64) - if (env->insn_flags & ISA_MIPS32R6) { + if (env->insn_flags & ISA_MIPS_R6) { int entryhi_r =3D extract64(arg1, 62, 2); int config0_at =3D extract32(env->CP0_Config0, 13, 2); bool no_supervisor =3D (env->CP0_Status_rw_bitmask & 0x8) =3D=3D 0; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 2283214c879..12126d37f16 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -71,7 +71,7 @@ static bool mips_cpu_has_work(CPUState *cs) if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && cpu_mips_hw_interrupts_pending(env)) { if (cpu_mips_hw_interrupts_enabled(env) || - (env->insn_flags & ISA_MIPS32R6)) { + (env->insn_flags & ISA_MIPS_R6)) { has_work =3D true; } } @@ -287,13 +287,13 @@ static void cpu_state_reset(CPUMIPSState *env) /* XKPhys (note, SegCtl2.XR =3D 0, so XAM won't be used) */ env->CP0_SegCtl1 |=3D (CP0SC_AM_UK << CP0SC1_XAM); #endif /* !CONFIG_USER_ONLY */ - if ((env->insn_flags & ISA_MIPS32R6) && + if ((env->insn_flags & ISA_MIPS_R6) && (env->active_fpu.fcr0 & (1 << FCR0_F64))) { /* Status.FR =3D 0 mode in 64-bit FPU not allowed in R6 */ env->CP0_Status |=3D (1 << CP0St_FR); } =20 - if (env->insn_flags & ISA_MIPS32R6) { + if (env->insn_flags & ISA_MIPS_R6) { /* PTW =3D 1 */ env->CP0_PWSize =3D 0x40; /* GDI =3D 12 */ diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index bdb65065ee7..91b6a2e11fc 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -145,7 +145,7 @@ void helper_ctc1(CPUMIPSState *env, target_ulong arg1, = uint32_t fs, uint32_t rt) } break; case 25: - if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) { + if ((env->insn_flags & ISA_MIPS_R6) || (arg1 & 0xffffff00)) { return; } env->active_fpu.fcr31 =3D (env->active_fpu.fcr31 & 0x017fffff) | @@ -172,7 +172,7 @@ void helper_ctc1(CPUMIPSState *env, target_ulong arg1, = uint32_t fs, uint32_t rt) (env->active_fpu.fcr31 & ~(env->active_fpu.fcr31_rw_bitmask= )); break; default: - if (env->insn_flags & ISA_MIPS32R6) { + if (env->insn_flags & ISA_MIPS_R6) { do_raise_exception(env, EXCP_RI, GETPC()); } return; diff --git a/target/mips/helper.c b/target/mips/helper.c index 98d6ecaa65e..d1b6bb6fb23 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -397,7 +397,7 @@ void cpu_mips_store_status(CPUMIPSState *env, target_ul= ong val) uint32_t mask =3D env->CP0_Status_rw_bitmask; target_ulong old =3D env->CP0_Status; =20 - if (env->insn_flags & ISA_MIPS32R6) { + if (env->insn_flags & ISA_MIPS_R6) { bool has_supervisor =3D extract32(mask, CP0St_KSU, 2) =3D=3D 0x3; #if defined(TARGET_MIPS64) uint32_t ksux =3D (1 << CP0St_KX) & val; @@ -434,7 +434,7 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulo= ng val) if (env->insn_flags & ISA_MIPS_R2) { mask |=3D 1 << CP0Ca_DC; } - if (env->insn_flags & ISA_MIPS32R6) { + if (env->insn_flags & ISA_MIPS_R6) { mask &=3D ~((1 << CP0Ca_WP) & val); } =20 @@ -1145,7 +1145,7 @@ void mips_cpu_do_interrupt(CPUState *cs) enter_debug_mode: if (env->insn_flags & ISA_MIPS3) { env->hflags |=3D MIPS_HFLAG_64; - if (!(env->insn_flags & ISA_MIPS32R6) || + if (!(env->insn_flags & ISA_MIPS_R6) || env->CP0_Status & (1 << CP0St_KX)) { env->hflags &=3D ~MIPS_HFLAG_AWRAP; } @@ -1174,7 +1174,7 @@ void mips_cpu_do_interrupt(CPUState *cs) env->CP0_Status |=3D (1 << CP0St_ERL) | (1 << CP0St_BEV); if (env->insn_flags & ISA_MIPS3) { env->hflags |=3D MIPS_HFLAG_64; - if (!(env->insn_flags & ISA_MIPS32R6) || + if (!(env->insn_flags & ISA_MIPS_R6) || env->CP0_Status & (1 << CP0St_KX)) { env->hflags &=3D ~MIPS_HFLAG_AWRAP; } @@ -1360,7 +1360,7 @@ void mips_cpu_do_interrupt(CPUState *cs) env->CP0_Status |=3D (1 << CP0St_EXL); if (env->insn_flags & ISA_MIPS3) { env->hflags |=3D MIPS_HFLAG_64; - if (!(env->insn_flags & ISA_MIPS32R6) || + if (!(env->insn_flags & ISA_MIPS_R6) || env->CP0_Status & (1 << CP0St_KX)) { env->hflags &=3D ~MIPS_HFLAG_AWRAP; } diff --git a/target/mips/translate.c b/target/mips/translate.c index 83fd6c473a5..e813add99c5 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -4014,7 +4014,7 @@ static void gen_logic_imm(DisasContext *ctx, uint32_t= opc, } break; case OPC_LUI: - if (rs !=3D 0 && (ctx->insn_flags & ISA_MIPS32R6)) { + if (rs !=3D 0 && (ctx->insn_flags & ISA_MIPS_R6)) { /* OPC_AUI */ tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], imm << 16); tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); @@ -7399,7 +7399,7 @@ cp0_unimplemented: =20 static inline void gen_mfc0_unimplemented(DisasContext *ctx, TCGv arg) { - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { tcg_gen_movi_tl(arg, 0); } else { tcg_gen_movi_tl(arg, ~0); @@ -7448,7 +7448,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REGISTER_01: switch (sel) { case CP0_REG01__RANDOM: - CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); + CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); gen_helper_mfc0_random(arg, cpu_env); register_name =3D "Random"; break; @@ -7964,7 +7964,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) break; case CP0_REGISTER_21: /* Officially reserved, but sel 0 is used for R1x000 framemask */ - CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); + CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); switch (sel) { case 0: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Framemask)); @@ -8709,7 +8709,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) break; case CP0_REGISTER_21: /* Officially reserved, but sel 0 is used for R1x000 framemask */ - CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); + CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); switch (sel) { case 0: gen_helper_mtc0_framemask(cpu_env, arg); @@ -8980,7 +8980,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case CP0_REGISTER_01: switch (sel) { case CP0_REG01__RANDOM: - CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); + CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); gen_helper_mfc0_random(arg, cpu_env); register_name =3D "Random"; break; @@ -9461,7 +9461,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) break; case CP0_REGISTER_21: /* Officially reserved, but sel 0 is used for R1x000 framemask */ - CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); + CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); switch (sel) { case 0: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Framemask)); @@ -10191,7 +10191,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_21: /* Officially reserved, but sel 0 is used for R1x000 framemask */ - CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); + CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); switch (sel) { case 0: gen_helper_mtc0_framemask(cpu_env, arg); @@ -10985,7 +10985,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext= *ctx, uint32_t opc, gen_helper_tlbr(cpu_env); break; case OPC_ERET: /* OPC_ERETNC */ - if ((ctx->insn_flags & ISA_MIPS32R6) && + if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { goto die; } else { @@ -11007,7 +11007,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext= *ctx, uint32_t opc, case OPC_DERET: opn =3D "deret"; check_insn(ctx, ISA_MIPS_R1); - if ((ctx->insn_flags & ISA_MIPS32R6) && + if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { goto die; } @@ -11022,7 +11022,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext= *ctx, uint32_t opc, case OPC_WAIT: opn =3D "wait"; check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1); - if ((ctx->insn_flags & ISA_MIPS32R6) && + if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { goto die; } @@ -11050,7 +11050,7 @@ static void gen_compute_branch1(DisasContext *ctx, = uint32_t op, target_ulong btarget; TCGv_i32 t0 =3D tcg_temp_new_i32(); =20 - if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->hflags & MIPS_HFLAG_BMAS= K)) { + if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags & MIPS_HFLAG_BMASK= )) { generate_exception_end(ctx, EXCP_RI); goto out; } @@ -11906,23 +11906,23 @@ static void gen_farith(DisasContext *ctx, enum fo= pcode op1, } break; case OPC_SEL_S: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_sel_s(ctx, op1, fd, ft, fs); break; case OPC_SELEQZ_S: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_sel_s(ctx, op1, fd, ft, fs); break; case OPC_SELNEZ_S: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_sel_s(ctx, op1, fd, ft, fs); break; case OPC_MOVCF_S: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_movcf_s(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1); break; case OPC_MOVZ_S: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); { TCGLabel *l1 =3D gen_new_label(); TCGv_i32 fp0; @@ -11938,7 +11938,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MOVN_S: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); { TCGLabel *l1 =3D gen_new_label(); TCGv_i32 fp0; @@ -11974,7 +11974,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MADDF_S: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); { TCGv_i32 fp0 =3D tcg_temp_new_i32(); TCGv_i32 fp1 =3D tcg_temp_new_i32(); @@ -11990,7 +11990,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MSUBF_S: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); { TCGv_i32 fp0 =3D tcg_temp_new_i32(); TCGv_i32 fp1 =3D tcg_temp_new_i32(); @@ -12006,7 +12006,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_RINT_S: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); { TCGv_i32 fp0 =3D tcg_temp_new_i32(); gen_load_fpr32(ctx, fp0, fs); @@ -12016,7 +12016,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_CLASS_S: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); { TCGv_i32 fp0 =3D tcg_temp_new_i32(); gen_load_fpr32(ctx, fp0, fs); @@ -12026,7 +12026,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MIN_S: /* OPC_RECIP2_S */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_MIN_S */ TCGv_i32 fp0 =3D tcg_temp_new_i32(); TCGv_i32 fp1 =3D tcg_temp_new_i32(); @@ -12055,7 +12055,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MINA_S: /* OPC_RECIP1_S */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_MINA_S */ TCGv_i32 fp0 =3D tcg_temp_new_i32(); TCGv_i32 fp1 =3D tcg_temp_new_i32(); @@ -12081,7 +12081,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MAX_S: /* OPC_RSQRT1_S */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_MAX_S */ TCGv_i32 fp0 =3D tcg_temp_new_i32(); TCGv_i32 fp1 =3D tcg_temp_new_i32(); @@ -12105,7 +12105,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MAXA_S: /* OPC_RSQRT2_S */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_MAXA_S */ TCGv_i32 fp0 =3D tcg_temp_new_i32(); TCGv_i32 fp1 =3D tcg_temp_new_i32(); @@ -12207,7 +12207,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, case OPC_CMP_NGE_S: case OPC_CMP_LE_S: case OPC_CMP_NGT_S: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); if (ctx->opcode & (1 << 6)) { gen_cmpabs_s(ctx, func - 48, ft, fs, cc); } else { @@ -12450,23 +12450,23 @@ static void gen_farith(DisasContext *ctx, enum fo= pcode op1, } break; case OPC_SEL_D: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_sel_d(ctx, op1, fd, ft, fs); break; case OPC_SELEQZ_D: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_sel_d(ctx, op1, fd, ft, fs); break; case OPC_SELNEZ_D: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_sel_d(ctx, op1, fd, ft, fs); break; case OPC_MOVCF_D: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_movcf_d(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1); break; case OPC_MOVZ_D: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); { TCGLabel *l1 =3D gen_new_label(); TCGv_i64 fp0; @@ -12482,7 +12482,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MOVN_D: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); { TCGLabel *l1 =3D gen_new_label(); TCGv_i64 fp0; @@ -12520,7 +12520,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MADDF_D: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); { TCGv_i64 fp0 =3D tcg_temp_new_i64(); TCGv_i64 fp1 =3D tcg_temp_new_i64(); @@ -12536,7 +12536,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MSUBF_D: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); { TCGv_i64 fp0 =3D tcg_temp_new_i64(); TCGv_i64 fp1 =3D tcg_temp_new_i64(); @@ -12552,7 +12552,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_RINT_D: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); { TCGv_i64 fp0 =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); @@ -12562,7 +12562,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_CLASS_D: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); { TCGv_i64 fp0 =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); @@ -12572,7 +12572,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MIN_D: /* OPC_RECIP2_D */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_MIN_D */ TCGv_i64 fp0 =3D tcg_temp_new_i64(); TCGv_i64 fp1 =3D tcg_temp_new_i64(); @@ -12599,7 +12599,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MINA_D: /* OPC_RECIP1_D */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_MINA_D */ TCGv_i64 fp0 =3D tcg_temp_new_i64(); TCGv_i64 fp1 =3D tcg_temp_new_i64(); @@ -12623,7 +12623,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MAX_D: /* OPC_RSQRT1_D */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_MAX_D */ TCGv_i64 fp0 =3D tcg_temp_new_i64(); TCGv_i64 fp1 =3D tcg_temp_new_i64(); @@ -12647,7 +12647,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MAXA_D: /* OPC_RSQRT2_D */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_MAXA_D */ TCGv_i64 fp0 =3D tcg_temp_new_i64(); TCGv_i64 fp1 =3D tcg_temp_new_i64(); @@ -12689,7 +12689,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, case OPC_CMP_NGE_D: case OPC_CMP_LE_D: case OPC_CMP_NGT_D: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); if (ctx->opcode & (1 << 6)) { gen_cmpabs_d(ctx, func - 48, ft, fs, cc); } else { @@ -13485,7 +13485,7 @@ static void gen_rdhwr(DisasContext *ctx, int rt, in= t rd, int sel) gen_store_gpr(t0, rt); break; case 4: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); if (sel !=3D 0) { /* * Performance counter registers are not implemented other than @@ -13497,7 +13497,7 @@ static void gen_rdhwr(DisasContext *ctx, int rt, in= t rd, int sel) gen_store_gpr(t0, rt); break; case 5: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_helper_rdhwr_xnp(t0, cpu_env); gen_store_gpr(t0, rt); break; @@ -16160,7 +16160,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasC= ontext *ctx, int rt, int rs) case 0x2c: switch (minor) { case BITSWAP: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_bitswap(ctx, OPC_BITSWAP, rs, rt); break; case SEB: @@ -16179,26 +16179,26 @@ static void gen_pool32axf(CPUMIPSState *env, Disa= sContext *ctx, int rt, int rs) gen_cl(ctx, mips32_op, rt, rs); break; case RDHWR: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_rdhwr(ctx, rt, rs, 0); break; case WSBH: gen_bshfl(ctx, OPC_WSBH, rs, rt); break; case MULT: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_MULT; goto do_mul; case MULTU: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_MULTU; goto do_mul; case DIV: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_DIV; goto do_div; case DIVU: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_DIVU; goto do_div; do_div: @@ -16206,19 +16206,19 @@ static void gen_pool32axf(CPUMIPSState *env, Disa= sContext *ctx, int rt, int rs) gen_muldiv(ctx, mips32_op, 0, rs, rt); break; case MADD: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_MADD; goto do_mul; case MADDU: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_MADDU; goto do_mul; case MSUB: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_MSUB; goto do_mul; case MSUBU: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_MSUBU; do_mul: check_insn(ctx, ISA_MIPS_R1); @@ -16246,7 +16246,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasC= ontext *ctx, int rt, int rs) switch (minor) { case JALR: /* JALRC */ case JALR_HB: /* JALRC_HB */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* JALRC, JALRC_HB */ gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 0); } else { @@ -16257,7 +16257,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasC= ontext *ctx, int rt, int rs) break; case JALRS: case JALRS_HB: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 2); ctx->hflags |=3D MIPS_HFLAG_BDS_STRICT; break; @@ -16400,7 +16400,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasC= ontext *ctx, int rt, int rs) } break; case 0x35: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); switch (minor) { case MFHI32: gen_HILO(ctx, OPC_MFHI, 0, rs); @@ -16674,7 +16674,7 @@ static void gen_pool32fxf(DisasContext *ctx, int rt= , int rs) case COND_FLOAT_MOV(MOVT, 5): case COND_FLOAT_MOV(MOVT, 6): case COND_FLOAT_MOV(MOVT, 7): - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_movci(ctx, rt, rs, (ctx->opcode >> 13) & 0x7, 1); break; case COND_FLOAT_MOV(MOVF, 0): @@ -16685,7 +16685,7 @@ static void gen_pool32fxf(DisasContext *ctx, int rt= , int rs) case COND_FLOAT_MOV(MOVF, 5): case COND_FLOAT_MOV(MOVF, 6): case COND_FLOAT_MOV(MOVF, 7): - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_movci(ctx, rt, rs, (ctx->opcode >> 13) & 0x7, 0); break; default: @@ -16736,15 +16736,15 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) gen_shift_imm(ctx, mips32_op, rt, rs, rd); break; case SELEQZ: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_cond_move(ctx, OPC_SELEQZ, rd, rs, rt); break; case SELNEZ: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_cond_move(ctx, OPC_SELNEZ, rd, rs, rt); break; case R6_RDHWR: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_rdhwr(ctx, rt, rs, extract32(ctx->opcode, 11, 3)); break; default: @@ -16768,7 +16768,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) mips32_op =3D OPC_SUBU; goto do_arith; case MUL: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_MUL; do_arith: gen_arith(ctx, mips32_op, rd, rs, rt); @@ -16821,7 +16821,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) switch (minor) { /* Conditional moves */ case MOVN: /* MUL */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* MUL */ gen_r6_muldiv(ctx, R6_OPC_MUL, rd, rs, rt); } else { @@ -16830,7 +16830,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case MOVZ: /* MUH */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* MUH */ gen_r6_muldiv(ctx, R6_OPC_MUH, rd, rs, rt); } else { @@ -16839,15 +16839,15 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) } break; case MULU: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_r6_muldiv(ctx, R6_OPC_MULU, rd, rs, rt); break; case MUHU: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_r6_muldiv(ctx, R6_OPC_MUHU, rd, rs, rt); break; case LWXS: /* DIV */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* DIV */ gen_r6_muldiv(ctx, R6_OPC_DIV, rd, rs, rt); } else { @@ -16856,15 +16856,15 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) } break; case MOD: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_r6_muldiv(ctx, R6_OPC_MOD, rd, rs, rt); break; case R6_DIVU: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_r6_muldiv(ctx, R6_OPC_DIVU, rd, rs, rt); break; case MODU: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_r6_muldiv(ctx, R6_OPC_MODU, rd, rs, rt); break; default: @@ -16875,12 +16875,12 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) gen_bitops(ctx, OPC_INS, rt, rs, rr, rd); return; case LSA: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_lsa(ctx, OPC_LSA, rd, rs, rt, extract32(ctx->opcode, 9, 2)); break; case ALIGN: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_align(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 9, 2)); break; case EXT: @@ -16893,7 +16893,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) generate_exception_end(ctx, EXCP_BREAK); break; case SIGRIE: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); generate_exception_end(ctx, EXCP_RI); break; default: @@ -16951,61 +16951,61 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) check_cp1_enabled(ctx); switch (minor) { case ALNV_PS: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_ALNV_PS; goto do_madd; case MADD_S: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_MADD_S; goto do_madd; case MADD_D: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_MADD_D; goto do_madd; case MADD_PS: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_MADD_PS; goto do_madd; case MSUB_S: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_MSUB_S; goto do_madd; case MSUB_D: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_MSUB_D; goto do_madd; case MSUB_PS: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_MSUB_PS; goto do_madd; case NMADD_S: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_NMADD_S; goto do_madd; case NMADD_D: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_NMADD_D; goto do_madd; case NMADD_PS: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_NMADD_PS; goto do_madd; case NMSUB_S: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_NMSUB_S; goto do_madd; case NMSUB_D: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_NMSUB_D; goto do_madd; case NMSUB_PS: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_NMSUB_PS; do_madd: gen_flt3_arith(ctx, mips32_op, rd, rr, rs, rt); break; case CABS_COND_FMT: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); cond =3D (ctx->opcode >> 6) & 0xf; cc =3D (ctx->opcode >> 13) & 0x7; fmt =3D (ctx->opcode >> 10) & 0x3; @@ -17024,7 +17024,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case C_COND_FMT: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); cond =3D (ctx->opcode >> 6) & 0xf; cc =3D (ctx->opcode >> 13) & 0x7; fmt =3D (ctx->opcode >> 10) & 0x3; @@ -17043,11 +17043,11 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) } break; case CMP_CONDN_S: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_r6_cmp_s(ctx, (ctx->opcode >> 6) & 0x1f, rt, rs, rd); break; case CMP_CONDN_D: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_r6_cmp_d(ctx, (ctx->opcode >> 6) & 0x1f, rt, rs, rd); break; case POOL32FXF: @@ -17069,7 +17069,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) mips32_op =3D OPC_PUU_PS; goto do_ps; case CVT_PS_S: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_CVT_PS_S; do_ps: gen_farith(ctx, mips32_op, rt, rs, rd, 0); @@ -17079,7 +17079,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case MIN_FMT: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); switch ((ctx->opcode >> 9) & 0x3) { case FMT_SDPS_S: gen_farith(ctx, OPC_MIN_S, rt, rs, rd, 0); @@ -17095,27 +17095,27 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) /* [LS][WDU]XC1 */ switch ((ctx->opcode >> 6) & 0x7) { case LWXC1: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_LWXC1; goto do_ldst_cp1; case SWXC1: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_SWXC1; goto do_ldst_cp1; case LDXC1: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_LDXC1; goto do_ldst_cp1; case SDXC1: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_SDXC1; goto do_ldst_cp1; case LUXC1: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_LUXC1; goto do_ldst_cp1; case SUXC1: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_SUXC1; do_ldst_cp1: gen_flt3_ldst(ctx, mips32_op, rd, rd, rt, rs); @@ -17125,7 +17125,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case MAX_FMT: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); switch ((ctx->opcode >> 9) & 0x3) { case FMT_SDPS_S: gen_farith(ctx, OPC_MAX_S, rt, rs, rd, 0); @@ -17139,7 +17139,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) break; case 0x18: /* 3D insns */ - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); fmt =3D (ctx->opcode >> 9) & 0x3; switch ((ctx->opcode >> 6) & 0x7) { case RSQRT2_FMT: @@ -17190,7 +17190,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) fmt =3D (ctx->opcode >> 9) & 0x3; switch ((ctx->opcode >> 6) & 0x7) { case MOVF_FMT: /* RINT_FMT */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* RINT_FMT */ switch (fmt) { case FMT_SDPS_S: @@ -17221,7 +17221,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case MOVT_FMT: /* CLASS_FMT */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* CLASS_FMT */ switch (fmt) { case FMT_SDPS_S: @@ -17252,7 +17252,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case PREFX: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); break; default: goto pool32f_invalid; @@ -17274,7 +17274,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) goto pool32f_invalid; \ } case MINA_FMT: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); switch ((ctx->opcode >> 9) & 0x3) { case FMT_SDPS_S: gen_farith(ctx, OPC_MINA_S, rt, rs, rd, 0); @@ -17287,7 +17287,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case MAXA_FMT: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); switch ((ctx->opcode >> 9) & 0x3) { case FMT_SDPS_S: gen_farith(ctx, OPC_MAXA_S, rt, rs, rd, 0); @@ -17329,7 +17329,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) /* cmovs */ switch ((ctx->opcode >> 6) & 0x7) { case MOVN_FMT: /* SELEQZ_FMT */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* SELEQZ_FMT */ switch ((ctx->opcode >> 9) & 0x3) { case FMT_SDPS_S: @@ -17347,11 +17347,11 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) } break; case MOVN_FMT_04: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); FINSN_3ARG_SDPS(MOVN); break; case MOVZ_FMT: /* SELNEZ_FMT */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* SELNEZ_FMT */ switch ((ctx->opcode >> 9) & 0x3) { case FMT_SDPS_S: @@ -17369,11 +17369,11 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) } break; case MOVZ_FMT_05: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); FINSN_3ARG_SDPS(MOVZ); break; case SEL_FMT: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); switch ((ctx->opcode >> 9) & 0x3) { case FMT_SDPS_S: gen_sel_s(ctx, OPC_SEL_S, rd, rt, rs); @@ -17386,7 +17386,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case MADDF_FMT: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); switch ((ctx->opcode >> 9) & 0x3) { case FMT_SDPS_S: mips32_op =3D OPC_MADDF_S; @@ -17399,7 +17399,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case MSUBF_FMT: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); switch ((ctx->opcode >> 9) & 0x3) { case FMT_SDPS_S: mips32_op =3D OPC_MSUBF_S; @@ -17432,45 +17432,45 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) minor =3D (ctx->opcode >> 21) & 0x1f; switch (minor) { case BLTZ: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch(ctx, OPC_BLTZ, 4, rs, -1, imm << 1, 4); break; case BLTZAL: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch(ctx, OPC_BLTZAL, 4, rs, -1, imm << 1, 4); ctx->hflags |=3D MIPS_HFLAG_BDS_STRICT; break; case BLTZALS: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch(ctx, OPC_BLTZAL, 4, rs, -1, imm << 1, 2); ctx->hflags |=3D MIPS_HFLAG_BDS_STRICT; break; case BGEZ: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch(ctx, OPC_BGEZ, 4, rs, -1, imm << 1, 4); break; case BGEZAL: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch(ctx, OPC_BGEZAL, 4, rs, -1, imm << 1, 4); ctx->hflags |=3D MIPS_HFLAG_BDS_STRICT; break; case BGEZALS: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch(ctx, OPC_BGEZAL, 4, rs, -1, imm << 1, 2); ctx->hflags |=3D MIPS_HFLAG_BDS_STRICT; break; case BLEZ: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch(ctx, OPC_BLEZ, 4, rs, -1, imm << 1, 4); break; case BGTZ: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch(ctx, OPC_BGTZ, 4, rs, -1, imm << 1, 4); break; =20 /* Traps */ case TLTI: /* BC1EQZC */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* BC1EQZC */ check_cp1_enabled(ctx); gen_compute_branch1_r6(ctx, OPC_BC1EQZ, rs, imm << 1, 0); @@ -17481,7 +17481,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case TGEI: /* BC1NEZC */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* BC1NEZC */ check_cp1_enabled(ctx); gen_compute_branch1_r6(ctx, OPC_BC1NEZ, rs, imm << 1, 0); @@ -17492,15 +17492,15 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) } break; case TLTIU: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_TLTIU; goto do_trapi; case TGEIU: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_TGEIU; goto do_trapi; case TNEI: /* SYNCI */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* SYNCI */ /* * Break the TB to be able to sync copied instructions @@ -17514,7 +17514,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case TEQI: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_TEQI; do_trapi: gen_trap(ctx, mips32_op, rs, -1, imm); @@ -17522,7 +17522,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) =20 case BNEZC: case BEQZC: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch(ctx, minor =3D=3D BNEZC ? OPC_BNE : OPC_BEQ, 4, rs, 0, imm << 1, 0); /* @@ -17532,11 +17532,11 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) */ break; case LUI: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_logic_imm(ctx, OPC_LUI, rs, 0, imm); break; case SYNCI: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* * Break the TB to be able to sync copied instructions * immediately. @@ -17545,24 +17545,24 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) break; case BC2F: case BC2T: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* COP2: Not implemented. */ generate_exception_err(ctx, EXCP_CpU, 2); break; case BC1F: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D (ctx->opcode & (1 << 16)) ? OPC_BC1FANY2 : OPC_B= C1F; goto do_cp1branch; case BC1T: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D (ctx->opcode & (1 << 16)) ? OPC_BC1TANY2 : OPC_B= C1T; goto do_cp1branch; case BC1ANY4F: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_BC1FANY4; goto do_cp1mips3d; case BC1ANY4T: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_BC1TANY4; do_cp1mips3d: check_cop1x(ctx); @@ -17590,47 +17590,47 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) case POOL32C: minor =3D (ctx->opcode >> 12) & 0xf; offset =3D sextract32(ctx->opcode, 0, - (ctx->insn_flags & ISA_MIPS32R6) ? 9 : 12); + (ctx->insn_flags & ISA_MIPS_R6) ? 9 : 12); switch (minor) { case LWL: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_LWL; goto do_ld_lr; case SWL: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_SWL; goto do_st_lr; case LWR: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_LWR; goto do_ld_lr; case SWR: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_SWR; goto do_st_lr; #if defined(TARGET_MIPS64) case LDL: check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_LDL; goto do_ld_lr; case SDL: check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_SDL; goto do_st_lr; case LDR: check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_LDR; goto do_ld_lr; case SDR: check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_SDR; goto do_st_lr; case LWU: @@ -17681,11 +17681,11 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) mips32_op =3D OPC_LHUE; goto do_ld_lr; case LWLE: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_LWLE; goto do_ld_lr; case LWRE: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_LWRE; goto do_ld_lr; case LBE: @@ -17714,16 +17714,16 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) offset =3D sextract32(ctx->opcode, 0, 9); switch (minor2) { case SWLE: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_SWLE; goto do_st_lr; case SWRE: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_SWRE; goto do_st_lr; case PREFE: /* Treat as no-op */ - if ((ctx->insn_flags & ISA_MIPS32R6) && (rt >=3D 24)) { + if ((ctx->insn_flags & ISA_MIPS_R6) && (rt >=3D 24)) { /* hint codes 24-31 are reserved and signal RI */ generate_exception(ctx, EXCP_RI); } @@ -17750,7 +17750,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) break; case PREF: /* Treat as no-op */ - if ((ctx->insn_flags & ISA_MIPS32R6) && (rt >=3D 24)) { + if ((ctx->insn_flags & ISA_MIPS_R6) && (rt >=3D 24)) { /* hint codes 24-31 are reserved and signal RI */ generate_exception(ctx, EXCP_RI); } @@ -17762,7 +17762,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case ADDI32: /* AUI, LUI */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* AUI, LUI */ gen_logic_imm(ctx, OPC_LUI, rt, rs, imm); } else { @@ -17800,13 +17800,13 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) gen_slt_imm(ctx, mips32_op, rt, rs, imm); break; case JALX32: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); offset =3D (int32_t)(ctx->opcode & 0x3FFFFFF) << 2; gen_compute_branch(ctx, OPC_JALX, 4, rt, rs, offset, 4); ctx->hflags |=3D MIPS_HFLAG_BDS_STRICT; break; case JALS32: /* BOVC, BEQC, BEQZALC */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { if (rs >=3D rt) { /* BOVC */ mips32_op =3D OPC_BOVC; @@ -17826,7 +17826,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case BEQ32: /* BC */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* BC */ gen_compute_compact_branch(ctx, OPC_BC, 0, 0, sextract32(ctx->opcode << 1, 0, 27)= ); @@ -17836,7 +17836,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case BNE32: /* BALC */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* BALC */ gen_compute_compact_branch(ctx, OPC_BALC, 0, 0, sextract32(ctx->opcode << 1, 0, 27)= ); @@ -17846,7 +17846,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case J32: /* BGTZC, BLTZC, BLTC */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { if (rs =3D=3D 0 && rt !=3D 0) { /* BGTZC */ mips32_op =3D OPC_BGTZC; @@ -17865,7 +17865,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case JAL32: /* BLEZC, BGEZC, BGEC */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { if (rs =3D=3D 0 && rt !=3D 0) { /* BLEZC */ mips32_op =3D OPC_BLEZC; @@ -17900,7 +17900,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) gen_cop1_ldst(ctx, mips32_op, rt, rs, imm); break; case ADDIUPC: /* PCREL: ADDIUPC, AUIPC, ALUIPC, LWPC */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* PCREL: ADDIUPC, AUIPC, ALUIPC, LWPC */ switch ((ctx->opcode >> 16) & 0x1f) { case ADDIUPC_00: @@ -17942,7 +17942,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case BNVC: /* BNEC, BNEZALC */ - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); if (rs >=3D rt) { /* BNVC */ mips32_op =3D OPC_BNVC; @@ -17956,7 +17956,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1); break; case R6_BNEZC: /* JIALC */ - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); if (rt !=3D 0) { /* BNEZC */ gen_compute_compact_branch(ctx, OPC_BNEZC, rt, 0, @@ -17967,7 +17967,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case R6_BEQZC: /* JIC */ - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); if (rt !=3D 0) { /* BEQZC */ gen_compute_compact_branch(ctx, OPC_BEQZC, rt, 0, @@ -17978,7 +17978,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case BLEZALC: /* BGEZALC, BGEUC */ - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); if (rs =3D=3D 0 && rt !=3D 0) { /* BLEZALC */ mips32_op =3D OPC_BLEZALC; @@ -17992,7 +17992,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1); break; case BGTZALC: /* BLTZALC, BLTUC */ - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); if (rs =3D=3D 0 && rt !=3D 0) { /* BGTZALC */ mips32_op =3D OPC_BGTZALC; @@ -18114,7 +18114,7 @@ static int decode_micromips_opc(CPUMIPSState *env, = DisasContext *ctx) opc =3D OPC_SUBU; break; } - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* * In the Release 6, the register number location in * the instruction encoding has changed. @@ -18146,7 +18146,7 @@ static int decode_micromips_opc(CPUMIPSState *env, = DisasContext *ctx) } break; case POOL16C: - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { gen_pool16c_r6_insn(ctx); } else { gen_pool16c_insn(ctx); @@ -18162,7 +18162,7 @@ static int decode_micromips_opc(CPUMIPSState *env, = DisasContext *ctx) } break; case POOL16F: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); if (ctx->opcode & 1) { generate_exception_end(ctx, EXCP_RI); } else { @@ -18280,14 +18280,14 @@ static int decode_micromips_opc(CPUMIPSState *env= , DisasContext *ctx) case B16: /* BC16 */ gen_compute_branch(ctx, OPC_BEQ, 2, 0, 0, sextract32(ctx->opcode, 0, 10) << 1, - (ctx->insn_flags & ISA_MIPS32R6) ? 0 : 4); + (ctx->insn_flags & ISA_MIPS_R6) ? 0 : 4); break; case BNEZ16: /* BNEZC16 */ case BEQZ16: /* BEQZC16 */ gen_compute_branch(ctx, op =3D=3D BNEZ16 ? OPC_BNE : OPC_BEQ, 2, mmreg(uMIPS_RD(ctx->opcode)), 0, sextract32(ctx->opcode, 0, 7) << 1, - (ctx->insn_flags & ISA_MIPS32R6) ? 0 : 4); + (ctx->insn_flags & ISA_MIPS_R6) ? 0 : 4); =20 break; case LI16: @@ -24970,7 +24970,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) case OPC_SLL: /* Shift with immediate */ if (sa =3D=3D 5 && rd =3D=3D 0 && rs =3D=3D 0 && rt =3D=3D 0) { /* PAUSE */ - if ((ctx->insn_flags & ISA_MIPS32R6) && + if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { generate_exception_end(ctx, EXCP_RI); break; @@ -25045,7 +25045,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) gen_trap(ctx, op1, rs, rt, -1); break; case OPC_LSA: /* OPC_PMON */ - if ((ctx->insn_flags & ISA_MIPS32R6) || + if ((ctx->insn_flags & ISA_MIPS_R6) || (env->CP0_Config3 & (1 << CP0C3_MSAP))) { decode_opc_special_r6(env, ctx); } else { @@ -25148,14 +25148,14 @@ static void decode_opc_special(CPUMIPSState *env,= DisasContext *ctx) } break; case OPC_DLSA: - if ((ctx->insn_flags & ISA_MIPS32R6) || + if ((ctx->insn_flags & ISA_MIPS_R6) || (env->CP0_Config3 & (1 << CP0C3_MSAP))) { decode_opc_special_r6(env, ctx); } break; #endif default: - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { decode_opc_special_r6(env, ctx); } else if (ctx->insn_flags & INSN_R5900) { decode_opc_special_tx79(env, ctx); @@ -27565,7 +27565,7 @@ static void decode_opc_special2_legacy(CPUMIPSState= *env, DisasContext *ctx) int rs, rt, rd; uint32_t op1; =20 - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); =20 rs =3D (ctx->opcode >> 21) & 0x1f; rt =3D (ctx->opcode >> 16) & 0x1f; @@ -28552,7 +28552,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) switch (op1) { case OPC_LWLE: case OPC_LWRE: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* fall through */ case OPC_LBUE: case OPC_LHUE: @@ -28565,7 +28565,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) return; case OPC_SWLE: case OPC_SWRE: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* fall through */ case OPC_SBE: case OPC_SHE: @@ -28605,7 +28605,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) case OPC_ALIGN_2: case OPC_ALIGN_3: case OPC_BITSWAP: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); decode_opc_special3_r6(env, ctx); break; default: @@ -28637,7 +28637,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) case OPC_DALIGN_6: case OPC_DALIGN_7: case OPC_DBITSWAP: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); decode_opc_special3_r6(env, ctx); break; default: @@ -28677,7 +28677,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) } break; default: - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { decode_opc_special3_r6(env, ctx); } else { decode_opc_special3_legacy(env, ctx); @@ -30706,7 +30706,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_BLTZALL: case OPC_BGEZALL: check_insn(ctx, ISA_MIPS2); - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* Fallthrough */ case OPC_BLTZ: case OPC_BGEZ: @@ -30714,7 +30714,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) break; case OPC_BLTZAL: case OPC_BGEZAL: - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { if (rs =3D=3D 0) { /* OPC_NAL, OPC_BAL */ gen_compute_branch(ctx, op1, 4, 0, -1, imm << 2, 4); @@ -30733,11 +30733,11 @@ static void decode_opc(CPUMIPSState *env, DisasCo= ntext *ctx) =20 case OPC_TNEI: check_insn(ctx, ISA_MIPS2); - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_trap(ctx, op1, rs, -1, imm); break; case OPC_SIGRIE: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); generate_exception_end(ctx, EXCP_RI); break; case OPC_SYNCI: @@ -30757,14 +30757,14 @@ static void decode_opc(CPUMIPSState *env, DisasCo= ntext *ctx) break; #if defined(TARGET_MIPS64) case OPC_DAHI: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); check_mips_64(ctx); if (rs !=3D 0) { tcg_gen_addi_tl(cpu_gpr[rs], cpu_gpr[rs], (int64_t)imm << = 32); } break; case OPC_DATI: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); check_mips_64(ctx); if (rs !=3D 0) { tcg_gen_addi_tl(cpu_gpr[rs], cpu_gpr[rs], (int64_t)imm << = 48); @@ -30844,14 +30844,14 @@ static void decode_opc(CPUMIPSState *env, DisasCo= ntext *ctx) gen_store_gpr(t0, rt); break; case OPC_DVP: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); if (ctx->vp) { gen_helper_dvp(t0, cpu_env); gen_store_gpr(t0, rt); } break; case OPC_EVP: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); if (ctx->vp) { gen_helper_evp(t0, cpu_env); gen_store_gpr(t0, rt); @@ -30904,7 +30904,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) } break; case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC, OPC_ADDI */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_BOVC, OPC_BEQZALC, OPC_BEQC */ gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); } else { @@ -30933,7 +30933,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) break; /* Branch */ case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC, OPC_BLEZL */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { if (rt =3D=3D 0) { generate_exception_end(ctx, EXCP_RI); break; @@ -30946,7 +30946,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) } break; case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC, OPC_BGTZL */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { if (rt =3D=3D 0) { generate_exception_end(ctx, EXCP_RI); break; @@ -30963,7 +30963,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) /* OPC_BLEZ */ gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4); } else { - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); /* OPC_BLEZALC, OPC_BGEZALC, OPC_BGEUC */ gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); } @@ -30973,7 +30973,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) /* OPC_BGTZ */ gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4); } else { - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); /* OPC_BGTZALC, OPC_BLTZALC, OPC_BLTUC */ gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); } @@ -30981,7 +30981,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_BEQL: case OPC_BNEL: check_insn(ctx, ISA_MIPS2); - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* Fallthrough */ case OPC_BEQ: case OPC_BNE: @@ -30995,7 +30995,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) /* Fallthrough */ case OPC_LWL: case OPC_LWR: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* Fallthrough */ case OPC_LB: case OPC_LH: @@ -31007,7 +31007,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) break; case OPC_SWL: case OPC_SWR: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* fall through */ case OPC_SB: case OPC_SH: @@ -31016,14 +31016,14 @@ static void decode_opc(CPUMIPSState *env, DisasCo= ntext *ctx) break; case OPC_SC: check_insn(ctx, ISA_MIPS2); - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); if (ctx->insn_flags & INSN_R5900) { check_insn_opc_user_only(ctx, INSN_R5900); } gen_st_cond(ctx, rt, rs, imm, MO_TESL, false); break; case OPC_CACHE: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); check_cp0_enabled(ctx); check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1); if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { @@ -31032,7 +31032,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) /* Treat as NOP. */ break; case OPC_PREF: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); if (ctx->insn_flags & INSN_R5900) { /* Treat as NOP. */ } else { @@ -31076,7 +31076,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) #endif case OPC_BC1EQZ: /* OPC_BC1ANY2 */ check_cp1_enabled(ctx); - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_BC1EQZ */ gen_compute_branch1_r6(ctx, MASK_CP1(ctx->opcode), rt, imm << 2, 4); @@ -31090,19 +31090,19 @@ static void decode_opc(CPUMIPSState *env, DisasCo= ntext *ctx) break; case OPC_BC1NEZ: check_cp1_enabled(ctx); - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_compute_branch1_r6(ctx, MASK_CP1(ctx->opcode), rt, imm << 2, 4); break; case OPC_BC1ANY4: check_cp1_enabled(ctx); - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); check_cop1x(ctx); check_insn(ctx, ASE_MIPS3D); /* fall through */ case OPC_BC1: check_cp1_enabled(ctx); - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch1(ctx, MASK_BC1(ctx->opcode), (rt >> 2) & 0x7, imm << 2); break; @@ -31120,7 +31120,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) { int r6_op =3D ctx->opcode & FOP(0x3f, 0x1f); check_cp1_enabled(ctx); - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { switch (r6_op) { case R6_OPC_CMP_AF_S: case R6_OPC_CMP_UN_S: @@ -31205,7 +31205,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) /* Compact branches [R6] and COP2 [non-R6] */ case OPC_BC: /* OPC_LWC2 */ case OPC_BALC: /* OPC_SWC2 */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_BC, OPC_BALC */ gen_compute_compact_branch(ctx, op, 0, 0, sextract32(ctx->opcode << 2, 0, 28)= ); @@ -31219,7 +31219,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) break; case OPC_BEQZC: /* OPC_JIC, OPC_LDC2 */ case OPC_BNEZC: /* OPC_JIALC, OPC_SDC2 */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { if (rs !=3D 0) { /* OPC_BEQZC, OPC_BNEZC */ gen_compute_compact_branch(ctx, op, rs, 0, @@ -31243,7 +31243,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) break; =20 case OPC_CP3: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); if (ctx->CP0_Config1 & (1 << CP0C1_FP)) { check_cp1_enabled(ctx); op1 =3D MASK_CP3(ctx->opcode); @@ -31300,7 +31300,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) /* fall through */ case OPC_LDL: case OPC_LDR: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* fall through */ case OPC_LWU: case OPC_LD: @@ -31310,7 +31310,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) break; case OPC_SDL: case OPC_SDR: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* fall through */ case OPC_SD: check_insn(ctx, ISA_MIPS3); @@ -31318,7 +31318,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) gen_st(ctx, op, rt, rs, imm); break; case OPC_SCD: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); check_insn(ctx, ISA_MIPS3); if (ctx->insn_flags & INSN_R5900) { check_insn_opc_user_only(ctx, INSN_R5900); @@ -31327,7 +31327,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) gen_st_cond(ctx, rt, rs, imm, MO_TEQ, false); break; case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC, OPC_DADDI */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_BNVC, OPC_BNEZALC, OPC_BNEC */ gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); } else { @@ -31344,7 +31344,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) break; #else case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); } else { MIPS_INVAL("major opcode"); @@ -31353,7 +31353,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) break; #endif case OPC_DAUI: /* OPC_JALX */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { #if defined(TARGET_MIPS64) /* OPC_DAUI */ check_mips_64(ctx); @@ -31387,7 +31387,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) } break; case OPC_PCREL: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_pcrel(ctx, ctx->opcode, ctx->base.pc_next, rs); break; default: /* Invalid */ @@ -31438,7 +31438,7 @@ static void mips_tr_init_disas_context(DisasContext= Base *dcbase, CPUState *cs) #else ctx->mem_idx =3D hflags_mmu_index(ctx->hflags); #endif - ctx->default_tcg_memop_mask =3D (ctx->insn_flags & (ISA_MIPS32R6 | + ctx->default_tcg_memop_mask =3D (ctx->insn_flags & (ISA_MIPS_R6 | INSN_LOONGSON3A)) ? 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Thu, 07 Jan 2021 14:24:35 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 19/66] target/mips: Inline cpu_state_reset() in mips_cpu_reset() Date: Thu, 7 Jan 2021 23:22:06 +0100 Message-Id: <20210107222253.20382-20-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.78 on 10.11.54.6 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201214183739.500368-2-f4bug@amsat.org> --- target/mips/cpu.c | 26 +++++++++----------------- 1 file changed, 9 insertions(+), 17 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 12126d37f16..4a251e2d3e8 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -104,10 +104,16 @@ static bool mips_cpu_has_work(CPUState *cs) =20 #include "translate_init.c.inc" =20 -/* TODO QOM'ify CPU reset and remove */ -static void cpu_state_reset(CPUMIPSState *env) +static void mips_cpu_reset(DeviceState *dev) { - CPUState *cs =3D env_cpu(env); + CPUState *cs =3D CPU(dev); + MIPSCPU *cpu =3D MIPS_CPU(cs); + MIPSCPUClass *mcc =3D MIPS_CPU_GET_CLASS(cpu); + CPUMIPSState *env =3D &cpu->env; + + mcc->parent_reset(dev); + + memset(env, 0, offsetof(CPUMIPSState, end_reset_fields)); =20 /* Reset registers to their default values */ env->CP0_PRid =3D env->cpu_model->CP0_PRid; @@ -330,20 +336,6 @@ static void cpu_state_reset(CPUMIPSState *env) /* UHI interface can be used to obtain argc and argv */ env->active_tc.gpr[4] =3D -1; } -} - -static void mips_cpu_reset(DeviceState *dev) -{ - CPUState *s =3D CPU(dev); - MIPSCPU *cpu =3D MIPS_CPU(s); - MIPSCPUClass *mcc =3D MIPS_CPU_GET_CLASS(cpu); - CPUMIPSState *env =3D &cpu->env; - - mcc->parent_reset(dev); - - memset(env, 0, offsetof(CPUMIPSState, end_reset_fields)); - - cpu_state_reset(env); =20 #ifndef CONFIG_USER_ONLY if (kvm_enabled()) { --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 63.128.21.124 as permitted sender) client-ip=63.128.21.124; envelope-from=libvir-list-bounces@redhat.com; helo=us-smtp-delivery-124.mimecast.com; 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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id m21sm9418533wml.13.2021.01.07.14.24.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:24:39 -0800 (PST) X-MC-Unique: C2OuULOOMmiZ8o5QC6_StQ-1 X-MC-Unique: n-oSvog_P1-2jK2KHPDw1A-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=BdvOr2p5e3AFDonK5fThCYYux8AoIQfWjQUjO/9FW44=; b=mPAVlSisQ27Tk6NxOt5RsluXsZFjnvGdLRWsM+tzjrPKq7xMysLVtWsBcrwtMsG2UQ O4peonMgOEmXj9BEtwVWyddK/t/aHJ5nyXfN8jimbeMig73Ufm4d/FvOxYvqEaxbm1pZ Pii3m/tHDaZhUt8TGoEcD/UoLoQUVnn87qvO3x/EjlYOg8VGcusWP6AnVrXbJq/R7Kc7 YchxK+kyRB4BlmBKznlLQ3QfRVQlZQXTx9+QV4uyfqLExJMmKXixjNRkLDead0SiqWHN XAFQ8JWCgs2HXnlAysIpK+8miA+ELtVJUs66MmliqxVgNDRbYygdghMuKZevAKRXC3hv BhBQ== X-Gm-Message-State: AOAM532+Uuvz9p3To+bdSFwPn8fCqYPK2JpfJ66hUE4VyiQkQmJJ8I5K AKV+9n+XE+r4Le+lS7Q863Uo1W4Uzys= X-Google-Smtp-Source: ABdhPJwoOP4/MnQmrVOFNw4uDBAloO9OP/Lwaa31bQpI1Ive3RvPcRsEVeF3b1fqUYw6lGLA+fd/1Q== X-Received: by 2002:a5d:6cd4:: with SMTP id c20mr671220wrc.57.1610058280376; Thu, 07 Jan 2021 14:24:40 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 20/66] target/mips: Extract FPU helpers to 'fpu_helper.h' Date: Thu, 7 Jan 2021 23:22:07 +0100 Message-Id: <20210107222253.20382-21-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Extract FPU specific helpers from "internal.h" to "fpu_helper.h". Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20201120210844.2625602-2-f4bug@amsat.org> --- target/mips/fpu_helper.h | 59 ++++++++++++++++++++++++++++++++ target/mips/internal.h | 49 -------------------------- linux-user/mips/cpu_loop.c | 1 + target/mips/fpu_helper.c | 1 + target/mips/gdbstub.c | 1 + target/mips/kvm.c | 1 + target/mips/machine.c | 1 + target/mips/msa_helper.c | 1 + target/mips/op_helper.c | 2 +- target/mips/translate.c | 1 + target/mips/translate_init.c.inc | 2 ++ 11 files changed, 69 insertions(+), 50 deletions(-) create mode 100644 target/mips/fpu_helper.h diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h new file mode 100644 index 00000000000..1c2d6d35a71 --- /dev/null +++ b/target/mips/fpu_helper.h @@ -0,0 +1,59 @@ +/* + * Helpers for emulation of FPU-related MIPS instructions. + * + * Copyright (C) 2004-2005 Jocelyn Mayer + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ +#include "fpu/softfloat-helpers.h" +#include "cpu.h" + +extern const FloatRoundMode ieee_rm[4]; + +uint32_t float_class_s(uint32_t arg, float_status *fst); +uint64_t float_class_d(uint64_t arg, float_status *fst); + +static inline void restore_rounding_mode(CPUMIPSState *env) +{ + set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], + &env->active_fpu.fp_status); +} + +static inline void restore_flush_mode(CPUMIPSState *env) +{ + set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) !=3D 0, + &env->active_fpu.fp_status); +} + +static inline void restore_snan_bit_mode(CPUMIPSState *env) +{ + set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) =3D= =3D 0, + &env->active_fpu.fp_status); +} + +static inline void restore_fp_status(CPUMIPSState *env) +{ + restore_rounding_mode(env); + restore_flush_mode(env); + restore_snan_bit_mode(env); +} + +/* MSA */ + +enum CPUMIPSMSADataFormat { + DF_BYTE =3D 0, + DF_HALF, + DF_WORD, + DF_DOUBLE +}; + +static inline void restore_msa_fp_status(CPUMIPSState *env) +{ + float_status *status =3D &env->active_tc.msa_fp_status; + int rounding_mode =3D (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSAC= SR_RM; + bool flush_to_zero =3D (env->active_tc.msacsr & MSACSR_FS_MASK) !=3D 0; + + set_float_rounding_mode(ieee_rm[rounding_mode], status); + set_flush_to_zero(flush_to_zero, status); + set_flush_inputs_to_zero(flush_to_zero, status); +} diff --git a/target/mips/internal.h b/target/mips/internal.h index 77a648bcf9c..f159187b246 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -9,7 +9,6 @@ #define MIPS_INTERNAL_H =20 #include "exec/memattrs.h" -#include "fpu/softfloat-helpers.h" =20 /* * MMU types, the first four entries have the same layout as the @@ -75,13 +74,6 @@ struct mips_def_t { extern const struct mips_def_t mips_defs[]; extern const int mips_defs_number; =20 -enum CPUMIPSMSADataFormat { - DF_BYTE =3D 0, - DF_HALF, - DF_WORD, - DF_DOUBLE -}; - void mips_cpu_do_interrupt(CPUState *cpu); bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); void mips_cpu_dump_state(CPUState *cpu, FILE *f, int flags); @@ -220,49 +212,8 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, bool probe, uintptr_t retaddr); =20 /* op_helper.c */ -uint32_t float_class_s(uint32_t arg, float_status *fst); -uint64_t float_class_d(uint64_t arg, float_status *fst); - -extern const FloatRoundMode ieee_rm[4]; - void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagema= sk); =20 -static inline void restore_rounding_mode(CPUMIPSState *env) -{ - set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], - &env->active_fpu.fp_status); -} - -static inline void restore_flush_mode(CPUMIPSState *env) -{ - set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) !=3D 0, - &env->active_fpu.fp_status); -} - -static inline void restore_snan_bit_mode(CPUMIPSState *env) -{ - set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) =3D= =3D 0, - &env->active_fpu.fp_status); -} - -static inline void restore_fp_status(CPUMIPSState *env) -{ - restore_rounding_mode(env); - restore_flush_mode(env); - restore_snan_bit_mode(env); -} - -static inline void restore_msa_fp_status(CPUMIPSState *env) -{ - float_status *status =3D &env->active_tc.msa_fp_status; - int rounding_mode =3D (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSAC= SR_RM; - bool flush_to_zero =3D (env->active_tc.msacsr & MSACSR_FS_MASK) !=3D 0; - - set_float_rounding_mode(ieee_rm[rounding_mode], status); - set_flush_to_zero(flush_to_zero, status); - set_flush_inputs_to_zero(flush_to_zero, status); -} - static inline void restore_pamask(CPUMIPSState *env) { if (env->hflags & MIPS_HFLAG_ELPA) { diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index 19947448a25..9d813ece4e7 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -23,6 +23,7 @@ #include "cpu_loop-common.h" #include "elf.h" #include "internal.h" +#include "fpu_helper.h" =20 # ifdef TARGET_ABI_MIPSO32 # define MIPS_SYSCALL_NUMBER_UNUSED -1 diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index 91b6a2e11fc..6dd853259e2 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -27,6 +27,7 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "fpu/softfloat.h" +#include "fpu_helper.h" =20 =20 /* Complex FPU operations which may need stack space. */ diff --git a/target/mips/gdbstub.c b/target/mips/gdbstub.c index e39f8d75cf0..f1c2a2cf6d6 100644 --- a/target/mips/gdbstub.c +++ b/target/mips/gdbstub.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "internal.h" #include "exec/gdbstub.h" +#include "fpu_helper.h" =20 int mips_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { diff --git a/target/mips/kvm.c b/target/mips/kvm.c index 477692566a4..a5b6fe35dbc 100644 --- a/target/mips/kvm.c +++ b/target/mips/kvm.c @@ -24,6 +24,7 @@ #include "sysemu/runstate.h" #include "kvm_mips.h" #include "hw/boards.h" +#include "fpu_helper.h" =20 #define DEBUG_KVM 0 =20 diff --git a/target/mips/machine.c b/target/mips/machine.c index 77afe654e91..b5fda6a2786 100644 --- a/target/mips/machine.c +++ b/target/mips/machine.c @@ -2,6 +2,7 @@ #include "cpu.h" #include "internal.h" #include "migration/cpu.h" +#include "fpu_helper.h" =20 static int cpu_post_load(void *opaque, int version_id) { diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 249f0fdad80..b89b4c44902 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -23,6 +23,7 @@ #include "exec/exec-all.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" +#include "fpu_helper.h" =20 /* Data format min and max values */ #define DF_BITS(df) (1 << ((df) + 3)) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 5aa97902e98..3386b8228e9 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -24,7 +24,7 @@ #include "exec/helper-proto.h" #include "exec/exec-all.h" #include "exec/memop.h" - +#include "fpu_helper.h" =20 /*************************************************************************= ****/ /* Exceptions processing helpers */ diff --git a/target/mips/translate.c b/target/mips/translate.c index e813add99c5..f8f0f95509c 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -35,6 +35,7 @@ #include "exec/translator.h" #include "exec/log.h" #include "qemu/qemu-print.h" +#include "fpu_helper.h" =20 #define MIPS_DEBUG_DISAS 0 =20 diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.= c.inc index 0ba3cf18ef7..044052fb77c 100644 --- a/target/mips/translate_init.c.inc +++ b/target/mips/translate_init.c.inc @@ -18,6 +18,8 @@ * License along with this library; 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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id n9sm10103105wrq.41.2021.01.07.14.24.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:24:44 -0800 (PST) X-MC-Unique: e7VRwF5AOTuHgTMW8J2Ztw-1 X-MC-Unique: JYbeK1JWN5G6LOA7YptIAw-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=r446af/BEgIH/8cqnACVmQPnVuqEMMgc7/K3JtKHKOk=; b=pQVluOrjw//URwoOyui2TvZePM36UGGMC0+1ypclJ8TFfXSsM5v+zzKKyyycURTtxY jrNwVaA7huY5ioCxMT+IzuXxte7u6eSgvahixTaXmkyr8fFU98H/7Iu95D3mENeF8c7I MLOadYh1bjioZC1B0venzkzvNRq3qbXhf89iqgCG1TvKd9bldR1fSMI/RWADucz08juh buwkxJtcsfFlikefQcuhsZKD3k+x85G0kTxXh/ueNhtvi820DwEtXr405fEKik4rIeF5 B+4C26qnYcomyDh/GajAdu/5FRpCY+mt/Am4rYqM0L9siIyF8DFHweCXKz4ycFDQSIkv R+rQ== X-Gm-Message-State: AOAM532Nun/U/oNfl0und87t9fgxv+PDov2vNJazNrMk5vuRIbRqh5Aj 7kXxIKfWZ+uQkdq+4ugo8q8= X-Google-Smtp-Source: ABdhPJwCsmyU6k2gmlk9eYhvqhY92VyIIL3GWXGM3B7ZnDJ3ScTAoH3Xic2OzXnKHm6okNdHJVKirQ== X-Received: by 2002:a5d:4ad0:: with SMTP id y16mr662380wrs.424.1610058285366; Thu, 07 Jan 2021 14:24:45 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 21/66] target/mips: Add !CONFIG_USER_ONLY comment after #endif Date: Thu, 7 Jan 2021 23:22:08 +0100 Message-Id: <20210107222253.20382-22-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable To help understand ifdef'ry, add comment after #endif. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201214183739.500368-4-f4bug@amsat.org> --- target/mips/helper.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/target/mips/helper.c b/target/mips/helper.c index d1b6bb6fb23..92bd3fb8550 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -455,7 +455,8 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulo= ng val) } } } -#endif + +#endif /* !CONFIG_USER_ONLY */ =20 static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, int rw, int tlb_error) @@ -537,6 +538,7 @@ static void raise_mmu_exception(CPUMIPSState *env, targ= et_ulong address, } =20 #if !defined(CONFIG_USER_ONLY) + hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { MIPSCPU *cpu =3D MIPS_CPU(cs); @@ -550,7 +552,7 @@ hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr= addr) } return phys_addr; } -#endif +#endif /* !CONFIG_USER_ONLY */ =20 #if !defined(CONFIG_USER_ONLY) #if !defined(TARGET_MIPS64) @@ -886,7 +888,7 @@ refill: return true; } #endif -#endif +#endif /* !CONFIG_USER_ONLY */ =20 bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, @@ -1088,7 +1090,8 @@ static inline void set_badinstr_registers(CPUMIPSStat= e *env) env->CP0_BadInstrP =3D cpu_ldl_code(env, env->active_tc.PC - 4); } } -#endif + +#endif /* !CONFIG_USER_ONLY */ =20 void mips_cpu_do_interrupt(CPUState *cs) { @@ -1482,7 +1485,7 @@ void r4k_invalidate_tlb(CPUMIPSState *env, int idx, i= nt use_extra) } } } -#endif +#endif /* !CONFIG_USER_ONLY */ =20 void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception, --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) client-ip=216.205.24.124; envelope-from=libvir-list-bounces@redhat.com; helo=us-smtp-delivery-124.mimecast.com; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) smtp.mailfrom=libvir-list-bounces@redhat.com ARC-Seal: i=1; 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Thu, 07 Jan 2021 14:24:50 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 22/66] target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs Date: Thu, 7 Jan 2021 23:22:09 +0100 Message-Id: <20210107222253.20382-23-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.78 on 10.11.54.6 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201214183739.500368-5-f4bug@amsat.org> --- target/mips/helper.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/mips/helper.c b/target/mips/helper.c index 92bd3fb8550..cfb6d82fd33 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -552,9 +552,7 @@ hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr= addr) } return phys_addr; } -#endif /* !CONFIG_USER_ONLY */ =20 -#if !defined(CONFIG_USER_ONLY) #if !defined(TARGET_MIPS64) =20 /* --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) client-ip=216.205.24.124; envelope-from=libvir-list-bounces@redhat.com; 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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id u9sm9799784wmb.32.2021.01.07.14.24.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:24:55 -0800 (PST) X-MC-Unique: Jg8bbxqQN_24QCHMHXDu8A-1 X-MC-Unique: 20T6z9d0OqCAaN4mNOahuA-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=xuQvuHCVEZAh72d2SismUVVThKi2PJBBdEAx4eAa8xA=; b=s87lrfuuDyB2WZZj0ABA8e0N6NiHbnxVJZR6+NQStX25VIrA5HUsh8x3tpMLIElV0w IrStVdXKAZskLsfnuoS6dHA0z2voxGBn+PHWWiVfU1PQD9xm/J410m6b6VP//+EeHbYn qw1ip5hjvgnGjEW2WQqag+gRbtH9fflDod0LLlV9ELGYS829c7/JmQzjgGStTiF3GCuS iFXZVfCAtTYjjFqplLNMlwE2WRIaCH6R1wSIoLnfeqWIttfk13NeGXQhSQ4xGjyhaTdO gEfrHy7SE6V5Zh/jl7zUkBqORqHbMjYf9Ixf4qgFfl5wIyzdFWCiizLdD37e490yvZKb 9KZg== X-Gm-Message-State: AOAM5318dBurY10t8w+mm9WQgB943BeUGcaC2G12g2GNQE6+ZjWtYGke Pe29Zbqufcq5iKhA5dU+GMo= X-Google-Smtp-Source: ABdhPJxq3F0JGBmt7EbcwdQWI7gMPkSM0l1prQN7QshireE7IIB2B4smMCPKyoPIy8z+koUNe2rRCw== X-Received: by 2002:adf:ec86:: with SMTP id z6mr670954wrn.17.1610058295678; Thu, 07 Jan 2021 14:24:55 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 23/66] target/mips: Move common helpers from helper.c to cpu.c Date: Thu, 7 Jan 2021 23:22:10 +0100 Message-Id: <20210107222253.20382-24-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The rest of helper.c is TLB related. Extract the non TLB specific functions to cpu.c, so we can rename helper.c as tlb_helper.c in the next commit. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201214183739.500368-6-f4bug@amsat.org> --- target/mips/internal.h | 2 + target/mips/cpu.c | 215 +++++++++++++++++++++++++++++++++++++++-- target/mips/helper.c | 201 -------------------------------------- 3 files changed, 211 insertions(+), 207 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index f159187b246..ae1181d2029 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -399,6 +399,8 @@ void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cp= u, int tc); void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); =20 +const char *mips_exception_name(int32_t exception); + void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exce= ption, int error_code, uintptr_t pc); =20 diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 4a251e2d3e8..26b4c3e9cd5 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -34,6 +34,215 @@ #include "hw/semihosting/semihost.h" #include "qapi/qapi-commands-machine-target.h" =20 +#if !defined(CONFIG_USER_ONLY) + +/* Called for updates to CP0_Status. */ +void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) +{ + int32_t tcstatus, *tcst; + uint32_t v =3D cpu->CP0_Status; + uint32_t cu, mx, asid, ksu; + uint32_t mask =3D ((1 << CP0TCSt_TCU3) + | (1 << CP0TCSt_TCU2) + | (1 << CP0TCSt_TCU1) + | (1 << CP0TCSt_TCU0) + | (1 << CP0TCSt_TMX) + | (3 << CP0TCSt_TKSU) + | (0xff << CP0TCSt_TASID)); + + cu =3D (v >> CP0St_CU0) & 0xf; + mx =3D (v >> CP0St_MX) & 0x1; + ksu =3D (v >> CP0St_KSU) & 0x3; + asid =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + + tcstatus =3D cu << CP0TCSt_TCU0; + tcstatus |=3D mx << CP0TCSt_TMX; + tcstatus |=3D ksu << CP0TCSt_TKSU; + tcstatus |=3D asid; + + if (tc =3D=3D cpu->current_tc) { + tcst =3D &cpu->active_tc.CP0_TCStatus; + } else { + tcst =3D &cpu->tcs[tc].CP0_TCStatus; + } + + *tcst &=3D ~mask; + *tcst |=3D tcstatus; + compute_hflags(cpu); +} + +void cpu_mips_store_status(CPUMIPSState *env, target_ulong val) +{ + uint32_t mask =3D env->CP0_Status_rw_bitmask; + target_ulong old =3D env->CP0_Status; + + if (env->insn_flags & ISA_MIPS_R6) { + bool has_supervisor =3D extract32(mask, CP0St_KSU, 2) =3D=3D 0x3; +#if defined(TARGET_MIPS64) + uint32_t ksux =3D (1 << CP0St_KX) & val; + ksux |=3D (ksux >> 1) & val; /* KX =3D 0 forces SX to be 0 */ + ksux |=3D (ksux >> 1) & val; /* SX =3D 0 forces UX to be 0 */ + val =3D (val & ~(7 << CP0St_UX)) | ksux; +#endif + if (has_supervisor && extract32(val, CP0St_KSU, 2) =3D=3D 0x3) { + mask &=3D ~(3 << CP0St_KSU); + } + mask &=3D ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val); + } + + env->CP0_Status =3D (old & ~mask) | (val & mask); +#if defined(TARGET_MIPS64) + if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) { + /* Access to at least one of the 64-bit segments has been disabled= */ + tlb_flush(env_cpu(env)); + } +#endif + if (ase_mt_available(env)) { + sync_c0_status(env, env, env->current_tc); + } else { + compute_hflags(env); + } +} + +void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val) +{ + uint32_t mask =3D 0x00C00300; + uint32_t old =3D env->CP0_Cause; + int i; + + if (env->insn_flags & ISA_MIPS_R2) { + mask |=3D 1 << CP0Ca_DC; + } + if (env->insn_flags & ISA_MIPS_R6) { + mask &=3D ~((1 << CP0Ca_WP) & val); + } + + env->CP0_Cause =3D (env->CP0_Cause & ~mask) | (val & mask); + + if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { + if (env->CP0_Cause & (1 << CP0Ca_DC)) { + cpu_mips_stop_count(env); + } else { + cpu_mips_start_count(env); + } + } + + /* Set/reset software interrupts */ + for (i =3D 0 ; i < 2 ; i++) { + if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) { + cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i= ))); + } + } +} + +#endif /* !CONFIG_USER_ONLY */ + +static const char * const excp_names[EXCP_LAST + 1] =3D { + [EXCP_RESET] =3D "reset", + [EXCP_SRESET] =3D "soft reset", + [EXCP_DSS] =3D "debug single step", + [EXCP_DINT] =3D "debug interrupt", + [EXCP_NMI] =3D "non-maskable interrupt", + [EXCP_MCHECK] =3D "machine check", + [EXCP_EXT_INTERRUPT] =3D "interrupt", + [EXCP_DFWATCH] =3D "deferred watchpoint", + [EXCP_DIB] =3D "debug instruction breakpoint", + [EXCP_IWATCH] =3D "instruction fetch watchpoint", + [EXCP_AdEL] =3D "address error load", + [EXCP_AdES] =3D "address error store", + [EXCP_TLBF] =3D "TLB refill", + [EXCP_IBE] =3D "instruction bus error", + [EXCP_DBp] =3D "debug breakpoint", + [EXCP_SYSCALL] =3D "syscall", + [EXCP_BREAK] =3D "break", + [EXCP_CpU] =3D "coprocessor unusable", + [EXCP_RI] =3D "reserved instruction", + [EXCP_OVERFLOW] =3D "arithmetic overflow", + [EXCP_TRAP] =3D "trap", + [EXCP_FPE] =3D "floating point", + [EXCP_DDBS] =3D "debug data break store", + [EXCP_DWATCH] =3D "data watchpoint", + [EXCP_LTLBL] =3D "TLB modify", + [EXCP_TLBL] =3D "TLB load", + [EXCP_TLBS] =3D "TLB store", + [EXCP_DBE] =3D "data bus error", + [EXCP_DDBL] =3D "debug data break load", + [EXCP_THREAD] =3D "thread", + [EXCP_MDMX] =3D "MDMX", + [EXCP_C2E] =3D "precise coprocessor 2", + [EXCP_CACHE] =3D "cache error", + [EXCP_TLBXI] =3D "TLB execute-inhibit", + [EXCP_TLBRI] =3D "TLB read-inhibit", + [EXCP_MSADIS] =3D "MSA disabled", + [EXCP_MSAFPE] =3D "MSA floating point", +}; + +const char *mips_exception_name(int32_t exception) +{ + if (exception < 0 || exception > EXCP_LAST) { + return "unknown"; + } + return excp_names[exception]; +} + +void cpu_set_exception_base(int vp_index, target_ulong address) +{ + MIPSCPU *vp =3D MIPS_CPU(qemu_get_cpu(vp_index)); + vp->env.exception_base =3D address; +} + +target_ulong exception_resume_pc(CPUMIPSState *env) +{ + target_ulong bad_pc; + target_ulong isa_mode; + + isa_mode =3D !!(env->hflags & MIPS_HFLAG_M16); + bad_pc =3D env->active_tc.PC | isa_mode; + if (env->hflags & MIPS_HFLAG_BMASK) { + /* + * If the exception was raised from a delay slot, come back to + * the jump. + */ + bad_pc -=3D (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); + } + + return bad_pc; +} + +bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + if (interrupt_request & CPU_INTERRUPT_HARD) { + MIPSCPU *cpu =3D MIPS_CPU(cs); + CPUMIPSState *env =3D &cpu->env; + + if (cpu_mips_hw_interrupts_enabled(env) && + cpu_mips_hw_interrupts_pending(env)) { + /* Raise it */ + cs->exception_index =3D EXCP_EXT_INTERRUPT; + env->error_code =3D 0; + mips_cpu_do_interrupt(cs); + return true; + } + } + return false; +} + +void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, + uint32_t exception, + int error_code, + uintptr_t pc) +{ + CPUState *cs =3D env_cpu(env); + + qemu_log_mask(CPU_LOG_INT, "%s: %d (%s) %d\n", + __func__, exception, mips_exception_name(exception), + error_code); + cs->exception_index =3D exception; + env->error_code =3D error_code; + + cpu_loop_exit_restore(cs, pc); +} + static void mips_cpu_set_pc(CPUState *cs, vaddr value) { MIPSCPU *cpu =3D MIPS_CPU(cs); @@ -587,9 +796,3 @@ bool cpu_type_supports_cps_smp(const char *cpu_type) const MIPSCPUClass *mcc =3D MIPS_CPU_CLASS(object_class_by_name(cpu_ty= pe)); return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) !=3D 0; } - -void cpu_set_exception_base(int vp_index, target_ulong address) -{ - MIPSCPU *vp =3D MIPS_CPU(qemu_get_cpu(vp_index)); - vp->env.exception_base =3D address; -} diff --git a/target/mips/helper.c b/target/mips/helper.c index cfb6d82fd33..68804b84b15 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -357,105 +357,6 @@ void cpu_mips_tlb_flush(CPUMIPSState *env) env->tlb->tlb_in_use =3D env->tlb->nb_tlb; } =20 -/* Called for updates to CP0_Status. */ -void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) -{ - int32_t tcstatus, *tcst; - uint32_t v =3D cpu->CP0_Status; - uint32_t cu, mx, asid, ksu; - uint32_t mask =3D ((1 << CP0TCSt_TCU3) - | (1 << CP0TCSt_TCU2) - | (1 << CP0TCSt_TCU1) - | (1 << CP0TCSt_TCU0) - | (1 << CP0TCSt_TMX) - | (3 << CP0TCSt_TKSU) - | (0xff << CP0TCSt_TASID)); - - cu =3D (v >> CP0St_CU0) & 0xf; - mx =3D (v >> CP0St_MX) & 0x1; - ksu =3D (v >> CP0St_KSU) & 0x3; - asid =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; - - tcstatus =3D cu << CP0TCSt_TCU0; - tcstatus |=3D mx << CP0TCSt_TMX; - tcstatus |=3D ksu << CP0TCSt_TKSU; - tcstatus |=3D asid; - - if (tc =3D=3D cpu->current_tc) { - tcst =3D &cpu->active_tc.CP0_TCStatus; - } else { - tcst =3D &cpu->tcs[tc].CP0_TCStatus; - } - - *tcst &=3D ~mask; - *tcst |=3D tcstatus; - compute_hflags(cpu); -} - -void cpu_mips_store_status(CPUMIPSState *env, target_ulong val) -{ - uint32_t mask =3D env->CP0_Status_rw_bitmask; - target_ulong old =3D env->CP0_Status; - - if (env->insn_flags & ISA_MIPS_R6) { - bool has_supervisor =3D extract32(mask, CP0St_KSU, 2) =3D=3D 0x3; -#if defined(TARGET_MIPS64) - uint32_t ksux =3D (1 << CP0St_KX) & val; - ksux |=3D (ksux >> 1) & val; /* KX =3D 0 forces SX to be 0 */ - ksux |=3D (ksux >> 1) & val; /* SX =3D 0 forces UX to be 0 */ - val =3D (val & ~(7 << CP0St_UX)) | ksux; -#endif - if (has_supervisor && extract32(val, CP0St_KSU, 2) =3D=3D 0x3) { - mask &=3D ~(3 << CP0St_KSU); - } - mask &=3D ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val); - } - - env->CP0_Status =3D (old & ~mask) | (val & mask); -#if defined(TARGET_MIPS64) - if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) { - /* Access to at least one of the 64-bit segments has been disabled= */ - tlb_flush(env_cpu(env)); - } -#endif - if (ase_mt_available(env)) { - sync_c0_status(env, env, env->current_tc); - } else { - compute_hflags(env); - } -} - -void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val) -{ - uint32_t mask =3D 0x00C00300; - uint32_t old =3D env->CP0_Cause; - int i; - - if (env->insn_flags & ISA_MIPS_R2) { - mask |=3D 1 << CP0Ca_DC; - } - if (env->insn_flags & ISA_MIPS_R6) { - mask &=3D ~((1 << CP0Ca_WP) & val); - } - - env->CP0_Cause =3D (env->CP0_Cause & ~mask) | (val & mask); - - if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { - if (env->CP0_Cause & (1 << CP0Ca_DC)) { - cpu_mips_stop_count(env); - } else { - cpu_mips_start_count(env); - } - } - - /* Set/reset software interrupts */ - for (i =3D 0 ; i < 2 ; i++) { - if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) { - cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i= ))); - } - } -} - #endif /* !CONFIG_USER_ONLY */ =20 static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, @@ -977,75 +878,7 @@ hwaddr cpu_mips_translate_address(CPUMIPSState *env, t= arget_ulong address, return physical; } } -#endif /* !CONFIG_USER_ONLY */ =20 -static const char * const excp_names[EXCP_LAST + 1] =3D { - [EXCP_RESET] =3D "reset", - [EXCP_SRESET] =3D "soft reset", - [EXCP_DSS] =3D "debug single step", - [EXCP_DINT] =3D "debug interrupt", - [EXCP_NMI] =3D "non-maskable interrupt", - [EXCP_MCHECK] =3D "machine check", - [EXCP_EXT_INTERRUPT] =3D "interrupt", - [EXCP_DFWATCH] =3D "deferred watchpoint", - [EXCP_DIB] =3D "debug instruction breakpoint", - [EXCP_IWATCH] =3D "instruction fetch watchpoint", - [EXCP_AdEL] =3D "address error load", - [EXCP_AdES] =3D "address error store", - [EXCP_TLBF] =3D "TLB refill", - [EXCP_IBE] =3D "instruction bus error", - [EXCP_DBp] =3D "debug breakpoint", - [EXCP_SYSCALL] =3D "syscall", - [EXCP_BREAK] =3D "break", - [EXCP_CpU] =3D "coprocessor unusable", - [EXCP_RI] =3D "reserved instruction", - [EXCP_OVERFLOW] =3D "arithmetic overflow", - [EXCP_TRAP] =3D "trap", - [EXCP_FPE] =3D "floating point", - [EXCP_DDBS] =3D "debug data break store", - [EXCP_DWATCH] =3D "data watchpoint", - [EXCP_LTLBL] =3D "TLB modify", - [EXCP_TLBL] =3D "TLB load", - [EXCP_TLBS] =3D "TLB store", - [EXCP_DBE] =3D "data bus error", - [EXCP_DDBL] =3D "debug data break load", - [EXCP_THREAD] =3D "thread", - [EXCP_MDMX] =3D "MDMX", - [EXCP_C2E] =3D "precise coprocessor 2", - [EXCP_CACHE] =3D "cache error", - [EXCP_TLBXI] =3D "TLB execute-inhibit", - [EXCP_TLBRI] =3D "TLB read-inhibit", - [EXCP_MSADIS] =3D "MSA disabled", - [EXCP_MSAFPE] =3D "MSA floating point", -}; - -static const char *mips_exception_name(int32_t exception) -{ - if (exception < 0 || exception > EXCP_LAST) { - return "unknown"; - } - return excp_names[exception]; -} - -target_ulong exception_resume_pc(CPUMIPSState *env) -{ - target_ulong bad_pc; - target_ulong isa_mode; - - isa_mode =3D !!(env->hflags & MIPS_HFLAG_M16); - bad_pc =3D env->active_tc.PC | isa_mode; - if (env->hflags & MIPS_HFLAG_BMASK) { - /* - * If the exception was raised from a delay slot, come back to - * the jump. - */ - bad_pc -=3D (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); - } - - return bad_pc; -} - -#if !defined(CONFIG_USER_ONLY) static void set_hflags_for_handler(CPUMIPSState *env) { /* Exception handlers are entered in 32-bit mode. */ @@ -1400,24 +1233,6 @@ void mips_cpu_do_interrupt(CPUState *cs) cs->exception_index =3D EXCP_NONE; } =20 -bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) -{ - if (interrupt_request & CPU_INTERRUPT_HARD) { - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; - - if (cpu_mips_hw_interrupts_enabled(env) && - cpu_mips_hw_interrupts_pending(env)) { - /* Raise it */ - cs->exception_index =3D EXCP_EXT_INTERRUPT; - env->error_code =3D 0; - mips_cpu_do_interrupt(cs); - return true; - } - } - return false; -} - #if !defined(CONFIG_USER_ONLY) void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra) { @@ -1484,19 +1299,3 @@ void r4k_invalidate_tlb(CPUMIPSState *env, int idx, = int use_extra) } } #endif /* !CONFIG_USER_ONLY */ - -void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, - uint32_t exception, - int error_code, - uintptr_t pc) -{ - CPUState *cs =3D env_cpu(env); - - qemu_log_mask(CPU_LOG_INT, "%s: %d (%s) %d\n", - __func__, exception, mips_exception_name(exception), - error_code); - cs->exception_index =3D exception; - env->error_code =3D error_code; - - cpu_loop_exit_restore(cs, pc); -} --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 63.128.21.124 as permitted sender) client-ip=63.128.21.124; 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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id h9sm9773734wme.11.2021.01.07.14.24.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:25:00 -0800 (PST) X-MC-Unique: zulQQ45KN1G26WAerdpmOg-1 X-MC-Unique: oRiCXFNiOcSBkjsDV82Afw-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=gI14Ji2kQ24pI0kCRkP9vvsGbZB3n+f8o62PO5KS7K4=; b=UBxkT1EbcdxoPlITFdx+lRym2AQFhJ52wFD7eD1G09aanBi/U0GCiohwGrbAtf0edL pcFFeUMxowZu8dGCZmBYvZ+ZN21GHJnl9PSr2WOBDYOnzgnpLTcy7tCdtHoxcowt4CNg QFNSiomcHIL12noZApMPNWgorJGZ0O97R3bARNjAkBdmj71zSMm7AQ79AQImG9iOx1NV yd+bK2L3A0Z5AKAVEaqUxoyV2JjLgdwkyY75M3Rnwr7u6e4XsNO4XASihfj/gm/ujgcp P/CrrXzISowhunr9Wi0a1E3VtMkKPAALaalj98Hz+YYn6sthbsEpvzbT/cAjh7XULH+W 3EVg== X-Gm-Message-State: AOAM530vEA45jcx2kNp1Kw9QRlwoldioQCjA3cp6NL0Um8S0yw/ovuyb 27b120I0+7aVEPMPlKwNiIHCx/T4Or4= X-Google-Smtp-Source: ABdhPJw15tAhDZ4T7gT3ayIVkuqHqqJlWYyDvjljJaWQJpFYLDbZMgZTYcpXwM5yCxkV09NCfHPK3Q== X-Received: by 2002:adf:fd0c:: with SMTP id e12mr667290wrr.61.1610058300729; Thu, 07 Jan 2021 14:25:00 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 24/66] target/mips: Rename helper.c as tlb_helper.c Date: Thu, 7 Jan 2021 23:22:11 +0100 Message-Id: <20210107222253.20382-25-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.78 on 10.11.54.4 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable This file contains functions related to TLB management, rename it as 'tlb_helper.c'. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201206233949.3783184-13-f4bug@amsat.org> --- target/mips/{helper.c =3D> tlb_helper.c} | 2 +- target/mips/meson.build | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) rename target/mips/{helper.c =3D> tlb_helper.c} (99%) diff --git a/target/mips/helper.c b/target/mips/tlb_helper.c similarity index 99% rename from target/mips/helper.c rename to target/mips/tlb_helper.c index 68804b84b15..b02c0479e79 100644 --- a/target/mips/helper.c +++ b/target/mips/tlb_helper.c @@ -1,5 +1,5 @@ /* - * MIPS emulation helpers for qemu. + * MIPS TLB (Translation lookaside buffer) helpers. * * Copyright (c) 2004-2005 Jocelyn Mayer * diff --git a/target/mips/meson.build b/target/mips/meson.build index 4179395a8ea..5a49951c6d7 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -4,10 +4,10 @@ 'dsp_helper.c', 'fpu_helper.c', 'gdbstub.c', - 'helper.c', 'lmmi_helper.c', 'msa_helper.c', 'op_helper.c', + 'tlb_helper.c', 'translate.c', )) mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 63.128.21.124 as permitted sender) client-ip=63.128.21.124; envelope-from=libvir-list-bounces@redhat.com; helo=us-smtp-delivery-124.mimecast.com; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of redhat.com designates 63.128.21.124 as permitted sender) smtp.mailfrom=libvir-list-bounces@redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1610058323; cv=none; d=zohomail.com; s=zohoarc; b=Qmy9Rrb/5149V1yYK7aKnsN8cGERkSOJLzOZtuSuWfBDEusEzg9cT/6GILx1SDaZ4T7qMcadP1x4LU25QvIswKlmG7XeNWH9yUfag7dmewAwSb5MdiSEp1+WK3t2x2yZBLMys+T2GN1e5KW2m7BPYB615LXbjywQu3pQyCGWELY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610058323; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ZbrS3lwYRxTRTFDPc0/zNPF7RtQTn+hbYyf7KgsVbYc=; b=GGLR6XXnOfOETAyUqMVzYpO1MhjyeAlW3ROXlIG9h3uIudQfqIZFFNRvhIbt1MdKLlZRhNSG3qP1akfytqqaqsPqySaaaOJdBo9WYaIf85g6Yc8jycRkLbmxrsP2XOftfLZZkZthB8CHPzkjnm5ncjt9TpaB3xkAH5WnYus1sYY= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of redhat.com designates 63.128.21.124 as permitted sender) smtp.mailfrom=libvir-list-bounces@redhat.com Return-Path: Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [63.128.21.124]) by mx.zohomail.com with SMTPS id 1610058323931628.1268779818281; Thu, 7 Jan 2021 14:25:23 -0800 (PST) Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-190-8RP77OobOZC26nCsPTOlvQ-1; Thu, 07 Jan 2021 17:25:20 -0500 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 488028015C6; Thu, 7 Jan 2021 22:25:14 +0000 (UTC) Received: from colo-mx.corp.redhat.com (colo-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.20]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 22EAC100AE2E; Thu, 7 Jan 2021 22:25:14 +0000 (UTC) Received: from lists01.pubmisc.prod.ext.phx2.redhat.com (lists01.pubmisc.prod.ext.phx2.redhat.com [10.5.19.33]) by colo-mx.corp.redhat.com (Postfix) with ESMTP id E18821809CA2; Thu, 7 Jan 2021 22:25:13 +0000 (UTC) Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.rdu2.redhat.com [10.11.54.4]) by lists01.pubmisc.prod.ext.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id 107MPCw2029964 for ; Thu, 7 Jan 2021 17:25:12 -0500 Received: by smtp.corp.redhat.com (Postfix) id 69A162026D49; Thu, 7 Jan 2021 22:25:12 +0000 (UTC) Received: from mimecast-mx02.redhat.com (mimecast03.extmail.prod.ext.rdu2.redhat.com [10.11.55.19]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 64CB62026D46 for ; Thu, 7 Jan 2021 22:25:12 +0000 (UTC) Received: from us-smtp-1.mimecast.com (us-smtp-1.mimecast.com [205.139.110.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 50DBB811E84 for ; Thu, 7 Jan 2021 22:25:12 +0000 (UTC) Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-588-0rr2kpnpOdW3cEoJWKf9NA-1; Thu, 07 Jan 2021 17:25:07 -0500 Received: by mail-wm1-f44.google.com with SMTP id y23so6838066wmi.1; Thu, 07 Jan 2021 14:25:06 -0800 (PST) Received: from x1w.redhat.com (241.red-88-10-103.dynamicip.rima-tde.net. [88.10.103.241]) by smtp.gmail.com with ESMTPSA id m2sm9131291wml.34.2021.01.07.14.25.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:25:05 -0800 (PST) X-MC-Unique: 8RP77OobOZC26nCsPTOlvQ-1 X-MC-Unique: 0rr2kpnpOdW3cEoJWKf9NA-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=ZbrS3lwYRxTRTFDPc0/zNPF7RtQTn+hbYyf7KgsVbYc=; b=jqMOe+Tu10qVWHb+XZp5ZvrvBO+BX+k/DAbIx3+1UU8wPmplcnvx/AesZtyL4Yrlng Pq4ClMs1WvC8RTJBhxYN7uo9g/ziG7uV5cZ47mVVKVUzWgsBo7NqLwk7JGuxD5UW0ncw hmG+uBr2U5KhxwTU+IAk9Um3ipIEacW56Vrl4AfHt/AV7OaYTy1nMmMNVF/TrFOcY522 btqfgPFOKuLLwwclgDujyRZRFvgXQMuUmhxRqgE877VDuf8rPStyPy59OCvuKN5t7SQr y7YJHqw6uYPwKtEytmFBdynwU/Qe/kM5VcLca0Io+87GDT0rlHv9X0LzAQehLB5T+wLZ HkIA== X-Gm-Message-State: AOAM532id+ELy+grnONbQHFSWUL8SsLVB8nF2deDIFBP9pSb6M/JnymV vvVyJj3hu49h2BgQopAkiqc= X-Google-Smtp-Source: ABdhPJzbX3i0+o+WsTnVEJ4EExrsavAWV4+8h19zG+o5Hahro23lxmuhWyBBgQorIBRxeCpsbjMgAQ== X-Received: by 2002:a7b:c406:: with SMTP id k6mr520768wmi.90.1610058305846; Thu, 07 Jan 2021 14:25:05 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 25/66] target/mips: Fix code style for checkpatch.pl Date: Thu, 7 Jan 2021 23:22:12 +0100 Message-Id: <20210107222253.20382-26-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.78 on 10.11.54.4 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable We are going to move this code, fix its style first. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201206233949.3783184-14-f4bug@amsat.org> --- target/mips/translate_init.c.inc | 36 ++++++++++++++++---------------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.= c.inc index 044052fb77c..21ee22c05dc 100644 --- a/target/mips/translate_init.c.inc +++ b/target/mips/translate_init.c.inc @@ -936,19 +936,19 @@ void mips_cpu_list(void) } =20 #ifndef CONFIG_USER_ONLY -static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def) +static void no_mmu_init(CPUMIPSState *env, const mips_def_t *def) { env->tlb->nb_tlb =3D 1; env->tlb->map_address =3D &no_mmu_map_address; } =20 -static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def) +static void fixed_mmu_init(CPUMIPSState *env, const mips_def_t *def) { env->tlb->nb_tlb =3D 1; env->tlb->map_address =3D &fixed_mmu_map_address; } =20 -static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def) +static void r4k_mmu_init(CPUMIPSState *env, const mips_def_t *def) { env->tlb->nb_tlb =3D 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); env->tlb->map_address =3D &r4k_map_address; @@ -960,25 +960,25 @@ static void r4k_mmu_init (CPUMIPSState *env, const mi= ps_def_t *def) env->tlb->helper_tlbinvf =3D r4k_helper_tlbinvf; } =20 -static void mmu_init (CPUMIPSState *env, const mips_def_t *def) +static void mmu_init(CPUMIPSState *env, const mips_def_t *def) { env->tlb =3D g_malloc0(sizeof(CPUMIPSTLBContext)); =20 switch (def->mmu_type) { - case MMU_TYPE_NONE: - no_mmu_init(env, def); - break; - case MMU_TYPE_R4000: - r4k_mmu_init(env, def); - break; - case MMU_TYPE_FMT: - fixed_mmu_init(env, def); - break; - case MMU_TYPE_R3000: - case MMU_TYPE_R6000: - case MMU_TYPE_R8000: - default: - cpu_abort(env_cpu(env), "MMU type not supported\n"); + case MMU_TYPE_NONE: + no_mmu_init(env, def); + break; + case MMU_TYPE_R4000: + r4k_mmu_init(env, def); + break; + case MMU_TYPE_FMT: + fixed_mmu_init(env, def); + break; + case MMU_TYPE_R3000: + case MMU_TYPE_R6000: + case MMU_TYPE_R8000: + default: + cpu_abort(env_cpu(env), "MMU type not supported\n"); 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Thu, 07 Jan 2021 14:25:11 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 26/66] target/mips: Move mmu_init() functions to tlb_helper.c Date: Thu, 7 Jan 2021 23:22:13 +0100 Message-Id: <20210107222253.20382-27-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.79 on 10.11.54.5 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201206233949.3783184-15-f4bug@amsat.org> --- target/mips/internal.h | 1 + target/mips/tlb_helper.c | 46 ++++++++++++++++++++++++++++++ target/mips/translate_init.c.inc | 48 -------------------------------- 3 files changed, 47 insertions(+), 48 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index ae1181d2029..9a7698019e2 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -207,6 +207,7 @@ void cpu_mips_start_count(CPUMIPSState *env); void cpu_mips_stop_count(CPUMIPSState *env); =20 /* helper.c */ +void mmu_init(CPUMIPSState *env, const mips_def_t *def); bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c index b02c0479e79..082c17928d3 100644 --- a/target/mips/tlb_helper.c +++ b/target/mips/tlb_helper.c @@ -120,6 +120,52 @@ int r4k_map_address(CPUMIPSState *env, hwaddr *physica= l, int *prot, return TLBRET_NOMATCH; } =20 +static void no_mmu_init(CPUMIPSState *env, const mips_def_t *def) +{ + env->tlb->nb_tlb =3D 1; + env->tlb->map_address =3D &no_mmu_map_address; +} + +static void fixed_mmu_init(CPUMIPSState *env, const mips_def_t *def) +{ + env->tlb->nb_tlb =3D 1; + env->tlb->map_address =3D &fixed_mmu_map_address; +} + +static void r4k_mmu_init(CPUMIPSState *env, const mips_def_t *def) +{ + env->tlb->nb_tlb =3D 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); + env->tlb->map_address =3D &r4k_map_address; + env->tlb->helper_tlbwi =3D r4k_helper_tlbwi; + env->tlb->helper_tlbwr =3D r4k_helper_tlbwr; + env->tlb->helper_tlbp =3D r4k_helper_tlbp; + env->tlb->helper_tlbr =3D r4k_helper_tlbr; + env->tlb->helper_tlbinv =3D r4k_helper_tlbinv; + env->tlb->helper_tlbinvf =3D r4k_helper_tlbinvf; +} + +void mmu_init(CPUMIPSState *env, const mips_def_t *def) +{ + env->tlb =3D g_malloc0(sizeof(CPUMIPSTLBContext)); + + switch (def->mmu_type) { + case MMU_TYPE_NONE: + no_mmu_init(env, def); + break; + case MMU_TYPE_R4000: + r4k_mmu_init(env, def); + break; + case MMU_TYPE_FMT: + fixed_mmu_init(env, def); + break; + case MMU_TYPE_R3000: + case MMU_TYPE_R6000: + case MMU_TYPE_R8000: + default: + cpu_abort(env_cpu(env), "MMU type not supported\n"); + } +} + static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx) { /* diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.= c.inc index 21ee22c05dc..535d4c0c702 100644 --- a/target/mips/translate_init.c.inc +++ b/target/mips/translate_init.c.inc @@ -935,54 +935,6 @@ void mips_cpu_list(void) } } =20 -#ifndef CONFIG_USER_ONLY -static void no_mmu_init(CPUMIPSState *env, const mips_def_t *def) -{ - env->tlb->nb_tlb =3D 1; - env->tlb->map_address =3D &no_mmu_map_address; -} - -static void fixed_mmu_init(CPUMIPSState *env, const mips_def_t *def) -{ - env->tlb->nb_tlb =3D 1; - env->tlb->map_address =3D &fixed_mmu_map_address; -} - -static void r4k_mmu_init(CPUMIPSState *env, const mips_def_t *def) -{ - env->tlb->nb_tlb =3D 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); - env->tlb->map_address =3D &r4k_map_address; - env->tlb->helper_tlbwi =3D r4k_helper_tlbwi; - env->tlb->helper_tlbwr =3D r4k_helper_tlbwr; - env->tlb->helper_tlbp =3D r4k_helper_tlbp; - env->tlb->helper_tlbr =3D r4k_helper_tlbr; - env->tlb->helper_tlbinv =3D r4k_helper_tlbinv; - env->tlb->helper_tlbinvf =3D r4k_helper_tlbinvf; -} - -static void mmu_init(CPUMIPSState *env, const mips_def_t *def) -{ - env->tlb =3D g_malloc0(sizeof(CPUMIPSTLBContext)); - - switch (def->mmu_type) { - case MMU_TYPE_NONE: - no_mmu_init(env, def); - break; - case MMU_TYPE_R4000: - r4k_mmu_init(env, def); - break; - case MMU_TYPE_FMT: - fixed_mmu_init(env, def); - break; - case MMU_TYPE_R3000: - case MMU_TYPE_R6000: - case MMU_TYPE_R8000: - default: - cpu_abort(env_cpu(env), "MMU type not supported\n"); - } -} -#endif /* CONFIG_USER_ONLY */ - static void fpu_init (CPUMIPSState *env, const mips_def_t *def) { int i; --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 63.128.21.124 as permitted sender) client-ip=63.128.21.124; envelope-from=libvir-list-bounces@redhat.com; helo=us-smtp-delivery-124.mimecast.com; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of redhat.com designates 63.128.21.124 as permitted sender) smtp.mailfrom=libvir-list-bounces@redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1610058334; cv=none; d=zohomail.com; s=zohoarc; b=RA55sS3WC73uJr9h4npz1kybYQJt3iJ8P6zdw0NqceQojy8d35uS1YbtR8TWFx2ZqBNiQJwrzeste3/JjBqBq7W8E80BEW9+KtJ1NgbBkyGGOwXWh6CSQP3gO2Aol/EKS4uTmZJRJmZRCI9fEcJwnsw5E+7LgSnWwrIpuJe0f3M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610058334; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id s3sm8998055wmc.44.2021.01.07.14.25.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:25:15 -0800 (PST) X-MC-Unique: iIq9c9IxMwuee3NUIG7y9Q-1 X-MC-Unique: EKJuEC-TMmqoMU8Tz1DEAQ-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=QyeTQF7UvXhfCkJ2JeL3ZW1k3uAkuDX0bwVNyPuFC3M=; b=ZoT7XH4bldId9aCHttm9IAPTAVZ1e3Vmdm7EUIQW2vjg/st9OXGS+iAzNhbjwzXOys St+Hjr3e7hy5BedlAk9A0w8jmbz9Amc/UCailT7z1lz1Cltz4FNR5D306wr4IWfLNOmi DoPPpagcABK9fQ54lkMQfCpAm1sDRhjoQCVNfNRbehJFSflotLBQOrH8UA56j+3gazlA Gv/ddKcDm2CXSBhthXsc7/VlVbLJQsNurAIOkMLH3D1HVlTrHujCDauy60TApN+g6YnP Ey7KLedGtT/vzAINbBZcE7lDCkdEWuCSa4n9qpnKgKpWaZ3FoDD5g578/MjqX6j1iiOS tqKg== X-Gm-Message-State: AOAM532+cm2WwpZwRQ+IMwDQkFX5xFSbod+yyLTu59CEJM0rYy3+cOEz w9ezST1BlstiLZRUDMkXirc= X-Google-Smtp-Source: ABdhPJyH6h8WC+O5aY6j+igrFTma98XjZTCEhgTN14u1Bv21LP2Kk6nJIKKMpVHv549JiPNNjfbaMQ== X-Received: by 2002:a05:6000:90:: with SMTP id m16mr668214wrx.165.1610058316126; Thu, 07 Jan 2021 14:25:16 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 27/66] target/mips: Rename translate_init.c as cpu-defs.c Date: Thu, 7 Jan 2021 23:22:14 +0100 Message-Id: <20210107222253.20382-28-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.78 on 10.11.54.4 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable This file is not TCG specific, contains CPU definitions and is consumed by cpu.c. Rename it as such. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201214183739.500368-10-f4bug@amsat.org> --- target/mips/cpu.c | 2 +- target/mips/{translate_init.c.inc =3D> cpu-defs.c.inc} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename target/mips/{translate_init.c.inc =3D> cpu-defs.c.inc} (100%) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 26b4c3e9cd5..55c6a054bba 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -311,7 +311,7 @@ static bool mips_cpu_has_work(CPUState *cs) return has_work; } =20 -#include "translate_init.c.inc" +#include "cpu-defs.c.inc" =20 static void mips_cpu_reset(DeviceState *dev) { diff --git a/target/mips/translate_init.c.inc b/target/mips/cpu-defs.c.inc similarity index 100% rename from target/mips/translate_init.c.inc rename to target/mips/cpu-defs.c.inc --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) client-ip=216.205.24.124; envelope-from=libvir-list-bounces@redhat.com; helo=us-smtp-delivery-124.mimecast.com; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) smtp.mailfrom=libvir-list-bounces@redhat.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1610058339; cv=none; d=zohomail.com; s=zohoarc; b=Hvw8kEVdTclVutuWPyqxKiUZBzbW+LMcK8PTriPjhjW6O59+cXPInc4bT0lE6vo3Y+n/9NQzxE8UKcS8/BCBDaAI0IydM9Tp08aa1gBXxZzqkG0vcLfycAQXQDuHd1garq6XLsEFVn4TfI5pPuh25XSrjtjh9vCBfxwaB/0vrhI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610058339; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=2UuX+ygCL9NQhxyYPo8S/tX8V99CFSpKYjvju/1WTRw=; b=BRxfObOJArPppsQhj1bxQi9LEgtzOEXL9Pu3EppkMhG2zelk9lUBhpxJDyTgHvrItDzVAbTG6ZXkX+ETpUSl4q9WEmKXqIlW0YjBczh1iyc0YMeqQyzcl0AncWQD95it23RMcycHnn7mwW4uMMPKTdGxPYHxJxIVEYNUul7Nw2s= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) smtp.mailfrom=libvir-list-bounces@redhat.com; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [216.205.24.124]) by mx.zohomail.com with SMTPS id 1610058339473277.51964342848487; Thu, 7 Jan 2021 14:25:39 -0800 (PST) Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-567-0g78oL7pMYiWo0Bqk49L7A-1; Thu, 07 Jan 2021 17:25:35 -0500 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id AFB25801FDA; Thu, 7 Jan 2021 22:25:28 +0000 (UTC) Received: from colo-mx.corp.redhat.com (colo-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.20]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 8C1955B4BD; Thu, 7 Jan 2021 22:25:28 +0000 (UTC) Received: from lists01.pubmisc.prod.ext.phx2.redhat.com (lists01.pubmisc.prod.ext.phx2.redhat.com [10.5.19.33]) by colo-mx.corp.redhat.com (Postfix) with ESMTP id 56B601809CAC; Thu, 7 Jan 2021 22:25:28 +0000 (UTC) Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.rdu2.redhat.com [10.11.54.5]) by lists01.pubmisc.prod.ext.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id 107MPRMA030150 for ; Thu, 7 Jan 2021 17:25:27 -0500 Received: by smtp.corp.redhat.com (Postfix) id 2AE8BD7B10; Thu, 7 Jan 2021 22:25:27 +0000 (UTC) Received: from mimecast-mx02.redhat.com (mimecast06.extmail.prod.ext.rdu2.redhat.com [10.11.55.22]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 25B0AD7B0E for ; Thu, 7 Jan 2021 22:25:27 +0000 (UTC) Received: from us-smtp-1.mimecast.com (us-smtp-2.mimecast.com [207.211.31.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 12918185A794 for ; Thu, 7 Jan 2021 22:25:27 +0000 (UTC) Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-183-Y_I3yj80NKWy9nrEKZgqjg-1; Thu, 07 Jan 2021 17:25:22 -0500 Received: by mail-wr1-f45.google.com with SMTP id t16so7144329wra.3; Thu, 07 Jan 2021 14:25:22 -0800 (PST) Received: from x1w.redhat.com (241.red-88-10-103.dynamicip.rima-tde.net. [88.10.103.241]) by smtp.gmail.com with ESMTPSA id c7sm11513721wro.16.2021.01.07.14.25.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:25:20 -0800 (PST) X-MC-Unique: 0g78oL7pMYiWo0Bqk49L7A-1 X-MC-Unique: Y_I3yj80NKWy9nrEKZgqjg-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=2UuX+ygCL9NQhxyYPo8S/tX8V99CFSpKYjvju/1WTRw=; b=rEtL/M2NZ9cUgUSBZQ3O/0b5yknDNaFzQ9JT/afHsicEtP9yZoQfRrkhVJjkSc1MX2 FSTGRJxuTc/cWV5VGZ0biORX0wavhFhaiurY/gTosDQEKdIZKD5HGNKgIXNxcUBPadvS A7gUWkiL+G46tdVjvzydwguyebuz4yX5sTOy98aVtx7vfxPPZ3Vd9epyS+XDZoCfl5Oh lbheakIjZiftK+Cz3+BSvymimiDqkx+jST1d5HiM10t9mDI+JR6r4/oMUjn/X9inp8mm eVS1knpC6vpa4xiOt9F9eX15bsJGWZrPZuINjlS+N+MWyy6OBhKlwQ+EG6OvboAE04yy JoMA== X-Gm-Message-State: AOAM530al8HSxQofoeku0YgIyglGt+SnXt1sZ/3sAdSn4LUizNmu6D3Z pzeCfGQ08CzMhEOV6/qyk9Q= X-Google-Smtp-Source: ABdhPJzMyJdqE/eO0phoPlTa/qBVpXHkKqr9ihmwxJoBQBQQQe/goVibMYsBjjZd/5mLbkiF7PY3xg== X-Received: by 2002:adf:f891:: with SMTP id u17mr662412wrp.253.1610058321171; Thu, 07 Jan 2021 14:25:21 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 28/66] target/mips/translate: Extract DisasContext structure Date: Thu, 7 Jan 2021 23:22:15 +0100 Message-Id: <20210107222253.20382-29-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.79 on 10.11.54.5 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Extract DisasContext to a new 'translate.h' header so different translation files (ISA, ASE, extensions) can use it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201207235539.4070364-2-f4bug@amsat.org> --- target/mips/translate.h | 50 +++++++++++++++++++++++++++++++++++++++++ target/mips/translate.c | 38 +------------------------------ 2 files changed, 51 insertions(+), 37 deletions(-) create mode 100644 target/mips/translate.h diff --git a/target/mips/translate.h b/target/mips/translate.h new file mode 100644 index 00000000000..fcda1a99001 --- /dev/null +++ b/target/mips/translate.h @@ -0,0 +1,50 @@ +/* + * MIPS translation routines. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ +#ifndef TARGET_MIPS_TRANSLATE_H +#define TARGET_MIPS_TRANSLATE_H + +#include "exec/translator.h" + +typedef struct DisasContext { + DisasContextBase base; + target_ulong saved_pc; + target_ulong page_start; + uint32_t opcode; + uint64_t insn_flags; + int32_t CP0_Config1; + int32_t CP0_Config2; + int32_t CP0_Config3; + int32_t CP0_Config5; + /* Routine used to access memory */ + int mem_idx; + MemOp default_tcg_memop_mask; + uint32_t hflags, saved_hflags; + target_ulong btarget; + bool ulri; + int kscrexist; + bool rxi; + int ie; + bool bi; + bool bp; + uint64_t PAMask; + bool mvh; + bool eva; + bool sc; + int CP0_LLAddr_shift; + bool ps; + bool vp; + bool cmgcr; + bool mrp; + bool nan2008; + bool abs2008; + bool saar; + bool mi; + int gi; +} DisasContext; + +#endif diff --git a/target/mips/translate.c b/target/mips/translate.c index f8f0f95509c..9e824e12d44 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -36,6 +36,7 @@ #include "exec/log.h" #include "qemu/qemu-print.h" #include "fpu_helper.h" +#include "translate.h" =20 #define MIPS_DEBUG_DISAS 0 =20 @@ -2554,43 +2555,6 @@ static TCGv mxu_CR; tcg_temp_free_i32(helper_tmp); \ } while (0) =20 -typedef struct DisasContext { - DisasContextBase base; - target_ulong saved_pc; - target_ulong page_start; - uint32_t opcode; - uint64_t insn_flags; - int32_t CP0_Config1; - int32_t CP0_Config2; - int32_t CP0_Config3; - int32_t CP0_Config5; - /* Routine used to access memory */ - int mem_idx; - MemOp default_tcg_memop_mask; - uint32_t hflags, saved_hflags; - target_ulong btarget; - bool ulri; - int kscrexist; - bool rxi; - int ie; - bool bi; - bool bp; - uint64_t PAMask; - bool mvh; - bool eva; - bool sc; - int CP0_LLAddr_shift; - bool ps; - bool vp; - bool cmgcr; - bool mrp; - bool nan2008; - bool abs2008; - bool saar; - bool mi; - int gi; -} DisasContext; - #define DISAS_STOP DISAS_TARGET_0 #define DISAS_EXIT DISAS_TARGET_1 =20 --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) client-ip=216.205.24.124; envelope-from=libvir-list-bounces@redhat.com; helo=us-smtp-delivery-124.mimecast.com; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) smtp.mailfrom=libvir-list-bounces@redhat.com; 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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id w21sm9110700wmi.45.2021.01.07.14.25.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:25:25 -0800 (PST) X-MC-Unique: FHEBk4hgMk6CKfmGwHF8NA-1 X-MC-Unique: ZjgmIABBPVWr58q3MaG7AQ-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Md8yMDtPFL047sc9GnACrU93Gm/4UH0JKJe4iaxMljk=; b=EGWJtgA8gEjVlg/a9y8oKoXqTsbBRMnfNH/svaV8YugysrnnuW/7sfNbDJSUyAMcny Q7qSp8cQs/1430Efa/fd9z8XhnvgysQTvnYT3ys90vT6qhxc/Ln+RZj0gMwrs7oZxyl+ 2dIvoZSo19Sj0NO9Xdn4vgcRAlhmR765AyDnpyHbXmg1mO3AF1rRT9EUKs+zMN2Vu8s7 YY+WSoucJafuyZU9tN6N1WL49VYrH/AcI9lPN0jr9xjs8OOG+Pg4FJJg/7EqW8F7DIq4 QMqRSCGTWWtrMDykr17SFAP1+yh4Z4/heb5RSzCow5k0+SWgUmPXAEDRZv2fG4ND5wAy 42NA== X-Gm-Message-State: AOAM532i6qkxogECOSrn/DyA9tktCSnxlOYQnCmERH5Qzjqyf/SvmWmv TY5gijNG2RA1Gh7BrLGIEL3AmpLwa7o= X-Google-Smtp-Source: ABdhPJx/wlXEytr69sTyc89ncUwNXATKyBRfUcaBAbtdnUC6Nhbkylim6JvAaQ2HSmkJNXRQw6PVOQ== X-Received: by 2002:a7b:c7d3:: with SMTP id z19mr521782wmk.31.1610058326194; Thu, 07 Jan 2021 14:25:26 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 29/66] target/mips/translate: Add declarations for generic code Date: Thu, 7 Jan 2021 23:22:16 +0100 Message-Id: <20210107222253.20382-30-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.79 on 10.11.54.5 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Some CPU translation functions / registers / macros and definitions can be used by ISA / ASE / extensions out of the big translate.c file. Declare them in "translate.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201207235539.4070364-3-f4bug@amsat.org> --- target/mips/translate.h | 38 ++++++++++++++++++++++++++++++++++ target/mips/translate.c | 45 ++++++++++------------------------------- 2 files changed, 49 insertions(+), 34 deletions(-) diff --git a/target/mips/translate.h b/target/mips/translate.h index fcda1a99001..d9d4d3943af 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -10,6 +10,8 @@ =20 #include "exec/translator.h" =20 +#define MIPS_DEBUG_DISAS 0 + typedef struct DisasContext { DisasContextBase base; target_ulong saved_pc; @@ -47,4 +49,40 @@ typedef struct DisasContext { int gi; } DisasContext; =20 +/* MIPS major opcodes */ +#define MASK_OP_MAJOR(op) (op & (0x3F << 26)) + +void generate_exception(DisasContext *ctx, int excp); +void generate_exception_err(DisasContext *ctx, int excp, int err); +void generate_exception_end(DisasContext *ctx, int excp); +void check_insn(DisasContext *ctx, uint64_t flags); +#ifdef TARGET_MIPS64 +void check_mips_64(DisasContext *ctx); +#endif + +void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offs= et); +void gen_load_gpr(TCGv t, int reg); +void gen_store_gpr(TCGv t, int reg); + +extern TCGv cpu_gpr[32], cpu_PC; +extern TCGv bcond; + +#define LOG_DISAS(...) = \ + do { = \ + if (MIPS_DEBUG_DISAS) { = \ + qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__); = \ + } = \ + } while (0) + +#define MIPS_INVAL(op) = \ + do { = \ + if (MIPS_DEBUG_DISAS) { = \ + qemu_log_mask(CPU_LOG_TB_IN_ASM, = \ + TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\= n", \ + ctx->base.pc_next, ctx->opcode, op, = \ + ctx->opcode >> 26, ctx->opcode & 0x3F, = \ + ((ctx->opcode >> 16) & 0x1F)); = \ + } = \ + } while (0) + #endif diff --git a/target/mips/translate.c b/target/mips/translate.c index 9e824e12d44..5889d24eb65 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -38,11 +38,6 @@ #include "fpu_helper.h" #include "translate.h" =20 -#define MIPS_DEBUG_DISAS 0 - -/* MIPS major opcodes */ -#define MASK_OP_MAJOR(op) (op & (0x3F << 26)) - enum { /* indirect opcode tables */ OPC_SPECIAL =3D (0x00 << 26), @@ -2491,9 +2486,10 @@ enum { }; =20 /* global register indices */ -static TCGv cpu_gpr[32], cpu_PC; +TCGv cpu_gpr[32], cpu_PC; static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; -static TCGv cpu_dspctrl, btarget, bcond; +static TCGv cpu_dspctrl, btarget; +TCGv bcond; static TCGv cpu_lladdr, cpu_llval; static TCGv_i32 hflags; static TCGv_i32 fpu_fcr0, fpu_fcr31; @@ -2606,26 +2602,8 @@ static const char * const mxuregnames[] =3D { }; #endif =20 -#define LOG_DISAS(...) = \ - do { = \ - if (MIPS_DEBUG_DISAS) { = \ - qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__); = \ - } = \ - } while (0) - -#define MIPS_INVAL(op) = \ - do { = \ - if (MIPS_DEBUG_DISAS) { = \ - qemu_log_mask(CPU_LOG_TB_IN_ASM, = \ - TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\= n", \ - ctx->base.pc_next, ctx->opcode, op, = \ - ctx->opcode >> 26, ctx->opcode & 0x3F, = \ - ((ctx->opcode >> 16) & 0x1F)); = \ - } = \ - } while (0) - /* General purpose registers moves. */ -static inline void gen_load_gpr(TCGv t, int reg) +void gen_load_gpr(TCGv t, int reg) { if (reg =3D=3D 0) { tcg_gen_movi_tl(t, 0); @@ -2634,7 +2612,7 @@ static inline void gen_load_gpr(TCGv t, int reg) } } =20 -static inline void gen_store_gpr(TCGv t, int reg) +void gen_store_gpr(TCGv t, int reg) { if (reg !=3D 0) { tcg_gen_mov_tl(cpu_gpr[reg], t); @@ -2763,7 +2741,7 @@ static inline void restore_cpu_state(CPUMIPSState *en= v, DisasContext *ctx) } } =20 -static inline void generate_exception_err(DisasContext *ctx, int excp, int= err) +void generate_exception_err(DisasContext *ctx, int excp, int err) { TCGv_i32 texcp =3D tcg_const_i32(excp); TCGv_i32 terr =3D tcg_const_i32(err); @@ -2774,12 +2752,12 @@ static inline void generate_exception_err(DisasCont= ext *ctx, int excp, int err) ctx->base.is_jmp =3D DISAS_NORETURN; } =20 -static inline void generate_exception(DisasContext *ctx, int excp) +void generate_exception(DisasContext *ctx, int excp) { gen_helper_0e0i(raise_exception, excp); } =20 -static inline void generate_exception_end(DisasContext *ctx, int excp) +void generate_exception_end(DisasContext *ctx, int excp) { generate_exception_err(ctx, excp, 0); } @@ -3013,7 +2991,7 @@ static inline void check_dsp_r3(DisasContext *ctx) * This code generates a "reserved instruction" exception if the * CPU does not support the instruction set corresponding to flags. */ -static inline void check_insn(DisasContext *ctx, uint64_t flags) +void check_insn(DisasContext *ctx, uint64_t flags) { if (unlikely(!(ctx->insn_flags & flags))) { generate_exception_end(ctx, EXCP_RI); @@ -3064,7 +3042,7 @@ static inline void check_ps(DisasContext *ctx) * This code generates a "reserved instruction" exception if 64-bit * instructions are not enabled. */ -static inline void check_mips_64(DisasContext *ctx) +void check_mips_64(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) { generate_exception_end(ctx, EXCP_RI); @@ -3390,8 +3368,7 @@ OP_LD_ATOMIC(lld, ld64); #endif #undef OP_LD_ATOMIC =20 -static void gen_base_offset_addr(DisasContext *ctx, TCGv addr, - int base, int offset) +void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offs= et) { if (base =3D=3D 0) { tcg_gen_movi_tl(addr, offset); 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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id k18sm12295867wrd.45.2021.01.07.14.25.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:25:30 -0800 (PST) X-MC-Unique: ICuStUP3MPC21a2L6g2Htg-1 X-MC-Unique: ru5ZxJJ4OsiuD5QcQyBsNg-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=TMeZXBPfIw0UjpZf8Gz8v4KrcSgueeNPugH/0sy+Pio=; b=aE46Jke0YkuKC567cXfjgq18yzeE28K9/tFKl+NP7v1+BlzcOmcY4HBc+FLm4PrOpR o94ATD70LHey7rk1JRN6y7LdJpUhavNOB/59F2pjt5GvTI/vjuip83TdPIZWhnMchf00 GdeIeeVZAj9wNEDwcIKIbwyd2KrAIERH4cyS6k7Y7zbLpxkIFVI8/88BZ//cOjcimMh0 OrDr+2LM7jcq7Mluwh7zR4DuyxDSx5qNSXww0x2Km58BKJ0EuYyS/SRRjA/FNt9B9Eft m8v9Idt0Gx6vKhHA5Oy/A10SelkLkJKYcrrg06ZBl71gagS98jUhiSaf9QV7S6cSI/MV ZwVA== X-Gm-Message-State: AOAM532vyoiDiUq7zh/I7eikdoSIlVSEFdloshygtTqMQJOOmUhRFS7N QV77XKwM4WgU+lOOWQ2Ew6U= X-Google-Smtp-Source: ABdhPJyQheiVWednPyzYmSRVjnmfiD7VWxSYgMeazBYkbky7oQAAQ3mn/UgeIi/xUbmp1CUcnp2SVQ== X-Received: by 2002:adf:fbd2:: with SMTP id d18mr703316wrs.222.1610058331183; Thu, 07 Jan 2021 14:25:31 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 30/66] target/mips: Replace gen_exception_err(err=0) by gen_exception_end() Date: Thu, 7 Jan 2021 23:22:17 +0100 Message-Id: <20210107222253.20382-31-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.78 on 10.11.54.4 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable generate_exception_err(err=3D0) is simply generate_exception_end(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201214183739.500368-11-f4bug@amsat.org> --- target/mips/translate.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 5889d24eb65..445858591a4 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2898,7 +2898,7 @@ static inline void gen_move_high32(TCGv ret, TCGv_i64= arg) static inline void check_cp0_enabled(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) { - generate_exception_err(ctx, EXCP_CpU, 0); + generate_exception_end(ctx, EXCP_CpU); } } =20 @@ -3104,10 +3104,10 @@ static inline void check_mt(DisasContext *ctx) static inline void check_cp0_mt(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) { - generate_exception_err(ctx, EXCP_CpU, 0); + generate_exception_end(ctx, EXCP_CpU); } else { if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) { - generate_exception_err(ctx, EXCP_RI, 0); + generate_exception_end(ctx, EXCP_RI); } } } --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) client-ip=209.85.221.44; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f44.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1610058339; cv=none; d=zohomail.com; s=zohoarc; b=lTzCeKAtp1pGRMCsXso4mDc/S71MxMHxDgG0QkwozbJdIC1+dzDHnZR5Wr2YbYW/NKCQ0KAe1Bv1EXxmNUulPFYL3DN3JeCQQNH7fTUy9bjuK3bKZF1GyUAeiPOLrii4ZaCuszbRrznZzSGvTL58cSFZjWF0hTxfzOSjPLKVZsg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610058339; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=iP/yQoC1cC5h4WW93lkmoKE9d3fh72SY6xP1uvGMMus=; b=HWnW1qsh0eLTcxjASCOwoS6Xm9eetQfu5JSUOIOIbYtkKwuYE6b+7BLDwqT1YgZcKvV67bLhAAsk8Wwe22cYdRTqWJEBMcQs9Iq0NdjMChHbKbazP0Hvl+a3YoOEVzyn+exih0raoUZiK6WkGzOsn+nrGKqWXkM9rQmkrhrjX7s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) by mx.zohomail.com with SMTPS id 1610058339898678.0233267288563; Thu, 7 Jan 2021 14:25:39 -0800 (PST) Received: by mail-wr1-f44.google.com with SMTP id c5so7107918wrp.6 for ; Thu, 07 Jan 2021 14:25:38 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (241.red-88-10-103.dynamicip.rima-tde.net. [88.10.103.241]) by smtp.gmail.com with ESMTPSA id k10sm9756189wrq.38.2021.01.07.14.25.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:25:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iP/yQoC1cC5h4WW93lkmoKE9d3fh72SY6xP1uvGMMus=; b=utJOYDZg6XKw+KkqbJ763aS2EPNB2GOad/LxuEkpTp4tSSY6dq2wwJ2YkgrmTUS6S3 OjORntCMJ1lDIph9xEtaLjb1Z+skrj826mEnsMDIhgd0Vrb8DWz3WxMDFCpDcZtC8UDm vfu8i9mfdW4lByFb3GYfOXAB6OkDznpztDCyoXo98vc0S+QP2oUW6EKZP9NHGA9dBG2m hJovz6BzVUhYvow44TukNNB3wghNV9E8MKux5UnrIe9i2b8DHIytocqMvTAz1UBJg+jz 36vuvNUTp1tYWpS1t3fRhoSXduNBelGri88FtbGpzxDSsOLqAz0HH/U52GZ8R1aJ4tYW k3RA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=iP/yQoC1cC5h4WW93lkmoKE9d3fh72SY6xP1uvGMMus=; b=f4uxceFxDn4gYL4HbikFHCK8iPHQHQqPw8GB4Jny/PVGKCtJS/JweGM6Mbt95XPUzR 1lygVKpenldL6sO7VKfD1QXhpDHB6umeokH3g5A78selW69IRcVFnQikprgCfpfCnDpC I05pHBa6R1YsYXbSx3AFvuS24v32eEQhs+RFz9afWkq6y3Ex27S3cemij5K3TPKvnrlP TY9QURJVT2bIH5AVsHeNAyqeuPz4laOkVnX9Cmz87QP7ghmkSj7d4RZhMDGc94HGrF/p iGpGv2K2ZGDJaaZHHao6tSZLToK9RI9MfzXxgH+bVbAYlQlnRDG1VKyea/bae1dO1TNL uxwQ== X-Gm-Message-State: AOAM532mY9gc3FM3dQo831kbdHVnpOOolVQCM2jIKWD8CQZ+Rf92bATq QG4uvJ6UIQwG0iEx8JdjbBc= X-Google-Smtp-Source: ABdhPJxkKq6yQzdrlG9eIC2WHLlijAmyslqLgl9VgulSHcaQSnlx0gmORs1FIjup5Px30rhElcVcJg== X-Received: by 2002:adf:a543:: with SMTP id j3mr635715wrb.175.1610058336798; Thu, 07 Jan 2021 14:25:36 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: libvir-list@redhat.com, Paolo Bonzini , Laurent Vivier , kvm@vger.kernel.org, Jiaxun Yang , Aurelien Jarno , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Paul Burton , Richard Henderson Subject: [PULL 31/66] target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instruction Date: Thu, 7 Jan 2021 23:22:18 +0100 Message-Id: <20210107222253.20382-32-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) gen_reserved_instruction() is easier to read than generate_exception_end(ctx, EXCP_RI), replace it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201214183739.500368-12-f4bug@amsat.org> --- target/mips/translate.h | 1 + target/mips/translate.c | 729 ++++++++++++++++++++-------------------- 2 files changed, 368 insertions(+), 362 deletions(-) diff --git a/target/mips/translate.h b/target/mips/translate.h index d9d4d3943af..5f744c63374 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -55,6 +55,7 @@ typedef struct DisasContext { void generate_exception(DisasContext *ctx, int excp); void generate_exception_err(DisasContext *ctx, int excp, int err); void generate_exception_end(DisasContext *ctx, int excp); +void gen_reserved_instruction(DisasContext *ctx); void check_insn(DisasContext *ctx, uint64_t flags); #ifdef TARGET_MIPS64 void check_mips_64(DisasContext *ctx); diff --git a/target/mips/translate.c b/target/mips/translate.c index 445858591a4..7c20ed33df7 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2762,6 +2762,11 @@ void generate_exception_end(DisasContext *ctx, int e= xcp) generate_exception_err(ctx, excp, 0); } =20 +void gen_reserved_instruction(DisasContext *ctx) +{ + generate_exception_end(ctx, EXCP_RI); +} + /* Floating point register moves. */ static void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg) { @@ -2917,7 +2922,7 @@ static inline void check_cp1_enabled(DisasContext *ct= x) static inline void check_cop1x(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } =20 @@ -2928,7 +2933,7 @@ static inline void check_cop1x(DisasContext *ctx) static inline void check_cp1_64bitmode(DisasContext *ctx) { if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } =20 @@ -2946,7 +2951,7 @@ static inline void check_cp1_64bitmode(DisasContext *= ctx) static inline void check_cp1_registers(DisasContext *ctx, int regs) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } =20 @@ -2960,7 +2965,7 @@ static inline void check_dsp(DisasContext *ctx) if (ctx->insn_flags & ASE_DSP) { generate_exception_end(ctx, EXCP_DSPDIS); } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } } @@ -2971,7 +2976,7 @@ static inline void check_dsp_r2(DisasContext *ctx) if (ctx->insn_flags & ASE_DSP) { generate_exception_end(ctx, EXCP_DSPDIS); } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } } @@ -2982,7 +2987,7 @@ static inline void check_dsp_r3(DisasContext *ctx) if (ctx->insn_flags & ASE_DSP) { generate_exception_end(ctx, EXCP_DSPDIS); } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } } @@ -2994,7 +2999,7 @@ static inline void check_dsp_r3(DisasContext *ctx) void check_insn(DisasContext *ctx, uint64_t flags) { if (unlikely(!(ctx->insn_flags & flags))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } =20 @@ -3006,7 +3011,7 @@ void check_insn(DisasContext *ctx, uint64_t flags) static inline void check_insn_opc_removed(DisasContext *ctx, uint64_t flag= s) { if (unlikely(ctx->insn_flags & flags)) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } =20 @@ -3045,7 +3050,7 @@ static inline void check_ps(DisasContext *ctx) void check_mips_64(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } #endif @@ -3066,7 +3071,7 @@ static inline void check_mvh(DisasContext *ctx) static inline void check_xnp(DisasContext *ctx) { if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_XNP))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } =20 @@ -3078,7 +3083,7 @@ static inline void check_xnp(DisasContext *ctx) static inline void check_pw(DisasContext *ctx) { if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_PW)))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } #endif @@ -3090,7 +3095,7 @@ static inline void check_pw(DisasContext *ctx) static inline void check_mt(DisasContext *ctx) { if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } =20 @@ -3107,7 +3112,7 @@ static inline void check_cp0_mt(DisasContext *ctx) generate_exception_end(ctx, EXCP_CpU); } else { if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } } @@ -3120,7 +3125,7 @@ static inline void check_cp0_mt(DisasContext *ctx) static inline void check_nms(DisasContext *ctx) { if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_NMS))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } =20 @@ -3137,7 +3142,7 @@ static inline void check_nms_dl_il_sl_tl_l2c(DisasCon= text *ctx) !(ctx->CP0_Config2 & (1 << CP0C2_SL)) && !(ctx->CP0_Config2 & (1 << CP0C2_TL)) && !(ctx->CP0_Config5 & (1 << CP0C5_L2C)))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } =20 @@ -3148,7 +3153,7 @@ static inline void check_nms_dl_il_sl_tl_l2c(DisasCon= text *ctx) static inline void check_eva(DisasContext *ctx) { if (unlikely(!(ctx->CP0_Config5 & (1 << CP0C5_EVA)))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } =20 @@ -3813,7 +3818,7 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t = opc, int ft, break; default: MIPS_INVAL("flt_ldst"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -4462,7 +4467,7 @@ static void gen_HILO1_tx79(DisasContext *ctx, uint32_= t opc, int reg) break; default: MIPS_INVAL("mfthilo1 TX79"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -4597,7 +4602,7 @@ static inline void gen_pcrel(DisasContext *ctx, int o= pc, target_ulong pc, #endif default: MIPS_INVAL("OPC_PCREL"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -4808,7 +4813,7 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc,= int rd, int rs, int rt) #endif default: MIPS_INVAL("r6 mul/div"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } out: @@ -4866,7 +4871,7 @@ static void gen_div1_tx79(DisasContext *ctx, uint32_t= opc, int rs, int rt) break; default: MIPS_INVAL("div1 TX79"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } out: @@ -5059,7 +5064,7 @@ static void gen_muldiv(DisasContext *ctx, uint32_t op= c, break; default: MIPS_INVAL("mul/div"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } out: @@ -5190,7 +5195,7 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t = opc, break; default: MIPS_INVAL("mul/madd TXx9"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } =20 @@ -5253,7 +5258,7 @@ static void gen_mul_vr54xx(DisasContext *ctx, uint32_= t opc, break; default: MIPS_INVAL("mul vr54xx"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } gen_store_gpr(t0, rd); @@ -5879,7 +5884,7 @@ static void gen_loongson_multimedia(DisasContext *ctx= , int rd, int rs, int rt) break; default: MIPS_INVAL("loongson_cp2"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } =20 @@ -6068,7 +6073,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int= rt, #endif default: MIPS_INVAL("loongson_gsshfl"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -6116,13 +6121,13 @@ static void gen_loongson_lswc2(DisasContext *ctx, i= nt rt, #endif default: MIPS_INVAL("loongson_gsshfs"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; default: MIPS_INVAL("loongson_gslsq"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } tcg_temp_free(t0); @@ -6171,7 +6176,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int= rt, break; default: MIPS_INVAL("loongson_lsdc2"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; break; } @@ -6427,7 +6432,7 @@ static void gen_compute_branch(DisasContext *ctx, uin= t32_t opc, LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx "\n", ctx->base.pc_next); #endif - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } =20 @@ -6490,14 +6495,14 @@ static void gen_compute_branch(DisasContext *ctx, u= int32_t opc, * others are reserved. */ MIPS_INVAL("jump hint"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } gen_load_gpr(btarget, rs); break; default: MIPS_INVAL("branch/jump"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } if (bcond_compute =3D=3D 0) { @@ -6562,7 +6567,7 @@ static void gen_compute_branch(DisasContext *ctx, uin= t32_t opc, break; default: MIPS_INVAL("branch/jump"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } } else { @@ -6633,7 +6638,7 @@ static void gen_compute_branch(DisasContext *ctx, uin= t32_t opc, break; default: MIPS_INVAL("conditional branch/jump"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } } @@ -6710,14 +6715,14 @@ static void gen_compute_branch_nm(DisasContext *ctx= , uint32_t opc, * others are reserved. */ MIPS_INVAL("jump hint"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } gen_load_gpr(btarget, rs); break; default: MIPS_INVAL("branch/jump"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } if (bcond_compute =3D=3D 0) { @@ -6750,7 +6755,7 @@ static void gen_compute_branch_nm(DisasContext *ctx, = uint32_t opc, break; default: MIPS_INVAL("branch/jump"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } } else { @@ -6773,7 +6778,7 @@ static void gen_compute_branch_nm(DisasContext *ctx, = uint32_t opc, break; default: MIPS_INVAL("conditional branch/jump"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } } @@ -6853,7 +6858,7 @@ static void gen_bitops(DisasContext *ctx, uint32_t op= c, int rt, default: fail: MIPS_INVAL("bitops"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); tcg_temp_free(t0); tcg_temp_free(t1); return; @@ -6931,7 +6936,7 @@ static void gen_bshfl(DisasContext *ctx, uint32_t op2= , int rt, int rd) #endif default: MIPS_INVAL("bsfhl"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); tcg_temp_free(t0); return; } @@ -10585,7 +10590,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContex= t *ctx, int rt, int rd, die: tcg_temp_free(t0); LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } =20 static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt, @@ -10795,7 +10800,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContex= t *ctx, int rd, int rt, die: tcg_temp_free(t0); LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } =20 static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, @@ -10955,7 +10960,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext= *ctx, uint32_t opc, } if (!(ctx->hflags & MIPS_HFLAG_DM)) { MIPS_INVAL(opn); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } else { gen_helper_deret(cpu_env); ctx->base.is_jmp =3D DISAS_EXIT; @@ -10978,7 +10983,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext= *ctx, uint32_t opc, default: die: MIPS_INVAL(opn); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } (void)opn; /* avoid a compiler warning */ @@ -10993,7 +10998,7 @@ static void gen_compute_branch1(DisasContext *ctx, = uint32_t op, TCGv_i32 t0 =3D tcg_temp_new_i32(); =20 if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags & MIPS_HFLAG_BMASK= )) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } =20 @@ -11084,7 +11089,7 @@ static void gen_compute_branch1(DisasContext *ctx, = uint32_t op, break; default: MIPS_INVAL("cp1 cond branch"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } ctx->btarget =3D btarget; @@ -11106,7 +11111,7 @@ static void gen_compute_branch1_r6(DisasContext *ct= x, uint32_t op, LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx "\n", ctx->base.pc_next); #endif - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } =20 @@ -11126,7 +11131,7 @@ static void gen_compute_branch1_r6(DisasContext *ct= x, uint32_t op, break; default: MIPS_INVAL("cp1 cond branch"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } =20 @@ -11434,7 +11439,7 @@ static void gen_cp1(DisasContext *ctx, uint32_t opc= , int rt, int fs) break; default: MIPS_INVAL("cp1 move"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } =20 @@ -11571,7 +11576,7 @@ static void gen_sel_s(DisasContext *ctx, enum fopco= de op1, int fd, int ft, break; default: MIPS_INVAL("gen_sel_s"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } =20 @@ -11608,7 +11613,7 @@ static void gen_sel_d(DisasContext *ctx, enum fopco= de op1, int fd, int ft, break; default: MIPS_INVAL("gen_sel_d"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } =20 @@ -13042,7 +13047,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, break; default: MIPS_INVAL("farith"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } } @@ -13381,7 +13386,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint3= 2_t opc, break; default: MIPS_INVAL("flt3_arith"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } } @@ -13456,13 +13461,13 @@ static void gen_rdhwr(DisasContext *ctx, int rt, = int rd, int sel) offsetof(CPUMIPSState, active_tc.CP0_UserLocal)); gen_store_gpr(t0, rt); } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } break; #endif default: /* Invalid */ MIPS_INVAL("rdhwr"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } tcg_temp_free(t0); @@ -13561,7 +13566,7 @@ static void gen_compute_compact_branch(DisasContext= *ctx, uint32_t opc, LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx "\n", ctx->base.pc_next); #endif - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } =20 @@ -13623,7 +13628,7 @@ static void gen_compute_compact_branch(DisasContext= *ctx, uint32_t opc, break; default: MIPS_INVAL("Compact branch/jump"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } =20 @@ -13644,7 +13649,7 @@ static void gen_compute_compact_branch(DisasContext= *ctx, uint32_t opc, break; default: MIPS_INVAL("Compact branch/jump"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } =20 @@ -13767,7 +13772,7 @@ static void gen_compute_compact_branch(DisasContext= *ctx, uint32_t opc, break; default: MIPS_INVAL("Compact conditional branch/jump"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } =20 @@ -13941,7 +13946,7 @@ static void gen_mips16_save(DisasContext *ctx, args =3D 4; break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } =20 @@ -14037,7 +14042,7 @@ static void gen_mips16_save(DisasContext *ctx, astatic =3D 4; break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } =20 @@ -14143,7 +14148,7 @@ static void gen_mips16_restore(DisasContext *ctx, astatic =3D 4; break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } =20 @@ -14174,7 +14179,7 @@ static void gen_addiupc(DisasContext *ctx, int rx, = int imm, TCGv t0; =20 if (extended && (ctx->hflags & MIPS_HFLAG_BMASK)) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } =20 @@ -14232,7 +14237,7 @@ static void decode_i64_mips16(DisasContext *ctx, check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); if (extended && (ctx->hflags & MIPS_HFLAG_BMASK)) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } else { offset =3D extended ? offset : offset << 3; gen_ld(ctx, OPC_LDPC, ry, 0, offset); @@ -14309,7 +14314,7 @@ static int decode_extended_mips16_opc(CPUMIPSState = *env, DisasContext *ctx) check_mips_64(ctx); gen_shift_imm(ctx, OPC_DSLL, rx, ry, sa); #else - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); #endif break; case 0x2: @@ -14337,7 +14342,7 @@ static int decode_extended_mips16_opc(CPUMIPSState = *env, DisasContext *ctx) check_mips_64(ctx); gen_arith_imm(ctx, OPC_DADDIU, ry, rx, imm); #else - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); #endif } else { gen_arith_imm(ctx, OPC_ADDIU, ry, rx, imm); @@ -14389,7 +14394,7 @@ static int decode_extended_mips16_opc(CPUMIPSState = *env, DisasContext *ctx) } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -14452,7 +14457,7 @@ static int decode_extended_mips16_opc(CPUMIPSState = *env, DisasContext *ctx) break; #endif default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } =20 @@ -14541,7 +14546,7 @@ static int decode_mips16_opc(CPUMIPSState *env, Dis= asContext *ctx) check_mips_64(ctx); gen_shift_imm(ctx, OPC_DSLL, rx, ry, sa); #else - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); #endif break; case 0x2: @@ -14569,7 +14574,7 @@ static int decode_mips16_opc(CPUMIPSState *env, Dis= asContext *ctx) check_mips_64(ctx); gen_arith_imm(ctx, OPC_DADDIU, ry, rx, imm); #else - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); #endif } else { gen_arith_imm(ctx, OPC_ADDIU, ry, rx, imm); @@ -14653,7 +14658,7 @@ static int decode_mips16_opc(CPUMIPSState *env, Dis= asContext *ctx) gen_arith(ctx, OPC_ADDU, ry, reg32, 0); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -14743,7 +14748,7 @@ static int decode_mips16_opc(CPUMIPSState *env, Dis= asContext *ctx) break; #endif default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto done; } =20 @@ -14860,7 +14865,7 @@ static int decode_mips16_opc(CPUMIPSState *env, Dis= asContext *ctx) break; #endif default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -14924,7 +14929,7 @@ static int decode_mips16_opc(CPUMIPSState *env, Dis= asContext *ctx) break; #endif default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -14939,7 +14944,7 @@ static int decode_mips16_opc(CPUMIPSState *env, Dis= asContext *ctx) break; #endif default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } =20 @@ -15637,7 +15642,7 @@ static void gen_ldst_multiple(DisasContext *ctx, ui= nt32_t opc, int reglist, TCGv_i32 t2; =20 if (ctx->hflags & MIPS_HFLAG_BMASK) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } =20 @@ -15790,7 +15795,7 @@ static void gen_pool16c_insn(DisasContext *ctx) } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -15935,7 +15940,7 @@ static void gen_ldst_pair(DisasContext *ctx, uint32= _t opc, int rd, TCGv t0, t1; =20 if (ctx->hflags & MIPS_HFLAG_BMASK || rd =3D=3D 31) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } =20 @@ -15947,7 +15952,7 @@ static void gen_ldst_pair(DisasContext *ctx, uint32= _t opc, int rd, switch (opc) { case LWP: if (rd =3D=3D base) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL); @@ -15968,7 +15973,7 @@ static void gen_ldst_pair(DisasContext *ctx, uint32= _t opc, int rd, #ifdef TARGET_MIPS64 case LDP: if (rd =3D=3D base) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEQ); @@ -16313,7 +16318,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasC= ontext *ctx, int rt, int rs) } else { check_insn(ctx, ISA_MIPS_R1); if (ctx->hflags & MIPS_HFLAG_SBRI) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } else { generate_exception_end(ctx, EXCP_DBp); } @@ -16363,7 +16368,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasC= ontext *ctx, int rt, int rs) default: pool32axf_invalid: MIPS_INVAL("pool32axf"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -16632,7 +16637,7 @@ static void gen_pool32fxf(DisasContext *ctx, int rt= , int rs) break; default: MIPS_INVAL("pool32fxf"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -16836,12 +16841,12 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) break; case SIGRIE: check_insn(ctx, ISA_MIPS_R6); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: pool32a_invalid: MIPS_INVAL("pool32a"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -16883,7 +16888,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) break; default: MIPS_INVAL("pool32b"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -17363,7 +17368,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) default: pool32f_invalid: MIPS_INVAL("pool32f"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } else { @@ -17525,7 +17530,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) /* Fall through */ default: MIPS_INVAL("pool32i"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -17608,7 +17613,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) case LD_EVA: if (!ctx->eva) { MIPS_INVAL("pool32c ld-eva"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } check_cp0_enabled(ctx); @@ -17647,7 +17652,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) case ST_EVA: if (!ctx->eva) { MIPS_INVAL("pool32c st-eva"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } check_cp0_enabled(ctx); @@ -17699,7 +17704,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) break; default: MIPS_INVAL("pool32c"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -17991,7 +17996,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) gen_st(ctx, mips32_op, rt, rs, imm); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -18022,7 +18027,7 @@ static int decode_micromips_opc(CPUMIPSState *env, = DisasContext *ctx) case 7: /* LB32, LH32, LWC132, LDC132, LW32 */ if (ctx->hflags & MIPS_HFLAG_BDS16) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return 2; } break; @@ -18033,7 +18038,7 @@ static int decode_micromips_opc(CPUMIPSState *env, = DisasContext *ctx) case 3: /* MOVE16, ANDI16, POOL16D, POOL16E, BEQZ16, BNEZ16, B16, LI16 */ if (ctx->hflags & MIPS_HFLAG_BDS32) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return 2; } break; @@ -18106,7 +18111,7 @@ static int decode_micromips_opc(CPUMIPSState *env, = DisasContext *ctx) case POOL16F: check_insn_opc_removed(ctx, ISA_MIPS_R6); if (ctx->opcode & 1) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } else { /* MOVEP */ int enc_dest =3D uMIPS_RD(ctx->opcode); @@ -18244,7 +18249,7 @@ static int decode_micromips_opc(CPUMIPSState *env, = DisasContext *ctx) case RES_29: case RES_31: case RES_39: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: decode_micromips32_opc(env, ctx); @@ -19502,7 +19507,7 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState= *env, DisasContext *ctx) gen_helper_dvpe(t0, cpu_env); gen_store_gpr(t0, rt); } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } break; case 1: @@ -19517,7 +19522,7 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState= *env, DisasContext *ctx) gen_helper_evpe(t0, cpu_env); gen_store_gpr(t0, rt); } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } break; } @@ -19567,7 +19572,7 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState= *env, DisasContext *ctx) break; #endif default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -19608,7 +19613,7 @@ static void gen_pool32axf_1_5_nanomips_insn(DisasCo= ntext *ctx, uint32_t opc, gen_helper_maq_sa_w_phl(t0, v1_t, v0_t, cpu_env); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } =20 @@ -19659,7 +19664,7 @@ static void gen_pool32axf_1_nanomips_insn(DisasCont= ext *ctx, uint32_t opc, gen_helper_shilo(t0, v0_t, cpu_env); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -19733,7 +19738,7 @@ static void gen_pool32axf_1_nanomips_insn(DisasCont= ext *ctx, uint32_t opc, } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } =20 @@ -19771,7 +19776,7 @@ static void gen_pool32axf_2_multiply(DisasContext *= ctx, uint32_t opc, gen_helper_dpsq_s_w_ph(t0, v1, v0, cpu_env); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -19794,7 +19799,7 @@ static void gen_pool32axf_2_multiply(DisasContext *= ctx, uint32_t opc, gen_helper_dpsq_sa_l_w(t0, v0, v1, cpu_env); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -19821,7 +19826,7 @@ static void gen_pool32axf_2_multiply(DisasContext *= ctx, uint32_t opc, gen_helper_mulsa_w_ph(t0, v0, v1, cpu_env); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -19848,12 +19853,12 @@ static void gen_pool32axf_2_multiply(DisasContext= *ctx, uint32_t opc, gen_helper_mulsaq_s_w_ph(t0, v1, v0, cpu_env); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } =20 @@ -19997,7 +20002,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasCont= ext *ctx, uint32_t opc, gen_store_gpr(t0, ret); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -20090,7 +20095,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasCont= ext *ctx, uint32_t opc, } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } =20 @@ -20233,7 +20238,7 @@ static void gen_pool32axf_4_nanomips_insn(DisasCont= ext *ctx, uint32_t opc, gen_bshfl(ctx, OPC_WSBH, ret, rs); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } =20 @@ -20288,7 +20293,7 @@ static void gen_pool32axf_7_nanomips_insn(DisasCont= ext *ctx, uint32_t opc, } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } tcg_temp_free(t0); @@ -20385,7 +20390,7 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSStat= e *env, DisasContext *ctx) break; #endif default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -20396,7 +20401,7 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSStat= e *env, DisasContext *ctx) } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -20429,7 +20434,7 @@ static void gen_compute_imm_branch(DisasContext *ct= x, uint32_t opc, case NM_BBNEZC: check_nms(ctx); if (imm >=3D 32 && !(ctx->hflags & MIPS_HFLAG_64)) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } else if (rt =3D=3D 0 && opc =3D=3D NM_BBEQZC) { /* Unconditional branch */ @@ -20479,7 +20484,7 @@ static void gen_compute_imm_branch(DisasContext *ct= x, uint32_t opc, break; default: MIPS_INVAL("Immediate Value Compact branch"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } =20 @@ -20592,7 +20597,7 @@ static void gen_compute_compact_branch_nm(DisasCont= ext *ctx, uint32_t opc, break; default: MIPS_INVAL("Compact branch/jump"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } =20 @@ -20604,7 +20609,7 @@ static void gen_compute_compact_branch_nm(DisasCont= ext *ctx, uint32_t opc, break; default: MIPS_INVAL("Compact branch/jump"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } } else { @@ -20665,7 +20670,7 @@ static void gen_compute_compact_branch_nm(DisasCont= ext *ctx, uint32_t opc, break; default: MIPS_INVAL("Compact conditional branch/jump"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } =20 @@ -20709,7 +20714,7 @@ static void gen_compute_branch_cp1_nm(DisasContext = *ctx, uint32_t op, break; default: MIPS_INVAL("cp1 cond branch"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } =20 @@ -20839,7 +20844,7 @@ static void gen_p_lsx(DisasContext *ctx, int rd, in= t rs, int rt) } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } =20 @@ -20856,7 +20861,7 @@ static void gen_pool32f_nanomips_insn(DisasContext = *ctx) rd =3D extract32(ctx->opcode, 11, 5); =20 if (!(ctx->CP0_Config1 & (1 << CP0C1_FP))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } check_cp1_enabled(ctx); @@ -20930,7 +20935,7 @@ static void gen_pool32f_nanomips_insn(DisasContext = *ctx) gen_farith(ctx, OPC_MSUBF_D, rt, rs, rd, 0); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -21119,7 +21124,7 @@ static void gen_pool32f_nanomips_insn(DisasContext = *ctx) gen_farith(ctx, OPC_CVT_S_L, -1, rs, rt, 0); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -21136,12 +21141,12 @@ static void gen_pool32f_nanomips_insn(DisasContex= t *ctx) gen_r6_cmp_d(ctx, extract32(ctx->opcode, 6, 5), rt, rs, rd); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -21667,7 +21672,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext= *ctx, int opc, gen_store_gpr(v1_t, rt); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -21689,7 +21694,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext= *ctx, int opc, } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -21717,13 +21722,13 @@ static int decode_nanomips_32_48_opc(CPUMIPSState= *env, DisasContext *ctx) switch (extract32(ctx->opcode, 19, 2)) { case NM_SIGRIE: default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case NM_P_SYSCALL: if ((extract32(ctx->opcode, 18, 1)) =3D=3D NM_SYSCALL) { generate_exception_end(ctx, EXCP_SYSCALL); } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } break; case NM_BREAK: @@ -21734,7 +21739,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) gen_helper_do_semihosting(cpu_env); } else { if (ctx->hflags & MIPS_HFLAG_SBRI) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } else { generate_exception_end(ctx, EXCP_DBp); } @@ -21792,12 +21797,12 @@ static int decode_nanomips_32_48_opc(CPUMIPSState= *env, DisasContext *ctx) gen_pool32axf_nanomips_insn(env, ctx); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -21816,7 +21821,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) gen_st(ctx, OPC_SW, rt, 28, extract32(ctx->opcode, 2, 19) << 2= ); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -21887,7 +21892,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } return 6; @@ -21922,12 +21927,12 @@ static int decode_nanomips_32_48_opc(CPUMIPSState= *env, DisasContext *ctx) } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; case NM_P_SR_F: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -22015,7 +22020,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) extract32(ctx->opcode, 6, 5)); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -22028,12 +22033,12 @@ static int decode_nanomips_32_48_opc(CPUMIPSState= *env, DisasContext *ctx) extract32(ctx->opcode, 6, 5)); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -22101,7 +22106,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) gen_st(ctx, OPC_SH, rt, 28, u); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -22123,7 +22128,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -22183,7 +22188,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) gen_cop1_ldst(ctx, OPC_SDC1, rt, rs, u); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -22246,7 +22251,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -22386,7 +22391,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) gen_llwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3,= 5)); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -22406,7 +22411,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) true); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -22457,7 +22462,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -22501,7 +22506,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) gen_compute_nanomips_pbalrsc_branch(ctx, rs, rt); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -22536,7 +22541,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -22585,7 +22590,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -22601,7 +22606,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } return 4; @@ -22640,7 +22645,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, D= isasContext *ctx) if (extract32(ctx->opcode, 2, 1) =3D=3D 0) { generate_exception_end(ctx, EXCP_SYSCALL); } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } break; case NM_BREAK16: @@ -22651,14 +22656,14 @@ static int decode_nanomips_opc(CPUMIPSState *env,= DisasContext *ctx) gen_helper_do_semihosting(cpu_env); } else { if (ctx->hflags & MIPS_HFLAG_SBRI) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } else { generate_exception_end(ctx, EXCP_DBp); } } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -22697,7 +22702,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, D= isasContext *ctx) gen_arith_imm(ctx, OPC_ADDIU, rt, 29, imm); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -22746,7 +22751,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, D= isasContext *ctx) gen_r6_muldiv(ctx, R6_OPC_MUL, rt, rs, rt); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -22782,7 +22787,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, D= isasContext *ctx) gen_ld(ctx, OPC_LBU, rt, rs, offset); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -22801,7 +22806,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, D= isasContext *ctx) gen_ld(ctx, OPC_LHU, rt, rs, offset); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -23580,7 +23585,7 @@ static void gen_mipsdsp_shift(DisasContext *ctx, ui= nt32_t opc, break; default: /* Invalid */ MIPS_INVAL("MASK SHLL.QB"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -23695,7 +23700,7 @@ static void gen_mipsdsp_shift(DisasContext *ctx, ui= nt32_t opc, break; default: /* Invalid */ MIPS_INVAL("MASK SHLL.OB"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -24386,7 +24391,7 @@ static void gen_mipsdsp_append(CPUMIPSState *env, D= isasContext *ctx, break; default: /* Invalid */ MIPS_INVAL("MASK APPEND"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -24420,7 +24425,7 @@ static void gen_mipsdsp_append(CPUMIPSState *env, D= isasContext *ctx, break; default: /* Invalid */ MIPS_INVAL("MASK DAPPEND"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -24689,7 +24694,7 @@ static void decode_opc_special_r6(CPUMIPSState *env= , DisasContext *ctx) break; default: MIPS_INVAL("special_r6 muldiv"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -24706,7 +24711,7 @@ static void decode_opc_special_r6(CPUMIPSState *env= , DisasContext *ctx) */ gen_cl(ctx, op1, rd, rs); } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } break; case R6_OPC_SDBBP: @@ -24714,7 +24719,7 @@ static void decode_opc_special_r6(CPUMIPSState *env= , DisasContext *ctx) gen_helper_do_semihosting(cpu_env); } else { if (ctx->hflags & MIPS_HFLAG_SBRI) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } else { generate_exception_end(ctx, EXCP_DBp); } @@ -24735,7 +24740,7 @@ static void decode_opc_special_r6(CPUMIPSState *env= , DisasContext *ctx) check_mips_64(ctx); gen_cl(ctx, op1, rd, rs); } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } break; case OPC_DMULT: @@ -24758,14 +24763,14 @@ static void decode_opc_special_r6(CPUMIPSState *e= nv, DisasContext *ctx) break; default: MIPS_INVAL("special_r6 muldiv"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; #endif default: /* Invalid */ MIPS_INVAL("special_r6"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -24812,7 +24817,7 @@ static void decode_opc_special_tx79(CPUMIPSState *e= nv, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("special_tx79"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -24883,16 +24888,16 @@ static void decode_opc_special_legacy(CPUMIPSStat= e *env, DisasContext *ctx) case OPC_SPIM: #ifdef MIPS_STRICT_STANDARD MIPS_INVAL("SPIM"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); #else /* Implemented as RI exception for now. */ MIPS_INVAL("spim (unofficial)"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); #endif break; default: /* Invalid */ MIPS_INVAL("special_legacy"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -24914,7 +24919,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) rs =3D=3D 0 && rt =3D=3D 0) { /* PAUSE */ if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -24934,7 +24939,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) gen_shift_imm(ctx, op1, rd, rt, sa); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -24960,7 +24965,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) gen_shift(ctx, op1, rd, rs, rt); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -24994,7 +24999,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) /* Pmon entry point, also R4010 selsl */ #ifdef MIPS_STRICT_STANDARD MIPS_INVAL("PMON / selsl"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); #else gen_helper_0e0i(pmon, sa); #endif @@ -25035,7 +25040,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) gen_shift_imm(ctx, op1, rd, rt, sa); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -25053,7 +25058,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) gen_shift_imm(ctx, op1, rd, rt, sa); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -25085,7 +25090,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) gen_shift(ctx, op1, rd, rs, rt); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -25150,7 +25155,7 @@ static void gen_mmi_pcpyh(DisasContext *ctx) rd =3D extract32(opcode, 11, 5); =20 if (unlikely(pd !=3D 0)) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } else if (rd =3D=3D 0) { /* nop */ } else if (rt =3D=3D 0) { @@ -26357,16 +26362,16 @@ static void decode_opc_mxu__pool00(CPUMIPSState *= env, DisasContext *ctx) case OPC_MXU_Q8SLT: /* TODO: Implement emulation of Q8SLT instruction. */ MIPS_INVAL("OPC_MXU_Q8SLT"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q8SLTU: /* TODO: Implement emulation of Q8SLTU instruction. */ MIPS_INVAL("OPC_MXU_Q8SLTU"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26396,41 +26401,41 @@ static void decode_opc_mxu__pool01(CPUMIPSState *= env, DisasContext *ctx) case OPC_MXU_S32SLT: /* TODO: Implement emulation of S32SLT instruction. */ MIPS_INVAL("OPC_MXU_S32SLT"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D16SLT: /* TODO: Implement emulation of D16SLT instruction. */ MIPS_INVAL("OPC_MXU_D16SLT"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D16AVG: /* TODO: Implement emulation of D16AVG instruction. */ MIPS_INVAL("OPC_MXU_D16AVG"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D16AVGR: /* TODO: Implement emulation of D16AVGR instruction. */ MIPS_INVAL("OPC_MXU_D16AVGR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q8AVG: /* TODO: Implement emulation of Q8AVG instruction. */ MIPS_INVAL("OPC_MXU_Q8AVG"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q8AVGR: /* TODO: Implement emulation of Q8AVGR instruction. */ MIPS_INVAL("OPC_MXU_Q8AVGR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q8ADD: /* TODO: Implement emulation of Q8ADD instruction. */ MIPS_INVAL("OPC_MXU_Q8ADD"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26453,26 +26458,26 @@ static void decode_opc_mxu__pool02(CPUMIPSState *= env, DisasContext *ctx) case OPC_MXU_S32CPS: /* TODO: Implement emulation of S32CPS instruction. */ MIPS_INVAL("OPC_MXU_S32CPS"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D16CPS: /* TODO: Implement emulation of D16CPS instruction. */ MIPS_INVAL("OPC_MXU_D16CPS"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q8ABD: /* TODO: Implement emulation of Q8ABD instruction. */ MIPS_INVAL("OPC_MXU_Q8ABD"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q16SAT: /* TODO: Implement emulation of Q16SAT instruction. */ MIPS_INVAL("OPC_MXU_Q16SAT"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26502,16 +26507,16 @@ static void decode_opc_mxu__pool03(CPUMIPSState *= env, DisasContext *ctx) case OPC_MXU_D16MULF: /* TODO: Implement emulation of D16MULF instruction. */ MIPS_INVAL("OPC_MXU_D16MULF"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D16MULE: /* TODO: Implement emulation of D16MULE instruction. */ MIPS_INVAL("OPC_MXU_D16MULE"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26537,7 +26542,7 @@ static void decode_opc_mxu__pool04(CPUMIPSState *en= v, DisasContext *ctx) break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26560,16 +26565,16 @@ static void decode_opc_mxu__pool05(CPUMIPSState *= env, DisasContext *ctx) case OPC_MXU_S32STD: /* TODO: Implement emulation of S32STD instruction. */ MIPS_INVAL("OPC_MXU_S32STD"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32STDR: /* TODO: Implement emulation of S32STDR instruction. */ MIPS_INVAL("OPC_MXU_S32STDR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26592,16 +26597,16 @@ static void decode_opc_mxu__pool06(CPUMIPSState *= env, DisasContext *ctx) case OPC_MXU_S32LDDV: /* TODO: Implement emulation of S32LDDV instruction. */ MIPS_INVAL("OPC_MXU_S32LDDV"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32LDDVR: /* TODO: Implement emulation of S32LDDVR instruction. */ MIPS_INVAL("OPC_MXU_S32LDDVR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26624,16 +26629,16 @@ static void decode_opc_mxu__pool07(CPUMIPSState *= env, DisasContext *ctx) case OPC_MXU_S32STDV: /* TODO: Implement emulation of S32TDV instruction. */ MIPS_INVAL("OPC_MXU_S32TDV"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32STDVR: /* TODO: Implement emulation of S32TDVR instruction. */ MIPS_INVAL("OPC_MXU_S32TDVR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26656,16 +26661,16 @@ static void decode_opc_mxu__pool08(CPUMIPSState *= env, DisasContext *ctx) case OPC_MXU_S32LDI: /* TODO: Implement emulation of S32LDI instruction. */ MIPS_INVAL("OPC_MXU_S32LDI"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32LDIR: /* TODO: Implement emulation of S32LDIR instruction. */ MIPS_INVAL("OPC_MXU_S32LDIR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26688,16 +26693,16 @@ static void decode_opc_mxu__pool09(CPUMIPSState *= env, DisasContext *ctx) case OPC_MXU_S32SDI: /* TODO: Implement emulation of S32SDI instruction. */ MIPS_INVAL("OPC_MXU_S32SDI"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32SDIR: /* TODO: Implement emulation of S32SDIR instruction. */ MIPS_INVAL("OPC_MXU_S32SDIR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26720,16 +26725,16 @@ static void decode_opc_mxu__pool10(CPUMIPSState *= env, DisasContext *ctx) case OPC_MXU_S32LDIV: /* TODO: Implement emulation of S32LDIV instruction. */ MIPS_INVAL("OPC_MXU_S32LDIV"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32LDIVR: /* TODO: Implement emulation of S32LDIVR instruction. */ MIPS_INVAL("OPC_MXU_S32LDIVR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26752,16 +26757,16 @@ static void decode_opc_mxu__pool11(CPUMIPSState *= env, DisasContext *ctx) case OPC_MXU_S32SDIV: /* TODO: Implement emulation of S32SDIV instruction. */ MIPS_INVAL("OPC_MXU_S32SDIV"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32SDIVR: /* TODO: Implement emulation of S32SDIVR instruction. */ MIPS_INVAL("OPC_MXU_S32SDIVR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26784,21 +26789,21 @@ static void decode_opc_mxu__pool12(CPUMIPSState *= env, DisasContext *ctx) case OPC_MXU_D32ACC: /* TODO: Implement emulation of D32ACC instruction. */ MIPS_INVAL("OPC_MXU_D32ACC"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D32ACCM: /* TODO: Implement emulation of D32ACCM instruction. */ MIPS_INVAL("OPC_MXU_D32ACCM"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D32ASUM: /* TODO: Implement emulation of D32ASUM instruction. */ MIPS_INVAL("OPC_MXU_D32ASUM"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26821,21 +26826,21 @@ static void decode_opc_mxu__pool13(CPUMIPSState *= env, DisasContext *ctx) case OPC_MXU_Q16ACC: /* TODO: Implement emulation of Q16ACC instruction. */ MIPS_INVAL("OPC_MXU_Q16ACC"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q16ACCM: /* TODO: Implement emulation of Q16ACCM instruction. */ MIPS_INVAL("OPC_MXU_Q16ACCM"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q16ASUM: /* TODO: Implement emulation of Q16ASUM instruction. */ MIPS_INVAL("OPC_MXU_Q16ASUM"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26865,21 +26870,21 @@ static void decode_opc_mxu__pool14(CPUMIPSState *= env, DisasContext *ctx) case OPC_MXU_Q8ADDE: /* TODO: Implement emulation of Q8ADDE instruction. */ MIPS_INVAL("OPC_MXU_Q8ADDE"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D8SUM: /* TODO: Implement emulation of D8SUM instruction. */ MIPS_INVAL("OPC_MXU_D8SUM"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D8SUMC: /* TODO: Implement emulation of D8SUMC instruction. */ MIPS_INVAL("OPC_MXU_D8SUMC"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26909,26 +26914,26 @@ static void decode_opc_mxu__pool15(CPUMIPSState *= env, DisasContext *ctx) case OPC_MXU_S32MUL: /* TODO: Implement emulation of S32MUL instruction. */ MIPS_INVAL("OPC_MXU_S32MUL"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32MULU: /* TODO: Implement emulation of S32MULU instruction. */ MIPS_INVAL("OPC_MXU_S32MULU"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32EXTR: /* TODO: Implement emulation of S32EXTR instruction. */ MIPS_INVAL("OPC_MXU_S32EXTR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32EXTRV: /* TODO: Implement emulation of S32EXTRV instruction. */ MIPS_INVAL("OPC_MXU_S32EXTRV"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26976,12 +26981,12 @@ static void decode_opc_mxu__pool16(CPUMIPSState *= env, DisasContext *ctx) case OPC_MXU_D32SARW: /* TODO: Implement emulation of D32SARW instruction. */ MIPS_INVAL("OPC_MXU_D32SARW"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32ALN: /* TODO: Implement emulation of S32ALN instruction. */ MIPS_INVAL("OPC_MXU_S32ALN"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32ALNI: gen_mxu_S32ALNI(ctx); @@ -26989,7 +26994,7 @@ static void decode_opc_mxu__pool16(CPUMIPSState *en= v, DisasContext *ctx) case OPC_MXU_S32LUI: /* TODO: Implement emulation of S32LUI instruction. */ MIPS_INVAL("OPC_MXU_S32LUI"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32NOR: gen_mxu_S32NOR(ctx); @@ -27005,7 +27010,7 @@ static void decode_opc_mxu__pool16(CPUMIPSState *en= v, DisasContext *ctx) break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -27028,31 +27033,31 @@ static void decode_opc_mxu__pool17(CPUMIPSState *= env, DisasContext *ctx) case OPC_MXU_LXW: /* TODO: Implement emulation of LXW instruction. */ MIPS_INVAL("OPC_MXU_LXW"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_LXH: /* TODO: Implement emulation of LXH instruction. */ MIPS_INVAL("OPC_MXU_LXH"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_LXHU: /* TODO: Implement emulation of LXHU instruction. */ MIPS_INVAL("OPC_MXU_LXHU"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_LXB: /* TODO: Implement emulation of LXB instruction. */ MIPS_INVAL("OPC_MXU_LXB"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_LXBU: /* TODO: Implement emulation of LXBU instruction. */ MIPS_INVAL("OPC_MXU_LXBU"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -27074,36 +27079,36 @@ static void decode_opc_mxu__pool18(CPUMIPSState *= env, DisasContext *ctx) case OPC_MXU_D32SLLV: /* TODO: Implement emulation of D32SLLV instruction. */ MIPS_INVAL("OPC_MXU_D32SLLV"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D32SLRV: /* TODO: Implement emulation of D32SLRV instruction. */ MIPS_INVAL("OPC_MXU_D32SLRV"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D32SARV: /* TODO: Implement emulation of D32SARV instruction. */ MIPS_INVAL("OPC_MXU_D32SARV"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q16SLLV: /* TODO: Implement emulation of Q16SLLV instruction. */ MIPS_INVAL("OPC_MXU_Q16SLLV"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q16SLRV: /* TODO: Implement emulation of Q16SLRV instruction. */ MIPS_INVAL("OPC_MXU_Q16SLRV"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q16SARV: /* TODO: Implement emulation of Q16SARV instruction. */ MIPS_INVAL("OPC_MXU_Q16SARV"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -27129,7 +27134,7 @@ static void decode_opc_mxu__pool19(CPUMIPSState *en= v, DisasContext *ctx) break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -27152,36 +27157,36 @@ static void decode_opc_mxu__pool20(CPUMIPSState *= env, DisasContext *ctx) case OPC_MXU_Q8MOVZ: /* TODO: Implement emulation of Q8MOVZ instruction. */ MIPS_INVAL("OPC_MXU_Q8MOVZ"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q8MOVN: /* TODO: Implement emulation of Q8MOVN instruction. */ MIPS_INVAL("OPC_MXU_Q8MOVN"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D16MOVZ: /* TODO: Implement emulation of D16MOVZ instruction. */ MIPS_INVAL("OPC_MXU_D16MOVZ"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D16MOVN: /* TODO: Implement emulation of D16MOVN instruction. */ MIPS_INVAL("OPC_MXU_D16MOVN"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32MOVZ: /* TODO: Implement emulation of S32MOVZ instruction. */ MIPS_INVAL("OPC_MXU_S32MOVZ"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32MOVN: /* TODO: Implement emulation of S32MOVN instruction. */ MIPS_INVAL("OPC_MXU_S32MOVN"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -27204,16 +27209,16 @@ static void decode_opc_mxu__pool21(CPUMIPSState *= env, DisasContext *ctx) case OPC_MXU_Q8MAC: /* TODO: Implement emulation of Q8MAC instruction. */ MIPS_INVAL("OPC_MXU_Q8MAC"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q8MACSU: /* TODO: Implement emulation of Q8MACSU instruction. */ MIPS_INVAL("OPC_MXU_Q8MACSU"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -27272,12 +27277,12 @@ static void decode_opc_mxu(CPUMIPSState *env, Dis= asContext *ctx) case OPC_MXU_S32MADD: /* TODO: Implement emulation of S32MADD instruction. */ MIPS_INVAL("OPC_MXU_S32MADD"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32MADDU: /* TODO: Implement emulation of S32MADDU instruction. */ MIPS_INVAL("OPC_MXU_S32MADDU"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU__POOL00: decode_opc_mxu__pool00(env, ctx); @@ -27285,12 +27290,12 @@ static void decode_opc_mxu(CPUMIPSState *env, Dis= asContext *ctx) case OPC_MXU_S32MSUB: /* TODO: Implement emulation of S32MSUB instruction. */ MIPS_INVAL("OPC_MXU_S32MSUB"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32MSUBU: /* TODO: Implement emulation of S32MSUBU instruction. */ MIPS_INVAL("OPC_MXU_S32MSUBU"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU__POOL01: decode_opc_mxu__pool01(env, ctx); @@ -27310,27 +27315,27 @@ static void decode_opc_mxu(CPUMIPSState *env, Dis= asContext *ctx) case OPC_MXU_D16MACF: /* TODO: Implement emulation of D16MACF instruction. */ MIPS_INVAL("OPC_MXU_D16MACF"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D16MADL: /* TODO: Implement emulation of D16MADL instruction. */ MIPS_INVAL("OPC_MXU_D16MADL"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S16MAD: /* TODO: Implement emulation of S16MAD instruction. */ MIPS_INVAL("OPC_MXU_S16MAD"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q16ADD: /* TODO: Implement emulation of Q16ADD instruction. */ MIPS_INVAL("OPC_MXU_Q16ADD"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D16MACE: /* TODO: Implement emulation of D16MACE instruction. */ MIPS_INVAL("OPC_MXU_D16MACE"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU__POOL04: decode_opc_mxu__pool04(env, ctx); @@ -27359,7 +27364,7 @@ static void decode_opc_mxu(CPUMIPSState *env, Disas= Context *ctx) case OPC_MXU_D32ADD: /* TODO: Implement emulation of D32ADD instruction. */ MIPS_INVAL("OPC_MXU_D32ADD"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU__POOL12: decode_opc_mxu__pool12(env, ctx); @@ -27373,7 +27378,7 @@ static void decode_opc_mxu(CPUMIPSState *env, Disas= Context *ctx) case OPC_MXU_Q8ACCE: /* TODO: Implement emulation of Q8ACCE instruction. */ MIPS_INVAL("OPC_MXU_Q8ACCE"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S8LDD: gen_mxu_s8ldd(ctx); @@ -27381,17 +27386,17 @@ static void decode_opc_mxu(CPUMIPSState *env, Dis= asContext *ctx) case OPC_MXU_S8STD: /* TODO: Implement emulation of S8STD instruction. */ MIPS_INVAL("OPC_MXU_S8STD"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S8LDI: /* TODO: Implement emulation of S8LDI instruction. */ MIPS_INVAL("OPC_MXU_S8LDI"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S8SDI: /* TODO: Implement emulation of S8SDI instruction. */ MIPS_INVAL("OPC_MXU_S8SDI"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU__POOL15: decode_opc_mxu__pool15(env, ctx); @@ -27405,52 +27410,52 @@ static void decode_opc_mxu(CPUMIPSState *env, Dis= asContext *ctx) case OPC_MXU_S16LDD: /* TODO: Implement emulation of S16LDD instruction. */ MIPS_INVAL("OPC_MXU_S16LDD"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S16STD: /* TODO: Implement emulation of S16STD instruction. */ MIPS_INVAL("OPC_MXU_S16STD"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S16LDI: /* TODO: Implement emulation of S16LDI instruction. */ MIPS_INVAL("OPC_MXU_S16LDI"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S16SDI: /* TODO: Implement emulation of S16SDI instruction. */ MIPS_INVAL("OPC_MXU_S16SDI"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D32SLL: /* TODO: Implement emulation of D32SLL instruction. */ MIPS_INVAL("OPC_MXU_D32SLL"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D32SLR: /* TODO: Implement emulation of D32SLR instruction. */ MIPS_INVAL("OPC_MXU_D32SLR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D32SARL: /* TODO: Implement emulation of D32SARL instruction. */ MIPS_INVAL("OPC_MXU_D32SARL"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D32SAR: /* TODO: Implement emulation of D32SAR instruction. */ MIPS_INVAL("OPC_MXU_D32SAR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q16SLL: /* TODO: Implement emulation of Q16SLL instruction. */ MIPS_INVAL("OPC_MXU_Q16SLL"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q16SLR: /* TODO: Implement emulation of Q16SLR instruction. */ MIPS_INVAL("OPC_MXU_Q16SLR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU__POOL18: decode_opc_mxu__pool18(env, ctx); @@ -27458,7 +27463,7 @@ static void decode_opc_mxu(CPUMIPSState *env, Disas= Context *ctx) case OPC_MXU_Q16SAR: /* TODO: Implement emulation of Q16SAR instruction. */ MIPS_INVAL("OPC_MXU_Q16SAR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU__POOL19: decode_opc_mxu__pool19(env, ctx); @@ -27472,26 +27477,26 @@ static void decode_opc_mxu(CPUMIPSState *env, Dis= asContext *ctx) case OPC_MXU_Q16SCOP: /* TODO: Implement emulation of Q16SCOP instruction. */ MIPS_INVAL("OPC_MXU_Q16SCOP"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q8MADL: /* TODO: Implement emulation of Q8MADL instruction. */ MIPS_INVAL("OPC_MXU_Q8MADL"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32SFL: /* TODO: Implement emulation of S32SFL instruction. */ MIPS_INVAL("OPC_MXU_S32SFL"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q8SAD: /* TODO: Implement emulation of Q8SAD instruction. */ MIPS_INVAL("OPC_MXU_Q8SAD"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } =20 gen_set_label(l_exit); @@ -27570,7 +27575,7 @@ static void decode_opc_special2_legacy(CPUMIPSState= *env, DisasContext *ctx) #endif default: /* Invalid */ MIPS_INVAL("special2_legacy"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -27592,7 +27597,7 @@ static void decode_opc_special3_r6(CPUMIPSState *en= v, DisasContext *ctx) case R6_OPC_PREF: if (rt >=3D 24) { /* hint codes 24-31 are reserved and signal RI */ - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } /* Treat as NOP. */ break; @@ -27631,7 +27636,7 @@ static void decode_opc_special3_r6(CPUMIPSState *en= v, DisasContext *ctx) #ifndef CONFIG_USER_ONLY case OPC_GINV: if (unlikely(ctx->gi <=3D 1)) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } check_cp0_enabled(ctx); switch ((ctx->opcode >> 6) & 3) { @@ -27642,7 +27647,7 @@ static void decode_opc_special3_r6(CPUMIPSState *en= v, DisasContext *ctx) gen_helper_0e1i(ginvt, cpu_gpr[rs], extract32(ctx->opcode, 8, = 2)); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -27683,7 +27688,7 @@ static void decode_opc_special3_r6(CPUMIPSState *en= v, DisasContext *ctx) #endif default: /* Invalid */ MIPS_INVAL("special3_r6"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -27734,13 +27739,13 @@ static void decode_opc_special3_legacy(CPUMIPSSta= te *env, DisasContext *ctx) break; default: MIPS_INVAL("MASK ADDUH.QB"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } else if (ctx->insn_flags & INSN_LOONGSON2E) { gen_loongson_integer(ctx, op1, rd, rs, rt); } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } break; case OPC_LX_DSP: @@ -27756,7 +27761,7 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("MASK LX"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -27787,7 +27792,7 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) break; default: MIPS_INVAL("MASK ABSQ_S.PH"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -27824,7 +27829,7 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("MASK ADDU.QB"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; =20 } @@ -27864,7 +27869,7 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("MASK CMPU.EQ.QB"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -27900,7 +27905,7 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("MASK DPAW.PH"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -27930,7 +27935,7 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) } default: /* Invalid */ MIPS_INVAL("MASK INSV"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -27965,7 +27970,7 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("MASK EXTR.W"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -28011,7 +28016,7 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("MASK ABSQ_S.QH"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -28050,7 +28055,7 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("MASK ADDU.OB"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -28095,7 +28100,7 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("MASK CMPU_EQ.OB"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -28132,7 +28137,7 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("MASK EXTR.W"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -28171,7 +28176,7 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("MASK DPAQ.W.QH"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -28201,7 +28206,7 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) } default: /* Invalid */ MIPS_INVAL("MASK DINSV"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -28211,7 +28216,7 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) #endif default: /* Invalid */ MIPS_INVAL("special3_legacy"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -28249,11 +28254,11 @@ static void decode_mmi0(CPUMIPSState *env, DisasC= ontext *ctx) case MMI_OPC_0_PPACB: /* TODO: MMI_OPC_0_PPACB */ case MMI_OPC_0_PEXT5: /* TODO: MMI_OPC_0_PEXT5 */ case MMI_OPC_0_PPAC5: /* TODO: MMI_OPC_0_PPAC5 */ - generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI0 = */ + gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI0 */ break; default: MIPS_INVAL("TX79 MMI class MMI0"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -28281,11 +28286,11 @@ static void decode_mmi1(CPUMIPSState *env, DisasC= ontext *ctx) case MMI_OPC_1_PSUBUB: /* TODO: MMI_OPC_1_PSUBUB */ case MMI_OPC_1_PEXTUB: /* TODO: MMI_OPC_1_PEXTUB */ case MMI_OPC_1_QFSRV: /* TODO: MMI_OPC_1_QFSRV */ - generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI1 = */ + gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI1 */ break; default: MIPS_INVAL("TX79 MMI class MMI1"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -28316,14 +28321,14 @@ static void decode_mmi2(CPUMIPSState *env, DisasC= ontext *ctx) case MMI_OPC_2_PDIVBW: /* TODO: MMI_OPC_2_PDIVBW */ case MMI_OPC_2_PEXEW: /* TODO: MMI_OPC_2_PEXEW */ case MMI_OPC_2_PROT3W: /* TODO: MMI_OPC_2_PROT3W */ - generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI2 = */ + gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI2 */ break; case MMI_OPC_2_PCPYLD: gen_mmi_pcpyld(ctx); break; default: MIPS_INVAL("TX79 MMI class MMI2"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -28344,7 +28349,7 @@ static void decode_mmi3(CPUMIPSState *env, DisasCon= text *ctx) case MMI_OPC_3_PNOR: /* TODO: MMI_OPC_3_PNOR */ case MMI_OPC_3_PEXCH: /* TODO: MMI_OPC_3_PEXCH */ case MMI_OPC_3_PEXCW: /* TODO: MMI_OPC_3_PEXCW */ - generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI3 = */ + gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI3 */ break; case MMI_OPC_3_PCPYH: gen_mmi_pcpyh(ctx); @@ -28354,7 +28359,7 @@ static void decode_mmi3(CPUMIPSState *env, DisasCon= text *ctx) break; default: MIPS_INVAL("TX79 MMI class MMI3"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -28408,23 +28413,23 @@ static void decode_mmi(CPUMIPSState *env, DisasCo= ntext *ctx) case MMI_OPC_PSLLW: /* TODO: MMI_OPC_PSLLW */ case MMI_OPC_PSRLW: /* TODO: MMI_OPC_PSRLW */ case MMI_OPC_PSRAW: /* TODO: MMI_OPC_PSRAW */ - generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MM= I */ + gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI */ break; default: MIPS_INVAL("TX79 MMI class"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } =20 static void gen_mmi_lq(CPUMIPSState *env, DisasContext *ctx) { - generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_LQ */ + gen_reserved_instruction(ctx); /* TODO: MMI_OPC_LQ */ } =20 static void gen_mmi_sq(DisasContext *ctx, int base, int rt, int offset) { - generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_SQ */ + gen_reserved_instruction(ctx); /* TODO: MMI_OPC_SQ */ } =20 /* @@ -28632,7 +28637,7 @@ static inline int check_msa_access(DisasContext *ct= x) { if (unlikely((ctx->hflags & MIPS_HFLAG_FPU) && !(ctx->hflags & MIPS_HFLAG_F64))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return 0; } =20 @@ -28641,7 +28646,7 @@ static inline int check_msa_access(DisasContext *ct= x) generate_exception_end(ctx, EXCP_MSADIS); return 0; } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return 0; } } @@ -28698,7 +28703,7 @@ static void gen_msa_branch(CPUMIPSState *env, Disas= Context *ctx, uint32_t op1) check_msa_access(ctx); =20 if (ctx->hflags & MIPS_HFLAG_BMASK) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } switch (op1) { @@ -28773,7 +28778,7 @@ static void gen_msa_i8(CPUMIPSState *env, DisasCont= ext *ctx) { uint8_t df =3D (ctx->opcode >> 24) & 0x3; if (df =3D=3D DF_DOUBLE) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } else { TCGv_i32 tdf =3D tcg_const_i32(df); gen_helper_msa_shf_df(cpu_env, tdf, twd, tws, ti8); @@ -28783,7 +28788,7 @@ static void gen_msa_i8(CPUMIPSState *env, DisasCont= ext *ctx) break; default: MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } =20 @@ -28855,7 +28860,7 @@ static void gen_msa_i5(CPUMIPSState *env, DisasCont= ext *ctx) break; default: MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } =20 @@ -28891,7 +28896,7 @@ static void gen_msa_bit(CPUMIPSState *env, DisasCon= text *ctx) m =3D dfm & 0x7; df =3D DF_BYTE; } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } =20 @@ -28939,7 +28944,7 @@ static void gen_msa_bit(CPUMIPSState *env, DisasCon= text *ctx) break; default: MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } =20 @@ -29784,7 +29789,7 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_HSUB_S_df: case OPC_HSUB_U_df: if (df =3D=3D DF_BYTE) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } switch (MASK_MSA_3R(ctx->opcode)) { @@ -29922,7 +29927,7 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCont= ext *ctx) break; default: MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } tcg_temp_free_i32(twd); @@ -29954,7 +29959,7 @@ static void gen_msa_elm_3e(CPUMIPSState *env, Disas= Context *ctx) break; default: MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } =20 @@ -29991,12 +29996,12 @@ static void gen_msa_elm_df(CPUMIPSState *env, Dis= asContext *ctx, uint32_t df, #if !defined(TARGET_MIPS64) /* Double format valid only for MIPS64 */ if (df =3D=3D DF_DOUBLE) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } if ((MASK_MSA_ELM(ctx->opcode) =3D=3D OPC_COPY_U_df) && (df =3D=3D DF_WORD)) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } #endif @@ -30066,7 +30071,7 @@ static void gen_msa_elm_df(CPUMIPSState *env, Disas= Context *ctx, uint32_t df, break; default: MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } tcg_temp_free_i32(twd); tcg_temp_free_i32(tws); @@ -30096,7 +30101,7 @@ static void gen_msa_elm(CPUMIPSState *env, DisasCon= text *ctx) gen_msa_elm_3e(env, ctx); return; } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } =20 @@ -30251,7 +30256,7 @@ static void gen_msa_3rf(CPUMIPSState *env, DisasCon= text *ctx) break; default: MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } =20 @@ -30279,7 +30284,7 @@ static void gen_msa_2r(CPUMIPSState *env, DisasCont= ext *ctx) #if !defined(TARGET_MIPS64) /* Double format valid only for MIPS64 */ if (df =3D=3D DF_DOUBLE) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } #endif @@ -30335,7 +30340,7 @@ static void gen_msa_2r(CPUMIPSState *env, DisasCont= ext *ctx) break; default: MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } =20 @@ -30450,7 +30455,7 @@ static void gen_msa_vec_v(CPUMIPSState *env, DisasC= ontext *ctx) break; default: MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } =20 @@ -30479,7 +30484,7 @@ static void gen_msa_vec(CPUMIPSState *env, DisasCon= text *ctx) break; default: MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -30577,7 +30582,7 @@ static void gen_msa(CPUMIPSState *env, DisasContext= *ctx) break; default: MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } =20 @@ -30661,7 +30666,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) /* OPC_NAL, OPC_BAL */ gen_compute_branch(ctx, op1, 4, 0, -1, imm << 2, 4); } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } else { gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4); @@ -30680,7 +30685,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) break; case OPC_SIGRIE: check_insn(ctx, ISA_MIPS_R6); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_SYNCI: check_insn(ctx, ISA_MIPS_R2); @@ -30715,7 +30720,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) #endif default: /* Invalid */ MIPS_INVAL("regimm"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -30824,7 +30829,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) break; default: /* Invalid */ MIPS_INVAL("mfmc0"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } tcg_temp_free(t0); @@ -30841,7 +30846,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) break; default: MIPS_INVAL("cp0"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -30877,7 +30882,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC, OPC_BLEZL */ if (ctx->insn_flags & ISA_MIPS_R6) { if (rt =3D=3D 0) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } /* OPC_BLEZC, OPC_BGEZC, OPC_BGEC */ @@ -30890,7 +30895,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC, OPC_BGTZL */ if (ctx->insn_flags & ISA_MIPS_R6) { if (rt =3D=3D 0) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } /* OPC_BGTZC, OPC_BLTZC, OPC_BLTC */ @@ -31139,7 +31144,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) break; default: MIPS_INVAL("cp1"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -31225,7 +31230,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) break; default: MIPS_INVAL("cp3"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } else { @@ -31290,7 +31295,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); } else { MIPS_INVAL("major opcode"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } break; #endif @@ -31308,7 +31313,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) tcg_temp_free(t0); } #else - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); MIPS_INVAL("major opcode"); #endif } else { @@ -31334,7 +31339,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) break; default: /* Invalid */ MIPS_INVAL("major opcode"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -31439,7 +31444,7 @@ static void mips_tr_translate_insn(DisasContextBase= *dcbase, CPUState *cs) ctx->opcode =3D cpu_lduw_code(env, ctx->base.pc_next); insn_bytes =3D decode_mips16_opc(env, ctx); } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); g_assert(ctx->base.is_jmp =3D=3D DISAS_NORETURN); return; } --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.48 as permitted sender) client-ip=209.85.128.48; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f48.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1610058343; cv=none; d=zohomail.com; s=zohoarc; b=V8dBr4M5jt2Pv+blc5zWGCJyw2cydd0t6PnMdHS0JHUrdcZO0/dfTaChSYOEeUPgUBFO9UuUpTflZtCU3DWoWaxSL7ethTwoLFX5Fj539VCZallA85A2HtwOTM+PEw3pLsZPA5S7quDUt23vHys5HtqcHJ1dXw86nhC2SJSMr5E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id z15sm10584113wrv.67.2021.01.07.14.25.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:25:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QRsQWA6DviCLjfaBDg1WbGaXrnSa2ioMMoOlaaR//h8=; b=o0OBpaG8YioPmnh4pCi8uEIllIPToQK4Y/ZurcH7/jBgzM0iX59PpRROfAX9KSm9Qv y1M/po13UpDx0ukSBaTIFxHYx4VHSUOnpOezCQWu3EYtKGgUVDXSvNIKYeSmL+QOqnJ3 H3LDJGFF/dNekLL+AvkIY3R91mTDJTumFY9rCML71mGVTSCTUkRJh+qP8r3Y1PO7DNwe +vVhhyT1Goj5s5FDV6ldmMGa/D7ylClNjaujOItzpFp/UtcLBZrmMSInI5/Tm27RIoiW qOJaAURMH/V8wGZ1oYMX4RaTnB5af38vnwNyLA0iYwxXzmtjAbdKRecF63ma5xT19Ny3 7LQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=QRsQWA6DviCLjfaBDg1WbGaXrnSa2ioMMoOlaaR//h8=; b=btrxXoVjCcSzdXlCMYblszlF1s5S9wHR7U0ysV+WlTdlz0QG3596z84kccbibKFpkr Lx4YOWnqhfu3o+GzrObaNDc5VNqCRlozQhC7NhacUwp5uuWK0lSeMOIge73qe3GQSHvd 9ePljVRGpXXr547sR3Igb1ptJzJfdlwT6tx4WRNLfXApYwtL0YCkjDJRNXPVGCWu4CO6 CDbpQ+YAYv7SB9TqaG5ntR21kcjF+eMRGW+8iwhZFTy2e9Ohfd65C1eznyBhTgbZ+Kik 4eUXzw2tBETW9guhqXikrMldw+YXpypVclcyCgKwb7Ftvl/o5z91R/gtYb9x3EBsesSL NW6A== X-Gm-Message-State: AOAM532vTVcifDWsZB7rj2HifV6Om+0NBCI5GeB5tI+TDa12ZGfQlt42 Y9alQGk0fuBmpq6nHsOPonM= X-Google-Smtp-Source: ABdhPJzGmA4+ysp4m5XSrF57IUOYG8Bi+WA1SU7PAOx6p4FBWbHHquxLpd7/0eknqJS8F6BCz/U/mA== X-Received: by 2002:a1c:65d4:: with SMTP id z203mr509895wmb.65.1610058342032; Thu, 07 Jan 2021 14:25:42 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: libvir-list@redhat.com, Paolo Bonzini , Laurent Vivier , kvm@vger.kernel.org, Jiaxun Yang , Aurelien Jarno , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Paul Burton , Richard Henderson Subject: [PULL 32/66] target/mips: Declare generic FPU functions in 'translate.h' Date: Thu, 7 Jan 2021 23:22:19 +0100 Message-Id: <20210107222253.20382-33-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Some FPU translation functions / registers can be used by ISA / ASE / extensions out of the big translate.c file. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201214183739.500368-15-f4bug@amsat.org> --- target/mips/translate.h | 7 +++++++ target/mips/translate.c | 12 ++++++------ 2 files changed, 13 insertions(+), 6 deletions(-) diff --git a/target/mips/translate.h b/target/mips/translate.h index 5f744c63374..4c30a328e4b 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -60,12 +60,19 @@ void check_insn(DisasContext *ctx, uint64_t flags); #ifdef TARGET_MIPS64 void check_mips_64(DisasContext *ctx); #endif +void check_cp1_enabled(DisasContext *ctx); =20 void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offs= et); void gen_load_gpr(TCGv t, int reg); void gen_store_gpr(TCGv t, int reg); =20 +void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg); +void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg); +int get_fp_bit(int cc); + extern TCGv cpu_gpr[32], cpu_PC; +extern TCGv_i32 fpu_fcr0, fpu_fcr31; +extern TCGv_i64 fpu_f64[32]; extern TCGv bcond; =20 #define LOG_DISAS(...) = \ diff --git a/target/mips/translate.c b/target/mips/translate.c index 7c20ed33df7..610fba61de4 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2492,8 +2492,8 @@ static TCGv cpu_dspctrl, btarget; TCGv bcond; static TCGv cpu_lladdr, cpu_llval; static TCGv_i32 hflags; -static TCGv_i32 fpu_fcr0, fpu_fcr31; -static TCGv_i64 fpu_f64[32]; +TCGv_i32 fpu_fcr0, fpu_fcr31; +TCGv_i64 fpu_f64[32]; static TCGv_i64 msa_wr_d[64]; =20 #if defined(TARGET_MIPS64) @@ -2809,7 +2809,7 @@ static void gen_store_fpr32h(DisasContext *ctx, TCGv_= i32 t, int reg) } } =20 -static void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) +void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) { if (ctx->hflags & MIPS_HFLAG_F64) { tcg_gen_mov_i64(t, fpu_f64[reg]); @@ -2818,7 +2818,7 @@ static void gen_load_fpr64(DisasContext *ctx, TCGv_i6= 4 t, int reg) } } =20 -static void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) +void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) { if (ctx->hflags & MIPS_HFLAG_F64) { tcg_gen_mov_i64(fpu_f64[reg], t); @@ -2832,7 +2832,7 @@ static void gen_store_fpr64(DisasContext *ctx, TCGv_i= 64 t, int reg) } } =20 -static inline int get_fp_bit(int cc) +int get_fp_bit(int cc) { if (cc) { return 24 + cc; @@ -2907,7 +2907,7 @@ static inline void check_cp0_enabled(DisasContext *ct= x) } } =20 -static inline void check_cp1_enabled(DisasContext *ctx) +void check_cp1_enabled(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) { generate_exception_err(ctx, EXCP_CpU, 1); --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) client-ip=216.205.24.124; envelope-from=libvir-list-bounces@redhat.com; helo=us-smtp-delivery-124.mimecast.com; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) smtp.mailfrom=libvir-list-bounces@redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1610058366; cv=none; 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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id i9sm10794305wrs.70.2021.01.07.14.25.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:25:46 -0800 (PST) X-MC-Unique: 39d6BQCrP4Woj5B2yYHoBg-1 X-MC-Unique: 8FRJXsPAPXqAw3daOszfAg-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=M5/OHDIsfN90nSudp26zMHLuKLIpMGo4pYHfXrBeq+Y=; b=lnlFPcAVHnDr5jGMhz8tabrbbTkEXBqwjygYqzB9U+fuMwRu9Gv6ITBvly77Wsvec8 WQO8mU2yVL0Erc0jVlwZi0AL4NWQS3V0sLD3TCa6r777P9ky2wV0u+pwesNRU/PNzTn3 KyuNiL8PSt5tRaw1gnMm8UAfxwieIPrm7hVWiAE/e4u1+OAhBesHZvqKceC4eG0uUW1F Y+YzyneKZnw1RZcAZyOt7FflcvWZcquVCC6h4z969wXF7Bvy1N4IawVLxrXv/RbUJSFn W+sbOq8b3Vak8uKpuK7Xq7UaIhqYwSeLfIFI1WKW+jCPDdj/+qmANxd49L8+9FPz/xY2 Ycjg== X-Gm-Message-State: AOAM531+8bS7cjRJGcyaP8rQ8Xvcc+eApNMnN1c0ny6di7nfrXVJnc6I puA0f5yDKCUXnswcUzZKE7c= X-Google-Smtp-Source: ABdhPJy4mm0Ii5NGwleCxYIQNeng+A7yjLBn+FieY6iend0fQ9dqJVNukJWP7vcnXWJCCPP9dpT+oA== X-Received: by 2002:a5d:5256:: with SMTP id k22mr641108wrc.89.1610058347060; Thu, 07 Jan 2021 14:25:47 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 33/66] target/mips: Extract FPU specific definitions to translate.h Date: Thu, 7 Jan 2021 23:22:20 +0100 Message-Id: <20210107222253.20382-34-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Extract FPU specific definitions that can be used by ISA / ASE / extensions to translate.h header. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201214183739.500368-16-f4bug@amsat.org> --- target/mips/translate.h | 71 +++++++++++++++++++++++++++++++++++++++++ target/mips/translate.c | 70 ---------------------------------------- 2 files changed, 71 insertions(+), 70 deletions(-) diff --git a/target/mips/translate.h b/target/mips/translate.h index 4c30a328e4b..c70bca998fb 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -52,6 +52,77 @@ typedef struct DisasContext { /* MIPS major opcodes */ #define MASK_OP_MAJOR(op) (op & (0x3F << 26)) =20 +#define OPC_CP1 (0x11 << 26) + +/* Coprocessor 1 (rs field) */ +#define MASK_CP1(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21= ))) + +/* Values for the fmt field in FP instructions */ +enum { + /* 0 - 15 are reserved */ + FMT_S =3D 16, /* single fp */ + FMT_D =3D 17, /* double fp */ + FMT_E =3D 18, /* extended fp */ + FMT_Q =3D 19, /* quad fp */ + FMT_W =3D 20, /* 32-bit fixed */ + FMT_L =3D 21, /* 64-bit fixed */ + FMT_PS =3D 22, /* paired single fp */ + /* 23 - 31 are reserved */ +}; + +enum { + OPC_MFC1 =3D (0x00 << 21) | OPC_CP1, + OPC_DMFC1 =3D (0x01 << 21) | OPC_CP1, + OPC_CFC1 =3D (0x02 << 21) | OPC_CP1, + OPC_MFHC1 =3D (0x03 << 21) | OPC_CP1, + OPC_MTC1 =3D (0x04 << 21) | OPC_CP1, + OPC_DMTC1 =3D (0x05 << 21) | OPC_CP1, + OPC_CTC1 =3D (0x06 << 21) | OPC_CP1, + OPC_MTHC1 =3D (0x07 << 21) | OPC_CP1, + OPC_BC1 =3D (0x08 << 21) | OPC_CP1, /* bc */ + OPC_BC1ANY2 =3D (0x09 << 21) | OPC_CP1, + OPC_BC1ANY4 =3D (0x0A << 21) | OPC_CP1, + OPC_BZ_V =3D (0x0B << 21) | OPC_CP1, + OPC_BNZ_V =3D (0x0F << 21) | OPC_CP1, + OPC_S_FMT =3D (FMT_S << 21) | OPC_CP1, + OPC_D_FMT =3D (FMT_D << 21) | OPC_CP1, + OPC_E_FMT =3D (FMT_E << 21) | OPC_CP1, + OPC_Q_FMT =3D (FMT_Q << 21) | OPC_CP1, + OPC_W_FMT =3D (FMT_W << 21) | OPC_CP1, + OPC_L_FMT =3D (FMT_L << 21) | OPC_CP1, + OPC_PS_FMT =3D (FMT_PS << 21) | OPC_CP1, + OPC_BC1EQZ =3D (0x09 << 21) | OPC_CP1, + OPC_BC1NEZ =3D (0x0D << 21) | OPC_CP1, + OPC_BZ_B =3D (0x18 << 21) | OPC_CP1, + OPC_BZ_H =3D (0x19 << 21) | OPC_CP1, + OPC_BZ_W =3D (0x1A << 21) | OPC_CP1, + OPC_BZ_D =3D (0x1B << 21) | OPC_CP1, + OPC_BNZ_B =3D (0x1C << 21) | OPC_CP1, + OPC_BNZ_H =3D (0x1D << 21) | OPC_CP1, + OPC_BNZ_W =3D (0x1E << 21) | OPC_CP1, + OPC_BNZ_D =3D (0x1F << 21) | OPC_CP1, +}; + +#define MASK_CP1_FUNC(op) (MASK_CP1(op) | (op & 0x3F)) +#define MASK_BC1(op) (MASK_CP1(op) | (op & (0x3 << 16))) + +enum { + OPC_BC1F =3D (0x00 << 16) | OPC_BC1, + OPC_BC1T =3D (0x01 << 16) | OPC_BC1, + OPC_BC1FL =3D (0x02 << 16) | OPC_BC1, + OPC_BC1TL =3D (0x03 << 16) | OPC_BC1, +}; + +enum { + OPC_BC1FANY2 =3D (0x00 << 16) | OPC_BC1ANY2, + OPC_BC1TANY2 =3D (0x01 << 16) | OPC_BC1ANY2, +}; + +enum { + OPC_BC1FANY4 =3D (0x00 << 16) | OPC_BC1ANY4, + OPC_BC1TANY4 =3D (0x01 << 16) | OPC_BC1ANY4, +}; + void generate_exception(DisasContext *ctx, int excp); void generate_exception_err(DisasContext *ctx, int excp, int err); void generate_exception_end(DisasContext *ctx, int excp); diff --git a/target/mips/translate.c b/target/mips/translate.c index 610fba61de4..39b57794b36 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -43,7 +43,6 @@ enum { OPC_SPECIAL =3D (0x00 << 26), OPC_REGIMM =3D (0x01 << 26), OPC_CP0 =3D (0x10 << 26), - OPC_CP1 =3D (0x11 << 26), OPC_CP2 =3D (0x12 << 26), OPC_CP3 =3D (0x13 << 26), OPC_SPECIAL2 =3D (0x1C << 26), @@ -996,75 +995,6 @@ enum { OPC_WAIT =3D 0x20 | OPC_C0, }; =20 -/* Coprocessor 1 (rs field) */ -#define MASK_CP1(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21= ))) - -/* Values for the fmt field in FP instructions */ -enum { - /* 0 - 15 are reserved */ - FMT_S =3D 16, /* single fp */ - FMT_D =3D 17, /* double fp */ - FMT_E =3D 18, /* extended fp */ - FMT_Q =3D 19, /* quad fp */ - FMT_W =3D 20, /* 32-bit fixed */ - FMT_L =3D 21, /* 64-bit fixed */ - FMT_PS =3D 22, /* paired single fp */ - /* 23 - 31 are reserved */ -}; - -enum { - OPC_MFC1 =3D (0x00 << 21) | OPC_CP1, - OPC_DMFC1 =3D (0x01 << 21) | OPC_CP1, - OPC_CFC1 =3D (0x02 << 21) | OPC_CP1, - OPC_MFHC1 =3D (0x03 << 21) | OPC_CP1, - OPC_MTC1 =3D (0x04 << 21) | OPC_CP1, - OPC_DMTC1 =3D (0x05 << 21) | OPC_CP1, - OPC_CTC1 =3D (0x06 << 21) | OPC_CP1, - OPC_MTHC1 =3D (0x07 << 21) | OPC_CP1, - OPC_BC1 =3D (0x08 << 21) | OPC_CP1, /* bc */ - OPC_BC1ANY2 =3D (0x09 << 21) | OPC_CP1, - OPC_BC1ANY4 =3D (0x0A << 21) | OPC_CP1, - OPC_BZ_V =3D (0x0B << 21) | OPC_CP1, - OPC_BNZ_V =3D (0x0F << 21) | OPC_CP1, - OPC_S_FMT =3D (FMT_S << 21) | OPC_CP1, - OPC_D_FMT =3D (FMT_D << 21) | OPC_CP1, - OPC_E_FMT =3D (FMT_E << 21) | OPC_CP1, - OPC_Q_FMT =3D (FMT_Q << 21) | OPC_CP1, - OPC_W_FMT =3D (FMT_W << 21) | OPC_CP1, - OPC_L_FMT =3D (FMT_L << 21) | OPC_CP1, - OPC_PS_FMT =3D (FMT_PS << 21) | OPC_CP1, - OPC_BC1EQZ =3D (0x09 << 21) | OPC_CP1, - OPC_BC1NEZ =3D (0x0D << 21) | OPC_CP1, - OPC_BZ_B =3D (0x18 << 21) | OPC_CP1, - OPC_BZ_H =3D (0x19 << 21) | OPC_CP1, - OPC_BZ_W =3D (0x1A << 21) | OPC_CP1, - OPC_BZ_D =3D (0x1B << 21) | OPC_CP1, - OPC_BNZ_B =3D (0x1C << 21) | OPC_CP1, - OPC_BNZ_H =3D (0x1D << 21) | OPC_CP1, - OPC_BNZ_W =3D (0x1E << 21) | OPC_CP1, - OPC_BNZ_D =3D (0x1F << 21) | OPC_CP1, -}; - -#define MASK_CP1_FUNC(op) (MASK_CP1(op) | (op & 0x3F)) -#define MASK_BC1(op) (MASK_CP1(op) | (op & (0x3 << 16))) - -enum { - OPC_BC1F =3D (0x00 << 16) | OPC_BC1, - OPC_BC1T =3D (0x01 << 16) | OPC_BC1, - OPC_BC1FL =3D (0x02 << 16) | OPC_BC1, - OPC_BC1TL =3D (0x03 << 16) | OPC_BC1, -}; - -enum { - OPC_BC1FANY2 =3D (0x00 << 16) | OPC_BC1ANY2, - OPC_BC1TANY2 =3D (0x01 << 16) | OPC_BC1ANY2, -}; - -enum { - OPC_BC1FANY4 =3D (0x00 << 16) | OPC_BC1ANY4, - OPC_BC1TANY4 =3D (0x01 << 16) | OPC_BC1ANY4, -}; - #define MASK_CP2(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21= ))) =20 enum { --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 63.128.21.124 as permitted sender) client-ip=63.128.21.124; envelope-from=libvir-list-bounces@redhat.com; helo=us-smtp-delivery-124.mimecast.com; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of redhat.com designates 63.128.21.124 as permitted sender) smtp.mailfrom=libvir-list-bounces@redhat.com ARC-Seal: i=1; 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Thu, 07 Jan 2021 14:25:52 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 34/66] target/mips: Only build TCG code when CONFIG_TCG is set Date: Thu, 7 Jan 2021 23:22:21 +0100 Message-Id: <20210107222253.20382-35-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.78 on 10.11.54.6 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201206233949.3783184-20-f4bug@amsat.org> --- target/mips/meson.build | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/target/mips/meson.build b/target/mips/meson.build index 5a49951c6d7..596eb1aeeb3 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -1,9 +1,11 @@ mips_ss =3D ss.source_set() mips_ss.add(files( 'cpu.c', + 'gdbstub.c', +)) +mips_ss.add(when: 'CONFIG_TCG', if_true: files( 'dsp_helper.c', 'fpu_helper.c', - 'gdbstub.c', 'lmmi_helper.c', 'msa_helper.c', 'op_helper.c', @@ -15,11 +17,13 @@ mips_softmmu_ss =3D ss.source_set() mips_softmmu_ss.add(files( 'addr.c', - 'cp0_helper.c', 'cp0_timer.c', 'machine.c', 'mips-semi.c', )) +mips_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files( + 'cp0_helper.c', +)) =20 target_arch +=3D {'mips': mips_ss} target_softmmu_arch +=3D {'mips': mips_softmmu_ss} --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) client-ip=216.205.24.124; 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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id z3sm11193357wrn.59.2021.01.07.14.25.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:25:56 -0800 (PST) X-MC-Unique: pVUHGoipOpmRUe6WerLmJQ-1 X-MC-Unique: 0EMgXmTgNYWeRIeciwmOKg-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=RlmjZD/A3T2fr0JUoH85vuwC1Fo52rRxQmVB1QjBz9E=; b=FAblEkW7uZtg2REqj7rl9mgamTzFYeXU4AfnbvxyWFw52IaY7ilaABC2cbH8HL24F9 MLNaVFFq7UYRJEc3q+qjQSROr6cHZeLMeUe9Olk7fnrSQQR5LYXpd/+x4TRI5jzmUQKQ 06uAw0gA7VKkAsHeHT6cohz3VPsPCQ5i9MyWq2UM9A4IteXbx9+Dejq5NzYrSaHfvu23 eYmuIlPGt6y6Q1Gg81dMVjjWnnbsYcfd8B2rHr410EOS0DQ7wpTd1tpGyUwD17a7AVbs 5NAzaPWuHMrcDxSi/pPf8tYCeg6IT1zo2mzUFgyzHphGT8aTfPh6Evb6mvP+9NHtHgUO AiyQ== X-Gm-Message-State: AOAM530RTiqcZ8BMVJGB8xBShhoovb80jMTUvO3Jo7kppQO3L3CCvg6t 2sacKoX+94Jng8QkYpSnLMxS2vM+Wc8= X-Google-Smtp-Source: ABdhPJwoJVLzZ/qFA+Cy7r9W3UMAsAZQYt1Z3j0t6hvrmnMMZTF2r3KKkM6n6BLOL4rOpv3nSHSgnw== X-Received: by 2002:a1c:5410:: with SMTP id i16mr543118wmb.30.1610058357273; Thu, 07 Jan 2021 14:25:57 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 35/66] target/mips/translate: Extract decode_opc_legacy() from decode_opc() Date: Thu, 7 Jan 2021 23:22:22 +0100 Message-Id: <20210107222253.20382-36-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.79 on 10.11.54.5 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable As we will slowly move to decodetree generated decoders, extract the legacy decoding from decode_opc(), so new decoders are added in decode_opc() while old code is removed from decode_opc_legacy(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201215225757.764263-2-f4bug@amsat.org> --- target/mips/translate.c | 45 ++++++++++++++++++++++++----------------- 1 file changed, 26 insertions(+), 19 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 39b57794b36..7d2120dd51c 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -30518,30 +30518,13 @@ static void gen_msa(CPUMIPSState *env, DisasConte= xt *ctx) =20 } =20 -static void decode_opc(CPUMIPSState *env, DisasContext *ctx) +static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) { int32_t offset; int rs, rt, rd, sa; uint32_t op, op1; int16_t imm; =20 - /* make sure instructions are on a word boundary */ - if (ctx->base.pc_next & 0x3) { - env->CP0_BadVAddr =3D ctx->base.pc_next; - generate_exception_err(ctx, EXCP_AdEL, EXCP_INST_NOTAVAIL); - return; - } - - /* Handle blikely not taken case */ - if ((ctx->hflags & MIPS_HFLAG_BMASK_BASE) =3D=3D MIPS_HFLAG_BL) { - TCGLabel *l1 =3D gen_new_label(); - - tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1); - tcg_gen_movi_i32(hflags, ctx->hflags & ~MIPS_HFLAG_BMASK); - gen_goto_tb(ctx, 1, ctx->base.pc_next + 4); - gen_set_label(l1); - } - op =3D MASK_OP_MAJOR(ctx->opcode); rs =3D (ctx->opcode >> 21) & 0x1f; rt =3D (ctx->opcode >> 16) & 0x1f; @@ -31269,8 +31252,32 @@ static void decode_opc(CPUMIPSState *env, DisasCon= text *ctx) break; default: /* Invalid */ MIPS_INVAL("major opcode"); + return false; + } + return true; +} + +static void decode_opc(CPUMIPSState *env, DisasContext *ctx) +{ + /* make sure instructions are on a word boundary */ + if (ctx->base.pc_next & 0x3) { + env->CP0_BadVAddr =3D ctx->base.pc_next; + generate_exception_err(ctx, EXCP_AdEL, EXCP_INST_NOTAVAIL); + return; + } + + /* Handle blikely not taken case */ + if ((ctx->hflags & MIPS_HFLAG_BMASK_BASE) =3D=3D MIPS_HFLAG_BL) { + TCGLabel *l1 =3D gen_new_label(); + + tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1); + tcg_gen_movi_i32(hflags, ctx->hflags & ~MIPS_HFLAG_BMASK); + gen_goto_tb(ctx, 1, ctx->base.pc_next + 4); + gen_set_label(l1); + } + + if (!decode_opc_legacy(env, ctx)) { gen_reserved_instruction(ctx); - break; } } =20 --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) client-ip=209.85.221.51; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f51.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1610058364; cv=none; d=zohomail.com; s=zohoarc; b=Vkgb68WKxIhdniDuJw2U073h2qY8efRPpOp3PnTL7M65hcWSVRohoE5Z5ukhDjX/WtGY9VRHBf2s2ZjKlRjwe5a9ei8HH45y8LsfmBUBEhDIKivedr/cuDR1BKqFXX7HlDcTye81KB7j0DHLEpgXzcwSdVvzZS8Ift4gCtb5OgM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610058364; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xMINXm1sTVzeUT3ZE6sRQjEA5ZHRpEpLUaOQgOSkVsQ=; b=OXLHVt/vtMBwfmFRQD4tKxdQyKdzGJAXRh/hSB6tRKrlgHaT7YjwKrpcJ2G45Mu99aL9+ZLgvUyWxMMpqmKdVFIAVvRlZa27Tzo7wp8mTLftoE+PyQFQMNTLF4iR9oXMdMEjF/dLsSQuWqGUIjP9P5Us9M4wKW5UK+B6tn60aWI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) by mx.zohomail.com with SMTPS id 1610058364215513.882119331279; Thu, 7 Jan 2021 14:26:04 -0800 (PST) Received: by mail-wr1-f51.google.com with SMTP id r7so7119421wrc.5 for ; Thu, 07 Jan 2021 14:26:03 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (241.red-88-10-103.dynamicip.rima-tde.net. [88.10.103.241]) by smtp.gmail.com with ESMTPSA id i9sm10795243wrs.70.2021.01.07.14.26.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:26:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xMINXm1sTVzeUT3ZE6sRQjEA5ZHRpEpLUaOQgOSkVsQ=; b=EHAE3Ol5/HOD8NEgpNC9Z7QLjkfjlPScUCA/+1Ni7Wvc/Ouh8RmBNpTvF44ACC+O94 ui3rGx1wKxHQQoWQyUnB9heNVZifzrLk54YRq8z3DH4E8rDIK8hHUaSM/Kf04dakP5vJ Fd/RQeSsatodFbulCqF6x8TiPphBSmQSoE2oFdRH4mW2S4ao8xDf4CPQc974T0fgAWgw KUM9zTusnII0RIHXs5cxNPaR4GTj5lKYOe9TbQos2ZzdL0gfkCVrktIaf+TvwrLhWRw7 fAdNPsepUBUnfdlphWJmcp2vcwOQupadPCDedEMM2CG1BB56BBZBMIvmFZBdizHwPzJH WgPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=xMINXm1sTVzeUT3ZE6sRQjEA5ZHRpEpLUaOQgOSkVsQ=; b=XpRHYzH+Kd7zO3pDjXhFSYanIKrije2R6PyNf+FuK4wlyd5SyqiAZo7uS/atKK6bTD +b9FdM7sqsyCYbhPuIyw6w8q/cu6b1NHR3lWsiSUcBp5mBnLriqSYsKhRVdh5Y5d8iVc GrbujrdTyUqXsfOesvaXyHR3fKhj6wbrdXQLWC6I0wp6JA2Xu7GghiRc5LS15nzfPcYW fhFeq8DjT5KjR7qj5w+bagpPD7FvNJECP1EuGS3ZE+GzAB1FdTATvmnYunBQwV/N5pDJ IZ0t9eRHzYvF7Qn0Z3eBeSKoZhHrXfdKu9W55u9YTCOxBCJuafFiCwWP74ujpG+Smhw6 Z2gg== X-Gm-Message-State: AOAM532nNJffPOQCzKGBTYCURp8q5w26MwO/0gtH0qhs2ww+RLEMbE4C McDU6wMWu3wWAt9HY48evV8= X-Google-Smtp-Source: ABdhPJwjVucGLGwLTP8ZlzahNzVV4CW6S2hcO4HB4SrTqZzAZcO7bXWXd4P/foDdI4h565pPc3KKDw== X-Received: by 2002:a5d:60c1:: with SMTP id x1mr660228wrt.271.1610058362338; Thu, 07 Jan 2021 14:26:02 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: libvir-list@redhat.com, Paolo Bonzini , Laurent Vivier , kvm@vger.kernel.org, Jiaxun Yang , Aurelien Jarno , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Paul Burton Subject: [PULL 36/66] target/mips/translate: Expose check_mips_64() to 32-bit mode Date: Thu, 7 Jan 2021 23:22:23 +0100 Message-Id: <20210107222253.20382-37-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) To allow compiling 64-bit specific translation code more generically (and removing #ifdef'ry), allow compiling check_mips_64() on 32-bit targets. If ever called on 32-bit, we obviously emit a reserved instruction exception. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Jiaxun Yang Message-Id: <20201215225757.764263-3-f4bug@amsat.org> --- target/mips/translate.h | 2 -- target/mips/translate.c | 8 +++----- 2 files changed, 3 insertions(+), 7 deletions(-) diff --git a/target/mips/translate.h b/target/mips/translate.h index c70bca998fb..402bc5e8846 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -128,9 +128,7 @@ void generate_exception_err(DisasContext *ctx, int excp= , int err); void generate_exception_end(DisasContext *ctx, int excp); void gen_reserved_instruction(DisasContext *ctx); void check_insn(DisasContext *ctx, uint64_t flags); -#ifdef TARGET_MIPS64 void check_mips_64(DisasContext *ctx); -#endif void check_cp1_enabled(DisasContext *ctx); =20 void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offs= et); diff --git a/target/mips/translate.c b/target/mips/translate.c index 7d2120dd51c..69fa8a50790 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2972,18 +2972,16 @@ static inline void check_ps(DisasContext *ctx) check_cp1_64bitmode(ctx); } =20 -#ifdef TARGET_MIPS64 /* - * This code generates a "reserved instruction" exception if 64-bit - * instructions are not enabled. + * This code generates a "reserved instruction" exception if cpu is not + * 64-bit or 64-bit instructions are not enabled. */ void check_mips_64(DisasContext *ctx) { - if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) { + if (unlikely((TARGET_LONG_BITS !=3D 64) || !(ctx->hflags & MIPS_HFLAG_= 64))) { gen_reserved_instruction(ctx); } } -#endif =20 #ifndef CONFIG_USER_ONLY static inline void check_mvh(DisasContext *ctx) --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.51 as permitted sender) client-ip=209.85.128.51; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f51.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1610058369; cv=none; d=zohomail.com; s=zohoarc; b=Ax+V07FcECi4O2py25dKPPiudrJ6znh8qDRwSZMdUysZ1fCo9b9B+KQzjbeOJG9XdVQzu4eujQRC6uja/lAfZ34lzmxGYxBOMYTIpOWw3JKS2HDoMAm6k1Wi4CH+zHeOPs1zxrrWxxNKnmEdyivQCucWD3vxn/jdT3hxaYSiN9k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610058369; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=n6RRuYZ8EGGXTpGZvsOKW/oYziHM0vCJPjdxKK9QfP8=; b=ARcLphTB1A33TutgEt+ObUq4K8Tso2TzUr3FnRKsUt8rXMuqLGIfPJks56NKh0fYDwDihLEQvF574jMM0a3HhMc5QWra78ZYhHfLEJ2eN8MiFjH93xqTgWtbdlNpTqmZ4YclvUNrwn8ff/yBypP1QaRaNgI2jMnaCpBnxCzkngI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) by mx.zohomail.com with SMTPS id 1610058369216582.7580319263383; Thu, 7 Jan 2021 14:26:09 -0800 (PST) Received: by mail-wm1-f51.google.com with SMTP id c124so6332890wma.5 for ; Thu, 07 Jan 2021 14:26:08 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (241.red-88-10-103.dynamicip.rima-tde.net. [88.10.103.241]) by smtp.gmail.com with ESMTPSA id h29sm11023080wrc.68.2021.01.07.14.26.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:26:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=n6RRuYZ8EGGXTpGZvsOKW/oYziHM0vCJPjdxKK9QfP8=; b=b2liXW65beeD2lT7WvmvqnfKSev9lKyIOR/qt+3YfkcSBiqUXqCLub5tz2bF017rsZ KULF9vT4qroLXU7TSCScrYsnk11Jmz5bgKu6TL2rexVDoy5CRDrFPBiN0VXGes0eDzl4 FSLlY1Zb79pg3RHBItCHpYH82i0/l14lIvo91iXlO5xJhWaJ6jUN4z7qBhiAnv2NMYvF 3lo4E5vEwjugOPSLAVfwu88DkBRd1500Z/FZzKvHYODBzanfummJfxw3Td8hca/ciYxt P7Dwc+4SG3KxDNfnrlUlgv2HXu99MyObqsSwtGkZWsV21pMVDkD1zVPIJ9f0yX54znK8 Q1lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=n6RRuYZ8EGGXTpGZvsOKW/oYziHM0vCJPjdxKK9QfP8=; b=RioW1mAnU3GgljRVs0JZiQRGGEIOxe2SMzwPIDU0W7fzuYudoXLDoMN9gXn35xFfcU Q2o3mDt8iuwPM59D4JWkLWwidW1x4VAf84hmBAGfLio7+NFnwpLy15q9nIJxXMXxBDDm SlCHcB+x8AB8ZIyE/bpQln69JNFHm4SL0a3YtPQ+Vf5zV7aDATBELKRN+FNDjPmdMooz VgutgDugd97mT+cZWDMxfrmJKO6/Nw5dLIt/THMUueusVthOfUD0oNg3fPUZ/dFBPB/E rZtbC6tOjAHyz4tVmglhc3/0m/0EkJBSaLnAKWfKO1vlISIML4QS7zNYMpfmoLXWoWxr sTjQ== X-Gm-Message-State: AOAM530dl9/V8rTjaUCl2hUY9SRqDu/zKLPR4PVQickely4N+L07v6Ws /o1yjRV5kfQLdfFf0XehkUA= X-Google-Smtp-Source: ABdhPJy+Bhg02UrR6EUU7nIp/RZlfsHKVNh0/aLRhJdggPjtZEe9ZOqSEYDljYp/dpQUQlWvLHykMA== X-Received: by 2002:a7b:cb93:: with SMTP id m19mr522874wmi.45.1610058367428; Thu, 07 Jan 2021 14:26:07 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: libvir-list@redhat.com, Paolo Bonzini , Laurent Vivier , kvm@vger.kernel.org, Jiaxun Yang , Aurelien Jarno , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Paul Burton , Richard Henderson Subject: [PULL 37/66] target/mips: Introduce ase_msa_available() helper Date: Thu, 7 Jan 2021 23:22:24 +0100 Message-Id: <20210107222253.20382-38-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Instead of accessing CP0_Config3 directly and checking the 'MSA Present' bit, introduce an explicit helper, making the code easier to read. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Jiaxun Yang Message-Id: <20201208003702.4088927-2-f4bug@amsat.org> --- target/mips/cpu.h | 6 ++++++ target/mips/cpu.c | 2 +- target/mips/kvm.c | 12 ++++++------ target/mips/translate.c | 6 ++---- 4 files changed, 15 insertions(+), 11 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 9c45744c5c1..b9e227a30e9 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1299,6 +1299,12 @@ bool cpu_type_supports_cps_smp(const char *cpu_type); bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask); bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa); =20 +/* Check presence of MSA implementation */ +static inline bool ase_msa_available(CPUMIPSState *env) +{ + return env->CP0_Config3 & (1 << CP0C3_MSAP); +} + /* Check presence of multi-threading ASE implementation */ static inline bool ase_mt_available(CPUMIPSState *env) { diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 55c6a054bba..45375ebc45c 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -532,7 +532,7 @@ static void mips_cpu_reset(DeviceState *dev) } =20 /* MSA */ - if (env->CP0_Config3 & (1 << CP0C3_MSAP)) { + if (ase_msa_available(env)) { msa_reset(env); } =20 diff --git a/target/mips/kvm.c b/target/mips/kvm.c index a5b6fe35dbc..84fb10ea35d 100644 --- a/target/mips/kvm.c +++ b/target/mips/kvm.c @@ -79,7 +79,7 @@ int kvm_arch_init_vcpu(CPUState *cs) } } =20 - if (kvm_mips_msa_cap && env->CP0_Config3 & (1 << CP0C3_MSAP)) { + if (kvm_mips_msa_cap && ase_msa_available(env)) { ret =3D kvm_vcpu_enable_cap(cs, KVM_CAP_MIPS_MSA, 0, 0); if (ret < 0) { /* mark unsupported so it gets disabled on reset */ @@ -105,7 +105,7 @@ void kvm_mips_reset_vcpu(MIPSCPU *cpu) warn_report("KVM does not support FPU, disabling"); env->CP0_Config1 &=3D ~(1 << CP0C1_FP); } - if (!kvm_mips_msa_cap && env->CP0_Config3 & (1 << CP0C3_MSAP)) { + if (!kvm_mips_msa_cap && ase_msa_available(env)) { warn_report("KVM does not support MSA, disabling"); env->CP0_Config3 &=3D ~(1 << CP0C3_MSAP); } @@ -618,7 +618,7 @@ static int kvm_mips_put_fpu_registers(CPUState *cs, int= level) * FPU register state is a subset of MSA vector state, so don't pu= t FPU * registers if we're emulating a CPU with MSA. */ - if (!(env->CP0_Config3 & (1 << CP0C3_MSAP))) { + if (!ase_msa_available(env)) { /* Floating point registers */ for (i =3D 0; i < 32; ++i) { if (env->CP0_Status & (1 << CP0St_FR)) { @@ -637,7 +637,7 @@ static int kvm_mips_put_fpu_registers(CPUState *cs, int= level) } =20 /* Only put MSA state if we're emulating a CPU with MSA */ - if (env->CP0_Config3 & (1 << CP0C3_MSAP)) { + if (ase_msa_available(env)) { /* MSA Control Registers */ if (level =3D=3D KVM_PUT_FULL_STATE) { err =3D kvm_mips_put_one_reg(cs, KVM_REG_MIPS_MSA_IR, @@ -698,7 +698,7 @@ static int kvm_mips_get_fpu_registers(CPUState *cs) * FPU register state is a subset of MSA vector state, so don't sa= ve FPU * registers if we're emulating a CPU with MSA. */ - if (!(env->CP0_Config3 & (1 << CP0C3_MSAP))) { + if (!ase_msa_available(env)) { /* Floating point registers */ for (i =3D 0; i < 32; ++i) { if (env->CP0_Status & (1 << CP0St_FR)) { @@ -717,7 +717,7 @@ static int kvm_mips_get_fpu_registers(CPUState *cs) } =20 /* Only get MSA state if we're emulating a CPU with MSA */ - if (env->CP0_Config3 & (1 << CP0C3_MSAP)) { + if (ase_msa_available(env)) { /* MSA Control Registers */ err =3D kvm_mips_get_one_reg(cs, KVM_REG_MIPS_MSA_IR, &env->msair); diff --git a/target/mips/translate.c b/target/mips/translate.c index 69fa8a50790..c01db5f9d39 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -24920,8 +24920,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) gen_trap(ctx, op1, rs, rt, -1); break; case OPC_LSA: /* OPC_PMON */ - if ((ctx->insn_flags & ISA_MIPS_R6) || - (env->CP0_Config3 & (1 << CP0C3_MSAP))) { + if ((ctx->insn_flags & ISA_MIPS_R6) || ase_msa_available(env)) { decode_opc_special_r6(env, ctx); } else { /* Pmon entry point, also R4010 selsl */ @@ -25023,8 +25022,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) } break; case OPC_DLSA: - if ((ctx->insn_flags & ISA_MIPS_R6) || - (env->CP0_Config3 & (1 << CP0C3_MSAP))) { + if ((ctx->insn_flags & ISA_MIPS_R6) || ase_msa_available(env)) { decode_opc_special_r6(env, ctx); } break; --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) client-ip=209.85.221.53; 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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id r13sm10551180wrt.10.2021.01.07.14.26.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:26:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gpgHQHdilrFY/Au0x7qNpr3WUr1jSj6gUqKW5wcmkNw=; b=e7okNRHBZtMqgGM6d5VNmV9C7y+TdjUXNAA8R5c9aj9y+IDIowU9RL2Hqz+LPtcyMC 0L1s7+txvq7SZt9mQT7Kf8+YW0qXTa4X52bjKfCvZD60Y27a+NdtCwqjP5yXe8+OS42o D9TOnCzW2D5L00uWnL2WPnta0DxDCKGH4rokFeIkPGhXzAMxPcuh/49gKSrZtqQbpHlB MQkAhbqs/NdILIs/1iRc5oMJCsYwRResxCBWCf7YDkxKwdcPJG0wtwpC69Ck8TrbHLWW RL/C0tPAI/Uvs/xqHllBw7hhYYPX5czkP22v/7L3/i3p5J/5AfaOAIJuR6ArKuEaN9AY fBzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=gpgHQHdilrFY/Au0x7qNpr3WUr1jSj6gUqKW5wcmkNw=; b=V1CmLJX+D4GrjZhzlFroskUBOKWSVqDcQtSYuPHcqGTLuXVUBipNv9aPin7E2W98oW GJ658hH0tas2eqyFMpohWxTAKQPxQS1jOrqOF88fsMpa/YMYFORjpGa2KtpgahyR2vwr SGJwZsp/ViSi9/+rdbDeNMF4Kg+OSgKoCoOrLhDyoIgaxu3VxPGyAAwEvNdg5HZediJN rsW/JpyaFOfxnDB6QXvoUYYWe9RwVpwDoIjNwpfIgJ9CQ8sv259kFvNXKhDOS0NpVyS7 qB9khDxGb6hGIcYOHvqYChLJLYAA12I5cOavRFcPIiZTOsd1yhxQAgEiJtR7No/eY21Z MSZQ== X-Gm-Message-State: AOAM533xe6k7iqjxfmCsy2p7TkHj6ePCjh3xxJOCU5BehNsIsPrL/AxU 0AnpROTK5bUADuX2brkLRkA= X-Google-Smtp-Source: ABdhPJxkJD3JxPHzQTm/T+0q95uHk/ybzsKYtj/FjAirlGxa6q54t6h5V2wZ+EtDdMERaIxkpjsp/w== X-Received: by 2002:adf:e60f:: with SMTP id p15mr699194wrm.60.1610058372562; Thu, 07 Jan 2021 14:26:12 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: libvir-list@redhat.com, Paolo Bonzini , Laurent Vivier , kvm@vger.kernel.org, Jiaxun Yang , Aurelien Jarno , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Paul Burton , Richard Henderson Subject: [PULL 38/66] target/mips: Simplify msa_reset() Date: Thu, 7 Jan 2021 23:22:25 +0100 Message-Id: <20210107222253.20382-39-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Call msa_reset() unconditionally, but only reset the MSA registers if MSA is implemented. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Jiaxun Yang Message-Id: <20201208003702.4088927-3-f4bug@amsat.org> --- target/mips/cpu.c | 5 +---- target/mips/cpu-defs.c.inc | 4 ++++ 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 45375ebc45c..4c590b90b25 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -531,10 +531,7 @@ static void mips_cpu_reset(DeviceState *dev) env->hflags |=3D MIPS_HFLAG_M16; } =20 - /* MSA */ - if (ase_msa_available(env)) { - msa_reset(env); - } + msa_reset(env); =20 compute_hflags(env); restore_fp_status(env); diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index 535d4c0c702..fe0f47aadf8 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -978,6 +978,10 @@ static void mvp_init(CPUMIPSState *env) =20 static void msa_reset(CPUMIPSState *env) { + if (!ase_msa_available(env)) { + return; + } + #ifdef CONFIG_USER_ONLY /* MSA access enabled */ env->CP0_Config5 |=3D 1 << CP0C5_MSAEn; --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.54 as permitted sender) client-ip=209.85.128.54; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f54.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1610058379; cv=none; d=zohomail.com; s=zohoarc; b=UViuoJDs1My3QWp+Fxm4jsgPtYwtXHvr4cZ+EnA41P9OhjhVvlNFCmkbIrxKoBq0oCskSSM1Y37IVsSIS4NpR+/KHc/FqWe+iIEZQhNGEB0eZtUimatMY7/oDwalfL2Np/dhGxZY1QOSBAhXf7qOCXPor6nKJbFN6HBD0JfTAm0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610058379; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lMAe3ErcpY6GT5lLpyLZ/gixtllrok8K5UMFavL1mtI=; b=YGicSeyMpBIZB+06JGal5glePDpuQl973D/8wUJadrYVPVDLL1sCEB26WiVF2mLx04SjufjamysLzPzTD0N0LKQ8gRf787y0+MOkvJ9mMkuXtwosW7YZc7buYYesAS1aKgs0PYeD9o0bYviCi5AxaSrDHbYcAk/9BnmqVHtm/iI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) by mx.zohomail.com with SMTPS id 1610058379577137.45292336362888; Thu, 7 Jan 2021 14:26:19 -0800 (PST) Received: by mail-wm1-f54.google.com with SMTP id v14so6366621wml.1 for ; Thu, 07 Jan 2021 14:26:18 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (241.red-88-10-103.dynamicip.rima-tde.net. [88.10.103.241]) by smtp.gmail.com with ESMTPSA id i7sm10218260wrv.12.2021.01.07.14.26.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:26:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lMAe3ErcpY6GT5lLpyLZ/gixtllrok8K5UMFavL1mtI=; b=PWPFGmWNroy2+z8o046XV+RRv5ussCHdG8BVtGR00vYOqM9oX9LgL8nM6wOfr7q+9Y nzfGMFsMNq7GXwYqFxprRvZ3rQttFpo1vdLm08aKLmNfHhcpdVwN5L/4UBReJ6TY63KQ WWzsliI/pIz/Bx05xQ4XrJdUJHPHHq0unkex/6xe2UnUtwXlMMIT9E/QZrxtxkot08oA iaTh7YelP6zcHWaTMh2VFmgUOCeqhAIIAE80zpOr4LYQBj4KEBvhTp6Ei9Idq0zX6iDE +ZK2ZCgJ90WtNKH4N0IbrZCKk1Vpmbml60Vu0AR/u39KP11q2FrwE9jZvBbZ/2BNJqg0 F2qg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=lMAe3ErcpY6GT5lLpyLZ/gixtllrok8K5UMFavL1mtI=; b=aDIqOW3kOwKA9V6qNsmdR/+add2lf8nISxILzDpu9NMn2GBieEw4uBxsbVjc9k/flK NDflO9fdXJq3u4XegHQussN1rDkCflIR27+Ui7sb/UPO+IcTbU/7YBeNUOg7TljpxQm6 eolhtTg46nP5nGB8sGQtyPzl1OcJkESFtd7rhZceqouParNhon1/2pvJmUDmhKjAI8zQ Z7WmY5bwzN7GsncfvKk9mT9lX6zqN+yMoyQv2OlwjalU0wjNmE5+HThHaZryfKMB7bgl 5/5Ld9oaHhnj/rlbeP/w9AeroP20EO6cgwpy54o3BDq1S85ux7Y6CNR8nVCwU3lrWYkh v1pw== X-Gm-Message-State: AOAM5319xjWfADxup0kXh+g4qWAtyAkSA7zXahxCpEZFpHz4n9GefSb9 7yV+ZSlZZerl1D4zo1rFdzM= X-Google-Smtp-Source: ABdhPJyGDwF7m1uVQYBA4ggoEa6lGAw05oUCdgZak1buPwMk2BLm6IfyffQb+MhOHXU/UoyBigfjwQ== X-Received: by 2002:a05:600c:d8:: with SMTP id u24mr499760wmm.103.1610058377747; Thu, 07 Jan 2021 14:26:17 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: libvir-list@redhat.com, Paolo Bonzini , Laurent Vivier , kvm@vger.kernel.org, Jiaxun Yang , Aurelien Jarno , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Paul Burton , Richard Henderson Subject: [PULL 39/66] target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA Date: Thu, 7 Jan 2021 23:22:26 +0100 Message-Id: <20210107222253.20382-40-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) MSA presence is expressed by the MSAP bit of CP0_Config3. We don't need to check anything else. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Jiaxun Yang Message-Id: <20201208003702.4088927-4-f4bug@amsat.org> --- target/mips/internal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 9a7698019e2..1048781bcf4 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -378,7 +378,7 @@ static inline void compute_hflags(CPUMIPSState *env) env->hflags |=3D MIPS_HFLAG_COP1X; } } - if (env->insn_flags & ASE_MSA) { + if (ase_msa_available(env)) { if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) { env->hflags |=3D MIPS_HFLAG_MSA; } --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.51 as permitted sender) client-ip=209.85.128.51; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f51.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1610058384; cv=none; d=zohomail.com; s=zohoarc; b=FAEi/fgSJ/3q6qwASR2D30gtbrO4FJ++zjgK/7UwX9vNx6Loxv5niwCllG9yZZNs22q1ZYAZGCW0zCJlh4AV26FhAkz4oYpKcMDfrIW18hgsjx9Fls/2FUkvODNzkRdDQIKRbasxWUuw4wn1VLljQ9xDiGOeRN7GRavCjchCy68= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610058384; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=VfYlsVfQrXnabjTXXkFkj4bzS4FCzoFbCGst2ujqd0Q=; b=nF5Ek3PfyF+jjd94ZWHba86I9bFvlzqgXn4rEobd7/8cPREnetTHhXep1YyfvZXx5rY+C69IiGnCyxtd3ZA6jYdA/2/l9Vw9yKWf1BP0dJWnrC172cFpkvjqzDPfhDs6sNtDewAYFsHv6xeEa+4fEaMe/VLd1Hyov//8eVMJysk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) by mx.zohomail.com with SMTPS id 1610058384549300.8131006327292; Thu, 7 Jan 2021 14:26:24 -0800 (PST) Received: by mail-wm1-f51.google.com with SMTP id y23so6839939wmi.1 for ; Thu, 07 Jan 2021 14:26:23 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (241.red-88-10-103.dynamicip.rima-tde.net. [88.10.103.241]) by smtp.gmail.com with ESMTPSA id z6sm10681403wrw.58.2021.01.07.14.26.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:26:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VfYlsVfQrXnabjTXXkFkj4bzS4FCzoFbCGst2ujqd0Q=; b=pW1Zb8pev9GO4TUM9GY6gZDLX4t4GaeD4uraukSwhqJJkoUA4i4lRS5n497MFqD4eF VHvCngigU9DZrCP5g6LmBL736BkvhGwf9Fe4Bqx3yDpfwGcX6u3e8MtfZRLqrYdXCem7 vZ4fkI0op3/4/p0tKvuH+IVaYT56LZOTWJbVC0aZ8Zas6hX3qwvLmjMpt93Xoaaus6ii yoWxFhcczE4vkgUQIaVqdRPE3SWP4JvkY1XuICN6279OG4Vy2f4cLe6vmaQTBbkFQ+Tk JBiKA0DPw3QG/OndqLZPXRTkfZOmGbdpZ0WTBkSFC1Us1qG7f6eTSFbJoAqwi065YXD2 okfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=VfYlsVfQrXnabjTXXkFkj4bzS4FCzoFbCGst2ujqd0Q=; b=QxwQEq9WhTnOVgvfb8z8+T5ALfsgsdLXVp21s+UnH7BgFhGciEOMCeyf00d8PE53n7 UbvSHW9PtCcvwcKkXovUlXjR8o3/o8rY+wzhBDH60iKYbmV4eabnzOlOiqjjjAN5Tpy/ rSiBJClFIvXqd5BAghl7UiceWSybtkV7HwZgnv4V7EHGwUpgH4oyp2vxjRvsqNYnSPFD D+r10v16Dd7SptxXMExJe+iPVWwKAPVkvdj0KzAFX9AIMmbR8ACgeyemONcSUSr11z1/ XSxh4DCougkL6TY+EJFUbOjAWNtkMDpht7U9GHfSYEG6Lh8DAl1MdhvRqxkf6oOoE6XF A1OQ== X-Gm-Message-State: AOAM533Ryv15lqBJdqZObWz4izE6mx/OgKHaF+KXaN61pAHAn5q7LiQ5 7/7wYrn4TrKbGLx6ZAEKGQw= X-Google-Smtp-Source: ABdhPJyuyk/uuo1jE+1Ma9y+rdP3wcRZcepOSreGLlzAjvYUHlv2HHczclLyJP+4aKOK9Wz7lwVN/w== X-Received: by 2002:a7b:c85a:: with SMTP id c26mr503813wml.160.1610058382799; Thu, 07 Jan 2021 14:26:22 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: libvir-list@redhat.com, Paolo Bonzini , Laurent Vivier , kvm@vger.kernel.org, Jiaxun Yang , Aurelien Jarno , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Paul Burton , Richard Henderson Subject: [PULL 40/66] target/mips: Simplify MSA TCG logic Date: Thu, 7 Jan 2021 23:22:27 +0100 Message-Id: <20210107222253.20382-41-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Only decode MSA opcodes if MSA is present (implemented). Now than check_msa_access() will only be called if MSA is present, the only way to have MIPS_HFLAG_MSA unset is if MSA is disabled (bit CP0C5_MSAEn cleared, see previous commit). Therefore we can remove the 'reserved instruction' exception. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Jiaxun Yang Message-Id: <20201208003702.4088927-5-f4bug@amsat.org> --- target/mips/translate.c | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index c01db5f9d39..e3cea5899f3 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28568,13 +28568,8 @@ static inline int check_msa_access(DisasContext *c= tx) } =20 if (unlikely(!(ctx->hflags & MIPS_HFLAG_MSA))) { - if (ctx->insn_flags & ASE_MSA) { - generate_exception_end(ctx, EXCP_MSADIS); - return 0; - } else { - gen_reserved_instruction(ctx); - return 0; - } + generate_exception_end(ctx, EXCP_MSADIS); + return 0; } return 1; } @@ -30418,7 +30413,7 @@ static void gen_msa_vec(CPUMIPSState *env, DisasCon= text *ctx) static void gen_msa(CPUMIPSState *env, DisasContext *ctx) { uint32_t opcode =3D ctx->opcode; - check_insn(ctx, ASE_MSA); + check_msa_access(ctx); =20 switch (MASK_MSA_MINOR(opcode)) { @@ -31048,9 +31043,11 @@ static bool decode_opc_legacy(CPUMIPSState *env, D= isasContext *ctx) case OPC_BNZ_H: case OPC_BNZ_W: case OPC_BNZ_D: - check_insn(ctx, ASE_MSA); - gen_msa_branch(env, ctx, op1); - break; + if (ase_msa_available(env)) { + gen_msa_branch(env, ctx, op1); + break; + } + /* fall through */ default: MIPS_INVAL("cp1"); gen_reserved_instruction(ctx); @@ -31239,7 +31236,9 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) #endif } else { /* MDMX: Not implemented. */ - gen_msa(env, ctx); + if (ase_msa_available(env)) { + gen_msa(env, ctx); + } } break; case OPC_PCREL: --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 63.128.21.124 as permitted sender) client-ip=63.128.21.124; envelope-from=libvir-list-bounces@redhat.com; helo=us-smtp-delivery-124.mimecast.com; Authentication-Results: mx.zohomail.com; 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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id l5sm10517666wrv.44.2021.01.07.14.26.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:26:27 -0800 (PST) X-MC-Unique: tD8ZYyWRN_6jKdgCZK4DKw-1 X-MC-Unique: SZ1nsYkNO6GmdtgH74HEPQ-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=sIZITomoctnrg7h438bGjGhxwrMRbJgeE72R2oM+qvs=; b=CzRYgWjwwO3xDRhSRRKT8iOhGth1qBuvwLMcmFKpy5Uc2hyg1OeoWjVzwCZlUA5qIa swgeWPmYy93yrvoB5n6Hqnlrs3HQ6S4yQXARka4AN0qjrNIfVXwLwebhBiVH1ho3Ts3a zFpEmzeFRDInAufqeyA9xBGpQyYsAgO6WKkVrGMWnamAoQVfRqUjNRSsSJYFDto9yWQu ZaAUnfI2JDzlVI2M6K0iU+DwwlkFbjPslN3zs9IzMdVSBFR/6QtjGYQ+eyfUKTnIv0MV EdnpOzQPRCO1xvy9PS4UoA/qvMSMN8Wht7BQfSGlio/DQcTHr2mXye5L+kNdz2TFkFy1 go7Q== X-Gm-Message-State: AOAM531I9wHBret+1H9Ufh2A5wDieIdeY/L6e9TnU6dyRajP1gVuVgS1 90Qnbp0RfR8atp/K8UwGd1A= X-Google-Smtp-Source: ABdhPJyyA9DkDecms4e6imKW1wY4KetEc5pLg7CYsciqR3ze1CMjyrI87mZDUwtj/Zw1OWmM6byPBg== X-Received: by 2002:adf:c387:: with SMTP id p7mr668077wrf.95.1610058387817; Thu, 07 Jan 2021 14:26:27 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 41/66] target/mips: Remove now unused ASE_MSA definition Date: Thu, 7 Jan 2021 23:22:28 +0100 Message-Id: <20210107222253.20382-42-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.79 on 10.11.54.5 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable We don't use ASE_MSA anymore (replaced by ase_msa_available() checking MSAP bit from CP0_Config3). Remove it. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Jiaxun Yang Message-Id: <20201208003702.4088927-6-f4bug@amsat.org> --- target/mips/mips-defs.h | 1 - target/mips/cpu-defs.c.inc | 8 ++++---- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 97866019a72..6b8e6800115 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -34,7 +34,6 @@ #define ASE_MT 0x0000000040000000ULL #define ASE_SMARTMIPS 0x0000000080000000ULL #define ASE_MICROMIPS 0x0000000100000000ULL -#define ASE_MSA 0x0000000200000000ULL /* * bits 40-51: vendor-specific base instruction sets */ diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index fe0f47aadf8..3d44b394773 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -410,7 +410,7 @@ const mips_def_t mips_defs[] =3D .CP1_fcr31_rw_bitmask =3D 0xFF83FFFF, .SEGBITS =3D 32, .PABITS =3D 40, - .insn_flags =3D CPU_MIPS32R5 | ASE_MSA, + .insn_flags =3D CPU_MIPS32R5, .mmu_type =3D MMU_TYPE_R4000, }, { @@ -723,7 +723,7 @@ const mips_def_t mips_defs[] =3D .MSAIR =3D 0x03 << MSAIR_ProcID, .SEGBITS =3D 48, .PABITS =3D 48, - .insn_flags =3D CPU_MIPS64R6 | ASE_MSA, + .insn_flags =3D CPU_MIPS64R6, .mmu_type =3D MMU_TYPE_R4000, }, { @@ -763,7 +763,7 @@ const mips_def_t mips_defs[] =3D .MSAIR =3D 0x03 << MSAIR_ProcID, .SEGBITS =3D 48, .PABITS =3D 48, - .insn_flags =3D CPU_MIPS64R6 | ASE_MSA, + .insn_flags =3D CPU_MIPS64R6, .mmu_type =3D MMU_TYPE_R4000, }, { @@ -889,7 +889,7 @@ const mips_def_t mips_defs[] =3D .CP1_fcr31_rw_bitmask =3D 0xFF83FFFF, .SEGBITS =3D 48, .PABITS =3D 48, - .insn_flags =3D CPU_LOONGSON3A | ASE_MSA, + .insn_flags =3D CPU_LOONGSON3A, .mmu_type =3D MMU_TYPE_R4000, }, { --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) client-ip=209.85.221.44; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f44.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1610058394; cv=none; d=zohomail.com; s=zohoarc; b=ZFQQ/0yMkbDcqbR/7j8mNQOWr3bB8UK+F4lWjDX4pheyH257YBZpzQ818f92tNNb4f8x7Y7KqfCpRvufzqz+4KQPwdomx2oSmgQbd72RVyFYU0FreQmOciUUQSIsKCd8fowsEDSwk3eZcpevZ0LSIXx5rRKvnFDmTUq1zbcjodY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610058394; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=SLgFG7YcdrjVHzWVWnO7xpT2n5lITWbqMk/I8sXWfOk=; b=cMyKaRZtGIchHjDyV4E938pDYa46ZxqvsjzYtrxhS6F8yJy93F7Koqv4Y6kKEdJgicNYgNp6i2E9571kEtp5A5O04iqeU3ZLoiAkx6wSbY2ZdoXogYdC8qbweGJqVLUSyxDHRV8cyIv5NInuNeHPRxpowlotIfeuzIo2PquSPVY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) by mx.zohomail.com with SMTPS id 1610058394564570.9642368661142; Thu, 7 Jan 2021 14:26:34 -0800 (PST) Received: by mail-wr1-f44.google.com with SMTP id r7so7120342wrc.5 for ; Thu, 07 Jan 2021 14:26:33 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (241.red-88-10-103.dynamicip.rima-tde.net. [88.10.103.241]) by smtp.gmail.com with ESMTPSA id o124sm10003482wmb.5.2021.01.07.14.26.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:26:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SLgFG7YcdrjVHzWVWnO7xpT2n5lITWbqMk/I8sXWfOk=; b=d/2kXACMCYQclLA1uft/PbEWTToOKXFyqPw7O1axl2zel4sbNPxpmJ5XC3TjHwoKyb CEzzvJI4PAqaea5ghcON4a6gP4M65sPAYy7wEC2imtZENY4uqrK0U6GLXZoPEZmTbNFO Np8//S9+Sl80Rp9AsJZ/sD/GMGolPSyN7A8loIZENr/TZNM45KsGZ1hIzHPRSqUOIj1Q r8lsYqMDqomOL6eczMsHZ4A5ZPjr6gArW2M+DOv6QJzEmGkAflMzXJ1cDfjaBSf5F5cj oC5/V/JYLot/Yg2ZuVl7Hc40x8cq5/jIAU/b4ld7YGv+wvO0wTR70yV/5b+r/zJAPjES PgcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=SLgFG7YcdrjVHzWVWnO7xpT2n5lITWbqMk/I8sXWfOk=; b=KUsC4rea1rGfzhfMM5m7boDdqtto5i8ir+XRYoDOS484oKx20IDTtMr1AaicQXRe/U CyIsWbrM6uCGrFxb4LpEpp88MuvMbCcnEDs11RiueuPXTmJ/oXfk6GVniDBACUyqV5L7 TOwtRY+GAjMOlm9cvXWB4j1Xgqj8St0rj8RixZx5ubtZ7SnJ7qUDHLOj2yrrCDu6Ahsx uXqBPz0TwIXnzo7tZEpx2CwaxYo3pWAcjbe6iMyJzWopAvUcPcmp0SiEg8QZxmOvz7UA p13wMfzTwg50Ppp+vyb3BpruHl+MScTdCLdKUGgftlxjtp65QdeCVa2TAua9HL9TjJ6C xt+A== X-Gm-Message-State: AOAM532lNVe0AfA/u7r7C3D3Loj6o3PQJ++XGD8vtHYL6yJTzPHFbL0f eq8V16aV1G2GFKeXPDgeLv8= X-Google-Smtp-Source: ABdhPJwABwkMalCqlOIOuUNqZu3FWRSiPZD48Pp+/a8H7j6j4kjy5sVuElCjluc7YUiLCJi3AklShw== X-Received: by 2002:a5d:6944:: with SMTP id r4mr688892wrw.134.1610058392803; Thu, 07 Jan 2021 14:26:32 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: libvir-list@redhat.com, Paolo Bonzini , Laurent Vivier , kvm@vger.kernel.org, Jiaxun Yang , Aurelien Jarno , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Paul Burton , Richard Henderson Subject: [PULL 42/66] target/mips: Alias MSA vector registers on FPU scalar registers Date: Thu, 7 Jan 2021 23:22:29 +0100 Message-Id: <20210107222253.20382-43-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Commits 863f264d10f ("add msa_reset(), global msa register") and cb269f273fd ("fix multiple TCG registers covering same data") removed the FPU scalar registers and replaced them by aliases to the MSA vector registers. It is not very clear to have FPU registers displayed with MSA register names, even if MSA ASE is not present. Instead of aliasing FPU registers to the MSA ones (even when MSA is absent), we now alias the MSA ones to the FPU ones (only when MSA is present). Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Jiaxun Yang Message-Id: <20201208003702.4088927-7-f4bug@amsat.org> --- target/mips/translate.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index e3cea5899f3..30354fee828 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -31561,16 +31561,20 @@ void mips_tcg_init(void) offsetof(CPUMIPSState, active_tc.gpr[i]), regnames[i]); - for (i =3D 0; i < 32; i++) { int off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); - msa_wr_d[i * 2] =3D - tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2]); + + fpu_f64[i] =3D tcg_global_mem_new_i64(cpu_env, off, fregnames[i]); + } + /* MSA */ + for (i =3D 0; i < 32; i++) { + int off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); + /* - * The scalar floating-point unit (FPU) registers are mapped on - * the MSA vector registers. + * The MSA vector registers are mapped on the + * scalar floating-point unit (FPU) registers. */ - fpu_f64[i] =3D msa_wr_d[i * 2]; + msa_wr_d[i * 2] =3D fpu_f64[i]; off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); msa_wr_d[i * 2 + 1] =3D tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1= ]); --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 63.128.21.124 as permitted sender) client-ip=63.128.21.124; envelope-from=libvir-list-bounces@redhat.com; helo=us-smtp-delivery-124.mimecast.com; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of redhat.com designates 63.128.21.124 as permitted sender) smtp.mailfrom=libvir-list-bounces@redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1610058414; cv=none; d=zohomail.com; s=zohoarc; b=AomnOuKSrS/lX03uNucqx4t+PpJIHGmBNQl4ag7LCAKrER3O979pKLnhyPH5+QoxP4TZ5v96N2+VFkNWPqX0QqUG2iJAzdffpZaujH++i7HiXhePOHU6DSKHp24rzw7INcyhh/sFIcy3yiDDFFUeUq5BoxmyoYi7ULh9mz7RqBw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610058414; 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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id c20sm9452590wmb.38.2021.01.07.14.26.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:26:37 -0800 (PST) X-MC-Unique: h0Pw8-WCM2eHo3D8XbQzGQ-1 X-MC-Unique: pqEoUYosMQmBPXA_D3nJnA-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=DQ4NcLmRVy40lLGUZw2vzkfPGYpNttR3tCsf5kFmz/8=; b=FwXLdCYiMPqUtdyJsztrp7TbEl+BMM8ymXuj/2JSYilW+Vmwp0y82FpExsN7VeURIZ xEVmp2FHVL9uPCe9omx0uPjO62qMS6ybcHoBk9OAuuItXtxH6zEZ7AjNQl1Zc67/zU14 3f1Cig87XdeGUT6WGLxVg67XPf2fcIuXSeNXConYn4Mdj0hhOmSzitlDLjoA6FBgKA08 X/l4HqOdeDZc+BlX5XUPj4M5XWs9rRVzZtGmEl4ILxfO0h66g7Ws+ejfFNwOvdrJD315 8G+/XjBvYFGvPkek4tPTcyRQJ8CwVgU3jRgG9gEo+03emQ0oqfe/H1hAqDjdnxy6EC2Z IPJg== X-Gm-Message-State: AOAM532QxCISqIBo5jZrA5+d1LqY9EsHwZgcQhDeKfUTvqsY/POodv/a djlV4jFSHkVsgZBlP8K8Mjg= X-Google-Smtp-Source: ABdhPJzthOoRVhYBVewfdJ5SzxIvoMQCudwx3jqR+BRb0cS7J1Aphov0/3GbpoYqe8QCK8ssEDuSNA== X-Received: by 2002:a5d:4704:: with SMTP id y4mr670512wrq.358.1610058397783; Thu, 07 Jan 2021 14:26:37 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 43/66] target/mips: Extract msa_translate_init() from mips_tcg_init() Date: Thu, 7 Jan 2021 23:22:30 +0100 Message-Id: <20210107222253.20382-44-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The msa_wr_d[] registers are only initialized/used by MSA. They are declared static. We want to move them to the new 'msa_translate.c' unit in few commits, without having to declare them global (with extern). Extract first the logic initialization of the MSA registers from the generic initialization. We will later move this function along with the MSA registers to the new C unit. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Jiaxun Yang Message-Id: <20201208003702.4088927-8-f4bug@amsat.org> --- target/mips/translate.h | 3 +++ target/mips/translate.c | 33 +++++++++++++++++++-------------- 2 files changed, 22 insertions(+), 14 deletions(-) diff --git a/target/mips/translate.h b/target/mips/translate.h index 402bc5e8846..b9cd315c7f4 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -162,4 +162,7 @@ extern TCGv bcond; } = \ } while (0) =20 +/* MSA */ +void msa_translate_init(void); + #endif diff --git a/target/mips/translate.c b/target/mips/translate.c index 30354fee828..bb9420b9f7f 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -31551,6 +31551,24 @@ void mips_cpu_dump_state(CPUState *cs, FILE *f, in= t flags) } } =20 +void msa_translate_init(void) +{ + int i; + + for (i =3D 0; i < 32; i++) { + int off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); + + /* + * The MSA vector registers are mapped on the + * scalar floating-point unit (FPU) registers. + */ + msa_wr_d[i * 2] =3D fpu_f64[i]; + off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); + msa_wr_d[i * 2 + 1] =3D + tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1= ]); + } +} + void mips_tcg_init(void) { int i; @@ -31566,20 +31584,7 @@ void mips_tcg_init(void) =20 fpu_f64[i] =3D tcg_global_mem_new_i64(cpu_env, off, fregnames[i]); } - /* MSA */ - for (i =3D 0; i < 32; i++) { - int off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); - - /* - * The MSA vector registers are mapped on the - * scalar floating-point unit (FPU) registers. - */ - msa_wr_d[i * 2] =3D fpu_f64[i]; - off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); - msa_wr_d[i * 2 + 1] =3D - tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1= ]); - } - + msa_translate_init(); cpu_PC =3D tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, active_tc.PC), "PC"= ); for (i =3D 0; i < MIPS_DSP_ACC; i++) { --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 63.128.21.124 as permitted sender) client-ip=63.128.21.124; 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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id a13sm10120831wrt.96.2021.01.07.14.26.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:26:42 -0800 (PST) X-MC-Unique: voAvfPC6PDGopRaHNQ8Hug-1 X-MC-Unique: KUo1O-ZxOduFUKBZeWtOzw-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=GAlr7Yg/YIz2ixZWT9Zck2hMBMZxfl4QxyfdbZb/wG0=; b=QC3GB92A3CgoAoAKo0s79Vo01GKOLxAwvdvJao/mXVNLdonyumov6f1GoZ4Y68WQgs 0uOmXIg5tY3BKgoW+h5xsVGFewpfERZXdhpRitY9cpyCHoB3vDBSHStMYpttj0mDDADK P06gVvXjhyMc7zXuVfCPF1nGbwXXdTr84THxzlJqbvZUuUCD409iaBLvI3jAk8milp8U J3Uyw8eiu/g7HPODTuCTdAmZadsTUAtXFteNMWQUnCTkdzin7Xd1b+uf4Fjxl+dVDBP5 ZrU1CIPID8QVfi3iBrZZZudHc/U6CZ9EgpcfgNsZ/VUzFhLGyyjqdNu6uWEnKOgWV+Ma Vv9w== X-Gm-Message-State: AOAM533IjjptbsVdjNjTH7uiSLw77MmUvJcJNTsXYEeznR/4LI/Nw+ZL ue+Xvmc/3wcidZlaZ1Nj3SJ+AGSd+0c= X-Google-Smtp-Source: ABdhPJzrxFZaLRADmPQ4Oo3Bc9rK/itUQ3lN9+wjKyg+kQQcuWXlyTAXIVVmCwkC3yrOm0yPGUVDDQ== X-Received: by 2002:adf:ec8c:: with SMTP id z12mr687401wrn.208.1610058403161; Thu, 07 Jan 2021 14:26:43 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 44/66] target/mips: Remove CPUMIPSState* argument from gen_msa*() methods Date: Thu, 7 Jan 2021 23:22:31 +0100 Message-Id: <20210107222253.20382-45-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The gen_msa*() methods don't use the "CPUMIPSState *env" argument. Remove it to simplify. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Jiaxun Yang Message-Id: <20201208003702.4088927-9-f4bug@amsat.org> --- target/mips/translate.c | 57 ++++++++++++++++++++--------------------- 1 file changed, 28 insertions(+), 29 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index bb9420b9f7f..18cebe26bde 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28615,7 +28615,7 @@ static void gen_check_zero_element(TCGv tresult, ui= nt8_t df, uint8_t wt) tcg_temp_free_i64(t1); } =20 -static void gen_msa_branch(CPUMIPSState *env, DisasContext *ctx, uint32_t = op1) +static void gen_msa_branch(DisasContext *ctx, uint32_t op1) { uint8_t df =3D (ctx->opcode >> 21) & 0x3; uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; @@ -28660,7 +28660,7 @@ static void gen_msa_branch(CPUMIPSState *env, Disas= Context *ctx, uint32_t op1) ctx->hflags |=3D MIPS_HFLAG_BDS32; } =20 -static void gen_msa_i8(CPUMIPSState *env, DisasContext *ctx) +static void gen_msa_i8(DisasContext *ctx) { #define MASK_MSA_I8(op) (MASK_MSA_MINOR(op) | (op & (0x03 << 24))) uint8_t i8 =3D (ctx->opcode >> 16) & 0xff; @@ -28718,7 +28718,7 @@ static void gen_msa_i8(CPUMIPSState *env, DisasCont= ext *ctx) tcg_temp_free_i32(ti8); } =20 -static void gen_msa_i5(CPUMIPSState *env, DisasContext *ctx) +static void gen_msa_i5(DisasContext *ctx) { #define MASK_MSA_I5(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) uint8_t df =3D (ctx->opcode >> 21) & 0x3; @@ -28791,7 +28791,7 @@ static void gen_msa_i5(CPUMIPSState *env, DisasCont= ext *ctx) tcg_temp_free_i32(timm); } =20 -static void gen_msa_bit(CPUMIPSState *env, DisasContext *ctx) +static void gen_msa_bit(DisasContext *ctx) { #define MASK_MSA_BIT(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) uint8_t dfm =3D (ctx->opcode >> 16) & 0x7f; @@ -28875,7 +28875,7 @@ static void gen_msa_bit(CPUMIPSState *env, DisasCon= text *ctx) tcg_temp_free_i32(tws); } =20 -static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx) +static void gen_msa_3r(DisasContext *ctx) { #define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) uint8_t df =3D (ctx->opcode >> 21) & 0x3; @@ -29857,7 +29857,7 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCont= ext *ctx) tcg_temp_free_i32(tdf); } =20 -static void gen_msa_elm_3e(CPUMIPSState *env, DisasContext *ctx) +static void gen_msa_elm_3e(DisasContext *ctx) { #define MASK_MSA_ELM_DF3E(op) (MASK_MSA_MINOR(op) | (op & (0x3FF << 16))) uint8_t source =3D (ctx->opcode >> 11) & 0x1f; @@ -29889,8 +29889,7 @@ static void gen_msa_elm_3e(CPUMIPSState *env, Disas= Context *ctx) tcg_temp_free_i32(tsr); } =20 -static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx, uint32_t = df, - uint32_t n) +static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n) { #define MASK_MSA_ELM(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22))) uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; @@ -30000,7 +29999,7 @@ static void gen_msa_elm_df(CPUMIPSState *env, Disas= Context *ctx, uint32_t df, tcg_temp_free_i32(tdf); } =20 -static void gen_msa_elm(CPUMIPSState *env, DisasContext *ctx) +static void gen_msa_elm(DisasContext *ctx) { uint8_t dfn =3D (ctx->opcode >> 16) & 0x3f; uint32_t df =3D 0, n =3D 0; @@ -30019,17 +30018,17 @@ static void gen_msa_elm(CPUMIPSState *env, DisasC= ontext *ctx) df =3D DF_DOUBLE; } else if (dfn =3D=3D 0x3E) { /* CTCMSA, CFCMSA, MOVE.V */ - gen_msa_elm_3e(env, ctx); + gen_msa_elm_3e(ctx); return; } else { gen_reserved_instruction(ctx); return; } =20 - gen_msa_elm_df(env, ctx, df, n); + gen_msa_elm_df(ctx, df, n); } =20 -static void gen_msa_3rf(CPUMIPSState *env, DisasContext *ctx) +static void gen_msa_3rf(DisasContext *ctx) { #define MASK_MSA_3RF(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22))) uint8_t df =3D (ctx->opcode >> 21) & 0x1; @@ -30187,7 +30186,7 @@ static void gen_msa_3rf(CPUMIPSState *env, DisasCon= text *ctx) tcg_temp_free_i32(tdf); } =20 -static void gen_msa_2r(CPUMIPSState *env, DisasContext *ctx) +static void gen_msa_2r(DisasContext *ctx) { #define MASK_MSA_2R(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \ (op & (0x7 << 18))) @@ -30271,7 +30270,7 @@ static void gen_msa_2r(CPUMIPSState *env, DisasCont= ext *ctx) tcg_temp_free_i32(tdf); } =20 -static void gen_msa_2rf(CPUMIPSState *env, DisasContext *ctx) +static void gen_msa_2rf(DisasContext *ctx) { #define MASK_MSA_2RF(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \ (op & (0xf << 17))) @@ -30342,7 +30341,7 @@ static void gen_msa_2rf(CPUMIPSState *env, DisasCon= text *ctx) tcg_temp_free_i32(tdf); } =20 -static void gen_msa_vec_v(CPUMIPSState *env, DisasContext *ctx) +static void gen_msa_vec_v(DisasContext *ctx) { #define MASK_MSA_VEC(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21))) uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; @@ -30385,7 +30384,7 @@ static void gen_msa_vec_v(CPUMIPSState *env, DisasC= ontext *ctx) tcg_temp_free_i32(twt); } =20 -static void gen_msa_vec(CPUMIPSState *env, DisasContext *ctx) +static void gen_msa_vec(DisasContext *ctx) { switch (MASK_MSA_VEC(ctx->opcode)) { case OPC_AND_V: @@ -30395,13 +30394,13 @@ static void gen_msa_vec(CPUMIPSState *env, DisasC= ontext *ctx) case OPC_BMNZ_V: case OPC_BMZ_V: case OPC_BSEL_V: - gen_msa_vec_v(env, ctx); + gen_msa_vec_v(ctx); break; case OPC_MSA_2R: - gen_msa_2r(env, ctx); + gen_msa_2r(ctx); break; case OPC_MSA_2RF: - gen_msa_2rf(env, ctx); + gen_msa_2rf(ctx); break; default: MIPS_INVAL("MSA instruction"); @@ -30410,7 +30409,7 @@ static void gen_msa_vec(CPUMIPSState *env, DisasCon= text *ctx) } } =20 -static void gen_msa(CPUMIPSState *env, DisasContext *ctx) +static void gen_msa(DisasContext *ctx) { uint32_t opcode =3D ctx->opcode; =20 @@ -30420,15 +30419,15 @@ static void gen_msa(CPUMIPSState *env, DisasConte= xt *ctx) case OPC_MSA_I8_00: case OPC_MSA_I8_01: case OPC_MSA_I8_02: - gen_msa_i8(env, ctx); + gen_msa_i8(ctx); break; case OPC_MSA_I5_06: case OPC_MSA_I5_07: - gen_msa_i5(env, ctx); + gen_msa_i5(ctx); break; case OPC_MSA_BIT_09: case OPC_MSA_BIT_0A: - gen_msa_bit(env, ctx); + gen_msa_bit(ctx); break; case OPC_MSA_3R_0D: case OPC_MSA_3R_0E: @@ -30439,18 +30438,18 @@ static void gen_msa(CPUMIPSState *env, DisasConte= xt *ctx) case OPC_MSA_3R_13: case OPC_MSA_3R_14: case OPC_MSA_3R_15: - gen_msa_3r(env, ctx); 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Thu, 07 Jan 2021 14:26:48 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 45/66] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ() Date: Thu, 7 Jan 2021 23:22:32 +0100 Message-Id: <20210107222253.20382-46-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.79 on 10.11.54.5 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable In preparation of using the decodetree script, explode gen_msa_branch() as following: - OPC_BZ_V -> BxZ_V(EQ) - OPC_BNZ_V -> BxZ_V(NE) - OPC_BZ_[BHWD] -> BxZ(false) - OPC_BNZ_[BHWD] -> BxZ(true) Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Jiaxun Yang Message-Id: <20201208003702.4088927-10-f4bug@amsat.org> --- target/mips/translate.c | 71 ++++++++++++++++++++++++++++------------- 1 file changed, 49 insertions(+), 22 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 18cebe26bde..0e7b2abe8bb 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28615,49 +28615,76 @@ static void gen_check_zero_element(TCGv tresult, = uint8_t df, uint8_t wt) tcg_temp_free_i64(t1); } =20 +static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond) +{ + TCGv_i64 t0; + + check_msa_access(ctx); + + if (ctx->hflags & MIPS_HFLAG_BMASK) { + gen_reserved_instruction(ctx); + return true; + } + t0 =3D tcg_temp_new_i64(); + tcg_gen_or_i64(t0, msa_wr_d[wt << 1], msa_wr_d[(wt << 1) + 1]); + tcg_gen_setcondi_i64(cond, t0, t0, 0); + tcg_gen_trunc_i64_tl(bcond, t0); + tcg_temp_free_i64(t0); + + ctx->btarget =3D ctx->base.pc_next + (s16 << 2) + 4; + + ctx->hflags |=3D MIPS_HFLAG_BC; + ctx->hflags |=3D MIPS_HFLAG_BDS32; + + return true; +} + +static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool i= f_not) +{ + check_msa_access(ctx); + + if (ctx->hflags & MIPS_HFLAG_BMASK) { + gen_reserved_instruction(ctx); + return true; + } + + gen_check_zero_element(bcond, df, wt); + if (if_not) { + tcg_gen_setcondi_tl(TCG_COND_EQ, bcond, bcond, 0); + } + + ctx->btarget =3D ctx->base.pc_next + (s16 << 2) + 4; + ctx->hflags |=3D MIPS_HFLAG_BC; + ctx->hflags |=3D MIPS_HFLAG_BDS32; + + return true; +} + static void gen_msa_branch(DisasContext *ctx, uint32_t op1) { uint8_t df =3D (ctx->opcode >> 21) & 0x3; uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; int64_t s16 =3D (int16_t)ctx->opcode; =20 - check_msa_access(ctx); - - if (ctx->hflags & MIPS_HFLAG_BMASK) { - gen_reserved_instruction(ctx); - return; - } switch (op1) { case OPC_BZ_V: case OPC_BNZ_V: - { - TCGv_i64 t0 =3D tcg_temp_new_i64(); - tcg_gen_or_i64(t0, msa_wr_d[wt << 1], msa_wr_d[(wt << 1) + 1]); - tcg_gen_setcondi_i64((op1 =3D=3D OPC_BZ_V) ? - TCG_COND_EQ : TCG_COND_NE, t0, t0, 0); - tcg_gen_trunc_i64_tl(bcond, t0); - tcg_temp_free_i64(t0); - } + gen_msa_BxZ_V(ctx, wt, s16, (op1 =3D=3D OPC_BZ_V) ? + TCG_COND_EQ : TCG_COND_NE); break; case OPC_BZ_B: case OPC_BZ_H: case OPC_BZ_W: case OPC_BZ_D: - gen_check_zero_element(bcond, df, wt); + gen_msa_BxZ(ctx, df, wt, s16, false); break; case OPC_BNZ_B: case OPC_BNZ_H: case OPC_BNZ_W: case OPC_BNZ_D: - gen_check_zero_element(bcond, df, wt); - tcg_gen_setcondi_tl(TCG_COND_EQ, bcond, bcond, 0); + gen_msa_BxZ(ctx, df, wt, s16, true); break; } - - ctx->btarget =3D ctx->base.pc_next + (s16 << 2) + 4; - - ctx->hflags |=3D MIPS_HFLAG_BC; - ctx->hflags |=3D MIPS_HFLAG_BDS32; } =20 static void gen_msa_i8(DisasContext *ctx) --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) client-ip=216.205.24.124; envelope-from=libvir-list-bounces@redhat.com; helo=us-smtp-delivery-124.mimecast.com; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) smtp.mailfrom=libvir-list-bounces@redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1610058434; cv=none; d=zohomail.com; s=zohoarc; b=PQeO8XG7ThSbhIOJfWXWwfuokzhQ12kU5mxoMIK1IO+c4WEhMEz7Ww+C5EdhirUvFImubokkV6SsO5sh6w3YzxzUBxw8RP6hvb3aRnfINEzLB+sD8nV8sA0NVtMfnM+2g1b8RXYP7+zbtjM9xU0ZybN5Aqs7/WHQ+ceM9irZeRs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id n9sm10110262wrq.41.2021.01.07.14.26.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:26:52 -0800 (PST) X-MC-Unique: 5dlU0rtsM1aoh1108wbAaQ-1 X-MC-Unique: fkKojhYOM2yCkNocxeiHkQ-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=bnGMuEIL+4VmlV+xdWwg0SJvZ11jLh/bemgKxGT4D88=; b=LZ8GZ3Vj32hXVCDEDBws1HOItTzlDxBDsBD/aBqdkpyVtgYTd4pOx2R67TXIPZSCbw 1blI0Q6wmfkMrZF88t3ql6zWcK12sGge6AuXXYjTSjNgQS/cAckKau7Bu1/9HO5d7+Jw v9KNPqgAi4sOgxIjbpJw53snuHbtP37wQppLi98Ybvbpy5QQ1YQ1c+kHEYE9Gnh6V1q8 6+HTWlhP/0H5MELczFi8xkp2ZBHt47L06j50ftxYvH3BhIK/U8C55SD5H8h78p1WWSqb lUM0ZH/E/FlEK/Xifr2IFGMVYHLs6SzoVrMwIiokrf94p5TjMa5NktznD1Te8S71j1gd PDjw== X-Gm-Message-State: AOAM532IGn0Z4IZsxvP6gpq80D5/clF6Rrm+/fSCKdE0O+KxlxAzvowT lifZyJB7SluTlWHpWDGl++fSmo44bMk= X-Google-Smtp-Source: ABdhPJxePIlJhzELurqoS+K7alNqibaKNHaRCBr8+ZkgFJMw/suk4RQ4msNEseH0yAh1UdMXMgkIOQ== X-Received: by 2002:adf:ec8c:: with SMTP id z12mr687776wrn.208.1610058413020; Thu, 07 Jan 2021 14:26:53 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 46/66] target/mips: Move msa_reset() to msa_helper.c Date: Thu, 7 Jan 2021 23:22:33 +0100 Message-Id: <20210107222253.20382-47-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable translate_init.c.inc mostly contains CPU definitions. msa_reset() doesn't belong here, move it with the MSA helpers. One comment style is updated to avoid checkpatch.pl warning. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201215225757.764263-15-f4bug@amsat.org> Tested-by: Jiaxun Yang --- target/mips/internal.h | 2 ++ target/mips/cpu.c | 1 + target/mips/msa_helper.c | 36 ++++++++++++++++++++++++++++++++++++ target/mips/cpu-defs.c.inc | 36 ------------------------------------ 4 files changed, 39 insertions(+), 36 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 1048781bcf4..5dd17ff7333 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -199,6 +199,8 @@ static inline bool cpu_mips_hw_interrupts_pending(CPUMI= PSState *env) =20 void mips_tcg_init(void); =20 +void msa_reset(CPUMIPSState *env); + /* cp0_timer.c */ uint32_t cpu_mips_get_count(CPUMIPSState *env); void cpu_mips_store_count(CPUMIPSState *env, uint32_t value); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 4c590b90b25..f45164012a4 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -33,6 +33,7 @@ #include "hw/qdev-clock.h" #include "hw/semihosting/semihost.h" #include "qapi/qapi-commands-machine-target.h" +#include "fpu_helper.h" =20 #if !defined(CONFIG_USER_ONLY) =20 diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index b89b4c44902..f0d728c03f0 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -8201,3 +8201,39 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint32= _t df, uint32_t wd, =20 msa_move_v(pwd, pwx); } + +void msa_reset(CPUMIPSState *env) +{ + if (!ase_msa_available(env)) { + return; + } + +#ifdef CONFIG_USER_ONLY + /* MSA access enabled */ + env->CP0_Config5 |=3D 1 << CP0C5_MSAEn; + env->CP0_Status |=3D (1 << CP0St_CU1) | (1 << CP0St_FR); +#endif + + /* + * MSA CSR: + * - non-signaling floating point exception mode off (NX bit is 0) + * - Cause, Enables, and Flags are all 0 + * - round to nearest / ties to even (RM bits are 0) + */ + env->active_tc.msacsr =3D 0; + + restore_msa_fp_status(env); + + /* tininess detected after rounding.*/ + set_float_detect_tininess(float_tininess_after_rounding, + &env->active_tc.msa_fp_status); + + /* clear float_status exception flags */ + set_float_exception_flags(0, &env->active_tc.msa_fp_status); + + /* clear float_status nan mode */ + set_default_nan_mode(0, &env->active_tc.msa_fp_status); + + /* set proper signanling bit meaning ("1" means "quiet") */ + set_snan_bit_is_one(0, &env->active_tc.msa_fp_status); +} diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index 3d44b394773..ba22ff4bcd1 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -18,8 +18,6 @@ * License along with this library; if not, see . */ =20 -#include "fpu_helper.h" - /* CPU / CPU family specific config register values. */ =20 /* Have config1, uncached coherency */ @@ -975,37 +973,3 @@ static void mvp_init(CPUMIPSState *env) (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2= ) | (0x1 << CP0MVPC1_PCP1); } - -static void msa_reset(CPUMIPSState *env) -{ - if (!ase_msa_available(env)) { - return; - } - -#ifdef CONFIG_USER_ONLY - /* MSA access enabled */ - env->CP0_Config5 |=3D 1 << CP0C5_MSAEn; - env->CP0_Status |=3D (1 << CP0St_CU1) | (1 << CP0St_FR); -#endif - - /* MSA CSR: - - non-signaling floating point exception mode off (NX bit is 0) - - Cause, Enables, and Flags are all 0 - - round to nearest / ties to even (RM bits are 0) */ - env->active_tc.msacsr =3D 0; - - restore_msa_fp_status(env); - - /* tininess detected after rounding.*/ - set_float_detect_tininess(float_tininess_after_rounding, - &env->active_tc.msa_fp_status); - - /* clear float_status exception flags */ - set_float_exception_flags(0, &env->active_tc.msa_fp_status); - - /* clear float_status nan mode */ - set_default_nan_mode(0, &env->active_tc.msa_fp_status); - - /* set proper signanling bit meaning ("1" means "quiet") */ - set_snan_bit_is_one(0, &env->active_tc.msa_fp_status); -} --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 170.10.133.124 as permitted sender) client-ip=170.10.133.124; envelope-from=libvir-list-bounces@redhat.com; helo=us-smtp-delivery-124.mimecast.com; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of redhat.com designates 170.10.133.124 as permitted sender) smtp.mailfrom=libvir-list-bounces@redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1610058437; cv=none; d=zohomail.com; s=zohoarc; b=SHG9mzFUbK7rPY90wi1XA8kcPeTO93TlzNLWdg7vtTgrqN0IPMlY3N5SavyLqVkfg2U7bjqS92SSg+5Xf2J9c7xCA0naqAQUCuexu1U5SeUdDH5Zx7seoAf5oBzlDFl5IxibHo9nu/FFgQP0Dy0xfdsxWo47biBwKFvJIlPPMck= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id c7sm11519364wro.16.2021.01.07.14.26.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:26:57 -0800 (PST) X-MC-Unique: fQuAxQBQPES9d09SaEOuHw-1 X-MC-Unique: -06Y8MocMV63YJpxLgUmWQ-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=IPfFbY95vXiM+Tou5uRQMz9PmcLmcEc8idssuy0S44U=; b=M0nzB3UwaDt7OL8n83ZA4htBkCiCJt7gYonGJ+wdtTdDxh1LaxyfWpxH+/MPQ+qIy1 Ivq0VCSi2HFendG4vDJOhDndOOu3A8ozSvTJRJw1T35RQUx7zDk8K23wXu5G60hWLYNc E+gv62i/NJF9wxwNYJXWnunu810QzaaRMt87LbSswKb1rLJsDuEz3gydBms07xlWNLZR jeKHTKTNxAAV0zUuZMYIVNoC6WWikSBV0mG5zuLA/c6MWOHFaj59efKL685N1TzUP5c5 c+3Y32RYCL/D/zWeeR7ejAsniinvrPwlH9N6EGjEQybJBEn0yaBcKdIuaD29CCvTkXfs 1kQQ== X-Gm-Message-State: AOAM532EBWkQMG1g0U5PuHKJrfz342UYR2lmu78jEcZvgkA2ZO2m68lg vdkSjBZ3qjVz/brPo2D2Zc0= X-Google-Smtp-Source: ABdhPJxG0QUdwh9oqsDEqXDNua8PP9H4dfyzGB2jT3+TjfP3F+O9xKBbRHhuk2m9lYMD5rSVvIYO2w== X-Received: by 2002:adf:9cca:: with SMTP id h10mr673793wre.77.1610058418113; Thu, 07 Jan 2021 14:26:58 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 47/66] target/mips: Extract MSA helpers from op_helper.c Date: Thu, 7 Jan 2021 23:22:34 +0100 Message-Id: <20210107222253.20382-48-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable We have ~400 lines of MSA helpers in the generic op_helper.c, move them with the other helpers in 'msa_helper.c'. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201123204448.3260804-5-f4bug@amsat.org> Tested-by: Jiaxun Yang --- target/mips/msa_helper.c | 393 ++++++++++++++++++++++++++++++++++++++ target/mips/op_helper.c | 394 --------------------------------------- 2 files changed, 393 insertions(+), 394 deletions(-) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index f0d728c03f0..1298a1917ce 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -22,6 +22,7 @@ #include "internal.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" +#include "exec/memop.h" #include "fpu/softfloat.h" #include "fpu_helper.h" =20 @@ -8202,6 +8203,398 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint3= 2_t df, uint32_t wd, msa_move_v(pwd, pwx); } =20 +/* Data format min and max values */ +#define DF_BITS(df) (1 << ((df) + 3)) + +/* Element-by-element access macros */ +#define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df)) + +#if !defined(CONFIG_USER_ONLY) +#define MEMOP_IDX(DF) \ + TCGMemOpIdx oi =3D make_memop_idx(MO_TE | DF | MO_UNALN, \ + cpu_mmu_index(env, false)); +#else +#define MEMOP_IDX(DF) +#endif + +void helper_msa_ld_b(CPUMIPSState *env, uint32_t wd, + target_ulong addr) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + MEMOP_IDX(DF_BYTE) +#if !defined(CONFIG_USER_ONLY) +#if !defined(HOST_WORDS_BIGENDIAN) + pwd->b[0] =3D helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GE= TPC()); + pwd->b[1] =3D helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GE= TPC()); + pwd->b[2] =3D helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GE= TPC()); + pwd->b[3] =3D helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GE= TPC()); + pwd->b[4] =3D helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GE= TPC()); + pwd->b[5] =3D helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GE= TPC()); + pwd->b[6] =3D helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GE= TPC()); + pwd->b[7] =3D helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GE= TPC()); + pwd->b[8] =3D helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GE= TPC()); + pwd->b[9] =3D helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GE= TPC()); + pwd->b[10] =3D helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GE= TPC()); + pwd->b[11] =3D helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GE= TPC()); + pwd->b[12] =3D helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GE= TPC()); + pwd->b[13] =3D helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GE= TPC()); + pwd->b[14] =3D helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GE= TPC()); + pwd->b[15] =3D helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GE= TPC()); +#else + pwd->b[0] =3D helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GE= TPC()); + pwd->b[1] =3D helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GE= TPC()); + pwd->b[2] =3D helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GE= TPC()); + pwd->b[3] =3D helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GE= TPC()); + pwd->b[4] =3D helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GE= TPC()); + pwd->b[5] =3D helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GE= TPC()); + pwd->b[6] =3D helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GE= TPC()); + pwd->b[7] =3D helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GE= TPC()); + pwd->b[8] =3D helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GE= TPC()); + pwd->b[9] =3D helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GE= TPC()); + pwd->b[10] =3D helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GE= TPC()); + pwd->b[11] =3D helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GE= TPC()); + pwd->b[12] =3D helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GE= TPC()); + pwd->b[13] =3D helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GE= TPC()); + pwd->b[14] =3D helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GE= TPC()); + pwd->b[15] =3D helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GE= TPC()); +#endif +#else +#if !defined(HOST_WORDS_BIGENDIAN) + pwd->b[0] =3D cpu_ldub_data(env, addr + (0 << DF_BYTE)); + pwd->b[1] =3D cpu_ldub_data(env, addr + (1 << DF_BYTE)); + pwd->b[2] =3D cpu_ldub_data(env, addr + (2 << DF_BYTE)); + pwd->b[3] =3D cpu_ldub_data(env, addr + (3 << DF_BYTE)); + pwd->b[4] =3D cpu_ldub_data(env, addr + (4 << DF_BYTE)); + pwd->b[5] =3D cpu_ldub_data(env, addr + (5 << DF_BYTE)); + pwd->b[6] =3D cpu_ldub_data(env, addr + (6 << DF_BYTE)); + pwd->b[7] =3D cpu_ldub_data(env, addr + (7 << DF_BYTE)); + pwd->b[8] =3D cpu_ldub_data(env, addr + (8 << DF_BYTE)); + pwd->b[9] =3D cpu_ldub_data(env, addr + (9 << DF_BYTE)); + pwd->b[10] =3D cpu_ldub_data(env, addr + (10 << DF_BYTE)); + pwd->b[11] =3D cpu_ldub_data(env, addr + (11 << DF_BYTE)); + pwd->b[12] =3D cpu_ldub_data(env, addr + (12 << DF_BYTE)); + pwd->b[13] =3D cpu_ldub_data(env, addr + (13 << DF_BYTE)); + pwd->b[14] =3D cpu_ldub_data(env, addr + (14 << DF_BYTE)); + pwd->b[15] =3D cpu_ldub_data(env, addr + (15 << DF_BYTE)); +#else + pwd->b[0] =3D cpu_ldub_data(env, addr + (7 << DF_BYTE)); + pwd->b[1] =3D cpu_ldub_data(env, addr + (6 << DF_BYTE)); + pwd->b[2] =3D cpu_ldub_data(env, addr + (5 << DF_BYTE)); + pwd->b[3] =3D cpu_ldub_data(env, addr + (4 << DF_BYTE)); + pwd->b[4] =3D cpu_ldub_data(env, addr + (3 << DF_BYTE)); + pwd->b[5] =3D cpu_ldub_data(env, addr + (2 << DF_BYTE)); + pwd->b[6] =3D cpu_ldub_data(env, addr + (1 << DF_BYTE)); + pwd->b[7] =3D cpu_ldub_data(env, addr + (0 << DF_BYTE)); + pwd->b[8] =3D cpu_ldub_data(env, addr + (15 << DF_BYTE)); + pwd->b[9] =3D cpu_ldub_data(env, addr + (14 << DF_BYTE)); + pwd->b[10] =3D cpu_ldub_data(env, addr + (13 << DF_BYTE)); + pwd->b[11] =3D cpu_ldub_data(env, addr + (12 << DF_BYTE)); + pwd->b[12] =3D cpu_ldub_data(env, addr + (11 << DF_BYTE)); + pwd->b[13] =3D cpu_ldub_data(env, addr + (10 << DF_BYTE)); + pwd->b[14] =3D cpu_ldub_data(env, addr + (9 << DF_BYTE)); + pwd->b[15] =3D cpu_ldub_data(env, addr + (8 << DF_BYTE)); +#endif +#endif +} + +void helper_msa_ld_h(CPUMIPSState *env, uint32_t wd, + target_ulong addr) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + MEMOP_IDX(DF_HALF) +#if !defined(CONFIG_USER_ONLY) +#if !defined(HOST_WORDS_BIGENDIAN) + pwd->h[0] =3D helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETP= C()); + pwd->h[1] =3D helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETP= C()); + pwd->h[2] =3D helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETP= C()); + pwd->h[3] =3D helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETP= C()); + pwd->h[4] =3D helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETP= C()); + pwd->h[5] =3D helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETP= C()); + pwd->h[6] =3D helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETP= C()); + pwd->h[7] =3D helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETP= C()); +#else + pwd->h[0] =3D helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETP= C()); + pwd->h[1] =3D helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETP= C()); + pwd->h[2] =3D helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETP= C()); + pwd->h[3] =3D helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETP= C()); + pwd->h[4] =3D helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETP= C()); + pwd->h[5] =3D helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETP= C()); + pwd->h[6] =3D helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETP= C()); + pwd->h[7] =3D helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETP= C()); +#endif +#else +#if !defined(HOST_WORDS_BIGENDIAN) + pwd->h[0] =3D cpu_lduw_data(env, addr + (0 << DF_HALF)); + pwd->h[1] =3D cpu_lduw_data(env, addr + (1 << DF_HALF)); + pwd->h[2] =3D cpu_lduw_data(env, addr + (2 << DF_HALF)); + pwd->h[3] =3D cpu_lduw_data(env, addr + (3 << DF_HALF)); + pwd->h[4] =3D cpu_lduw_data(env, addr + (4 << DF_HALF)); + pwd->h[5] =3D cpu_lduw_data(env, addr + (5 << DF_HALF)); + pwd->h[6] =3D cpu_lduw_data(env, addr + (6 << DF_HALF)); + pwd->h[7] =3D cpu_lduw_data(env, addr + (7 << DF_HALF)); +#else + pwd->h[0] =3D cpu_lduw_data(env, addr + (3 << DF_HALF)); + pwd->h[1] =3D cpu_lduw_data(env, addr + (2 << DF_HALF)); + pwd->h[2] =3D cpu_lduw_data(env, addr + (1 << DF_HALF)); + pwd->h[3] =3D cpu_lduw_data(env, addr + (0 << DF_HALF)); + pwd->h[4] =3D cpu_lduw_data(env, addr + (7 << DF_HALF)); + pwd->h[5] =3D cpu_lduw_data(env, addr + (6 << DF_HALF)); + pwd->h[6] =3D cpu_lduw_data(env, addr + (5 << DF_HALF)); + pwd->h[7] =3D cpu_lduw_data(env, addr + (4 << DF_HALF)); +#endif +#endif +} + +void helper_msa_ld_w(CPUMIPSState *env, uint32_t wd, + target_ulong addr) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + MEMOP_IDX(DF_WORD) +#if !defined(CONFIG_USER_ONLY) +#if !defined(HOST_WORDS_BIGENDIAN) + pwd->w[0] =3D helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETP= C()); + pwd->w[1] =3D helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETP= C()); + pwd->w[2] =3D helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETP= C()); + pwd->w[3] =3D helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETP= C()); +#else + pwd->w[0] =3D helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETP= C()); + pwd->w[1] =3D helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETP= C()); + pwd->w[2] =3D helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETP= C()); + pwd->w[3] =3D helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETP= C()); +#endif +#else +#if !defined(HOST_WORDS_BIGENDIAN) + pwd->w[0] =3D cpu_ldl_data(env, addr + (0 << DF_WORD)); + pwd->w[1] =3D cpu_ldl_data(env, addr + (1 << DF_WORD)); + pwd->w[2] =3D cpu_ldl_data(env, addr + (2 << DF_WORD)); + pwd->w[3] =3D cpu_ldl_data(env, addr + (3 << DF_WORD)); +#else + pwd->w[0] =3D cpu_ldl_data(env, addr + (1 << DF_WORD)); + pwd->w[1] =3D cpu_ldl_data(env, addr + (0 << DF_WORD)); + pwd->w[2] =3D cpu_ldl_data(env, addr + (3 << DF_WORD)); + pwd->w[3] =3D cpu_ldl_data(env, addr + (2 << DF_WORD)); +#endif +#endif +} + +void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd, + target_ulong addr) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + MEMOP_IDX(DF_DOUBLE) +#if !defined(CONFIG_USER_ONLY) + pwd->d[0] =3D helper_ret_ldq_mmu(env, addr + (0 << DF_DOUBLE), oi, GET= PC()); + pwd->d[1] =3D helper_ret_ldq_mmu(env, addr + (1 << DF_DOUBLE), oi, GET= PC()); +#else + pwd->d[0] =3D cpu_ldq_data(env, addr + (0 << DF_DOUBLE)); + pwd->d[1] =3D cpu_ldq_data(env, addr + (1 << DF_DOUBLE)); +#endif +} + +#define MSA_PAGESPAN(x) \ + ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN / 8 - 1) >=3D TARGET_PAGE_= SIZE) + +static inline void ensure_writable_pages(CPUMIPSState *env, + target_ulong addr, + int mmu_idx, + uintptr_t retaddr) +{ + /* FIXME: Probe the actual accesses (pass and use a size) */ + if (unlikely(MSA_PAGESPAN(addr))) { + /* first page */ + probe_write(env, addr, 0, mmu_idx, retaddr); + /* second page */ + addr =3D (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; + probe_write(env, addr, 0, mmu_idx, retaddr); + } +} + +void helper_msa_st_b(CPUMIPSState *env, uint32_t wd, + target_ulong addr) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + int mmu_idx =3D cpu_mmu_index(env, false); + + MEMOP_IDX(DF_BYTE) + ensure_writable_pages(env, addr, mmu_idx, GETPC()); +#if !defined(CONFIG_USER_ONLY) +#if !defined(HOST_WORDS_BIGENDIAN) + helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[0], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[1], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[2], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[3], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[4], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[5], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[6], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[7], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[8], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[9], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[10], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[11], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[12], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[13], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[14], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[15], oi, GETPC(= )); +#else + helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[0], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[1], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[2], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[3], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[4], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[5], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[6], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[7], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[8], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[9], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[10], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[11], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[12], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[13], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[14], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[15], oi, GETPC(= )); +#endif +#else +#if !defined(HOST_WORDS_BIGENDIAN) + cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[0]); + cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[1]); + cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[2]); + cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[3]); + cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[4]); + cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[5]); + cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[6]); + cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[7]); + cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[8]); + cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[9]); + cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[10]); + cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[11]); + cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[12]); + cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[13]); + cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[14]); + cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[15]); +#else + cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[0]); + cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[1]); + cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[2]); + cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[3]); + cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[4]); + cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[5]); + cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[6]); + cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[7]); + cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[8]); + cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[9]); + cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[10]); + cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[11]); + cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[12]); + cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[13]); + cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[14]); + cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[15]); +#endif +#endif +} + +void helper_msa_st_h(CPUMIPSState *env, uint32_t wd, + target_ulong addr) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + int mmu_idx =3D cpu_mmu_index(env, false); + + MEMOP_IDX(DF_HALF) + ensure_writable_pages(env, addr, mmu_idx, GETPC()); +#if !defined(CONFIG_USER_ONLY) +#if !defined(HOST_WORDS_BIGENDIAN) + helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[0], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[1], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[2], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[3], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[4], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[5], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[6], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[7], oi, GETPC()); +#else + helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[0], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[1], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[2], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[3], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[4], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[5], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[6], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[7], oi, GETPC()); +#endif +#else +#if !defined(HOST_WORDS_BIGENDIAN) + cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[0]); + cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[1]); + cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[2]); + cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[3]); + cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[4]); + cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[5]); + cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[6]); + cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[7]); +#else + cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[0]); + cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[1]); + cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[2]); + cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[3]); + cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[4]); + cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[5]); + cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[6]); + cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[7]); +#endif +#endif +} + +void helper_msa_st_w(CPUMIPSState *env, uint32_t wd, + target_ulong addr) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + int mmu_idx =3D cpu_mmu_index(env, false); + + MEMOP_IDX(DF_WORD) + ensure_writable_pages(env, addr, mmu_idx, GETPC()); +#if !defined(CONFIG_USER_ONLY) +#if !defined(HOST_WORDS_BIGENDIAN) + helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[0], oi, GETPC()); + helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[1], oi, GETPC()); + helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[2], oi, GETPC()); + helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[3], oi, GETPC()); +#else + helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[0], oi, GETPC()); + helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[1], oi, GETPC()); + helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[2], oi, GETPC()); + helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[3], oi, GETPC()); +#endif +#else +#if !defined(HOST_WORDS_BIGENDIAN) + cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[0]); + cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[1]); + cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[2]); + cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[3]); +#else + cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[0]); + cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[1]); + cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[2]); + cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[3]); +#endif +#endif +} + +void helper_msa_st_d(CPUMIPSState *env, uint32_t wd, + target_ulong addr) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + int mmu_idx =3D cpu_mmu_index(env, false); + + MEMOP_IDX(DF_DOUBLE) + ensure_writable_pages(env, addr, mmu_idx, GETPC()); +#if !defined(CONFIG_USER_ONLY) + helper_ret_stq_mmu(env, addr + (0 << DF_DOUBLE), pwd->d[0], oi, GETPC(= )); + helper_ret_stq_mmu(env, addr + (1 << DF_DOUBLE), pwd->d[1], oi, GETPC(= )); +#else + cpu_stq_data(env, addr + (0 << DF_DOUBLE), pwd->d[0]); + cpu_stq_data(env, addr + (1 << DF_DOUBLE), pwd->d[1]); +#endif +} + void msa_reset(CPUMIPSState *env) { if (!ase_msa_available(env)) { diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 3386b8228e9..89c7d4556a0 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -1173,400 +1173,6 @@ void mips_cpu_do_transaction_failed(CPUState *cs, h= waddr physaddr, } #endif /* !CONFIG_USER_ONLY */ =20 - -/* MSA */ -/* Data format min and max values */ -#define DF_BITS(df) (1 << ((df) + 3)) - -/* Element-by-element access macros */ -#define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df)) - -#if !defined(CONFIG_USER_ONLY) -#define MEMOP_IDX(DF) \ - TCGMemOpIdx oi =3D make_memop_idx(MO_TE | DF | MO_UNALN, \ - cpu_mmu_index(env, false)); -#else -#define MEMOP_IDX(DF) -#endif - -void helper_msa_ld_b(CPUMIPSState *env, uint32_t wd, - target_ulong addr) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - MEMOP_IDX(DF_BYTE) -#if !defined(CONFIG_USER_ONLY) -#if !defined(HOST_WORDS_BIGENDIAN) - pwd->b[0] =3D helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GE= TPC()); - pwd->b[1] =3D helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GE= TPC()); - pwd->b[2] =3D helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GE= TPC()); - pwd->b[3] =3D helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GE= TPC()); - pwd->b[4] =3D helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GE= TPC()); - pwd->b[5] =3D helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GE= TPC()); - pwd->b[6] =3D helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GE= TPC()); - pwd->b[7] =3D helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GE= TPC()); - pwd->b[8] =3D helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GE= TPC()); - pwd->b[9] =3D helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GE= TPC()); - pwd->b[10] =3D helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GE= TPC()); - pwd->b[11] =3D helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GE= TPC()); - pwd->b[12] =3D helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GE= TPC()); - pwd->b[13] =3D helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GE= TPC()); - pwd->b[14] =3D helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GE= TPC()); - pwd->b[15] =3D helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GE= TPC()); -#else - pwd->b[0] =3D helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GE= TPC()); - pwd->b[1] =3D helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GE= TPC()); - pwd->b[2] =3D helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GE= TPC()); - pwd->b[3] =3D helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GE= TPC()); - pwd->b[4] =3D helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GE= TPC()); - pwd->b[5] =3D helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GE= TPC()); - pwd->b[6] =3D helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GE= TPC()); - pwd->b[7] =3D helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GE= TPC()); - pwd->b[8] =3D helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GE= TPC()); - pwd->b[9] =3D helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GE= TPC()); - pwd->b[10] =3D helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GE= TPC()); - pwd->b[11] =3D helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GE= TPC()); - pwd->b[12] =3D helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GE= TPC()); - pwd->b[13] =3D helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GE= TPC()); - pwd->b[14] =3D helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GE= TPC()); - pwd->b[15] =3D helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GE= TPC()); -#endif -#else -#if !defined(HOST_WORDS_BIGENDIAN) - pwd->b[0] =3D cpu_ldub_data(env, addr + (0 << DF_BYTE)); - pwd->b[1] =3D cpu_ldub_data(env, addr + (1 << DF_BYTE)); - pwd->b[2] =3D cpu_ldub_data(env, addr + (2 << DF_BYTE)); - pwd->b[3] =3D cpu_ldub_data(env, addr + (3 << DF_BYTE)); - pwd->b[4] =3D cpu_ldub_data(env, addr + (4 << DF_BYTE)); - pwd->b[5] =3D cpu_ldub_data(env, addr + (5 << DF_BYTE)); - pwd->b[6] =3D cpu_ldub_data(env, addr + (6 << DF_BYTE)); - pwd->b[7] =3D cpu_ldub_data(env, addr + (7 << DF_BYTE)); - pwd->b[8] =3D cpu_ldub_data(env, addr + (8 << DF_BYTE)); - pwd->b[9] =3D cpu_ldub_data(env, addr + (9 << DF_BYTE)); - pwd->b[10] =3D cpu_ldub_data(env, addr + (10 << DF_BYTE)); - pwd->b[11] =3D cpu_ldub_data(env, addr + (11 << DF_BYTE)); - pwd->b[12] =3D cpu_ldub_data(env, addr + (12 << DF_BYTE)); - pwd->b[13] =3D cpu_ldub_data(env, addr + (13 << DF_BYTE)); - pwd->b[14] =3D cpu_ldub_data(env, addr + (14 << DF_BYTE)); - pwd->b[15] =3D cpu_ldub_data(env, addr + (15 << DF_BYTE)); -#else - pwd->b[0] =3D cpu_ldub_data(env, addr + (7 << DF_BYTE)); - pwd->b[1] =3D cpu_ldub_data(env, addr + (6 << DF_BYTE)); - pwd->b[2] =3D cpu_ldub_data(env, addr + (5 << DF_BYTE)); - pwd->b[3] =3D cpu_ldub_data(env, addr + (4 << DF_BYTE)); - pwd->b[4] =3D cpu_ldub_data(env, addr + (3 << DF_BYTE)); - pwd->b[5] =3D cpu_ldub_data(env, addr + (2 << DF_BYTE)); - pwd->b[6] =3D cpu_ldub_data(env, addr + (1 << DF_BYTE)); - pwd->b[7] =3D cpu_ldub_data(env, addr + (0 << DF_BYTE)); - pwd->b[8] =3D cpu_ldub_data(env, addr + (15 << DF_BYTE)); - pwd->b[9] =3D cpu_ldub_data(env, addr + (14 << DF_BYTE)); - pwd->b[10] =3D cpu_ldub_data(env, addr + (13 << DF_BYTE)); - pwd->b[11] =3D cpu_ldub_data(env, addr + (12 << DF_BYTE)); - pwd->b[12] =3D cpu_ldub_data(env, addr + (11 << DF_BYTE)); - pwd->b[13] =3D cpu_ldub_data(env, addr + (10 << DF_BYTE)); - pwd->b[14] =3D cpu_ldub_data(env, addr + (9 << DF_BYTE)); - pwd->b[15] =3D cpu_ldub_data(env, addr + (8 << DF_BYTE)); -#endif -#endif -} - -void helper_msa_ld_h(CPUMIPSState *env, uint32_t wd, - target_ulong addr) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - MEMOP_IDX(DF_HALF) -#if !defined(CONFIG_USER_ONLY) -#if !defined(HOST_WORDS_BIGENDIAN) - pwd->h[0] =3D helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETP= C()); - pwd->h[1] =3D helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETP= C()); - pwd->h[2] =3D helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETP= C()); - pwd->h[3] =3D helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETP= C()); - pwd->h[4] =3D helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETP= C()); - pwd->h[5] =3D helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETP= C()); - pwd->h[6] =3D helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETP= C()); - pwd->h[7] =3D helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETP= C()); -#else - pwd->h[0] =3D helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETP= C()); - pwd->h[1] =3D helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETP= C()); - pwd->h[2] =3D helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETP= C()); - pwd->h[3] =3D helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETP= C()); - pwd->h[4] =3D helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETP= C()); - pwd->h[5] =3D helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETP= C()); - pwd->h[6] =3D helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETP= C()); - pwd->h[7] =3D helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETP= C()); -#endif -#else -#if !defined(HOST_WORDS_BIGENDIAN) - pwd->h[0] =3D cpu_lduw_data(env, addr + (0 << DF_HALF)); - pwd->h[1] =3D cpu_lduw_data(env, addr + (1 << DF_HALF)); - pwd->h[2] =3D cpu_lduw_data(env, addr + (2 << DF_HALF)); - pwd->h[3] =3D cpu_lduw_data(env, addr + (3 << DF_HALF)); - pwd->h[4] =3D cpu_lduw_data(env, addr + (4 << DF_HALF)); - pwd->h[5] =3D cpu_lduw_data(env, addr + (5 << DF_HALF)); - pwd->h[6] =3D cpu_lduw_data(env, addr + (6 << DF_HALF)); - pwd->h[7] =3D cpu_lduw_data(env, addr + (7 << DF_HALF)); -#else - pwd->h[0] =3D cpu_lduw_data(env, addr + (3 << DF_HALF)); - pwd->h[1] =3D cpu_lduw_data(env, addr + (2 << DF_HALF)); - pwd->h[2] =3D cpu_lduw_data(env, addr + (1 << DF_HALF)); - pwd->h[3] =3D cpu_lduw_data(env, addr + (0 << DF_HALF)); - pwd->h[4] =3D cpu_lduw_data(env, addr + (7 << DF_HALF)); - pwd->h[5] =3D cpu_lduw_data(env, addr + (6 << DF_HALF)); - pwd->h[6] =3D cpu_lduw_data(env, addr + (5 << DF_HALF)); - pwd->h[7] =3D cpu_lduw_data(env, addr + (4 << DF_HALF)); -#endif -#endif -} - -void helper_msa_ld_w(CPUMIPSState *env, uint32_t wd, - target_ulong addr) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - MEMOP_IDX(DF_WORD) -#if !defined(CONFIG_USER_ONLY) -#if !defined(HOST_WORDS_BIGENDIAN) - pwd->w[0] =3D helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETP= C()); - pwd->w[1] =3D helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETP= C()); - pwd->w[2] =3D helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETP= C()); - pwd->w[3] =3D helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETP= C()); -#else - pwd->w[0] =3D helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETP= C()); - pwd->w[1] =3D helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETP= C()); - pwd->w[2] =3D helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETP= C()); - pwd->w[3] =3D helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETP= C()); -#endif -#else -#if !defined(HOST_WORDS_BIGENDIAN) - pwd->w[0] =3D cpu_ldl_data(env, addr + (0 << DF_WORD)); - pwd->w[1] =3D cpu_ldl_data(env, addr + (1 << DF_WORD)); - pwd->w[2] =3D cpu_ldl_data(env, addr + (2 << DF_WORD)); - pwd->w[3] =3D cpu_ldl_data(env, addr + (3 << DF_WORD)); -#else - pwd->w[0] =3D cpu_ldl_data(env, addr + (1 << DF_WORD)); - pwd->w[1] =3D cpu_ldl_data(env, addr + (0 << DF_WORD)); - pwd->w[2] =3D cpu_ldl_data(env, addr + (3 << DF_WORD)); - pwd->w[3] =3D cpu_ldl_data(env, addr + (2 << DF_WORD)); -#endif -#endif -} - -void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd, - target_ulong addr) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - MEMOP_IDX(DF_DOUBLE) -#if !defined(CONFIG_USER_ONLY) - pwd->d[0] =3D helper_ret_ldq_mmu(env, addr + (0 << DF_DOUBLE), oi, GET= PC()); - pwd->d[1] =3D helper_ret_ldq_mmu(env, addr + (1 << DF_DOUBLE), oi, GET= PC()); -#else - pwd->d[0] =3D cpu_ldq_data(env, addr + (0 << DF_DOUBLE)); - pwd->d[1] =3D cpu_ldq_data(env, addr + (1 << DF_DOUBLE)); -#endif -} - -#define MSA_PAGESPAN(x) \ - ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN / 8 - 1) >=3D TARGET_PAGE_= SIZE) - -static inline void ensure_writable_pages(CPUMIPSState *env, - target_ulong addr, - int mmu_idx, - uintptr_t retaddr) -{ - /* FIXME: Probe the actual accesses (pass and use a size) */ - if (unlikely(MSA_PAGESPAN(addr))) { - /* first page */ - probe_write(env, addr, 0, mmu_idx, retaddr); - /* second page */ - addr =3D (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; - probe_write(env, addr, 0, mmu_idx, retaddr); - } -} - -void helper_msa_st_b(CPUMIPSState *env, uint32_t wd, - target_ulong addr) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - int mmu_idx =3D cpu_mmu_index(env, false); - - MEMOP_IDX(DF_BYTE) - ensure_writable_pages(env, addr, mmu_idx, GETPC()); -#if !defined(CONFIG_USER_ONLY) -#if !defined(HOST_WORDS_BIGENDIAN) - helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[0], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[1], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[2], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[3], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[4], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[5], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[6], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[7], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[8], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[9], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[10], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[11], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[12], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[13], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[14], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[15], oi, GETPC(= )); -#else - helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[0], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[1], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[2], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[3], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[4], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[5], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[6], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[7], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[8], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[9], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[10], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[11], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[12], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[13], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[14], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[15], oi, GETPC(= )); -#endif -#else -#if !defined(HOST_WORDS_BIGENDIAN) - cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[0]); - cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[1]); - cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[2]); - cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[3]); - cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[4]); - cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[5]); - cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[6]); - cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[7]); - cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[8]); - cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[9]); - cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[10]); - cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[11]); - cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[12]); - cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[13]); - cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[14]); - cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[15]); -#else - cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[0]); - cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[1]); - cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[2]); - cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[3]); - cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[4]); - cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[5]); - cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[6]); - cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[7]); - cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[8]); - cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[9]); - cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[10]); - cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[11]); - cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[12]); - cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[13]); - cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[14]); - cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[15]); -#endif -#endif -} - -void helper_msa_st_h(CPUMIPSState *env, uint32_t wd, - target_ulong addr) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - int mmu_idx =3D cpu_mmu_index(env, false); - - MEMOP_IDX(DF_HALF) - ensure_writable_pages(env, addr, mmu_idx, GETPC()); -#if !defined(CONFIG_USER_ONLY) -#if !defined(HOST_WORDS_BIGENDIAN) - helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[0], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[1], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[2], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[3], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[4], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[5], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[6], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[7], oi, GETPC()); -#else - helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[0], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[1], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[2], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[3], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[4], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[5], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[6], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[7], oi, GETPC()); -#endif -#else -#if !defined(HOST_WORDS_BIGENDIAN) - cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[0]); - cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[1]); - cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[2]); - cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[3]); - cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[4]); - cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[5]); - cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[6]); - cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[7]); -#else - cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[0]); - cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[1]); - cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[2]); - cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[3]); - cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[4]); - cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[5]); - cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[6]); - cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[7]); -#endif -#endif -} - -void helper_msa_st_w(CPUMIPSState *env, uint32_t wd, - target_ulong addr) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - int mmu_idx =3D cpu_mmu_index(env, false); - - MEMOP_IDX(DF_WORD) - ensure_writable_pages(env, addr, mmu_idx, GETPC()); -#if !defined(CONFIG_USER_ONLY) -#if !defined(HOST_WORDS_BIGENDIAN) - helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[0], oi, GETPC()); - helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[1], oi, GETPC()); - helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[2], oi, GETPC()); - helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[3], oi, GETPC()); -#else - helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[0], oi, GETPC()); - helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[1], oi, GETPC()); - helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[2], oi, GETPC()); - helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[3], oi, GETPC()); -#endif -#else -#if !defined(HOST_WORDS_BIGENDIAN) - cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[0]); - cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[1]); - cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[2]); - cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[3]); -#else - cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[0]); - cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[1]); - cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[2]); - cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[3]); -#endif -#endif -} - -void helper_msa_st_d(CPUMIPSState *env, uint32_t wd, - target_ulong addr) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - int mmu_idx =3D cpu_mmu_index(env, false); - - MEMOP_IDX(DF_DOUBLE) - ensure_writable_pages(env, addr, mmu_idx, GETPC()); -#if !defined(CONFIG_USER_ONLY) - helper_ret_stq_mmu(env, addr + (0 << DF_DOUBLE), pwd->d[0], oi, GETPC(= )); - helper_ret_stq_mmu(env, addr + (1 << DF_DOUBLE), pwd->d[1], oi, GETPC(= )); -#else - cpu_stq_data(env, addr + (0 << DF_DOUBLE), pwd->d[0]); - cpu_stq_data(env, addr + (1 << DF_DOUBLE), pwd->d[1]); -#endif -} - void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op) { #ifndef CONFIG_USER_ONLY --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 63.128.21.124 as permitted sender) client-ip=63.128.21.124; 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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id a14sm10131057wrn.3.2021.01.07.14.27.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:27:02 -0800 (PST) X-MC-Unique: pAHI7cHGMaOnFtd9BfOk4Q-1 X-MC-Unique: 8OogCFHUOJGxZJGHJx_Vhg-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=vGDQCmouQR39Ws4zTMOXUe5wAq7PwBxciYPsXSjmS+Y=; b=jIZroUP1rH/GXhDEeiFiPXgTiRoQ+hpqiLHFjXJ0pTp4RPWwh3Im+QfiJpCVMvJQiC GuJkGAB09jTNZoAEzTYOMS0V9HgqTnR+n/++wy9eZDTXzYYOqmEHIYziRyrO3bRk0mI+ FwCf2LleJSHOGgPiuwVhJnHXczF6LdgstskPBkhtNUylZrjEJygjCNSzqcRAwBKrxw5M epJcnlHsSLDvpvsSYAk1IQNdN96IKu4FW0BP5b9UjABLhMz1hRmC3GQZL80E4OSCJqTO B+NJ3eKfcZZaCEBxkQR2cnH0IfyeTQM4vKQvTE79Za/iybdjvktkqmBhzmOt6cC51gsB v2BQ== X-Gm-Message-State: AOAM531ccTdPXD5ACNPvmxuey6ACp2+VFs4X9M1dB1y0DjFHiAiRdNxl sfkwE6ZF1NJjg8qex+Ugxsc= X-Google-Smtp-Source: ABdhPJzp0E8rR0XLj17MQAkJR1Jhd02p2WUxwfz8QZdk4Gi2vxmkF7nlOa4S8saYY5O/4n1//CmgXQ== X-Received: by 2002:adf:f60b:: with SMTP id t11mr660098wrp.401.1610058423399; Thu, 07 Jan 2021 14:27:03 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 48/66] target/mips: Extract MSA helper definitions Date: Thu, 7 Jan 2021 23:22:35 +0100 Message-Id: <20210107222253.20382-49-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.78 on 10.11.54.4 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Keep all MSA-related code altogether. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20201120210844.2625602-4-f4bug@amsat.org> Tested-by: Jiaxun Yang --- target/mips/helper.h | 436 +--------------------------------- target/mips/msa_helper.h.inc | 443 +++++++++++++++++++++++++++++++++++ 2 files changed, 445 insertions(+), 434 deletions(-) create mode 100644 target/mips/msa_helper.h.inc diff --git a/target/mips/helper.h b/target/mips/helper.h index e97655dc0eb..709494445dd 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -781,438 +781,6 @@ DEF_HELPER_FLAGS_3(dmthlip, 0, void, tl, tl, env) DEF_HELPER_FLAGS_3(wrdsp, 0, void, tl, tl, env) DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env) =20 -/* MIPS SIMD Architecture */ - -DEF_HELPER_3(msa_nloc_b, void, env, i32, i32) -DEF_HELPER_3(msa_nloc_h, void, env, i32, i32) -DEF_HELPER_3(msa_nloc_w, void, env, i32, i32) -DEF_HELPER_3(msa_nloc_d, void, env, i32, i32) - -DEF_HELPER_3(msa_nlzc_b, void, env, i32, i32) -DEF_HELPER_3(msa_nlzc_h, void, env, i32, i32) -DEF_HELPER_3(msa_nlzc_w, void, env, i32, i32) -DEF_HELPER_3(msa_nlzc_d, void, env, i32, i32) - -DEF_HELPER_3(msa_pcnt_b, void, env, i32, i32) -DEF_HELPER_3(msa_pcnt_h, void, env, i32, i32) -DEF_HELPER_3(msa_pcnt_w, void, env, i32, i32) -DEF_HELPER_3(msa_pcnt_d, void, env, i32, i32) - -DEF_HELPER_4(msa_binsl_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_binsl_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_binsl_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_binsl_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_binsr_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_binsr_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_binsr_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_binsr_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_bmnz_v, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bmz_v, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bsel_v, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_bclr_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bclr_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bclr_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bclr_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_bneg_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bneg_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bneg_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bneg_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_bset_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bset_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bset_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bset_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_add_a_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_add_a_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_add_a_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_add_a_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_adds_a_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_adds_a_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_adds_a_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_adds_a_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_adds_s_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_adds_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_adds_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_adds_s_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_adds_u_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_adds_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_adds_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_adds_u_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_addv_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_addv_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_addv_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_addv_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_hadd_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_hadd_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_hadd_s_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_hadd_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_hadd_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_hadd_u_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_ave_s_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ave_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ave_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ave_s_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_ave_u_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ave_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ave_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ave_u_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_aver_s_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_aver_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_aver_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_aver_s_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_aver_u_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_aver_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_aver_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_aver_u_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_ceq_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ceq_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ceq_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ceq_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_cle_s_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_cle_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_cle_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_cle_s_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_cle_u_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_cle_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_cle_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_cle_u_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_clt_s_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_clt_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_clt_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_clt_s_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_clt_u_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_clt_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_clt_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_clt_u_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_div_s_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_div_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_div_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_div_s_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_div_u_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_div_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_div_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_div_u_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_max_a_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_max_a_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_max_a_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_max_a_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_max_s_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_max_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_max_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_max_s_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_max_u_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_max_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_max_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_max_u_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_min_a_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_min_a_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_min_a_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_min_a_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_min_s_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_min_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_min_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_min_s_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_min_u_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_min_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_min_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_min_u_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_mod_u_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_mod_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_mod_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_mod_u_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_mod_s_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_mod_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_mod_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_mod_s_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_maddv_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_maddv_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_maddv_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_maddv_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_msubv_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_msubv_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_msubv_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_msubv_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_mulv_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_mulv_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_mulv_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_mulv_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_asub_s_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_asub_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_asub_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_asub_s_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_asub_u_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_asub_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_asub_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_asub_u_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_hsub_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_hsub_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_hsub_s_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_hsub_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_hsub_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_hsub_u_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_subs_s_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subs_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subs_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subs_s_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_subs_u_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subs_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subs_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subs_u_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_subsus_u_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subsus_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subsus_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subsus_u_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_subsuu_s_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subsuu_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subsuu_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subsuu_s_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_subv_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subv_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subv_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subv_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_ilvev_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvev_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvev_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvev_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvod_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvod_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvod_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvod_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvl_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvl_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvl_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvl_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvr_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvr_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvr_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvr_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_and_v, void, env, i32, i32, i32) -DEF_HELPER_4(msa_nor_v, void, env, i32, i32, i32) -DEF_HELPER_4(msa_or_v, void, env, i32, i32, i32) -DEF_HELPER_4(msa_xor_v, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_pckev_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_pckev_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_pckev_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_pckev_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_pckod_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_pckod_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_pckod_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_pckod_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_sll_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_sll_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_sll_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_sll_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_sra_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_sra_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_sra_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_sra_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_srar_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_srar_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_srar_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_srar_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_srl_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_srl_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_srl_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_srl_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_srlr_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_srlr_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_srlr_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_srlr_d, void, env, i32, i32, i32) - -DEF_HELPER_3(msa_move_v, void, env, i32, i32) - -DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_nori_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_xori_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bmnzi_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bmzi_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bseli_b, void, env, i32, i32, i32) -DEF_HELPER_5(msa_shf_df, void, env, i32, i32, i32, i32) - -DEF_HELPER_5(msa_addvi_df, void, env, i32, i32, i32, s32) -DEF_HELPER_5(msa_subvi_df, void, env, i32, i32, i32, s32) -DEF_HELPER_5(msa_maxi_s_df, void, env, i32, i32, i32, s32) -DEF_HELPER_5(msa_maxi_u_df, void, env, i32, i32, i32, s32) -DEF_HELPER_5(msa_mini_s_df, void, env, i32, i32, i32, s32) -DEF_HELPER_5(msa_mini_u_df, void, env, i32, i32, i32, s32) -DEF_HELPER_5(msa_ceqi_df, void, env, i32, i32, i32, s32) -DEF_HELPER_5(msa_clti_s_df, void, env, i32, i32, i32, s32) -DEF_HELPER_5(msa_clti_u_df, void, env, i32, i32, i32, s32) -DEF_HELPER_5(msa_clei_s_df, void, env, i32, i32, i32, s32) -DEF_HELPER_5(msa_clei_u_df, void, env, i32, i32, i32, s32) -DEF_HELPER_4(msa_ldi_df, void, env, i32, i32, s32) - -DEF_HELPER_5(msa_slli_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_srai_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_srli_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_bclri_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_bseti_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_bnegi_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_binsli_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_binsri_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_sat_s_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_sat_u_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_srari_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_srlri_df, void, env, i32, i32, i32, i32) - -DEF_HELPER_5(msa_binsl_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_binsr_df, void, env, i32, i32, i32, i32) - -DEF_HELPER_4(msa_dotp_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dotp_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dotp_s_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dotp_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dotp_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dotp_u_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dpadd_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dpadd_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dpadd_s_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dpadd_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dpadd_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dpadd_u_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dpsub_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dpsub_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dpsub_s_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dpsub_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dpsub_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dpsub_u_d, void, env, i32, i32, i32) -DEF_HELPER_5(msa_sld_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_splat_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_vshf_df, void, env, i32, i32, i32, i32) - -DEF_HELPER_5(msa_sldi_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_splati_df, void, env, i32, i32, i32, i32) - -DEF_HELPER_5(msa_insve_df, void, env, i32, i32, i32, i32) -DEF_HELPER_3(msa_ctcmsa, void, env, tl, i32) -DEF_HELPER_2(msa_cfcmsa, tl, env, i32) - -DEF_HELPER_5(msa_fcaf_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fcun_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fceq_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fcueq_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fclt_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fcult_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fcle_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fcule_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fsaf_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fsun_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fseq_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fsueq_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fslt_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fsult_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fsle_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fsule_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fadd_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fsub_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fmul_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fdiv_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fmadd_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fmsub_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fexp2_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fexdo_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_ftq_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fmin_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fmin_a_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fmax_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fmax_a_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fcor_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fcune_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fcne_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_mul_q_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_madd_q_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_msub_q_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fsor_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fsune_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fsne_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_mulr_q_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_maddr_q_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_msubr_q_df, void, env, i32, i32, i32, i32) - -DEF_HELPER_4(msa_fill_df, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_copy_s_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_copy_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_copy_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_copy_s_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_copy_u_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_copy_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_copy_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_insert_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_insert_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_insert_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_insert_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_fclass_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ftrunc_s_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ftrunc_u_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_fsqrt_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_frsqrt_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_frcp_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_frint_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_flog2_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_fexupl_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_fexupr_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ffql_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ffqr_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ftint_s_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ftint_u_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ffint_s_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ffint_u_df, void, env, i32, i32, i32) - -#define MSALDST_PROTO(type) \ -DEF_HELPER_3(msa_ld_ ## type, void, env, i32, tl) \ -DEF_HELPER_3(msa_st_ ## type, void, env, i32, tl) -MSALDST_PROTO(b) -MSALDST_PROTO(h) -MSALDST_PROTO(w) -MSALDST_PROTO(d) -#undef MSALDST_PROTO - DEF_HELPER_3(cache, void, env, tl, i32) + +#include "msa_helper.h.inc" diff --git a/target/mips/msa_helper.h.inc b/target/mips/msa_helper.h.inc new file mode 100644 index 00000000000..4963d1553a0 --- /dev/null +++ b/target/mips/msa_helper.h.inc @@ -0,0 +1,443 @@ +/* + * MIPS SIMD Architecture Module (MSA) helpers for QEMU. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * Copyright (c) 2006 Marius Groeger (FPU operations) + * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) + * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support) + * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support) + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +DEF_HELPER_3(msa_nloc_b, void, env, i32, i32) +DEF_HELPER_3(msa_nloc_h, void, env, i32, i32) +DEF_HELPER_3(msa_nloc_w, void, env, i32, i32) +DEF_HELPER_3(msa_nloc_d, void, env, i32, i32) + +DEF_HELPER_3(msa_nlzc_b, void, env, i32, i32) +DEF_HELPER_3(msa_nlzc_h, void, env, i32, i32) +DEF_HELPER_3(msa_nlzc_w, void, env, i32, i32) +DEF_HELPER_3(msa_nlzc_d, void, env, i32, i32) + +DEF_HELPER_3(msa_pcnt_b, void, env, i32, i32) +DEF_HELPER_3(msa_pcnt_h, void, env, i32, i32) +DEF_HELPER_3(msa_pcnt_w, void, env, i32, i32) +DEF_HELPER_3(msa_pcnt_d, void, env, i32, i32) + +DEF_HELPER_4(msa_binsl_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_binsl_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_binsl_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_binsl_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_binsr_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_binsr_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_binsr_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_binsr_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_bmnz_v, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bmz_v, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bsel_v, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_bclr_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bclr_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bclr_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bclr_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_bneg_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bneg_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bneg_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bneg_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_bset_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bset_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bset_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bset_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_add_a_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_add_a_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_add_a_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_add_a_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_adds_a_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_a_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_a_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_a_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_adds_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_adds_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_addv_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_addv_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_addv_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_addv_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_hadd_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_hadd_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_hadd_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_hadd_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_hadd_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_hadd_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_ave_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ave_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ave_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ave_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_ave_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ave_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ave_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ave_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_aver_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_aver_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_aver_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_aver_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_aver_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_aver_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_aver_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_aver_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_ceq_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ceq_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ceq_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ceq_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_cle_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_cle_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_cle_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_cle_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_cle_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_cle_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_cle_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_cle_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_clt_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_clt_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_clt_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_clt_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_clt_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_clt_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_clt_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_clt_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_div_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_div_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_div_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_div_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_div_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_div_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_div_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_div_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_max_a_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_a_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_a_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_a_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_s_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_u_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_a_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_a_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_a_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_a_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_s_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_mod_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_mod_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_mod_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_mod_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_mod_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_mod_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_mod_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_mod_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_maddv_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_maddv_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_maddv_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_maddv_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_msubv_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_msubv_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_msubv_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_msubv_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_mulv_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_mulv_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_mulv_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_mulv_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_asub_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_asub_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_asub_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_asub_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_asub_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_asub_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_asub_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_asub_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_hsub_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_hsub_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_hsub_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_hsub_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_hsub_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_hsub_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_subs_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subs_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subs_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subs_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_subs_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subs_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subs_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subs_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_subsus_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subsus_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subsus_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subsus_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_subsuu_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subsuu_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subsuu_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subsuu_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_subv_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subv_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subv_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subv_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_ilvev_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvev_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvev_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvev_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvod_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvod_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvod_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvod_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvl_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvl_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvl_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvl_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvr_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvr_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvr_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvr_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_and_v, void, env, i32, i32, i32) +DEF_HELPER_4(msa_nor_v, void, env, i32, i32, i32) +DEF_HELPER_4(msa_or_v, void, env, i32, i32, i32) +DEF_HELPER_4(msa_xor_v, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_pckev_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_pckev_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_pckev_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_pckev_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_pckod_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_pckod_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_pckod_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_pckod_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_sll_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_sll_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_sll_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_sll_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_sra_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_sra_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_sra_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_sra_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_srar_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_srar_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_srar_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_srar_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_srl_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_srl_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_srl_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_srl_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_srlr_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_srlr_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_srlr_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_srlr_d, void, env, i32, i32, i32) + +DEF_HELPER_3(msa_move_v, void, env, i32, i32) + +DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_nori_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_xori_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bmnzi_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bmzi_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bseli_b, void, env, i32, i32, i32) +DEF_HELPER_5(msa_shf_df, void, env, i32, i32, i32, i32) + +DEF_HELPER_5(msa_addvi_df, void, env, i32, i32, i32, s32) +DEF_HELPER_5(msa_subvi_df, void, env, i32, i32, i32, s32) +DEF_HELPER_5(msa_maxi_s_df, void, env, i32, i32, i32, s32) +DEF_HELPER_5(msa_maxi_u_df, void, env, i32, i32, i32, s32) +DEF_HELPER_5(msa_mini_s_df, void, env, i32, i32, i32, s32) +DEF_HELPER_5(msa_mini_u_df, void, env, i32, i32, i32, s32) +DEF_HELPER_5(msa_ceqi_df, void, env, i32, i32, i32, s32) +DEF_HELPER_5(msa_clti_s_df, void, env, i32, i32, i32, s32) +DEF_HELPER_5(msa_clti_u_df, void, env, i32, i32, i32, s32) +DEF_HELPER_5(msa_clei_s_df, void, env, i32, i32, i32, s32) +DEF_HELPER_5(msa_clei_u_df, void, env, i32, i32, i32, s32) +DEF_HELPER_4(msa_ldi_df, void, env, i32, i32, s32) + +DEF_HELPER_5(msa_slli_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_srai_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_srli_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_bclri_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_bseti_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_bnegi_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_binsli_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_binsri_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_sat_s_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_sat_u_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_srari_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_srlri_df, void, env, i32, i32, i32, i32) + +DEF_HELPER_5(msa_binsl_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_binsr_df, void, env, i32, i32, i32, i32) + +DEF_HELPER_4(msa_dotp_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dotp_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dotp_s_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dotp_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dotp_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dotp_u_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dpadd_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dpadd_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dpadd_s_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dpadd_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dpadd_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dpadd_u_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dpsub_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dpsub_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dpsub_s_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dpsub_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dpsub_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dpsub_u_d, void, env, i32, i32, i32) +DEF_HELPER_5(msa_sld_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_splat_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_vshf_df, void, env, i32, i32, i32, i32) + +DEF_HELPER_5(msa_sldi_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_splati_df, void, env, i32, i32, i32, i32) + +DEF_HELPER_5(msa_insve_df, void, env, i32, i32, i32, i32) +DEF_HELPER_3(msa_ctcmsa, void, env, tl, i32) +DEF_HELPER_2(msa_cfcmsa, tl, env, i32) + +DEF_HELPER_5(msa_fcaf_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fcun_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fceq_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fcueq_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fclt_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fcult_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fcle_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fcule_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fsaf_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fsun_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fseq_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fsueq_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fslt_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fsult_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fsle_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fsule_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fadd_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fsub_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fmul_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fdiv_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fmadd_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fmsub_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fexp2_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fexdo_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_ftq_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fmin_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fmin_a_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fmax_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fmax_a_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fcor_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fcune_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fcne_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_mul_q_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_madd_q_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_msub_q_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fsor_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fsune_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fsne_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_mulr_q_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_maddr_q_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_msubr_q_df, void, env, i32, i32, i32, i32) + +DEF_HELPER_4(msa_fill_df, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_copy_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_copy_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_copy_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_copy_s_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_copy_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_copy_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_copy_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_insert_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_insert_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_insert_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_insert_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_fclass_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ftrunc_s_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ftrunc_u_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_fsqrt_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_frsqrt_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_frcp_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_frint_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_flog2_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_fexupl_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_fexupr_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ffql_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ffqr_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ftint_s_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ftint_u_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ffint_s_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ffint_u_df, void, env, i32, i32, i32) + +#define MSALDST_PROTO(type) \ +DEF_HELPER_3(msa_ld_ ## type, void, env, i32, tl) \ +DEF_HELPER_3(msa_st_ ## type, void, env, i32, tl) +MSALDST_PROTO(b) +MSALDST_PROTO(h) +MSALDST_PROTO(w) +MSALDST_PROTO(d) +#undef MSALDST_PROTO --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) client-ip=216.205.24.124; envelope-from=libvir-list-bounces@redhat.com; helo=us-smtp-delivery-124.mimecast.com; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) smtp.mailfrom=libvir-list-bounces@redhat.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1610058446; cv=none; d=zohomail.com; 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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id j7sm9627579wmb.40.2021.01.07.14.27.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:27:08 -0800 (PST) X-MC-Unique: do_ktx3MNhS06TBo0_ppOA-1 X-MC-Unique: sVxRi-R0PpqNH_tN8y6_Sw-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=lwE+1tMMYcVefJ6sciUgu2/141uGXgmmBukddjUxPuE=; b=c0JagLQL23n41oyQOA3BLos3Ro2iMN9iiobOHAV9pPdRGOhtP1kHOh3oTPfUqLfGM9 fYq4Gwo5rBztWBRipjNB/QjbkDOQoGA4gZrQrozGAGuy2oVFNxqiDSad63+EsceD0eYl BfzhtMtWiKuzOzdAbskShJ8eE6wICjg1WvXKWDz/1x/RkPxJ6lGkzV+9VX74bpqy4KS3 GLx+uogS0exP2JJ0FqUorrIhsvDQtFIIHf5n648LSQtKSLMueba+Dx8UsL8q3hu4WSRc ylBJGmGtg/zqyfAz8MT+GnkM4CYPvffqbMq/08Pt4jNAIxzR+mC8mSIDZdZJrR7CE74s MJmA== X-Gm-Message-State: AOAM532vM1pBVmlN6aeYM95ARz8AZgq5hAX0FvyeAcXvMJKgBVjIlpfD nodyFuJjTLJPQiWuINAmwq4= X-Google-Smtp-Source: ABdhPJyuhUKSjnxmzTAuIU1deebNQKXXaS14b97GAjx9A7kMfekrdrz6IK3CUxsMt03XGVdSqoRC8g== X-Received: by 2002:a05:600c:cc:: with SMTP id u12mr547735wmm.42.1610058428920; Thu, 07 Jan 2021 14:27:08 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 49/66] target/mips: Declare gen_msa/_branch() in 'translate.h' Date: Thu, 7 Jan 2021 23:22:36 +0100 Message-Id: <20210107222253.20382-50-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Make gen_msa() and gen_msa_branch() public declarations so we can keep calling them once extracted from the big translate.c in the next commit. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201215225757.764263-18-f4bug@amsat.org> Tested-by: Jiaxun Yang --- target/mips/translate.h | 2 ++ target/mips/translate.c | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/target/mips/translate.h b/target/mips/translate.h index b9cd315c7f4..c61c11978c2 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -164,5 +164,7 @@ extern TCGv bcond; =20 /* MSA */ void msa_translate_init(void); +void gen_msa(DisasContext *ctx); +void gen_msa_branch(DisasContext *ctx, uint32_t op1); =20 #endif diff --git a/target/mips/translate.c b/target/mips/translate.c index 0e7b2abe8bb..e1763e5bcec 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28660,7 +28660,7 @@ static bool gen_msa_BxZ(DisasContext *ctx, int df, = int wt, int s16, bool if_not) return true; } =20 -static void gen_msa_branch(DisasContext *ctx, uint32_t op1) +void gen_msa_branch(DisasContext *ctx, uint32_t op1) { uint8_t df =3D (ctx->opcode >> 21) & 0x3; uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; @@ -30436,7 +30436,7 @@ static void gen_msa_vec(DisasContext *ctx) } } =20 -static void gen_msa(DisasContext *ctx) +void gen_msa(DisasContext *ctx) { uint32_t opcode =3D ctx->opcode; =20 --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 63.128.21.124 as permitted sender) client-ip=63.128.21.124; envelope-from=libvir-list-bounces@redhat.com; helo=us-smtp-delivery-124.mimecast.com; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of redhat.com designates 63.128.21.124 as permitted sender) smtp.mailfrom=libvir-list-bounces@redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1610058452; cv=none; d=zohomail.com; s=zohoarc; b=AIhDGVX03xFpMjujxo/ZxhuSKXcfTPymX1MHl8yzLS6rS696vJNuR72VViF/bzvEgaEqDACflEUagERnTy+7U9Qdq+E3Ee2GAfM4KbOCYk9U5R3c/QNnHqM2/BRNE7t0M1z9+gnaaRk89QkhFKSLNE9ojcQzPC4RUWEkfvFB284= ARC-Message-Signature: i=1; a=rsa-sha256; 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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id w4sm9491375wmc.13.2021.01.07.14.27.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:27:13 -0800 (PST) X-MC-Unique: gBO1ARYkP1ezlLRn3zUUHw-1 X-MC-Unique: mIyCEvG8Mfuse6iQp2THng-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=eub8KCPiiztKWW/Duw3JbnNqrPTGxcVcbsVeGHualv0=; b=GFjmu5oMXZ+mL4y0deQBVuFVGzEBxhGWtrPikWgPzdcnr6VyUfYDsMLXZ/IrzgeI0M 6XTYtszifDFOVHIZbkj8M/X2tN4jR9F/mVBd2XMEdFk+L7ypO/1Fwm30eGATxKykoY6f sdTfmPwJbQlHbWot3uTdTt7EZuIbRK1tEdda1aHtoL4dvwSvfqng+H3EJG4qS75Gh+VT FGxYuJDiNCNBVSBi4JpTKXDoL2gvUhEyAfX/02Vo5c5hzoxFd529ZLsqSnmlcRSy2Xr+ w3CFCPkkinnW8joMt9jZJ+opEP9kwctbQc+XnewkxtwKaqP8g9r2fR0FWEeHFL7psaBG CVsg== X-Gm-Message-State: AOAM533vUuRzbxXiX9cVjnYKMLMpMqeJlQV9oLP1jsj5be4K6hZpR+8K K1K6fRSO52njVIXAIKfqZeg= X-Google-Smtp-Source: ABdhPJz3yWX0bqrwFElie/rtPKI0SPKXBASxglkNsJARiITObThgiY7Q+7/ABG1MgJy8Bc5vcNxg8A== X-Received: by 2002:a05:6000:1188:: with SMTP id g8mr692438wrx.111.1610058434558; Thu, 07 Jan 2021 14:27:14 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 50/66] target/mips: Extract MSA translation routines Date: Thu, 7 Jan 2021 23:22:37 +0100 Message-Id: <20210107222253.20382-51-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.78 on 10.11.54.4 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Extract 2200 lines from the huge translate.c to a new file, 'msa_translate.c'. As there are too many inter-dependencies we don't compile it as another object yet, but keep including it in the big translate.o. We gain in code maintainability. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201120210844.2625602-5-f4bug@amsat.org> Tested-by: Jiaxun Yang --- target/mips/msa_translate.c | 2265 +++++++++++++++++++++++++++++++++++ target/mips/translate.c | 2249 ---------------------------------- target/mips/meson.build | 1 + 3 files changed, 2266 insertions(+), 2249 deletions(-) create mode 100644 target/mips/msa_translate.c diff --git a/target/mips/msa_translate.c b/target/mips/msa_translate.c new file mode 100644 index 00000000000..a4f9a6c1285 --- /dev/null +++ b/target/mips/msa_translate.c @@ -0,0 +1,2265 @@ +/* + * MIPS SIMD Architecture (MSA) translation routines + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * Copyright (c) 2006 Marius Groeger (FPU operations) + * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) + * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support) + * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support) + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ +#include "qemu/osdep.h" +#include "tcg/tcg-op.h" +#include "exec/helper-gen.h" +#include "translate.h" +#include "fpu_helper.h" +#include "internal.h" + +#define OPC_MSA (0x1E << 26) + +#define MASK_MSA_MINOR(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) +enum { + OPC_MSA_I8_00 =3D 0x00 | OPC_MSA, + OPC_MSA_I8_01 =3D 0x01 | OPC_MSA, + OPC_MSA_I8_02 =3D 0x02 | OPC_MSA, + OPC_MSA_I5_06 =3D 0x06 | OPC_MSA, + OPC_MSA_I5_07 =3D 0x07 | OPC_MSA, + OPC_MSA_BIT_09 =3D 0x09 | OPC_MSA, + OPC_MSA_BIT_0A =3D 0x0A | OPC_MSA, + OPC_MSA_3R_0D =3D 0x0D | OPC_MSA, + OPC_MSA_3R_0E =3D 0x0E | OPC_MSA, + OPC_MSA_3R_0F =3D 0x0F | OPC_MSA, + OPC_MSA_3R_10 =3D 0x10 | OPC_MSA, + OPC_MSA_3R_11 =3D 0x11 | OPC_MSA, + OPC_MSA_3R_12 =3D 0x12 | OPC_MSA, + OPC_MSA_3R_13 =3D 0x13 | OPC_MSA, + OPC_MSA_3R_14 =3D 0x14 | OPC_MSA, + OPC_MSA_3R_15 =3D 0x15 | OPC_MSA, + OPC_MSA_ELM =3D 0x19 | OPC_MSA, + OPC_MSA_3RF_1A =3D 0x1A | OPC_MSA, + OPC_MSA_3RF_1B =3D 0x1B | OPC_MSA, + OPC_MSA_3RF_1C =3D 0x1C | OPC_MSA, + OPC_MSA_VEC =3D 0x1E | OPC_MSA, + + /* MI10 instruction */ + OPC_LD_B =3D (0x20) | OPC_MSA, + OPC_LD_H =3D (0x21) | OPC_MSA, + OPC_LD_W =3D (0x22) | OPC_MSA, + OPC_LD_D =3D (0x23) | OPC_MSA, + OPC_ST_B =3D (0x24) | OPC_MSA, + OPC_ST_H =3D (0x25) | OPC_MSA, + OPC_ST_W =3D (0x26) | OPC_MSA, + OPC_ST_D =3D (0x27) | OPC_MSA, +}; + +enum { + /* I5 instruction df(bits 22..21) =3D _b, _h, _w, _d */ + OPC_ADDVI_df =3D (0x0 << 23) | OPC_MSA_I5_06, + OPC_CEQI_df =3D (0x0 << 23) | OPC_MSA_I5_07, + OPC_SUBVI_df =3D (0x1 << 23) | OPC_MSA_I5_06, + OPC_MAXI_S_df =3D (0x2 << 23) | OPC_MSA_I5_06, + OPC_CLTI_S_df =3D (0x2 << 23) | OPC_MSA_I5_07, + OPC_MAXI_U_df =3D (0x3 << 23) | OPC_MSA_I5_06, + OPC_CLTI_U_df =3D (0x3 << 23) | OPC_MSA_I5_07, + OPC_MINI_S_df =3D (0x4 << 23) | OPC_MSA_I5_06, + OPC_CLEI_S_df =3D (0x4 << 23) | OPC_MSA_I5_07, + OPC_MINI_U_df =3D (0x5 << 23) | OPC_MSA_I5_06, + OPC_CLEI_U_df =3D (0x5 << 23) | OPC_MSA_I5_07, + OPC_LDI_df =3D (0x6 << 23) | OPC_MSA_I5_07, + + /* I8 instruction */ + OPC_ANDI_B =3D (0x0 << 24) | OPC_MSA_I8_00, + OPC_BMNZI_B =3D (0x0 << 24) | OPC_MSA_I8_01, + OPC_SHF_B =3D (0x0 << 24) | OPC_MSA_I8_02, + OPC_ORI_B =3D (0x1 << 24) | OPC_MSA_I8_00, + OPC_BMZI_B =3D (0x1 << 24) | OPC_MSA_I8_01, + OPC_SHF_H =3D (0x1 << 24) | OPC_MSA_I8_02, + OPC_NORI_B =3D (0x2 << 24) | OPC_MSA_I8_00, + OPC_BSELI_B =3D (0x2 << 24) | OPC_MSA_I8_01, + OPC_SHF_W =3D (0x2 << 24) | OPC_MSA_I8_02, + OPC_XORI_B =3D (0x3 << 24) | OPC_MSA_I8_00, + + /* VEC/2R/2RF instruction */ + OPC_AND_V =3D (0x00 << 21) | OPC_MSA_VEC, + OPC_OR_V =3D (0x01 << 21) | OPC_MSA_VEC, + OPC_NOR_V =3D (0x02 << 21) | OPC_MSA_VEC, + OPC_XOR_V =3D (0x03 << 21) | OPC_MSA_VEC, + OPC_BMNZ_V =3D (0x04 << 21) | OPC_MSA_VEC, + OPC_BMZ_V =3D (0x05 << 21) | OPC_MSA_VEC, + OPC_BSEL_V =3D (0x06 << 21) | OPC_MSA_VEC, + + OPC_MSA_2R =3D (0x18 << 21) | OPC_MSA_VEC, + OPC_MSA_2RF =3D (0x19 << 21) | OPC_MSA_VEC, + + /* 2R instruction df(bits 17..16) =3D _b, _h, _w, _d */ + OPC_FILL_df =3D (0x00 << 18) | OPC_MSA_2R, + OPC_PCNT_df =3D (0x01 << 18) | OPC_MSA_2R, + OPC_NLOC_df =3D (0x02 << 18) | OPC_MSA_2R, + OPC_NLZC_df =3D (0x03 << 18) | OPC_MSA_2R, + + /* 2RF instruction df(bit 16) =3D _w, _d */ + OPC_FCLASS_df =3D (0x00 << 17) | OPC_MSA_2RF, + OPC_FTRUNC_S_df =3D (0x01 << 17) | OPC_MSA_2RF, + OPC_FTRUNC_U_df =3D (0x02 << 17) | OPC_MSA_2RF, + OPC_FSQRT_df =3D (0x03 << 17) | OPC_MSA_2RF, + OPC_FRSQRT_df =3D (0x04 << 17) | OPC_MSA_2RF, + OPC_FRCP_df =3D (0x05 << 17) | OPC_MSA_2RF, + OPC_FRINT_df =3D (0x06 << 17) | OPC_MSA_2RF, + OPC_FLOG2_df =3D (0x07 << 17) | OPC_MSA_2RF, + OPC_FEXUPL_df =3D (0x08 << 17) | OPC_MSA_2RF, + OPC_FEXUPR_df =3D (0x09 << 17) | OPC_MSA_2RF, + OPC_FFQL_df =3D (0x0A << 17) | OPC_MSA_2RF, + OPC_FFQR_df =3D (0x0B << 17) | OPC_MSA_2RF, + OPC_FTINT_S_df =3D (0x0C << 17) | OPC_MSA_2RF, + OPC_FTINT_U_df =3D (0x0D << 17) | OPC_MSA_2RF, + OPC_FFINT_S_df =3D (0x0E << 17) | OPC_MSA_2RF, + OPC_FFINT_U_df =3D (0x0F << 17) | OPC_MSA_2RF, + + /* 3R instruction df(bits 22..21) =3D _b, _h, _w, d */ + OPC_SLL_df =3D (0x0 << 23) | OPC_MSA_3R_0D, + OPC_ADDV_df =3D (0x0 << 23) | OPC_MSA_3R_0E, + OPC_CEQ_df =3D (0x0 << 23) | OPC_MSA_3R_0F, + OPC_ADD_A_df =3D (0x0 << 23) | OPC_MSA_3R_10, + OPC_SUBS_S_df =3D (0x0 << 23) | OPC_MSA_3R_11, + OPC_MULV_df =3D (0x0 << 23) | OPC_MSA_3R_12, + OPC_DOTP_S_df =3D (0x0 << 23) | OPC_MSA_3R_13, + OPC_SLD_df =3D (0x0 << 23) | OPC_MSA_3R_14, + OPC_VSHF_df =3D (0x0 << 23) | OPC_MSA_3R_15, + OPC_SRA_df =3D (0x1 << 23) | OPC_MSA_3R_0D, + OPC_SUBV_df =3D (0x1 << 23) | OPC_MSA_3R_0E, + OPC_ADDS_A_df =3D (0x1 << 23) | OPC_MSA_3R_10, + OPC_SUBS_U_df =3D (0x1 << 23) | OPC_MSA_3R_11, + OPC_MADDV_df =3D (0x1 << 23) | OPC_MSA_3R_12, + OPC_DOTP_U_df =3D (0x1 << 23) | OPC_MSA_3R_13, + OPC_SPLAT_df =3D (0x1 << 23) | OPC_MSA_3R_14, + OPC_SRAR_df =3D (0x1 << 23) | OPC_MSA_3R_15, + OPC_SRL_df =3D (0x2 << 23) | OPC_MSA_3R_0D, + OPC_MAX_S_df =3D (0x2 << 23) | OPC_MSA_3R_0E, + OPC_CLT_S_df =3D (0x2 << 23) | OPC_MSA_3R_0F, + OPC_ADDS_S_df =3D (0x2 << 23) | OPC_MSA_3R_10, + OPC_SUBSUS_U_df =3D (0x2 << 23) | OPC_MSA_3R_11, + OPC_MSUBV_df =3D (0x2 << 23) | OPC_MSA_3R_12, + OPC_DPADD_S_df =3D (0x2 << 23) | OPC_MSA_3R_13, + OPC_PCKEV_df =3D (0x2 << 23) | OPC_MSA_3R_14, + OPC_SRLR_df =3D (0x2 << 23) | OPC_MSA_3R_15, + OPC_BCLR_df =3D (0x3 << 23) | OPC_MSA_3R_0D, + OPC_MAX_U_df =3D (0x3 << 23) | OPC_MSA_3R_0E, + OPC_CLT_U_df =3D (0x3 << 23) | OPC_MSA_3R_0F, + OPC_ADDS_U_df =3D (0x3 << 23) | OPC_MSA_3R_10, + OPC_SUBSUU_S_df =3D (0x3 << 23) | OPC_MSA_3R_11, + OPC_DPADD_U_df =3D (0x3 << 23) | OPC_MSA_3R_13, + OPC_PCKOD_df =3D (0x3 << 23) | OPC_MSA_3R_14, + OPC_BSET_df =3D (0x4 << 23) | OPC_MSA_3R_0D, + OPC_MIN_S_df =3D (0x4 << 23) | OPC_MSA_3R_0E, + OPC_CLE_S_df =3D (0x4 << 23) | OPC_MSA_3R_0F, + OPC_AVE_S_df =3D (0x4 << 23) | OPC_MSA_3R_10, + OPC_ASUB_S_df =3D (0x4 << 23) | OPC_MSA_3R_11, + OPC_DIV_S_df =3D (0x4 << 23) | OPC_MSA_3R_12, + OPC_DPSUB_S_df =3D (0x4 << 23) | OPC_MSA_3R_13, + OPC_ILVL_df =3D (0x4 << 23) | OPC_MSA_3R_14, + OPC_HADD_S_df =3D (0x4 << 23) | OPC_MSA_3R_15, + OPC_BNEG_df =3D (0x5 << 23) | OPC_MSA_3R_0D, + OPC_MIN_U_df =3D (0x5 << 23) | OPC_MSA_3R_0E, + OPC_CLE_U_df =3D (0x5 << 23) | OPC_MSA_3R_0F, + OPC_AVE_U_df =3D (0x5 << 23) | OPC_MSA_3R_10, + OPC_ASUB_U_df =3D (0x5 << 23) | OPC_MSA_3R_11, + OPC_DIV_U_df =3D (0x5 << 23) | OPC_MSA_3R_12, + OPC_DPSUB_U_df =3D (0x5 << 23) | OPC_MSA_3R_13, + OPC_ILVR_df =3D (0x5 << 23) | OPC_MSA_3R_14, + OPC_HADD_U_df =3D (0x5 << 23) | OPC_MSA_3R_15, + OPC_BINSL_df =3D (0x6 << 23) | OPC_MSA_3R_0D, + OPC_MAX_A_df =3D (0x6 << 23) | OPC_MSA_3R_0E, + OPC_AVER_S_df =3D (0x6 << 23) | OPC_MSA_3R_10, + OPC_MOD_S_df =3D (0x6 << 23) | OPC_MSA_3R_12, + OPC_ILVEV_df =3D (0x6 << 23) | OPC_MSA_3R_14, + OPC_HSUB_S_df =3D (0x6 << 23) | OPC_MSA_3R_15, + OPC_BINSR_df =3D (0x7 << 23) | OPC_MSA_3R_0D, + OPC_MIN_A_df =3D (0x7 << 23) | OPC_MSA_3R_0E, + OPC_AVER_U_df =3D (0x7 << 23) | OPC_MSA_3R_10, + OPC_MOD_U_df =3D (0x7 << 23) | OPC_MSA_3R_12, + OPC_ILVOD_df =3D (0x7 << 23) | OPC_MSA_3R_14, + OPC_HSUB_U_df =3D (0x7 << 23) | OPC_MSA_3R_15, + + /* ELM instructions df(bits 21..16) =3D _b, _h, _w, _d */ + OPC_SLDI_df =3D (0x0 << 22) | (0x00 << 16) | OPC_MSA_ELM, + OPC_CTCMSA =3D (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM, + OPC_SPLATI_df =3D (0x1 << 22) | (0x00 << 16) | OPC_MSA_ELM, + OPC_CFCMSA =3D (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM, + OPC_COPY_S_df =3D (0x2 << 22) | (0x00 << 16) | OPC_MSA_ELM, + OPC_MOVE_V =3D (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM, + OPC_COPY_U_df =3D (0x3 << 22) | (0x00 << 16) | OPC_MSA_ELM, + OPC_INSERT_df =3D (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM, + OPC_INSVE_df =3D (0x5 << 22) | (0x00 << 16) | OPC_MSA_ELM, + + /* 3RF instruction _df(bit 21) =3D _w, _d */ + OPC_FCAF_df =3D (0x0 << 22) | OPC_MSA_3RF_1A, + OPC_FADD_df =3D (0x0 << 22) | OPC_MSA_3RF_1B, + OPC_FCUN_df =3D (0x1 << 22) | OPC_MSA_3RF_1A, + OPC_FSUB_df =3D (0x1 << 22) | OPC_MSA_3RF_1B, + OPC_FCOR_df =3D (0x1 << 22) | OPC_MSA_3RF_1C, + OPC_FCEQ_df =3D (0x2 << 22) | OPC_MSA_3RF_1A, + OPC_FMUL_df =3D (0x2 << 22) | OPC_MSA_3RF_1B, + OPC_FCUNE_df =3D (0x2 << 22) | OPC_MSA_3RF_1C, + OPC_FCUEQ_df =3D (0x3 << 22) | OPC_MSA_3RF_1A, + OPC_FDIV_df =3D (0x3 << 22) | OPC_MSA_3RF_1B, + OPC_FCNE_df =3D (0x3 << 22) | OPC_MSA_3RF_1C, + OPC_FCLT_df =3D (0x4 << 22) | OPC_MSA_3RF_1A, + OPC_FMADD_df =3D (0x4 << 22) | OPC_MSA_3RF_1B, + OPC_MUL_Q_df =3D (0x4 << 22) | OPC_MSA_3RF_1C, + OPC_FCULT_df =3D (0x5 << 22) | OPC_MSA_3RF_1A, + OPC_FMSUB_df =3D (0x5 << 22) | OPC_MSA_3RF_1B, + OPC_MADD_Q_df =3D (0x5 << 22) | OPC_MSA_3RF_1C, + OPC_FCLE_df =3D (0x6 << 22) | OPC_MSA_3RF_1A, + OPC_MSUB_Q_df =3D (0x6 << 22) | OPC_MSA_3RF_1C, + OPC_FCULE_df =3D (0x7 << 22) | OPC_MSA_3RF_1A, + OPC_FEXP2_df =3D (0x7 << 22) | OPC_MSA_3RF_1B, + OPC_FSAF_df =3D (0x8 << 22) | OPC_MSA_3RF_1A, + OPC_FEXDO_df =3D (0x8 << 22) | OPC_MSA_3RF_1B, + OPC_FSUN_df =3D (0x9 << 22) | OPC_MSA_3RF_1A, + OPC_FSOR_df =3D (0x9 << 22) | OPC_MSA_3RF_1C, + OPC_FSEQ_df =3D (0xA << 22) | OPC_MSA_3RF_1A, + OPC_FTQ_df =3D (0xA << 22) | OPC_MSA_3RF_1B, + OPC_FSUNE_df =3D (0xA << 22) | OPC_MSA_3RF_1C, + OPC_FSUEQ_df =3D (0xB << 22) | OPC_MSA_3RF_1A, + OPC_FSNE_df =3D (0xB << 22) | OPC_MSA_3RF_1C, + OPC_FSLT_df =3D (0xC << 22) | OPC_MSA_3RF_1A, + OPC_FMIN_df =3D (0xC << 22) | OPC_MSA_3RF_1B, + OPC_MULR_Q_df =3D (0xC << 22) | OPC_MSA_3RF_1C, + OPC_FSULT_df =3D (0xD << 22) | OPC_MSA_3RF_1A, + OPC_FMIN_A_df =3D (0xD << 22) | OPC_MSA_3RF_1B, + OPC_MADDR_Q_df =3D (0xD << 22) | OPC_MSA_3RF_1C, + OPC_FSLE_df =3D (0xE << 22) | OPC_MSA_3RF_1A, + OPC_FMAX_df =3D (0xE << 22) | OPC_MSA_3RF_1B, + OPC_MSUBR_Q_df =3D (0xE << 22) | OPC_MSA_3RF_1C, + OPC_FSULE_df =3D (0xF << 22) | OPC_MSA_3RF_1A, + OPC_FMAX_A_df =3D (0xF << 22) | OPC_MSA_3RF_1B, + + /* BIT instruction df(bits 22..16) =3D _B _H _W _D */ + OPC_SLLI_df =3D (0x0 << 23) | OPC_MSA_BIT_09, + OPC_SAT_S_df =3D (0x0 << 23) | OPC_MSA_BIT_0A, + OPC_SRAI_df =3D (0x1 << 23) | OPC_MSA_BIT_09, + OPC_SAT_U_df =3D (0x1 << 23) | OPC_MSA_BIT_0A, + OPC_SRLI_df =3D (0x2 << 23) | OPC_MSA_BIT_09, + OPC_SRARI_df =3D (0x2 << 23) | OPC_MSA_BIT_0A, + OPC_BCLRI_df =3D (0x3 << 23) | OPC_MSA_BIT_09, + OPC_SRLRI_df =3D (0x3 << 23) | OPC_MSA_BIT_0A, + OPC_BSETI_df =3D (0x4 << 23) | OPC_MSA_BIT_09, + OPC_BNEGI_df =3D (0x5 << 23) | OPC_MSA_BIT_09, + OPC_BINSLI_df =3D (0x6 << 23) | OPC_MSA_BIT_09, + OPC_BINSRI_df =3D (0x7 << 23) | OPC_MSA_BIT_09, +}; + +static const char * const msaregnames[] =3D { + "w0.d0", "w0.d1", "w1.d0", "w1.d1", + "w2.d0", "w2.d1", "w3.d0", "w3.d1", + "w4.d0", "w4.d1", "w5.d0", "w5.d1", + "w6.d0", "w6.d1", "w7.d0", "w7.d1", + "w8.d0", "w8.d1", "w9.d0", "w9.d1", + "w10.d0", "w10.d1", "w11.d0", "w11.d1", + "w12.d0", "w12.d1", "w13.d0", "w13.d1", + "w14.d0", "w14.d1", "w15.d0", "w15.d1", + "w16.d0", "w16.d1", "w17.d0", "w17.d1", + "w18.d0", "w18.d1", "w19.d0", "w19.d1", + "w20.d0", "w20.d1", "w21.d0", "w21.d1", + "w22.d0", "w22.d1", "w23.d0", "w23.d1", + "w24.d0", "w24.d1", "w25.d0", "w25.d1", + "w26.d0", "w26.d1", "w27.d0", "w27.d1", + "w28.d0", "w28.d1", "w29.d0", "w29.d1", + "w30.d0", "w30.d1", "w31.d0", "w31.d1", +}; + +static TCGv_i64 msa_wr_d[64]; + +void msa_translate_init(void) +{ + int i; + + for (i =3D 0; i < 32; i++) { + int off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); + + /* + * The MSA vector registers are mapped on the + * scalar floating-point unit (FPU) registers. + */ + msa_wr_d[i * 2] =3D fpu_f64[i]; + off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); + msa_wr_d[i * 2 + 1] =3D + tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1= ]); + } +} + +static inline int check_msa_access(DisasContext *ctx) +{ + if (unlikely((ctx->hflags & MIPS_HFLAG_FPU) && + !(ctx->hflags & MIPS_HFLAG_F64))) { + gen_reserved_instruction(ctx); + return 0; + } + + if (unlikely(!(ctx->hflags & MIPS_HFLAG_MSA))) { + generate_exception_end(ctx, EXCP_MSADIS); + return 0; + } + return 1; +} + +static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt) +{ + /* generates tcg ops to check if any element is 0 */ + /* Note this function only works with MSA_WRLEN =3D 128 */ + uint64_t eval_zero_or_big =3D 0; + uint64_t eval_big =3D 0; + TCGv_i64 t0 =3D tcg_temp_new_i64(); + TCGv_i64 t1 =3D tcg_temp_new_i64(); + switch (df) { + case DF_BYTE: + eval_zero_or_big =3D 0x0101010101010101ULL; + eval_big =3D 0x8080808080808080ULL; + break; + case DF_HALF: + eval_zero_or_big =3D 0x0001000100010001ULL; + eval_big =3D 0x8000800080008000ULL; + break; + case DF_WORD: + eval_zero_or_big =3D 0x0000000100000001ULL; + eval_big =3D 0x8000000080000000ULL; + break; + case DF_DOUBLE: + eval_zero_or_big =3D 0x0000000000000001ULL; + eval_big =3D 0x8000000000000000ULL; + break; + } + tcg_gen_subi_i64(t0, msa_wr_d[wt << 1], eval_zero_or_big); + tcg_gen_andc_i64(t0, t0, msa_wr_d[wt << 1]); + tcg_gen_andi_i64(t0, t0, eval_big); + tcg_gen_subi_i64(t1, msa_wr_d[(wt << 1) + 1], eval_zero_or_big); + tcg_gen_andc_i64(t1, t1, msa_wr_d[(wt << 1) + 1]); + tcg_gen_andi_i64(t1, t1, eval_big); + tcg_gen_or_i64(t0, t0, t1); + /* if all bits are zero then all elements are not zero */ + /* if some bit is non-zero then some element is zero */ + tcg_gen_setcondi_i64(TCG_COND_NE, t0, t0, 0); + tcg_gen_trunc_i64_tl(tresult, t0); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); +} + +static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond) +{ + TCGv_i64 t0; + + check_msa_access(ctx); + + if (ctx->hflags & MIPS_HFLAG_BMASK) { + gen_reserved_instruction(ctx); + return true; + } + t0 =3D tcg_temp_new_i64(); + tcg_gen_or_i64(t0, msa_wr_d[wt << 1], msa_wr_d[(wt << 1) + 1]); + tcg_gen_setcondi_i64(cond, t0, t0, 0); + tcg_gen_trunc_i64_tl(bcond, t0); + tcg_temp_free_i64(t0); + + ctx->btarget =3D ctx->base.pc_next + (s16 << 2) + 4; + + ctx->hflags |=3D MIPS_HFLAG_BC; + ctx->hflags |=3D MIPS_HFLAG_BDS32; + + return true; +} + +static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool i= f_not) +{ + check_msa_access(ctx); + + if (ctx->hflags & MIPS_HFLAG_BMASK) { + gen_reserved_instruction(ctx); + return true; + } + + gen_check_zero_element(bcond, df, wt); + if (if_not) { + tcg_gen_setcondi_tl(TCG_COND_EQ, bcond, bcond, 0); + } + + ctx->btarget =3D ctx->base.pc_next + (s16 << 2) + 4; + ctx->hflags |=3D MIPS_HFLAG_BC; + ctx->hflags |=3D MIPS_HFLAG_BDS32; + + return true; +} + +void gen_msa_branch(DisasContext *ctx, uint32_t op1) +{ + uint8_t df =3D (ctx->opcode >> 21) & 0x3; + uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; + int64_t s16 =3D (int16_t)ctx->opcode; + + switch (op1) { + case OPC_BZ_V: + case OPC_BNZ_V: + gen_msa_BxZ_V(ctx, wt, s16, (op1 =3D=3D OPC_BZ_V) ? + TCG_COND_EQ : TCG_COND_NE); + break; + case OPC_BZ_B: + case OPC_BZ_H: + case OPC_BZ_W: + case OPC_BZ_D: + gen_msa_BxZ(ctx, df, wt, s16, false); + break; + case OPC_BNZ_B: + case OPC_BNZ_H: + case OPC_BNZ_W: + case OPC_BNZ_D: + gen_msa_BxZ(ctx, df, wt, s16, true); + break; + } +} + +static void gen_msa_i8(DisasContext *ctx) +{ +#define MASK_MSA_I8(op) (MASK_MSA_MINOR(op) | (op & (0x03 << 24))) + uint8_t i8 =3D (ctx->opcode >> 16) & 0xff; + uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; + uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; + + TCGv_i32 twd =3D tcg_const_i32(wd); + TCGv_i32 tws =3D tcg_const_i32(ws); + TCGv_i32 ti8 =3D tcg_const_i32(i8); + + switch (MASK_MSA_I8(ctx->opcode)) { + case OPC_ANDI_B: + gen_helper_msa_andi_b(cpu_env, twd, tws, ti8); + break; + case OPC_ORI_B: + gen_helper_msa_ori_b(cpu_env, twd, tws, ti8); + break; + case OPC_NORI_B: + gen_helper_msa_nori_b(cpu_env, twd, tws, ti8); + break; + case OPC_XORI_B: + gen_helper_msa_xori_b(cpu_env, twd, tws, ti8); + break; + case OPC_BMNZI_B: + gen_helper_msa_bmnzi_b(cpu_env, twd, tws, ti8); + break; + case OPC_BMZI_B: + gen_helper_msa_bmzi_b(cpu_env, twd, tws, ti8); + break; + case OPC_BSELI_B: + gen_helper_msa_bseli_b(cpu_env, twd, tws, ti8); + break; + case OPC_SHF_B: + case OPC_SHF_H: + case OPC_SHF_W: + { + uint8_t df =3D (ctx->opcode >> 24) & 0x3; + if (df =3D=3D DF_DOUBLE) { + gen_reserved_instruction(ctx); + } else { + TCGv_i32 tdf =3D tcg_const_i32(df); + gen_helper_msa_shf_df(cpu_env, tdf, twd, tws, ti8); + tcg_temp_free_i32(tdf); + } + } + break; + default: + MIPS_INVAL("MSA instruction"); + gen_reserved_instruction(ctx); + break; + } + + tcg_temp_free_i32(twd); + tcg_temp_free_i32(tws); + tcg_temp_free_i32(ti8); +} + +static void gen_msa_i5(DisasContext *ctx) +{ +#define MASK_MSA_I5(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) + uint8_t df =3D (ctx->opcode >> 21) & 0x3; + int8_t s5 =3D (int8_t) sextract32(ctx->opcode, 16, 5); + uint8_t u5 =3D (ctx->opcode >> 16) & 0x1f; + uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; + uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; + + TCGv_i32 tdf =3D tcg_const_i32(df); + TCGv_i32 twd =3D tcg_const_i32(wd); + TCGv_i32 tws =3D tcg_const_i32(ws); + TCGv_i32 timm =3D tcg_temp_new_i32(); + tcg_gen_movi_i32(timm, u5); + + switch (MASK_MSA_I5(ctx->opcode)) { + case OPC_ADDVI_df: + gen_helper_msa_addvi_df(cpu_env, tdf, twd, tws, timm); + break; + case OPC_SUBVI_df: + gen_helper_msa_subvi_df(cpu_env, tdf, twd, tws, timm); + break; + case OPC_MAXI_S_df: + tcg_gen_movi_i32(timm, s5); + gen_helper_msa_maxi_s_df(cpu_env, tdf, twd, tws, timm); + break; + case OPC_MAXI_U_df: + gen_helper_msa_maxi_u_df(cpu_env, tdf, twd, tws, timm); + break; + case OPC_MINI_S_df: + tcg_gen_movi_i32(timm, s5); + gen_helper_msa_mini_s_df(cpu_env, tdf, twd, tws, timm); + break; + case OPC_MINI_U_df: + gen_helper_msa_mini_u_df(cpu_env, tdf, twd, tws, timm); + break; + case OPC_CEQI_df: + tcg_gen_movi_i32(timm, s5); + gen_helper_msa_ceqi_df(cpu_env, tdf, twd, tws, timm); + break; + case OPC_CLTI_S_df: + tcg_gen_movi_i32(timm, s5); + gen_helper_msa_clti_s_df(cpu_env, tdf, twd, tws, timm); + break; + case OPC_CLTI_U_df: + gen_helper_msa_clti_u_df(cpu_env, tdf, twd, tws, timm); + break; + case OPC_CLEI_S_df: + tcg_gen_movi_i32(timm, s5); + gen_helper_msa_clei_s_df(cpu_env, tdf, twd, tws, timm); + break; + case OPC_CLEI_U_df: + gen_helper_msa_clei_u_df(cpu_env, tdf, twd, tws, timm); + break; + case OPC_LDI_df: + { + int32_t s10 =3D sextract32(ctx->opcode, 11, 10); + tcg_gen_movi_i32(timm, s10); + gen_helper_msa_ldi_df(cpu_env, tdf, twd, timm); + } + break; + default: + MIPS_INVAL("MSA instruction"); + gen_reserved_instruction(ctx); + break; + } + + tcg_temp_free_i32(tdf); + tcg_temp_free_i32(twd); + tcg_temp_free_i32(tws); + tcg_temp_free_i32(timm); +} + +static void gen_msa_bit(DisasContext *ctx) +{ +#define MASK_MSA_BIT(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) + uint8_t dfm =3D (ctx->opcode >> 16) & 0x7f; + uint32_t df =3D 0, m =3D 0; + uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; + uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; + + TCGv_i32 tdf; + TCGv_i32 tm; + TCGv_i32 twd; + TCGv_i32 tws; + + if ((dfm & 0x40) =3D=3D 0x00) { + m =3D dfm & 0x3f; + df =3D DF_DOUBLE; + } else if ((dfm & 0x60) =3D=3D 0x40) { + m =3D dfm & 0x1f; + df =3D DF_WORD; + } else if ((dfm & 0x70) =3D=3D 0x60) { + m =3D dfm & 0x0f; + df =3D DF_HALF; + } else if ((dfm & 0x78) =3D=3D 0x70) { + m =3D dfm & 0x7; + df =3D DF_BYTE; + } else { + gen_reserved_instruction(ctx); + return; + } + + tdf =3D tcg_const_i32(df); + tm =3D tcg_const_i32(m); + twd =3D tcg_const_i32(wd); + tws =3D tcg_const_i32(ws); + + switch (MASK_MSA_BIT(ctx->opcode)) { + case OPC_SLLI_df: + gen_helper_msa_slli_df(cpu_env, tdf, twd, tws, tm); + break; + case OPC_SRAI_df: + gen_helper_msa_srai_df(cpu_env, tdf, twd, tws, tm); + break; + case OPC_SRLI_df: + gen_helper_msa_srli_df(cpu_env, tdf, twd, tws, tm); + break; + case OPC_BCLRI_df: + gen_helper_msa_bclri_df(cpu_env, tdf, twd, tws, tm); + break; + case OPC_BSETI_df: + gen_helper_msa_bseti_df(cpu_env, tdf, twd, tws, tm); + break; + case OPC_BNEGI_df: + gen_helper_msa_bnegi_df(cpu_env, tdf, twd, tws, tm); + break; + case OPC_BINSLI_df: + gen_helper_msa_binsli_df(cpu_env, tdf, twd, tws, tm); + break; + case OPC_BINSRI_df: + gen_helper_msa_binsri_df(cpu_env, tdf, twd, tws, tm); + break; + case OPC_SAT_S_df: + gen_helper_msa_sat_s_df(cpu_env, tdf, twd, tws, tm); + break; + case OPC_SAT_U_df: + gen_helper_msa_sat_u_df(cpu_env, tdf, twd, tws, tm); + break; + case OPC_SRARI_df: + gen_helper_msa_srari_df(cpu_env, tdf, twd, tws, tm); + break; + case OPC_SRLRI_df: + gen_helper_msa_srlri_df(cpu_env, tdf, twd, tws, tm); + break; + default: + MIPS_INVAL("MSA instruction"); + gen_reserved_instruction(ctx); + break; + } + + tcg_temp_free_i32(tdf); + tcg_temp_free_i32(tm); + tcg_temp_free_i32(twd); + tcg_temp_free_i32(tws); +} + +static void gen_msa_3r(DisasContext *ctx) +{ +#define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) + uint8_t df =3D (ctx->opcode >> 21) & 0x3; + uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; + uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; + uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; + + TCGv_i32 tdf =3D tcg_const_i32(df); + TCGv_i32 twd =3D tcg_const_i32(wd); + TCGv_i32 tws =3D tcg_const_i32(ws); + TCGv_i32 twt =3D tcg_const_i32(wt); + + switch (MASK_MSA_3R(ctx->opcode)) { + case OPC_BINSL_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_binsl_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_binsl_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_binsl_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_binsl_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_BINSR_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_binsr_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_binsr_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_binsr_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_binsr_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_BCLR_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_bclr_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_bclr_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_bclr_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_bclr_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_BNEG_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_bneg_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_bneg_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_bneg_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_bneg_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_BSET_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_bset_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_bset_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_bset_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_bset_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ADD_A_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_add_a_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_add_a_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_add_a_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_add_a_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ADDS_A_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_adds_a_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_adds_a_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_adds_a_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_adds_a_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ADDS_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_adds_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_adds_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_adds_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_adds_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ADDS_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_adds_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_adds_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_adds_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_adds_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ADDV_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_addv_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_addv_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_addv_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_addv_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_AVE_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_ave_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_ave_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_ave_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_ave_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_AVE_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_ave_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_ave_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_ave_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_ave_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_AVER_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_aver_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_aver_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_aver_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_aver_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_AVER_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_aver_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_aver_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_aver_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_aver_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_CEQ_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_ceq_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_ceq_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_ceq_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_ceq_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_CLE_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_cle_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_cle_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_cle_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_cle_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_CLE_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_cle_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_cle_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_cle_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_cle_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_CLT_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_clt_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_clt_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_clt_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_clt_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_CLT_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_clt_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_clt_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_clt_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_clt_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_DIV_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_div_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_div_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_div_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_div_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_DIV_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_div_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_div_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_div_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_div_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MAX_A_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_max_a_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_max_a_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_max_a_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_max_a_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MAX_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_max_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_max_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_max_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_max_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MAX_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_max_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_max_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_max_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_max_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MIN_A_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_min_a_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_min_a_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_min_a_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_min_a_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MIN_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_min_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_min_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_min_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_min_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MIN_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_min_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_min_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_min_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_min_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MOD_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_mod_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_mod_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_mod_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_mod_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MOD_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_mod_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_mod_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_mod_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_mod_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MADDV_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_maddv_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_maddv_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_maddv_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_maddv_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MSUBV_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_msubv_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_msubv_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_msubv_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_msubv_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ASUB_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_asub_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_asub_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_asub_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_asub_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ASUB_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_asub_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_asub_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_asub_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_asub_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ILVEV_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_ilvev_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_ilvev_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_ilvev_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_ilvev_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ILVOD_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_ilvod_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_ilvod_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_ilvod_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_ilvod_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ILVL_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_ilvl_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_ilvl_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_ilvl_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_ilvl_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ILVR_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_ilvr_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_ilvr_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_ilvr_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_ilvr_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_PCKEV_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_pckev_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_pckev_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_pckev_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_pckev_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_PCKOD_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_pckod_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_pckod_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_pckod_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_pckod_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_SLL_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_sll_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_sll_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_sll_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_sll_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_SRA_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_sra_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_sra_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_sra_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_sra_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_SRAR_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_srar_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_srar_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_srar_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_srar_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_SRL_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_srl_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_srl_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_srl_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_srl_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_SRLR_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_srlr_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_srlr_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_srlr_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_srlr_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_SUBS_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_subs_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_subs_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_subs_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_subs_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MULV_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_mulv_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_mulv_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_mulv_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_mulv_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_SLD_df: + gen_helper_msa_sld_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_VSHF_df: + gen_helper_msa_vshf_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_SUBV_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_subv_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_subv_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_subv_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_subv_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_SUBS_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_subs_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_subs_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_subs_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_subs_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_SPLAT_df: + gen_helper_msa_splat_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_SUBSUS_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_subsus_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_subsus_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_subsus_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_subsus_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_SUBSUU_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_subsuu_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_subsuu_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_subsuu_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_subsuu_s_d(cpu_env, twd, tws, twt); + break; + } + break; + + case OPC_DOTP_S_df: + case OPC_DOTP_U_df: + case OPC_DPADD_S_df: + case OPC_DPADD_U_df: + case OPC_DPSUB_S_df: + case OPC_HADD_S_df: + case OPC_DPSUB_U_df: + case OPC_HADD_U_df: + case OPC_HSUB_S_df: + case OPC_HSUB_U_df: + if (df =3D=3D DF_BYTE) { + gen_reserved_instruction(ctx); + break; + } + switch (MASK_MSA_3R(ctx->opcode)) { + case OPC_HADD_S_df: + switch (df) { + case DF_HALF: + gen_helper_msa_hadd_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_hadd_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_hadd_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_HADD_U_df: + switch (df) { + case DF_HALF: + gen_helper_msa_hadd_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_hadd_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_hadd_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_HSUB_S_df: + switch (df) { + case DF_HALF: + gen_helper_msa_hsub_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_hsub_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_hsub_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_HSUB_U_df: + switch (df) { + case DF_HALF: + gen_helper_msa_hsub_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_hsub_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_hsub_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_DOTP_S_df: + switch (df) { + case DF_HALF: + gen_helper_msa_dotp_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_dotp_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_dotp_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_DOTP_U_df: + switch (df) { + case DF_HALF: + gen_helper_msa_dotp_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_dotp_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_dotp_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_DPADD_S_df: + switch (df) { + case DF_HALF: + gen_helper_msa_dpadd_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_dpadd_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_dpadd_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_DPADD_U_df: + switch (df) { + case DF_HALF: + gen_helper_msa_dpadd_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_dpadd_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_dpadd_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_DPSUB_S_df: + switch (df) { + case DF_HALF: + gen_helper_msa_dpsub_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_dpsub_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_dpsub_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_DPSUB_U_df: + switch (df) { + case DF_HALF: + gen_helper_msa_dpsub_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_dpsub_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_dpsub_u_d(cpu_env, twd, tws, twt); + break; + } + break; + } + break; + default: + MIPS_INVAL("MSA instruction"); + gen_reserved_instruction(ctx); + break; + } + tcg_temp_free_i32(twd); + tcg_temp_free_i32(tws); + tcg_temp_free_i32(twt); + tcg_temp_free_i32(tdf); +} + +static void gen_msa_elm_3e(DisasContext *ctx) +{ +#define MASK_MSA_ELM_DF3E(op) (MASK_MSA_MINOR(op) | (op & (0x3FF << 16))) + uint8_t source =3D (ctx->opcode >> 11) & 0x1f; + uint8_t dest =3D (ctx->opcode >> 6) & 0x1f; + TCGv telm =3D tcg_temp_new(); + TCGv_i32 tsr =3D tcg_const_i32(source); + TCGv_i32 tdt =3D tcg_const_i32(dest); + + switch (MASK_MSA_ELM_DF3E(ctx->opcode)) { + case OPC_CTCMSA: + gen_load_gpr(telm, source); + gen_helper_msa_ctcmsa(cpu_env, telm, tdt); + break; + case OPC_CFCMSA: + gen_helper_msa_cfcmsa(telm, cpu_env, tsr); + gen_store_gpr(telm, dest); + break; + case OPC_MOVE_V: + gen_helper_msa_move_v(cpu_env, tdt, tsr); + break; + default: + MIPS_INVAL("MSA instruction"); + gen_reserved_instruction(ctx); + break; + } + + tcg_temp_free(telm); + tcg_temp_free_i32(tdt); + tcg_temp_free_i32(tsr); +} + +static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n) +{ +#define MASK_MSA_ELM(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22))) + uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; + uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; + + TCGv_i32 tws =3D tcg_const_i32(ws); + TCGv_i32 twd =3D tcg_const_i32(wd); + TCGv_i32 tn =3D tcg_const_i32(n); + TCGv_i32 tdf =3D tcg_const_i32(df); + + switch (MASK_MSA_ELM(ctx->opcode)) { + case OPC_SLDI_df: + gen_helper_msa_sldi_df(cpu_env, tdf, twd, tws, tn); + break; + case OPC_SPLATI_df: + gen_helper_msa_splati_df(cpu_env, tdf, twd, tws, tn); + break; + case OPC_INSVE_df: + gen_helper_msa_insve_df(cpu_env, tdf, twd, tws, tn); + break; + case OPC_COPY_S_df: + case OPC_COPY_U_df: + case OPC_INSERT_df: +#if !defined(TARGET_MIPS64) + /* Double format valid only for MIPS64 */ + if (df =3D=3D DF_DOUBLE) { + gen_reserved_instruction(ctx); + break; + } + if ((MASK_MSA_ELM(ctx->opcode) =3D=3D OPC_COPY_U_df) && + (df =3D=3D DF_WORD)) { + gen_reserved_instruction(ctx); + break; + } +#endif + switch (MASK_MSA_ELM(ctx->opcode)) { + case OPC_COPY_S_df: + if (likely(wd !=3D 0)) { + switch (df) { + case DF_BYTE: + gen_helper_msa_copy_s_b(cpu_env, twd, tws, tn); + break; + case DF_HALF: + gen_helper_msa_copy_s_h(cpu_env, twd, tws, tn); + break; + case DF_WORD: + gen_helper_msa_copy_s_w(cpu_env, twd, tws, tn); + break; +#if defined(TARGET_MIPS64) + case DF_DOUBLE: + gen_helper_msa_copy_s_d(cpu_env, twd, tws, tn); + break; +#endif + default: + assert(0); + } + } + break; + case OPC_COPY_U_df: + if (likely(wd !=3D 0)) { + switch (df) { + case DF_BYTE: + gen_helper_msa_copy_u_b(cpu_env, twd, tws, tn); + break; + case DF_HALF: + gen_helper_msa_copy_u_h(cpu_env, twd, tws, tn); + break; +#if defined(TARGET_MIPS64) + case DF_WORD: + gen_helper_msa_copy_u_w(cpu_env, twd, tws, tn); + break; +#endif + default: + assert(0); + } + } + break; + case OPC_INSERT_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_insert_b(cpu_env, twd, tws, tn); + break; + case DF_HALF: + gen_helper_msa_insert_h(cpu_env, twd, tws, tn); + break; + case DF_WORD: + gen_helper_msa_insert_w(cpu_env, twd, tws, tn); + break; +#if defined(TARGET_MIPS64) + case DF_DOUBLE: + gen_helper_msa_insert_d(cpu_env, twd, tws, tn); + break; +#endif + default: + assert(0); + } + break; + } + break; + default: + MIPS_INVAL("MSA instruction"); + gen_reserved_instruction(ctx); + } + tcg_temp_free_i32(twd); + tcg_temp_free_i32(tws); + tcg_temp_free_i32(tn); + tcg_temp_free_i32(tdf); +} + +static void gen_msa_elm(DisasContext *ctx) +{ + uint8_t dfn =3D (ctx->opcode >> 16) & 0x3f; + uint32_t df =3D 0, n =3D 0; + + if ((dfn & 0x30) =3D=3D 0x00) { + n =3D dfn & 0x0f; + df =3D DF_BYTE; + } else if ((dfn & 0x38) =3D=3D 0x20) { + n =3D dfn & 0x07; + df =3D DF_HALF; + } else if ((dfn & 0x3c) =3D=3D 0x30) { + n =3D dfn & 0x03; + df =3D DF_WORD; + } else if ((dfn & 0x3e) =3D=3D 0x38) { + n =3D dfn & 0x01; + df =3D DF_DOUBLE; + } else if (dfn =3D=3D 0x3E) { + /* CTCMSA, CFCMSA, MOVE.V */ + gen_msa_elm_3e(ctx); + return; + } else { + gen_reserved_instruction(ctx); + return; + } + + gen_msa_elm_df(ctx, df, n); +} + +static void gen_msa_3rf(DisasContext *ctx) +{ +#define MASK_MSA_3RF(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22))) + uint8_t df =3D (ctx->opcode >> 21) & 0x1; + uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; + uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; + uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; + + TCGv_i32 twd =3D tcg_const_i32(wd); + TCGv_i32 tws =3D tcg_const_i32(ws); + TCGv_i32 twt =3D tcg_const_i32(wt); + TCGv_i32 tdf =3D tcg_temp_new_i32(); + + /* adjust df value for floating-point instruction */ + tcg_gen_movi_i32(tdf, df + 2); + + switch (MASK_MSA_3RF(ctx->opcode)) { + case OPC_FCAF_df: + gen_helper_msa_fcaf_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FADD_df: + gen_helper_msa_fadd_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FCUN_df: + gen_helper_msa_fcun_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FSUB_df: + gen_helper_msa_fsub_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FCOR_df: + gen_helper_msa_fcor_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FCEQ_df: + gen_helper_msa_fceq_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FMUL_df: + gen_helper_msa_fmul_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FCUNE_df: + gen_helper_msa_fcune_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FCUEQ_df: + gen_helper_msa_fcueq_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FDIV_df: + gen_helper_msa_fdiv_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FCNE_df: + gen_helper_msa_fcne_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FCLT_df: + gen_helper_msa_fclt_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FMADD_df: + gen_helper_msa_fmadd_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_MUL_Q_df: + tcg_gen_movi_i32(tdf, df + 1); + gen_helper_msa_mul_q_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FCULT_df: + gen_helper_msa_fcult_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FMSUB_df: + gen_helper_msa_fmsub_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_MADD_Q_df: + tcg_gen_movi_i32(tdf, df + 1); + gen_helper_msa_madd_q_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FCLE_df: + gen_helper_msa_fcle_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_MSUB_Q_df: + tcg_gen_movi_i32(tdf, df + 1); + gen_helper_msa_msub_q_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FCULE_df: + gen_helper_msa_fcule_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FEXP2_df: + gen_helper_msa_fexp2_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FSAF_df: + gen_helper_msa_fsaf_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FEXDO_df: + gen_helper_msa_fexdo_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FSUN_df: + gen_helper_msa_fsun_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FSOR_df: + gen_helper_msa_fsor_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FSEQ_df: + gen_helper_msa_fseq_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FTQ_df: + gen_helper_msa_ftq_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FSUNE_df: + gen_helper_msa_fsune_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FSUEQ_df: + gen_helper_msa_fsueq_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FSNE_df: + gen_helper_msa_fsne_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FSLT_df: + gen_helper_msa_fslt_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FMIN_df: + gen_helper_msa_fmin_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_MULR_Q_df: + tcg_gen_movi_i32(tdf, df + 1); + gen_helper_msa_mulr_q_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FSULT_df: + gen_helper_msa_fsult_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FMIN_A_df: + gen_helper_msa_fmin_a_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_MADDR_Q_df: + tcg_gen_movi_i32(tdf, df + 1); + gen_helper_msa_maddr_q_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FSLE_df: + gen_helper_msa_fsle_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FMAX_df: + gen_helper_msa_fmax_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_MSUBR_Q_df: + tcg_gen_movi_i32(tdf, df + 1); + gen_helper_msa_msubr_q_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FSULE_df: + gen_helper_msa_fsule_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FMAX_A_df: + gen_helper_msa_fmax_a_df(cpu_env, tdf, twd, tws, twt); + break; + default: + MIPS_INVAL("MSA instruction"); + gen_reserved_instruction(ctx); + break; + } + + tcg_temp_free_i32(twd); + tcg_temp_free_i32(tws); + tcg_temp_free_i32(twt); + tcg_temp_free_i32(tdf); +} + +static void gen_msa_2r(DisasContext *ctx) +{ +#define MASK_MSA_2R(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \ + (op & (0x7 << 18))) + uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; + uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; + uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; + uint8_t df =3D (ctx->opcode >> 16) & 0x3; + TCGv_i32 twd =3D tcg_const_i32(wd); + TCGv_i32 tws =3D tcg_const_i32(ws); + TCGv_i32 twt =3D tcg_const_i32(wt); + TCGv_i32 tdf =3D tcg_const_i32(df); + + switch (MASK_MSA_2R(ctx->opcode)) { + case OPC_FILL_df: +#if !defined(TARGET_MIPS64) + /* Double format valid only for MIPS64 */ + if (df =3D=3D DF_DOUBLE) { + gen_reserved_instruction(ctx); + break; + } +#endif + gen_helper_msa_fill_df(cpu_env, tdf, twd, tws); /* trs */ + break; + case OPC_NLOC_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_nloc_b(cpu_env, twd, tws); + break; + case DF_HALF: + gen_helper_msa_nloc_h(cpu_env, twd, tws); + break; + case DF_WORD: + gen_helper_msa_nloc_w(cpu_env, twd, tws); + break; + case DF_DOUBLE: + gen_helper_msa_nloc_d(cpu_env, twd, tws); + break; + } + break; + case OPC_NLZC_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_nlzc_b(cpu_env, twd, tws); + break; + case DF_HALF: + gen_helper_msa_nlzc_h(cpu_env, twd, tws); + break; + case DF_WORD: + gen_helper_msa_nlzc_w(cpu_env, twd, tws); + break; + case DF_DOUBLE: + gen_helper_msa_nlzc_d(cpu_env, twd, tws); + break; + } + break; + case OPC_PCNT_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_pcnt_b(cpu_env, twd, tws); + break; + case DF_HALF: + gen_helper_msa_pcnt_h(cpu_env, twd, tws); + break; + case DF_WORD: + gen_helper_msa_pcnt_w(cpu_env, twd, tws); + break; + case DF_DOUBLE: + gen_helper_msa_pcnt_d(cpu_env, twd, tws); + break; + } + break; + default: + MIPS_INVAL("MSA instruction"); + gen_reserved_instruction(ctx); + break; + } + + tcg_temp_free_i32(twd); + tcg_temp_free_i32(tws); + tcg_temp_free_i32(twt); + tcg_temp_free_i32(tdf); +} + +static void gen_msa_2rf(DisasContext *ctx) +{ +#define MASK_MSA_2RF(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \ + (op & (0xf << 17))) + uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; + uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; + uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; + uint8_t df =3D (ctx->opcode >> 16) & 0x1; + TCGv_i32 twd =3D tcg_const_i32(wd); + TCGv_i32 tws =3D tcg_const_i32(ws); + TCGv_i32 twt =3D tcg_const_i32(wt); + /* adjust df value for floating-point instruction */ + TCGv_i32 tdf =3D tcg_const_i32(df + 2); + + switch (MASK_MSA_2RF(ctx->opcode)) { + case OPC_FCLASS_df: + gen_helper_msa_fclass_df(cpu_env, tdf, twd, tws); + break; + case OPC_FTRUNC_S_df: + gen_helper_msa_ftrunc_s_df(cpu_env, tdf, twd, tws); + break; + case OPC_FTRUNC_U_df: + gen_helper_msa_ftrunc_u_df(cpu_env, tdf, twd, tws); + break; + case OPC_FSQRT_df: + gen_helper_msa_fsqrt_df(cpu_env, tdf, twd, tws); + break; + case OPC_FRSQRT_df: + gen_helper_msa_frsqrt_df(cpu_env, tdf, twd, tws); + break; + case OPC_FRCP_df: + gen_helper_msa_frcp_df(cpu_env, tdf, twd, tws); + break; + case OPC_FRINT_df: + gen_helper_msa_frint_df(cpu_env, tdf, twd, tws); + break; + case OPC_FLOG2_df: + gen_helper_msa_flog2_df(cpu_env, tdf, twd, tws); + break; + case OPC_FEXUPL_df: + gen_helper_msa_fexupl_df(cpu_env, tdf, twd, tws); + break; + case OPC_FEXUPR_df: + gen_helper_msa_fexupr_df(cpu_env, tdf, twd, tws); + break; + case OPC_FFQL_df: + gen_helper_msa_ffql_df(cpu_env, tdf, twd, tws); + break; + case OPC_FFQR_df: + gen_helper_msa_ffqr_df(cpu_env, tdf, twd, tws); + break; + case OPC_FTINT_S_df: + gen_helper_msa_ftint_s_df(cpu_env, tdf, twd, tws); + break; + case OPC_FTINT_U_df: + gen_helper_msa_ftint_u_df(cpu_env, tdf, twd, tws); + break; + case OPC_FFINT_S_df: + gen_helper_msa_ffint_s_df(cpu_env, tdf, twd, tws); + break; + case OPC_FFINT_U_df: + gen_helper_msa_ffint_u_df(cpu_env, tdf, twd, tws); + break; + } + + tcg_temp_free_i32(twd); + tcg_temp_free_i32(tws); + tcg_temp_free_i32(twt); + tcg_temp_free_i32(tdf); +} + +static void gen_msa_vec_v(DisasContext *ctx) +{ +#define MASK_MSA_VEC(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21))) + uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; + uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; + uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; + TCGv_i32 twd =3D tcg_const_i32(wd); + TCGv_i32 tws =3D tcg_const_i32(ws); + TCGv_i32 twt =3D tcg_const_i32(wt); + + switch (MASK_MSA_VEC(ctx->opcode)) { + case OPC_AND_V: + gen_helper_msa_and_v(cpu_env, twd, tws, twt); + break; + case OPC_OR_V: + gen_helper_msa_or_v(cpu_env, twd, tws, twt); + break; + case OPC_NOR_V: + gen_helper_msa_nor_v(cpu_env, twd, tws, twt); + break; + case OPC_XOR_V: + gen_helper_msa_xor_v(cpu_env, twd, tws, twt); + break; + case OPC_BMNZ_V: + gen_helper_msa_bmnz_v(cpu_env, twd, tws, twt); + break; + case OPC_BMZ_V: + gen_helper_msa_bmz_v(cpu_env, twd, tws, twt); + break; + case OPC_BSEL_V: + gen_helper_msa_bsel_v(cpu_env, twd, tws, twt); + break; + default: + MIPS_INVAL("MSA instruction"); + gen_reserved_instruction(ctx); + break; + } + + tcg_temp_free_i32(twd); + tcg_temp_free_i32(tws); + tcg_temp_free_i32(twt); +} + +static void gen_msa_vec(DisasContext *ctx) +{ + switch (MASK_MSA_VEC(ctx->opcode)) { + case OPC_AND_V: + case OPC_OR_V: + case OPC_NOR_V: + case OPC_XOR_V: + case OPC_BMNZ_V: + case OPC_BMZ_V: + case OPC_BSEL_V: + gen_msa_vec_v(ctx); + break; + case OPC_MSA_2R: + gen_msa_2r(ctx); + break; + case OPC_MSA_2RF: + gen_msa_2rf(ctx); + break; + default: + MIPS_INVAL("MSA instruction"); + gen_reserved_instruction(ctx); + break; + } +} + +void gen_msa(DisasContext *ctx) +{ + uint32_t opcode =3D ctx->opcode; + + check_msa_access(ctx); + + switch (MASK_MSA_MINOR(opcode)) { + case OPC_MSA_I8_00: + case OPC_MSA_I8_01: + case OPC_MSA_I8_02: + gen_msa_i8(ctx); + break; + case OPC_MSA_I5_06: + case OPC_MSA_I5_07: + gen_msa_i5(ctx); + break; + case OPC_MSA_BIT_09: + case OPC_MSA_BIT_0A: + gen_msa_bit(ctx); + break; + case OPC_MSA_3R_0D: + case OPC_MSA_3R_0E: + case OPC_MSA_3R_0F: + case OPC_MSA_3R_10: + case OPC_MSA_3R_11: + case OPC_MSA_3R_12: + case OPC_MSA_3R_13: + case OPC_MSA_3R_14: + case OPC_MSA_3R_15: + gen_msa_3r(ctx); + break; + case OPC_MSA_ELM: + gen_msa_elm(ctx); + break; + case OPC_MSA_3RF_1A: + case OPC_MSA_3RF_1B: + case OPC_MSA_3RF_1C: + gen_msa_3rf(ctx); + break; + case OPC_MSA_VEC: + gen_msa_vec(ctx); + break; + case OPC_LD_B: + case OPC_LD_H: + case OPC_LD_W: + case OPC_LD_D: + case OPC_ST_B: + case OPC_ST_H: + case OPC_ST_W: + case OPC_ST_D: + { + int32_t s10 =3D sextract32(ctx->opcode, 16, 10); + uint8_t rs =3D (ctx->opcode >> 11) & 0x1f; + uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; + uint8_t df =3D (ctx->opcode >> 0) & 0x3; + + TCGv_i32 twd =3D tcg_const_i32(wd); + TCGv taddr =3D tcg_temp_new(); + gen_base_offset_addr(ctx, taddr, rs, s10 << df); + + switch (MASK_MSA_MINOR(opcode)) { + case OPC_LD_B: + gen_helper_msa_ld_b(cpu_env, twd, taddr); + break; + case OPC_LD_H: + gen_helper_msa_ld_h(cpu_env, twd, taddr); + break; + case OPC_LD_W: + gen_helper_msa_ld_w(cpu_env, twd, taddr); + break; + case OPC_LD_D: + gen_helper_msa_ld_d(cpu_env, twd, taddr); + break; + case OPC_ST_B: + gen_helper_msa_st_b(cpu_env, twd, taddr); + break; + case OPC_ST_H: + gen_helper_msa_st_h(cpu_env, twd, taddr); + break; + case OPC_ST_W: + gen_helper_msa_st_w(cpu_env, twd, taddr); + break; + case OPC_ST_D: + gen_helper_msa_st_d(cpu_env, twd, taddr); + break; + } + + tcg_temp_free_i32(twd); + tcg_temp_free(taddr); + } + break; + default: + MIPS_INVAL("MSA instruction"); + gen_reserved_instruction(ctx); + break; + } +} diff --git a/target/mips/translate.c b/target/mips/translate.c index e1763e5bcec..01fe4609c9d 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1133,240 +1133,6 @@ enum { OPC_NMSUB_PS =3D 0x3E | OPC_CP3, }; =20 -/* MSA Opcodes */ -#define MASK_MSA_MINOR(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) -enum { - OPC_MSA_I8_00 =3D 0x00 | OPC_MSA, - OPC_MSA_I8_01 =3D 0x01 | OPC_MSA, - OPC_MSA_I8_02 =3D 0x02 | OPC_MSA, - OPC_MSA_I5_06 =3D 0x06 | OPC_MSA, - OPC_MSA_I5_07 =3D 0x07 | OPC_MSA, - OPC_MSA_BIT_09 =3D 0x09 | OPC_MSA, - OPC_MSA_BIT_0A =3D 0x0A | OPC_MSA, - OPC_MSA_3R_0D =3D 0x0D | OPC_MSA, - OPC_MSA_3R_0E =3D 0x0E | OPC_MSA, - OPC_MSA_3R_0F =3D 0x0F | OPC_MSA, - OPC_MSA_3R_10 =3D 0x10 | OPC_MSA, - OPC_MSA_3R_11 =3D 0x11 | OPC_MSA, - OPC_MSA_3R_12 =3D 0x12 | OPC_MSA, - OPC_MSA_3R_13 =3D 0x13 | OPC_MSA, - OPC_MSA_3R_14 =3D 0x14 | OPC_MSA, - OPC_MSA_3R_15 =3D 0x15 | OPC_MSA, - OPC_MSA_ELM =3D 0x19 | OPC_MSA, - OPC_MSA_3RF_1A =3D 0x1A | OPC_MSA, - OPC_MSA_3RF_1B =3D 0x1B | OPC_MSA, - OPC_MSA_3RF_1C =3D 0x1C | OPC_MSA, - OPC_MSA_VEC =3D 0x1E | OPC_MSA, - - /* MI10 instruction */ - OPC_LD_B =3D (0x20) | OPC_MSA, - OPC_LD_H =3D (0x21) | OPC_MSA, - OPC_LD_W =3D (0x22) | OPC_MSA, - OPC_LD_D =3D (0x23) | OPC_MSA, - OPC_ST_B =3D (0x24) | OPC_MSA, - OPC_ST_H =3D (0x25) | OPC_MSA, - OPC_ST_W =3D (0x26) | OPC_MSA, - OPC_ST_D =3D (0x27) | OPC_MSA, -}; - -enum { - /* I5 instruction df(bits 22..21) =3D _b, _h, _w, _d */ - OPC_ADDVI_df =3D (0x0 << 23) | OPC_MSA_I5_06, - OPC_CEQI_df =3D (0x0 << 23) | OPC_MSA_I5_07, - OPC_SUBVI_df =3D (0x1 << 23) | OPC_MSA_I5_06, - OPC_MAXI_S_df =3D (0x2 << 23) | OPC_MSA_I5_06, - OPC_CLTI_S_df =3D (0x2 << 23) | OPC_MSA_I5_07, - OPC_MAXI_U_df =3D (0x3 << 23) | OPC_MSA_I5_06, - OPC_CLTI_U_df =3D (0x3 << 23) | OPC_MSA_I5_07, - OPC_MINI_S_df =3D (0x4 << 23) | OPC_MSA_I5_06, - OPC_CLEI_S_df =3D (0x4 << 23) | OPC_MSA_I5_07, - OPC_MINI_U_df =3D (0x5 << 23) | OPC_MSA_I5_06, - OPC_CLEI_U_df =3D (0x5 << 23) | OPC_MSA_I5_07, - OPC_LDI_df =3D (0x6 << 23) | OPC_MSA_I5_07, - - /* I8 instruction */ - OPC_ANDI_B =3D (0x0 << 24) | OPC_MSA_I8_00, - OPC_BMNZI_B =3D (0x0 << 24) | OPC_MSA_I8_01, - OPC_SHF_B =3D (0x0 << 24) | OPC_MSA_I8_02, - OPC_ORI_B =3D (0x1 << 24) | OPC_MSA_I8_00, - OPC_BMZI_B =3D (0x1 << 24) | OPC_MSA_I8_01, - OPC_SHF_H =3D (0x1 << 24) | OPC_MSA_I8_02, - OPC_NORI_B =3D (0x2 << 24) | OPC_MSA_I8_00, - OPC_BSELI_B =3D (0x2 << 24) | OPC_MSA_I8_01, - OPC_SHF_W =3D (0x2 << 24) | OPC_MSA_I8_02, - OPC_XORI_B =3D (0x3 << 24) | OPC_MSA_I8_00, - - /* VEC/2R/2RF instruction */ - OPC_AND_V =3D (0x00 << 21) | OPC_MSA_VEC, - OPC_OR_V =3D (0x01 << 21) | OPC_MSA_VEC, - OPC_NOR_V =3D (0x02 << 21) | OPC_MSA_VEC, - OPC_XOR_V =3D (0x03 << 21) | OPC_MSA_VEC, - OPC_BMNZ_V =3D (0x04 << 21) | OPC_MSA_VEC, - OPC_BMZ_V =3D (0x05 << 21) | OPC_MSA_VEC, - OPC_BSEL_V =3D (0x06 << 21) | OPC_MSA_VEC, - - OPC_MSA_2R =3D (0x18 << 21) | OPC_MSA_VEC, - OPC_MSA_2RF =3D (0x19 << 21) | OPC_MSA_VEC, - - /* 2R instruction df(bits 17..16) =3D _b, _h, _w, _d */ - OPC_FILL_df =3D (0x00 << 18) | OPC_MSA_2R, - OPC_PCNT_df =3D (0x01 << 18) | OPC_MSA_2R, - OPC_NLOC_df =3D (0x02 << 18) | OPC_MSA_2R, - OPC_NLZC_df =3D (0x03 << 18) | OPC_MSA_2R, - - /* 2RF instruction df(bit 16) =3D _w, _d */ - OPC_FCLASS_df =3D (0x00 << 17) | OPC_MSA_2RF, - OPC_FTRUNC_S_df =3D (0x01 << 17) | OPC_MSA_2RF, - OPC_FTRUNC_U_df =3D (0x02 << 17) | OPC_MSA_2RF, - OPC_FSQRT_df =3D (0x03 << 17) | OPC_MSA_2RF, - OPC_FRSQRT_df =3D (0x04 << 17) | OPC_MSA_2RF, - OPC_FRCP_df =3D (0x05 << 17) | OPC_MSA_2RF, - OPC_FRINT_df =3D (0x06 << 17) | OPC_MSA_2RF, - OPC_FLOG2_df =3D (0x07 << 17) | OPC_MSA_2RF, - OPC_FEXUPL_df =3D (0x08 << 17) | OPC_MSA_2RF, - OPC_FEXUPR_df =3D (0x09 << 17) | OPC_MSA_2RF, - OPC_FFQL_df =3D (0x0A << 17) | OPC_MSA_2RF, - OPC_FFQR_df =3D (0x0B << 17) | OPC_MSA_2RF, - OPC_FTINT_S_df =3D (0x0C << 17) | OPC_MSA_2RF, - OPC_FTINT_U_df =3D (0x0D << 17) | OPC_MSA_2RF, - OPC_FFINT_S_df =3D (0x0E << 17) | OPC_MSA_2RF, - OPC_FFINT_U_df =3D (0x0F << 17) | OPC_MSA_2RF, - - /* 3R instruction df(bits 22..21) =3D _b, _h, _w, d */ - OPC_SLL_df =3D (0x0 << 23) | OPC_MSA_3R_0D, - OPC_ADDV_df =3D (0x0 << 23) | OPC_MSA_3R_0E, - OPC_CEQ_df =3D (0x0 << 23) | OPC_MSA_3R_0F, - OPC_ADD_A_df =3D (0x0 << 23) | OPC_MSA_3R_10, - OPC_SUBS_S_df =3D (0x0 << 23) | OPC_MSA_3R_11, - OPC_MULV_df =3D (0x0 << 23) | OPC_MSA_3R_12, - OPC_DOTP_S_df =3D (0x0 << 23) | OPC_MSA_3R_13, - OPC_SLD_df =3D (0x0 << 23) | OPC_MSA_3R_14, - OPC_VSHF_df =3D (0x0 << 23) | OPC_MSA_3R_15, - OPC_SRA_df =3D (0x1 << 23) | OPC_MSA_3R_0D, - OPC_SUBV_df =3D (0x1 << 23) | OPC_MSA_3R_0E, - OPC_ADDS_A_df =3D (0x1 << 23) | OPC_MSA_3R_10, - OPC_SUBS_U_df =3D (0x1 << 23) | OPC_MSA_3R_11, - OPC_MADDV_df =3D (0x1 << 23) | OPC_MSA_3R_12, - OPC_DOTP_U_df =3D (0x1 << 23) | OPC_MSA_3R_13, - OPC_SPLAT_df =3D (0x1 << 23) | OPC_MSA_3R_14, - OPC_SRAR_df =3D (0x1 << 23) | OPC_MSA_3R_15, - OPC_SRL_df =3D (0x2 << 23) | OPC_MSA_3R_0D, - OPC_MAX_S_df =3D (0x2 << 23) | OPC_MSA_3R_0E, - OPC_CLT_S_df =3D (0x2 << 23) | OPC_MSA_3R_0F, - OPC_ADDS_S_df =3D (0x2 << 23) | OPC_MSA_3R_10, - OPC_SUBSUS_U_df =3D (0x2 << 23) | OPC_MSA_3R_11, - OPC_MSUBV_df =3D (0x2 << 23) | OPC_MSA_3R_12, - OPC_DPADD_S_df =3D (0x2 << 23) | OPC_MSA_3R_13, - OPC_PCKEV_df =3D (0x2 << 23) | OPC_MSA_3R_14, - OPC_SRLR_df =3D (0x2 << 23) | OPC_MSA_3R_15, - OPC_BCLR_df =3D (0x3 << 23) | OPC_MSA_3R_0D, - OPC_MAX_U_df =3D (0x3 << 23) | OPC_MSA_3R_0E, - OPC_CLT_U_df =3D (0x3 << 23) | OPC_MSA_3R_0F, - OPC_ADDS_U_df =3D (0x3 << 23) | OPC_MSA_3R_10, - OPC_SUBSUU_S_df =3D (0x3 << 23) | OPC_MSA_3R_11, - OPC_DPADD_U_df =3D (0x3 << 23) | OPC_MSA_3R_13, - OPC_PCKOD_df =3D (0x3 << 23) | OPC_MSA_3R_14, - OPC_BSET_df =3D (0x4 << 23) | OPC_MSA_3R_0D, - OPC_MIN_S_df =3D (0x4 << 23) | OPC_MSA_3R_0E, - OPC_CLE_S_df =3D (0x4 << 23) | OPC_MSA_3R_0F, - OPC_AVE_S_df =3D (0x4 << 23) | OPC_MSA_3R_10, - OPC_ASUB_S_df =3D (0x4 << 23) | OPC_MSA_3R_11, - OPC_DIV_S_df =3D (0x4 << 23) | OPC_MSA_3R_12, - OPC_DPSUB_S_df =3D (0x4 << 23) | OPC_MSA_3R_13, - OPC_ILVL_df =3D (0x4 << 23) | OPC_MSA_3R_14, - OPC_HADD_S_df =3D (0x4 << 23) | OPC_MSA_3R_15, - OPC_BNEG_df =3D (0x5 << 23) | OPC_MSA_3R_0D, - OPC_MIN_U_df =3D (0x5 << 23) | OPC_MSA_3R_0E, - OPC_CLE_U_df =3D (0x5 << 23) | OPC_MSA_3R_0F, - OPC_AVE_U_df =3D (0x5 << 23) | OPC_MSA_3R_10, - OPC_ASUB_U_df =3D (0x5 << 23) | OPC_MSA_3R_11, - OPC_DIV_U_df =3D (0x5 << 23) | OPC_MSA_3R_12, - OPC_DPSUB_U_df =3D (0x5 << 23) | OPC_MSA_3R_13, - OPC_ILVR_df =3D (0x5 << 23) | OPC_MSA_3R_14, - OPC_HADD_U_df =3D (0x5 << 23) | OPC_MSA_3R_15, - OPC_BINSL_df =3D (0x6 << 23) | OPC_MSA_3R_0D, - OPC_MAX_A_df =3D (0x6 << 23) | OPC_MSA_3R_0E, - OPC_AVER_S_df =3D (0x6 << 23) | OPC_MSA_3R_10, - OPC_MOD_S_df =3D (0x6 << 23) | OPC_MSA_3R_12, - OPC_ILVEV_df =3D (0x6 << 23) | OPC_MSA_3R_14, - OPC_HSUB_S_df =3D (0x6 << 23) | OPC_MSA_3R_15, - OPC_BINSR_df =3D (0x7 << 23) | OPC_MSA_3R_0D, - OPC_MIN_A_df =3D (0x7 << 23) | OPC_MSA_3R_0E, - OPC_AVER_U_df =3D (0x7 << 23) | OPC_MSA_3R_10, - OPC_MOD_U_df =3D (0x7 << 23) | OPC_MSA_3R_12, - OPC_ILVOD_df =3D (0x7 << 23) | OPC_MSA_3R_14, - OPC_HSUB_U_df =3D (0x7 << 23) | OPC_MSA_3R_15, - - /* ELM instructions df(bits 21..16) =3D _b, _h, _w, _d */ - OPC_SLDI_df =3D (0x0 << 22) | (0x00 << 16) | OPC_MSA_ELM, - OPC_CTCMSA =3D (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM, - OPC_SPLATI_df =3D (0x1 << 22) | (0x00 << 16) | OPC_MSA_ELM, - OPC_CFCMSA =3D (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM, - OPC_COPY_S_df =3D (0x2 << 22) | (0x00 << 16) | OPC_MSA_ELM, - OPC_MOVE_V =3D (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM, - OPC_COPY_U_df =3D (0x3 << 22) | (0x00 << 16) | OPC_MSA_ELM, - OPC_INSERT_df =3D (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM, - OPC_INSVE_df =3D (0x5 << 22) | (0x00 << 16) | OPC_MSA_ELM, - - /* 3RF instruction _df(bit 21) =3D _w, _d */ - OPC_FCAF_df =3D (0x0 << 22) | OPC_MSA_3RF_1A, - OPC_FADD_df =3D (0x0 << 22) | OPC_MSA_3RF_1B, - OPC_FCUN_df =3D (0x1 << 22) | OPC_MSA_3RF_1A, - OPC_FSUB_df =3D (0x1 << 22) | OPC_MSA_3RF_1B, - OPC_FCOR_df =3D (0x1 << 22) | OPC_MSA_3RF_1C, - OPC_FCEQ_df =3D (0x2 << 22) | OPC_MSA_3RF_1A, - OPC_FMUL_df =3D (0x2 << 22) | OPC_MSA_3RF_1B, - OPC_FCUNE_df =3D (0x2 << 22) | OPC_MSA_3RF_1C, - OPC_FCUEQ_df =3D (0x3 << 22) | OPC_MSA_3RF_1A, - OPC_FDIV_df =3D (0x3 << 22) | OPC_MSA_3RF_1B, - OPC_FCNE_df =3D (0x3 << 22) | OPC_MSA_3RF_1C, - OPC_FCLT_df =3D (0x4 << 22) | OPC_MSA_3RF_1A, - OPC_FMADD_df =3D (0x4 << 22) | OPC_MSA_3RF_1B, - OPC_MUL_Q_df =3D (0x4 << 22) | OPC_MSA_3RF_1C, - OPC_FCULT_df =3D (0x5 << 22) | OPC_MSA_3RF_1A, - OPC_FMSUB_df =3D (0x5 << 22) | OPC_MSA_3RF_1B, - OPC_MADD_Q_df =3D (0x5 << 22) | OPC_MSA_3RF_1C, - OPC_FCLE_df =3D (0x6 << 22) | OPC_MSA_3RF_1A, - OPC_MSUB_Q_df =3D (0x6 << 22) | OPC_MSA_3RF_1C, - OPC_FCULE_df =3D (0x7 << 22) | OPC_MSA_3RF_1A, - OPC_FEXP2_df =3D (0x7 << 22) | OPC_MSA_3RF_1B, - OPC_FSAF_df =3D (0x8 << 22) | OPC_MSA_3RF_1A, - OPC_FEXDO_df =3D (0x8 << 22) | OPC_MSA_3RF_1B, - OPC_FSUN_df =3D (0x9 << 22) | OPC_MSA_3RF_1A, - OPC_FSOR_df =3D (0x9 << 22) | OPC_MSA_3RF_1C, - OPC_FSEQ_df =3D (0xA << 22) | OPC_MSA_3RF_1A, - OPC_FTQ_df =3D (0xA << 22) | OPC_MSA_3RF_1B, - OPC_FSUNE_df =3D (0xA << 22) | OPC_MSA_3RF_1C, - OPC_FSUEQ_df =3D (0xB << 22) | OPC_MSA_3RF_1A, - OPC_FSNE_df =3D (0xB << 22) | OPC_MSA_3RF_1C, - OPC_FSLT_df =3D (0xC << 22) | OPC_MSA_3RF_1A, - OPC_FMIN_df =3D (0xC << 22) | OPC_MSA_3RF_1B, - OPC_MULR_Q_df =3D (0xC << 22) | OPC_MSA_3RF_1C, - OPC_FSULT_df =3D (0xD << 22) | OPC_MSA_3RF_1A, - OPC_FMIN_A_df =3D (0xD << 22) | OPC_MSA_3RF_1B, - OPC_MADDR_Q_df =3D (0xD << 22) | OPC_MSA_3RF_1C, - OPC_FSLE_df =3D (0xE << 22) | OPC_MSA_3RF_1A, - OPC_FMAX_df =3D (0xE << 22) | OPC_MSA_3RF_1B, - OPC_MSUBR_Q_df =3D (0xE << 22) | OPC_MSA_3RF_1C, - OPC_FSULE_df =3D (0xF << 22) | OPC_MSA_3RF_1A, - OPC_FMAX_A_df =3D (0xF << 22) | OPC_MSA_3RF_1B, - - /* BIT instruction df(bits 22..16) =3D _B _H _W _D */ - OPC_SLLI_df =3D (0x0 << 23) | OPC_MSA_BIT_09, - OPC_SAT_S_df =3D (0x0 << 23) | OPC_MSA_BIT_0A, - OPC_SRAI_df =3D (0x1 << 23) | OPC_MSA_BIT_09, - OPC_SAT_U_df =3D (0x1 << 23) | OPC_MSA_BIT_0A, - OPC_SRLI_df =3D (0x2 << 23) | OPC_MSA_BIT_09, - OPC_SRARI_df =3D (0x2 << 23) | OPC_MSA_BIT_0A, - OPC_BCLRI_df =3D (0x3 << 23) | OPC_MSA_BIT_09, - OPC_SRLRI_df =3D (0x3 << 23) | OPC_MSA_BIT_0A, - OPC_BSETI_df =3D (0x4 << 23) | OPC_MSA_BIT_09, - OPC_BNEGI_df =3D (0x5 << 23) | OPC_MSA_BIT_09, - OPC_BINSLI_df =3D (0x6 << 23) | OPC_MSA_BIT_09, - OPC_BINSRI_df =3D (0x7 << 23) | OPC_MSA_BIT_09, -}; - - /* * * AN OVERVIEW OF MXU EXTENSION INSTRUCTION SET @@ -2424,7 +2190,6 @@ static TCGv cpu_lladdr, cpu_llval; static TCGv_i32 hflags; TCGv_i32 fpu_fcr0, fpu_fcr31; TCGv_i64 fpu_f64[32]; -static TCGv_i64 msa_wr_d[64]; =20 #if defined(TARGET_MIPS64) /* Upper halves of R5900's 128-bit registers: MMRs (multimedia registers) = */ @@ -2506,25 +2271,6 @@ static const char * const fregnames[] =3D { "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", }; =20 -static const char * const msaregnames[] =3D { - "w0.d0", "w0.d1", "w1.d0", "w1.d1", - "w2.d0", "w2.d1", "w3.d0", "w3.d1", - "w4.d0", "w4.d1", "w5.d0", "w5.d1", - "w6.d0", "w6.d1", "w7.d0", "w7.d1", - "w8.d0", "w8.d1", "w9.d0", "w9.d1", - "w10.d0", "w10.d1", "w11.d0", "w11.d1", - "w12.d0", "w12.d1", "w13.d0", "w13.d1", - "w14.d0", "w14.d1", "w15.d0", "w15.d1", - "w16.d0", "w16.d1", "w17.d0", "w17.d1", - "w18.d0", "w18.d1", "w19.d0", "w19.d1", - "w20.d0", "w20.d1", "w21.d0", "w21.d1", - "w22.d0", "w22.d1", "w23.d0", "w23.d1", - "w24.d0", "w24.d1", "w25.d0", "w25.d1", - "w26.d0", "w26.d1", "w27.d0", "w27.d1", - "w28.d0", "w28.d1", "w29.d0", "w29.d1", - "w30.d0", "w30.d1", "w31.d0", "w31.d1", -}; - #if !defined(TARGET_MIPS64) static const char * const mxuregnames[] =3D { "XR1", "XR2", "XR3", "XR4", "XR5", "XR6", "XR7", "XR8", @@ -28558,1983 +28304,6 @@ static void decode_opc_special3(CPUMIPSState *en= v, DisasContext *ctx) } } =20 -/* MIPS SIMD Architecture (MSA) */ -static inline int check_msa_access(DisasContext *ctx) -{ - if (unlikely((ctx->hflags & MIPS_HFLAG_FPU) && - !(ctx->hflags & MIPS_HFLAG_F64))) { - gen_reserved_instruction(ctx); - return 0; - } - - if (unlikely(!(ctx->hflags & MIPS_HFLAG_MSA))) { - generate_exception_end(ctx, EXCP_MSADIS); - return 0; - } - return 1; -} - -static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt) -{ - /* generates tcg ops to check if any element is 0 */ - /* Note this function only works with MSA_WRLEN =3D 128 */ - uint64_t eval_zero_or_big =3D 0; - uint64_t eval_big =3D 0; - TCGv_i64 t0 =3D tcg_temp_new_i64(); - TCGv_i64 t1 =3D tcg_temp_new_i64(); - switch (df) { - case DF_BYTE: - eval_zero_or_big =3D 0x0101010101010101ULL; - eval_big =3D 0x8080808080808080ULL; - break; - case DF_HALF: - eval_zero_or_big =3D 0x0001000100010001ULL; - eval_big =3D 0x8000800080008000ULL; - break; - case DF_WORD: - eval_zero_or_big =3D 0x0000000100000001ULL; - eval_big =3D 0x8000000080000000ULL; - break; - case DF_DOUBLE: - eval_zero_or_big =3D 0x0000000000000001ULL; - eval_big =3D 0x8000000000000000ULL; - break; - } - tcg_gen_subi_i64(t0, msa_wr_d[wt << 1], eval_zero_or_big); - tcg_gen_andc_i64(t0, t0, msa_wr_d[wt << 1]); - tcg_gen_andi_i64(t0, t0, eval_big); - tcg_gen_subi_i64(t1, msa_wr_d[(wt << 1) + 1], eval_zero_or_big); - tcg_gen_andc_i64(t1, t1, msa_wr_d[(wt << 1) + 1]); - tcg_gen_andi_i64(t1, t1, eval_big); - tcg_gen_or_i64(t0, t0, t1); - /* if all bits are zero then all elements are not zero */ - /* if some bit is non-zero then some element is zero */ - tcg_gen_setcondi_i64(TCG_COND_NE, t0, t0, 0); - tcg_gen_trunc_i64_tl(tresult, t0); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); -} - -static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond) -{ - TCGv_i64 t0; - - check_msa_access(ctx); - - if (ctx->hflags & MIPS_HFLAG_BMASK) { - gen_reserved_instruction(ctx); - return true; - } - t0 =3D tcg_temp_new_i64(); - tcg_gen_or_i64(t0, msa_wr_d[wt << 1], msa_wr_d[(wt << 1) + 1]); - tcg_gen_setcondi_i64(cond, t0, t0, 0); - tcg_gen_trunc_i64_tl(bcond, t0); - tcg_temp_free_i64(t0); - - ctx->btarget =3D ctx->base.pc_next + (s16 << 2) + 4; - - ctx->hflags |=3D MIPS_HFLAG_BC; - ctx->hflags |=3D MIPS_HFLAG_BDS32; - - return true; -} - -static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool i= f_not) -{ - check_msa_access(ctx); - - if (ctx->hflags & MIPS_HFLAG_BMASK) { - gen_reserved_instruction(ctx); - return true; - } - - gen_check_zero_element(bcond, df, wt); - if (if_not) { - tcg_gen_setcondi_tl(TCG_COND_EQ, bcond, bcond, 0); - } - - ctx->btarget =3D ctx->base.pc_next + (s16 << 2) + 4; - ctx->hflags |=3D MIPS_HFLAG_BC; - ctx->hflags |=3D MIPS_HFLAG_BDS32; - - return true; -} - -void gen_msa_branch(DisasContext *ctx, uint32_t op1) -{ - uint8_t df =3D (ctx->opcode >> 21) & 0x3; - uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; - int64_t s16 =3D (int16_t)ctx->opcode; - - switch (op1) { - case OPC_BZ_V: - case OPC_BNZ_V: - gen_msa_BxZ_V(ctx, wt, s16, (op1 =3D=3D OPC_BZ_V) ? - TCG_COND_EQ : TCG_COND_NE); - break; - case OPC_BZ_B: - case OPC_BZ_H: - case OPC_BZ_W: - case OPC_BZ_D: - gen_msa_BxZ(ctx, df, wt, s16, false); - break; - case OPC_BNZ_B: - case OPC_BNZ_H: - case OPC_BNZ_W: - case OPC_BNZ_D: - gen_msa_BxZ(ctx, df, wt, s16, true); - break; - } -} - -static void gen_msa_i8(DisasContext *ctx) -{ -#define MASK_MSA_I8(op) (MASK_MSA_MINOR(op) | (op & (0x03 << 24))) - uint8_t i8 =3D (ctx->opcode >> 16) & 0xff; - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - - TCGv_i32 twd =3D tcg_const_i32(wd); - TCGv_i32 tws =3D tcg_const_i32(ws); - TCGv_i32 ti8 =3D tcg_const_i32(i8); - - switch (MASK_MSA_I8(ctx->opcode)) { - case OPC_ANDI_B: - gen_helper_msa_andi_b(cpu_env, twd, tws, ti8); - break; - case OPC_ORI_B: - gen_helper_msa_ori_b(cpu_env, twd, tws, ti8); - break; - case OPC_NORI_B: - gen_helper_msa_nori_b(cpu_env, twd, tws, ti8); - break; - case OPC_XORI_B: - gen_helper_msa_xori_b(cpu_env, twd, tws, ti8); - break; - case OPC_BMNZI_B: - gen_helper_msa_bmnzi_b(cpu_env, twd, tws, ti8); - break; - case OPC_BMZI_B: - gen_helper_msa_bmzi_b(cpu_env, twd, tws, ti8); - break; - case OPC_BSELI_B: - gen_helper_msa_bseli_b(cpu_env, twd, tws, ti8); - break; - case OPC_SHF_B: - case OPC_SHF_H: - case OPC_SHF_W: - { - uint8_t df =3D (ctx->opcode >> 24) & 0x3; - if (df =3D=3D DF_DOUBLE) { - gen_reserved_instruction(ctx); - } else { - TCGv_i32 tdf =3D tcg_const_i32(df); - gen_helper_msa_shf_df(cpu_env, tdf, twd, tws, ti8); - tcg_temp_free_i32(tdf); - } - } - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; - } - - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); - tcg_temp_free_i32(ti8); -} - -static void gen_msa_i5(DisasContext *ctx) -{ -#define MASK_MSA_I5(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) - uint8_t df =3D (ctx->opcode >> 21) & 0x3; - int8_t s5 =3D (int8_t) sextract32(ctx->opcode, 16, 5); - uint8_t u5 =3D (ctx->opcode >> 16) & 0x1f; - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - - TCGv_i32 tdf =3D tcg_const_i32(df); - TCGv_i32 twd =3D tcg_const_i32(wd); - TCGv_i32 tws =3D tcg_const_i32(ws); - TCGv_i32 timm =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(timm, u5); - - switch (MASK_MSA_I5(ctx->opcode)) { - case OPC_ADDVI_df: - gen_helper_msa_addvi_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_SUBVI_df: - gen_helper_msa_subvi_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_MAXI_S_df: - tcg_gen_movi_i32(timm, s5); - gen_helper_msa_maxi_s_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_MAXI_U_df: - gen_helper_msa_maxi_u_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_MINI_S_df: - tcg_gen_movi_i32(timm, s5); - gen_helper_msa_mini_s_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_MINI_U_df: - gen_helper_msa_mini_u_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_CEQI_df: - tcg_gen_movi_i32(timm, s5); - gen_helper_msa_ceqi_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_CLTI_S_df: - tcg_gen_movi_i32(timm, s5); - gen_helper_msa_clti_s_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_CLTI_U_df: - gen_helper_msa_clti_u_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_CLEI_S_df: - tcg_gen_movi_i32(timm, s5); - gen_helper_msa_clei_s_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_CLEI_U_df: - gen_helper_msa_clei_u_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_LDI_df: - { - int32_t s10 =3D sextract32(ctx->opcode, 11, 10); - tcg_gen_movi_i32(timm, s10); - gen_helper_msa_ldi_df(cpu_env, tdf, twd, timm); - } - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; - } - - tcg_temp_free_i32(tdf); - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); - tcg_temp_free_i32(timm); -} - -static void gen_msa_bit(DisasContext *ctx) -{ -#define MASK_MSA_BIT(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) - uint8_t dfm =3D (ctx->opcode >> 16) & 0x7f; - uint32_t df =3D 0, m =3D 0; - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - - TCGv_i32 tdf; - TCGv_i32 tm; - TCGv_i32 twd; - TCGv_i32 tws; - - if ((dfm & 0x40) =3D=3D 0x00) { - m =3D dfm & 0x3f; - df =3D DF_DOUBLE; - } else if ((dfm & 0x60) =3D=3D 0x40) { - m =3D dfm & 0x1f; - df =3D DF_WORD; - } else if ((dfm & 0x70) =3D=3D 0x60) { - m =3D dfm & 0x0f; - df =3D DF_HALF; - } else if ((dfm & 0x78) =3D=3D 0x70) { - m =3D dfm & 0x7; - df =3D DF_BYTE; - } else { - gen_reserved_instruction(ctx); - return; - } - - tdf =3D tcg_const_i32(df); - tm =3D tcg_const_i32(m); - twd =3D tcg_const_i32(wd); - tws =3D tcg_const_i32(ws); - - switch (MASK_MSA_BIT(ctx->opcode)) { - case OPC_SLLI_df: - gen_helper_msa_slli_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_SRAI_df: - gen_helper_msa_srai_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_SRLI_df: - gen_helper_msa_srli_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_BCLRI_df: - gen_helper_msa_bclri_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_BSETI_df: - gen_helper_msa_bseti_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_BNEGI_df: - gen_helper_msa_bnegi_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_BINSLI_df: - gen_helper_msa_binsli_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_BINSRI_df: - gen_helper_msa_binsri_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_SAT_S_df: - gen_helper_msa_sat_s_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_SAT_U_df: - gen_helper_msa_sat_u_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_SRARI_df: - gen_helper_msa_srari_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_SRLRI_df: - gen_helper_msa_srlri_df(cpu_env, tdf, twd, tws, tm); - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; - } - - tcg_temp_free_i32(tdf); - tcg_temp_free_i32(tm); - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); -} - -static void gen_msa_3r(DisasContext *ctx) -{ -#define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) - uint8_t df =3D (ctx->opcode >> 21) & 0x3; - uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - - TCGv_i32 tdf =3D tcg_const_i32(df); - TCGv_i32 twd =3D tcg_const_i32(wd); - TCGv_i32 tws =3D tcg_const_i32(ws); - TCGv_i32 twt =3D tcg_const_i32(wt); - - switch (MASK_MSA_3R(ctx->opcode)) { - case OPC_BINSL_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_binsl_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_binsl_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_binsl_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_binsl_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_BINSR_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_binsr_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_binsr_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_binsr_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_binsr_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_BCLR_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_bclr_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_bclr_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_bclr_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_bclr_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_BNEG_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_bneg_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_bneg_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_bneg_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_bneg_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_BSET_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_bset_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_bset_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_bset_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_bset_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ADD_A_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_add_a_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_add_a_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_add_a_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_add_a_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ADDS_A_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_adds_a_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_adds_a_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_adds_a_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_adds_a_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ADDS_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_adds_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_adds_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_adds_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_adds_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ADDS_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_adds_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_adds_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_adds_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_adds_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ADDV_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_addv_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_addv_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_addv_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_addv_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_AVE_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_ave_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_ave_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_ave_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_ave_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_AVE_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_ave_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_ave_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_ave_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_ave_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_AVER_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_aver_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_aver_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_aver_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_aver_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_AVER_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_aver_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_aver_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_aver_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_aver_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_CEQ_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_ceq_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_ceq_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_ceq_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_ceq_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_CLE_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_cle_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_cle_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_cle_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_cle_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_CLE_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_cle_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_cle_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_cle_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_cle_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_CLT_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_clt_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_clt_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_clt_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_clt_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_CLT_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_clt_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_clt_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_clt_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_clt_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DIV_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_div_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_div_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_div_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_div_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DIV_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_div_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_div_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_div_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_div_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MAX_A_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_max_a_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_max_a_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_max_a_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_max_a_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MAX_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_max_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_max_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_max_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_max_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MAX_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_max_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_max_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_max_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_max_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MIN_A_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_min_a_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_min_a_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_min_a_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_min_a_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MIN_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_min_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_min_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_min_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_min_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MIN_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_min_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_min_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_min_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_min_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MOD_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_mod_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_mod_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_mod_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_mod_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MOD_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_mod_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_mod_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_mod_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_mod_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MADDV_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_maddv_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_maddv_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_maddv_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_maddv_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MSUBV_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_msubv_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_msubv_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_msubv_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_msubv_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ASUB_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_asub_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_asub_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_asub_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_asub_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ASUB_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_asub_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_asub_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_asub_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_asub_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ILVEV_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_ilvev_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_ilvev_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_ilvev_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_ilvev_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ILVOD_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_ilvod_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_ilvod_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_ilvod_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_ilvod_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ILVL_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_ilvl_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_ilvl_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_ilvl_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_ilvl_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ILVR_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_ilvr_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_ilvr_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_ilvr_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_ilvr_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_PCKEV_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_pckev_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_pckev_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_pckev_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_pckev_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_PCKOD_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_pckod_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_pckod_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_pckod_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_pckod_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SLL_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_sll_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_sll_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_sll_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_sll_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SRA_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_sra_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_sra_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_sra_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_sra_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SRAR_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_srar_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_srar_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_srar_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_srar_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SRL_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_srl_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_srl_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_srl_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_srl_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SRLR_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_srlr_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_srlr_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_srlr_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_srlr_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SUBS_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_subs_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_subs_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_subs_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_subs_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MULV_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_mulv_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_mulv_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_mulv_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_mulv_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SLD_df: - gen_helper_msa_sld_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_VSHF_df: - gen_helper_msa_vshf_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_SUBV_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_subv_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_subv_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_subv_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_subv_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SUBS_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_subs_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_subs_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_subs_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_subs_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SPLAT_df: - gen_helper_msa_splat_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_SUBSUS_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_subsus_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_subsus_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_subsus_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_subsus_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SUBSUU_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_subsuu_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_subsuu_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_subsuu_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_subsuu_s_d(cpu_env, twd, tws, twt); - break; - } - break; - - case OPC_DOTP_S_df: - case OPC_DOTP_U_df: - case OPC_DPADD_S_df: - case OPC_DPADD_U_df: - case OPC_DPSUB_S_df: - case OPC_HADD_S_df: - case OPC_DPSUB_U_df: - case OPC_HADD_U_df: - case OPC_HSUB_S_df: - case OPC_HSUB_U_df: - if (df =3D=3D DF_BYTE) { - gen_reserved_instruction(ctx); - break; - } - switch (MASK_MSA_3R(ctx->opcode)) { - case OPC_HADD_S_df: - switch (df) { - case DF_HALF: - gen_helper_msa_hadd_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_hadd_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_hadd_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_HADD_U_df: - switch (df) { - case DF_HALF: - gen_helper_msa_hadd_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_hadd_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_hadd_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_HSUB_S_df: - switch (df) { - case DF_HALF: - gen_helper_msa_hsub_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_hsub_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_hsub_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_HSUB_U_df: - switch (df) { - case DF_HALF: - gen_helper_msa_hsub_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_hsub_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_hsub_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DOTP_S_df: - switch (df) { - case DF_HALF: - gen_helper_msa_dotp_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_dotp_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_dotp_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DOTP_U_df: - switch (df) { - case DF_HALF: - gen_helper_msa_dotp_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_dotp_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_dotp_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DPADD_S_df: - switch (df) { - case DF_HALF: - gen_helper_msa_dpadd_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_dpadd_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_dpadd_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DPADD_U_df: - switch (df) { - case DF_HALF: - gen_helper_msa_dpadd_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_dpadd_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_dpadd_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DPSUB_S_df: - switch (df) { - case DF_HALF: - gen_helper_msa_dpsub_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_dpsub_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_dpsub_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DPSUB_U_df: - switch (df) { - case DF_HALF: - gen_helper_msa_dpsub_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_dpsub_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_dpsub_u_d(cpu_env, twd, tws, twt); - break; - } - break; - } - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; - } - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); - tcg_temp_free_i32(twt); - tcg_temp_free_i32(tdf); -} - -static void gen_msa_elm_3e(DisasContext *ctx) -{ -#define MASK_MSA_ELM_DF3E(op) (MASK_MSA_MINOR(op) | (op & (0x3FF << 16))) - uint8_t source =3D (ctx->opcode >> 11) & 0x1f; - uint8_t dest =3D (ctx->opcode >> 6) & 0x1f; - TCGv telm =3D tcg_temp_new(); - TCGv_i32 tsr =3D tcg_const_i32(source); - TCGv_i32 tdt =3D tcg_const_i32(dest); - - switch (MASK_MSA_ELM_DF3E(ctx->opcode)) { - case OPC_CTCMSA: - gen_load_gpr(telm, source); - gen_helper_msa_ctcmsa(cpu_env, telm, tdt); - break; - case OPC_CFCMSA: - gen_helper_msa_cfcmsa(telm, cpu_env, tsr); - gen_store_gpr(telm, dest); - break; - case OPC_MOVE_V: - gen_helper_msa_move_v(cpu_env, tdt, tsr); - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; - } - - tcg_temp_free(telm); - tcg_temp_free_i32(tdt); - tcg_temp_free_i32(tsr); -} - -static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n) -{ -#define MASK_MSA_ELM(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22))) - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - - TCGv_i32 tws =3D tcg_const_i32(ws); - TCGv_i32 twd =3D tcg_const_i32(wd); - TCGv_i32 tn =3D tcg_const_i32(n); - TCGv_i32 tdf =3D tcg_const_i32(df); - - switch (MASK_MSA_ELM(ctx->opcode)) { - case OPC_SLDI_df: - gen_helper_msa_sldi_df(cpu_env, tdf, twd, tws, tn); - break; - case OPC_SPLATI_df: - gen_helper_msa_splati_df(cpu_env, tdf, twd, tws, tn); - break; - case OPC_INSVE_df: - gen_helper_msa_insve_df(cpu_env, tdf, twd, tws, tn); - break; - case OPC_COPY_S_df: - case OPC_COPY_U_df: - case OPC_INSERT_df: -#if !defined(TARGET_MIPS64) - /* Double format valid only for MIPS64 */ - if (df =3D=3D DF_DOUBLE) { - gen_reserved_instruction(ctx); - break; - } - if ((MASK_MSA_ELM(ctx->opcode) =3D=3D OPC_COPY_U_df) && - (df =3D=3D DF_WORD)) { - gen_reserved_instruction(ctx); - break; - } -#endif - switch (MASK_MSA_ELM(ctx->opcode)) { - case OPC_COPY_S_df: - if (likely(wd !=3D 0)) { - switch (df) { - case DF_BYTE: - gen_helper_msa_copy_s_b(cpu_env, twd, tws, tn); - break; - case DF_HALF: - gen_helper_msa_copy_s_h(cpu_env, twd, tws, tn); - break; - case DF_WORD: - gen_helper_msa_copy_s_w(cpu_env, twd, tws, tn); - break; -#if defined(TARGET_MIPS64) - case DF_DOUBLE: - gen_helper_msa_copy_s_d(cpu_env, twd, tws, tn); - break; -#endif - default: - assert(0); - } - } - break; - case OPC_COPY_U_df: - if (likely(wd !=3D 0)) { - switch (df) { - case DF_BYTE: - gen_helper_msa_copy_u_b(cpu_env, twd, tws, tn); - break; - case DF_HALF: - gen_helper_msa_copy_u_h(cpu_env, twd, tws, tn); - break; -#if defined(TARGET_MIPS64) - case DF_WORD: - gen_helper_msa_copy_u_w(cpu_env, twd, tws, tn); - break; -#endif - default: - assert(0); - } - } - break; - case OPC_INSERT_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_insert_b(cpu_env, twd, tws, tn); - break; - case DF_HALF: - gen_helper_msa_insert_h(cpu_env, twd, tws, tn); - break; - case DF_WORD: - gen_helper_msa_insert_w(cpu_env, twd, tws, tn); - break; -#if defined(TARGET_MIPS64) - case DF_DOUBLE: - gen_helper_msa_insert_d(cpu_env, twd, tws, tn); - break; -#endif - default: - assert(0); - } - break; - } - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - } - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); - tcg_temp_free_i32(tn); - tcg_temp_free_i32(tdf); -} - -static void gen_msa_elm(DisasContext *ctx) -{ - uint8_t dfn =3D (ctx->opcode >> 16) & 0x3f; - uint32_t df =3D 0, n =3D 0; - - if ((dfn & 0x30) =3D=3D 0x00) { - n =3D dfn & 0x0f; - df =3D DF_BYTE; - } else if ((dfn & 0x38) =3D=3D 0x20) { - n =3D dfn & 0x07; - df =3D DF_HALF; - } else if ((dfn & 0x3c) =3D=3D 0x30) { - n =3D dfn & 0x03; - df =3D DF_WORD; - } else if ((dfn & 0x3e) =3D=3D 0x38) { - n =3D dfn & 0x01; - df =3D DF_DOUBLE; - } else if (dfn =3D=3D 0x3E) { - /* CTCMSA, CFCMSA, MOVE.V */ - gen_msa_elm_3e(ctx); - return; - } else { - gen_reserved_instruction(ctx); - return; - } - - gen_msa_elm_df(ctx, df, n); -} - -static void gen_msa_3rf(DisasContext *ctx) -{ -#define MASK_MSA_3RF(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22))) - uint8_t df =3D (ctx->opcode >> 21) & 0x1; - uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - - TCGv_i32 twd =3D tcg_const_i32(wd); - TCGv_i32 tws =3D tcg_const_i32(ws); - TCGv_i32 twt =3D tcg_const_i32(wt); - TCGv_i32 tdf =3D tcg_temp_new_i32(); - - /* adjust df value for floating-point instruction */ - tcg_gen_movi_i32(tdf, df + 2); - - switch (MASK_MSA_3RF(ctx->opcode)) { - case OPC_FCAF_df: - gen_helper_msa_fcaf_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FADD_df: - gen_helper_msa_fadd_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCUN_df: - gen_helper_msa_fcun_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSUB_df: - gen_helper_msa_fsub_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCOR_df: - gen_helper_msa_fcor_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCEQ_df: - gen_helper_msa_fceq_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FMUL_df: - gen_helper_msa_fmul_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCUNE_df: - gen_helper_msa_fcune_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCUEQ_df: - gen_helper_msa_fcueq_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FDIV_df: - gen_helper_msa_fdiv_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCNE_df: - gen_helper_msa_fcne_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCLT_df: - gen_helper_msa_fclt_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FMADD_df: - gen_helper_msa_fmadd_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_MUL_Q_df: - tcg_gen_movi_i32(tdf, df + 1); - gen_helper_msa_mul_q_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCULT_df: - gen_helper_msa_fcult_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FMSUB_df: - gen_helper_msa_fmsub_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_MADD_Q_df: - tcg_gen_movi_i32(tdf, df + 1); - gen_helper_msa_madd_q_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCLE_df: - gen_helper_msa_fcle_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_MSUB_Q_df: - tcg_gen_movi_i32(tdf, df + 1); - gen_helper_msa_msub_q_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCULE_df: - gen_helper_msa_fcule_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FEXP2_df: - gen_helper_msa_fexp2_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSAF_df: - gen_helper_msa_fsaf_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FEXDO_df: - gen_helper_msa_fexdo_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSUN_df: - gen_helper_msa_fsun_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSOR_df: - gen_helper_msa_fsor_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSEQ_df: - gen_helper_msa_fseq_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FTQ_df: - gen_helper_msa_ftq_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSUNE_df: - gen_helper_msa_fsune_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSUEQ_df: - gen_helper_msa_fsueq_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSNE_df: - gen_helper_msa_fsne_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSLT_df: - gen_helper_msa_fslt_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FMIN_df: - gen_helper_msa_fmin_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_MULR_Q_df: - tcg_gen_movi_i32(tdf, df + 1); - gen_helper_msa_mulr_q_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSULT_df: - gen_helper_msa_fsult_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FMIN_A_df: - gen_helper_msa_fmin_a_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_MADDR_Q_df: - tcg_gen_movi_i32(tdf, df + 1); - gen_helper_msa_maddr_q_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSLE_df: - gen_helper_msa_fsle_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FMAX_df: - gen_helper_msa_fmax_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_MSUBR_Q_df: - tcg_gen_movi_i32(tdf, df + 1); - gen_helper_msa_msubr_q_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSULE_df: - gen_helper_msa_fsule_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FMAX_A_df: - gen_helper_msa_fmax_a_df(cpu_env, tdf, twd, tws, twt); - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; - } - - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); - tcg_temp_free_i32(twt); - tcg_temp_free_i32(tdf); -} - -static void gen_msa_2r(DisasContext *ctx) -{ -#define MASK_MSA_2R(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \ - (op & (0x7 << 18))) - uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - uint8_t df =3D (ctx->opcode >> 16) & 0x3; - TCGv_i32 twd =3D tcg_const_i32(wd); - TCGv_i32 tws =3D tcg_const_i32(ws); - TCGv_i32 twt =3D tcg_const_i32(wt); - TCGv_i32 tdf =3D tcg_const_i32(df); - - switch (MASK_MSA_2R(ctx->opcode)) { - case OPC_FILL_df: -#if !defined(TARGET_MIPS64) - /* Double format valid only for MIPS64 */ - if (df =3D=3D DF_DOUBLE) { - gen_reserved_instruction(ctx); - break; - } -#endif - gen_helper_msa_fill_df(cpu_env, tdf, twd, tws); /* trs */ - break; - case OPC_NLOC_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_nloc_b(cpu_env, twd, tws); - break; - case DF_HALF: - gen_helper_msa_nloc_h(cpu_env, twd, tws); - break; - case DF_WORD: - gen_helper_msa_nloc_w(cpu_env, twd, tws); - break; - case DF_DOUBLE: - gen_helper_msa_nloc_d(cpu_env, twd, tws); - break; - } - break; - case OPC_NLZC_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_nlzc_b(cpu_env, twd, tws); - break; - case DF_HALF: - gen_helper_msa_nlzc_h(cpu_env, twd, tws); - break; - case DF_WORD: - gen_helper_msa_nlzc_w(cpu_env, twd, tws); - break; - case DF_DOUBLE: - gen_helper_msa_nlzc_d(cpu_env, twd, tws); - break; - } - break; - case OPC_PCNT_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_pcnt_b(cpu_env, twd, tws); - break; - case DF_HALF: - gen_helper_msa_pcnt_h(cpu_env, twd, tws); - break; - case DF_WORD: - gen_helper_msa_pcnt_w(cpu_env, twd, tws); - break; - case DF_DOUBLE: - gen_helper_msa_pcnt_d(cpu_env, twd, tws); - break; - } - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; - } - - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); - tcg_temp_free_i32(twt); - tcg_temp_free_i32(tdf); -} - -static void gen_msa_2rf(DisasContext *ctx) -{ -#define MASK_MSA_2RF(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \ - (op & (0xf << 17))) - uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - uint8_t df =3D (ctx->opcode >> 16) & 0x1; - TCGv_i32 twd =3D tcg_const_i32(wd); - TCGv_i32 tws =3D tcg_const_i32(ws); - TCGv_i32 twt =3D tcg_const_i32(wt); - /* adjust df value for floating-point instruction */ - TCGv_i32 tdf =3D tcg_const_i32(df + 2); - - switch (MASK_MSA_2RF(ctx->opcode)) { - case OPC_FCLASS_df: - gen_helper_msa_fclass_df(cpu_env, tdf, twd, tws); - break; - case OPC_FTRUNC_S_df: - gen_helper_msa_ftrunc_s_df(cpu_env, tdf, twd, tws); - break; - case OPC_FTRUNC_U_df: - gen_helper_msa_ftrunc_u_df(cpu_env, tdf, twd, tws); - break; - case OPC_FSQRT_df: - gen_helper_msa_fsqrt_df(cpu_env, tdf, twd, tws); - break; - case OPC_FRSQRT_df: - gen_helper_msa_frsqrt_df(cpu_env, tdf, twd, tws); - break; - case OPC_FRCP_df: - gen_helper_msa_frcp_df(cpu_env, tdf, twd, tws); - break; - case OPC_FRINT_df: - gen_helper_msa_frint_df(cpu_env, tdf, twd, tws); - break; - case OPC_FLOG2_df: - gen_helper_msa_flog2_df(cpu_env, tdf, twd, tws); - break; - case OPC_FEXUPL_df: - gen_helper_msa_fexupl_df(cpu_env, tdf, twd, tws); - break; - case OPC_FEXUPR_df: - gen_helper_msa_fexupr_df(cpu_env, tdf, twd, tws); - break; - case OPC_FFQL_df: - gen_helper_msa_ffql_df(cpu_env, tdf, twd, tws); - break; - case OPC_FFQR_df: - gen_helper_msa_ffqr_df(cpu_env, tdf, twd, tws); - break; - case OPC_FTINT_S_df: - gen_helper_msa_ftint_s_df(cpu_env, tdf, twd, tws); - break; - case OPC_FTINT_U_df: - gen_helper_msa_ftint_u_df(cpu_env, tdf, twd, tws); - break; - case OPC_FFINT_S_df: - gen_helper_msa_ffint_s_df(cpu_env, tdf, twd, tws); - break; - case OPC_FFINT_U_df: - gen_helper_msa_ffint_u_df(cpu_env, tdf, twd, tws); - break; - } - - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); - tcg_temp_free_i32(twt); - tcg_temp_free_i32(tdf); -} - -static void gen_msa_vec_v(DisasContext *ctx) -{ -#define MASK_MSA_VEC(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21))) - uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - TCGv_i32 twd =3D tcg_const_i32(wd); - TCGv_i32 tws =3D tcg_const_i32(ws); - TCGv_i32 twt =3D tcg_const_i32(wt); - - switch (MASK_MSA_VEC(ctx->opcode)) { - case OPC_AND_V: - gen_helper_msa_and_v(cpu_env, twd, tws, twt); - break; - case OPC_OR_V: - gen_helper_msa_or_v(cpu_env, twd, tws, twt); - break; - case OPC_NOR_V: - gen_helper_msa_nor_v(cpu_env, twd, tws, twt); - break; - case OPC_XOR_V: - gen_helper_msa_xor_v(cpu_env, twd, tws, twt); - break; - case OPC_BMNZ_V: - gen_helper_msa_bmnz_v(cpu_env, twd, tws, twt); - break; - case OPC_BMZ_V: - gen_helper_msa_bmz_v(cpu_env, twd, tws, twt); - break; - case OPC_BSEL_V: - gen_helper_msa_bsel_v(cpu_env, twd, tws, twt); - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; - } - - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); - tcg_temp_free_i32(twt); -} - -static void gen_msa_vec(DisasContext *ctx) -{ - switch (MASK_MSA_VEC(ctx->opcode)) { - case OPC_AND_V: - case OPC_OR_V: - case OPC_NOR_V: - case OPC_XOR_V: - case OPC_BMNZ_V: - case OPC_BMZ_V: - case OPC_BSEL_V: - gen_msa_vec_v(ctx); - break; - case OPC_MSA_2R: - gen_msa_2r(ctx); - break; - case OPC_MSA_2RF: - gen_msa_2rf(ctx); - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; - } -} - -void gen_msa(DisasContext *ctx) -{ - uint32_t opcode =3D ctx->opcode; - - check_msa_access(ctx); - - switch (MASK_MSA_MINOR(opcode)) { - case OPC_MSA_I8_00: - case OPC_MSA_I8_01: - case OPC_MSA_I8_02: - gen_msa_i8(ctx); - break; - case OPC_MSA_I5_06: - case OPC_MSA_I5_07: - gen_msa_i5(ctx); - break; - case OPC_MSA_BIT_09: - case OPC_MSA_BIT_0A: - gen_msa_bit(ctx); - break; - case OPC_MSA_3R_0D: - case OPC_MSA_3R_0E: - case OPC_MSA_3R_0F: - case OPC_MSA_3R_10: - case OPC_MSA_3R_11: - case OPC_MSA_3R_12: - case OPC_MSA_3R_13: - case OPC_MSA_3R_14: - case OPC_MSA_3R_15: - gen_msa_3r(ctx); - break; - case OPC_MSA_ELM: - gen_msa_elm(ctx); - break; - case OPC_MSA_3RF_1A: - case OPC_MSA_3RF_1B: - case OPC_MSA_3RF_1C: - gen_msa_3rf(ctx); - break; - case OPC_MSA_VEC: - gen_msa_vec(ctx); - break; - case OPC_LD_B: - case OPC_LD_H: - case OPC_LD_W: - case OPC_LD_D: - case OPC_ST_B: - case OPC_ST_H: - case OPC_ST_W: - case OPC_ST_D: - { - int32_t s10 =3D sextract32(ctx->opcode, 16, 10); - uint8_t rs =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - uint8_t df =3D (ctx->opcode >> 0) & 0x3; - - TCGv_i32 twd =3D tcg_const_i32(wd); - TCGv taddr =3D tcg_temp_new(); - gen_base_offset_addr(ctx, taddr, rs, s10 << df); - - switch (MASK_MSA_MINOR(opcode)) { - case OPC_LD_B: - gen_helper_msa_ld_b(cpu_env, twd, taddr); - break; - case OPC_LD_H: - gen_helper_msa_ld_h(cpu_env, twd, taddr); - break; - case OPC_LD_W: - gen_helper_msa_ld_w(cpu_env, twd, taddr); - break; - case OPC_LD_D: - gen_helper_msa_ld_d(cpu_env, twd, taddr); - break; - case OPC_ST_B: - gen_helper_msa_st_b(cpu_env, twd, taddr); - break; - case OPC_ST_H: - gen_helper_msa_st_h(cpu_env, twd, taddr); - break; - case OPC_ST_W: - gen_helper_msa_st_w(cpu_env, twd, taddr); - break; - case OPC_ST_D: - gen_helper_msa_st_d(cpu_env, twd, taddr); - break; - } - - tcg_temp_free_i32(twd); - tcg_temp_free(taddr); - } - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; - } - -} - static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) { int32_t offset; @@ -31577,24 +29346,6 @@ void mips_cpu_dump_state(CPUState *cs, FILE *f, in= t flags) } } =20 -void msa_translate_init(void) -{ - int i; - - for (i =3D 0; i < 32; i++) { - int off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); - - /* - * The MSA vector registers are mapped on the - * scalar floating-point unit (FPU) registers. - */ - msa_wr_d[i * 2] =3D fpu_f64[i]; - off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); - msa_wr_d[i * 2 + 1] =3D - tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1= ]); - } -} - void mips_tcg_init(void) { int i; diff --git a/target/mips/meson.build b/target/mips/meson.build index 596eb1aeeb3..2aa4d81300b 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -8,6 +8,7 @@ 'fpu_helper.c', 'lmmi_helper.c', 'msa_helper.c', + 'msa_translate.c', 'op_helper.c', 'tlb_helper.c', 'translate.c', --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.48 as permitted sender) client-ip=209.85.128.48; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f48.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1610058441; cv=none; d=zohomail.com; s=zohoarc; b=B28DVI3FmxdjTPgclc6EYfxQAI81DDrUE6/asXA2Ry9Zpft0gB/s+TjIrcaselXPnkio1EjZGI6r5OQmixL1WLvQutX3dPwJgIxZpZYXHmgh7oV0ohJrjOGTVevpl71DJQu0Nir8JupFR71FWqIt3t8ywtliIejGz6nTAxXDIn4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id f77sm9367016wmf.42.2021.01.07.14.27.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:27:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rBzgLDqqE9tlixFb1w2Ems4Ej+21PfOS0dtp5Xnk1qE=; b=XbMQJGvj/ERQdAoqFOepJIDBJBm4DPyk7iHUwRpA3fFh+5xFh/FO+wULHMhIpPtpVU H1Ylr0RRBgLph1HF5h/zyUPw5cfKvJqceiULQvPmTTiey43fJhlF+sNyMcEUZ46prG92 QN+7j0zYlZTGJQO7doASweklnwwodL8ol0ZvtJNl6NxddseLXLPtrisuM/epcYJPLxrZ oewa1iIHa+nYlvFTn8ciNS2ZrXFMHkVnyidP2Zk+sYiFtpbJhrX5PfRQ9wHPF0xwV7Uv T2Rkjd7GhvS6ELbcbPEI/+4VwMqO5BPVJMyCbz6WWXRLJ40zDb1ERjkeg9hYrlL1hGeC TTYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=rBzgLDqqE9tlixFb1w2Ems4Ej+21PfOS0dtp5Xnk1qE=; b=OfyACNbVQj+uxqVVqZ1J0OLYM1wbur/UprKvMmWZp7ccE144DfOJUFBdDcYkBB2FRx YoDcQoDCkQJ5j0GfLnPrDNA+jRB68U5pLVDrFqEIsWiUTDmxgBdHXHnh6SVZR6OyTik6 uxZTUwFaJ+p+h6Cu4ICR+U3jVZ03g0douXtu/Sd5mq8exZ8EuVlYuyUTkg7tG3Bg7Of4 s5+ool2OXxCkLUAvHDIaU/LF9EVuBHM/1tta4JBioUTZZnJuH2sEA5R56QJJqwqT5Z4K m2i/JLyWVCFvEtYdY0HKb/ZRs3wekeM+w7DS70H/gPaHi5vaHYVJ52q9iV+KAyzCHmbS 4lEA== X-Gm-Message-State: AOAM5330HRgKuFJ4/Hy9X9alpTgLXd3sz7IGrKdo4zH0ZV2txgDO2YAt KKhQX2Xngry99Z5VHHIhoP8= X-Google-Smtp-Source: ABdhPJz3cwRLw1uViG9szTaeR7d2mfQE7xcFc/rcQiEksAumr9lADebyUs4v2fikkm9QTzErOR897w== X-Received: by 2002:a1c:4645:: with SMTP id t66mr510210wma.152.1610058439578; Thu, 07 Jan 2021 14:27:19 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: libvir-list@redhat.com, Paolo Bonzini , Laurent Vivier , kvm@vger.kernel.org, Jiaxun Yang , Aurelien Jarno , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Paul Burton , Richard Henderson Subject: [PULL 51/66] target/mips: Pass TCGCond argument to MSA gen_check_zero_element() Date: Thu, 7 Jan 2021 23:22:38 +0100 Message-Id: <20210107222253.20382-52-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Simplify gen_check_zero_element() by passing the TCGCond argument along. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201215225757.764263-25-f4bug@amsat.org> --- target/mips/msa_translate.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/target/mips/msa_translate.c b/target/mips/msa_translate.c index a4f9a6c1285..52bd428759a 100644 --- a/target/mips/msa_translate.c +++ b/target/mips/msa_translate.c @@ -304,7 +304,8 @@ static inline int check_msa_access(DisasContext *ctx) return 1; } =20 -static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt) +static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt, + TCGCond cond) { /* generates tcg ops to check if any element is 0 */ /* Note this function only works with MSA_WRLEN =3D 128 */ @@ -339,7 +340,7 @@ static void gen_check_zero_element(TCGv tresult, uint8_= t df, uint8_t wt) tcg_gen_or_i64(t0, t0, t1); /* if all bits are zero then all elements are not zero */ /* if some bit is non-zero then some element is zero */ - tcg_gen_setcondi_i64(TCG_COND_NE, t0, t0, 0); + tcg_gen_setcondi_i64(cond, t0, t0, 0); tcg_gen_trunc_i64_tl(tresult, t0); tcg_temp_free_i64(t0); tcg_temp_free_i64(t1); @@ -378,10 +379,7 @@ static bool gen_msa_BxZ(DisasContext *ctx, int df, int= wt, int s16, bool if_not) return true; } =20 - gen_check_zero_element(bcond, df, wt); - if (if_not) { - tcg_gen_setcondi_tl(TCG_COND_EQ, bcond, bcond, 0); - } + gen_check_zero_element(bcond, df, wt, if_not ? TCG_COND_EQ : TCG_COND_= NE); =20 ctx->btarget =3D ctx->base.pc_next + (s16 << 2) + 4; ctx->hflags |=3D MIPS_HFLAG_BC; --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) client-ip=209.85.221.50; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f50.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1610058446; cv=none; d=zohomail.com; s=zohoarc; b=hymNu7izjwK+0h33VrXy1Czy8CK+xycPiwysd/4VUKhOwasjLpbU/qv2n0AO8K7QyNpx4gg8EVrLKNvMAMGlNWM+wYi2dxwODYKR4w2vrpU/DNmM0hNCN2ugg2BcwUtb1QNNLav448aHyuocPoTIBw8WYbIkRM6efzNz7+KT5rE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610058446; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=gjB8bSNOV3jK0kQvU1bZejwEpXnNKlR5+WxJ3oM/DJ4=; b=n0dYSBBzxTQuYSLG04V4gr8hPs8uHbF4wbuHfOwv4wJRp8g1QeH6+POdVjVqBgddC0VPhpS9X95R9dIKlV/6pXJOJES7QDq2yxgIj+DhC0iBgMjMpsJYXmtziu+u+rtqCVM+eX5PFu6QM31KeoAXwXACm9ZY9Oe2s+BFpoLb5Wc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) by mx.zohomail.com with SMTPS id 1610058446571195.28009691352327; Thu, 7 Jan 2021 14:27:26 -0800 (PST) Received: by mail-wr1-f50.google.com with SMTP id t30so7156663wrb.0 for ; Thu, 07 Jan 2021 14:27:25 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (241.red-88-10-103.dynamicip.rima-tde.net. [88.10.103.241]) by smtp.gmail.com with ESMTPSA id x18sm11886030wrg.55.2021.01.07.14.27.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:27:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gjB8bSNOV3jK0kQvU1bZejwEpXnNKlR5+WxJ3oM/DJ4=; b=PU3XqAa4BYeNMoZIxAy6I2AgQiJaVnK77ogvCg+xEnqHGMYT44Q8XQqLMuQZS3OMc4 BH6ydZ3jiPQFw4w7ujUAneoJXDGAymLsiFy/d8Kuuy04v7pHsGgApouhSmlEVRL7V7+x v0KPqIqs7GQafgcS7X7K0cF4btSwTJ1sNiwTocQtPO7ZJ2YlxS/CfltLzu80U1+2LbzW bMXNEv13zSCP/C4dfhE+sVwSXs+9O2JKT+tPXRpzGh2pEr08ug/d6jQmFqgqFEDUnbq/ upTfXilz8SEwUQ9ROf2eIscQ5OB9g2i/FJvodHKkPn4w4mqQdL+8R1mVJXOtLuabEiFH UzLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=gjB8bSNOV3jK0kQvU1bZejwEpXnNKlR5+WxJ3oM/DJ4=; b=A94xFvXbpo+HLcSRIQS1xSxjYHV3wVB22OzFFgyzjovTn4z3osvK039nJbyhHe1YMC PnbBPqmowG4VQTc+6K+871bHzjzdj7hLajEWXqFNtNN3j/G11rjX2rObqH5xFmMkb66c uzeKylcSQga8aYmIwpWK/goAAOXnNPj4rsmJH4J0ub5tnD8iLW75gdGlxf/Ar95tYmEs 1c+jEy5UlLFUzGjUOzsS15GQ5yiJsIgdqr9wI7lfJfrOzQaxVtXRDXeLnJ+wyJXIdL2G f9O5rrADKVnYaZSDlxcWx6ABHE68DDGEn9cy6IDbEPn7TRJvETg1aJcTRkCbkT57Knm3 5tQA== X-Gm-Message-State: AOAM530ngS871be/MIDKM7ZFMwWE5NhrxIxDo7UW5PoOFmCZVND/JytV n3QZv+yjjrQlVhfkrdEdgww= X-Google-Smtp-Source: ABdhPJz2mhf6HC/yzYIQFD2jHFGCi1FU5ZgTRDBf8Mb3coydjvfxWtxN8gwuIWOi82ze45o+vViPiw== X-Received: by 2002:a5d:6983:: with SMTP id g3mr705027wru.168.1610058444739; Thu, 07 Jan 2021 14:27:24 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: libvir-list@redhat.com, Paolo Bonzini , Laurent Vivier , kvm@vger.kernel.org, Jiaxun Yang , Aurelien Jarno , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Paul Burton , Richard Henderson Subject: [PULL 52/66] target/mips: Introduce decode tree bindings for MSA ASE Date: Thu, 7 Jan 2021 23:22:39 +0100 Message-Id: <20210107222253.20382-53-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Introduce the 'msa32' decodetree config for the 32-bit MSA ASE. We start by decoding: - the branch instructions, - all instructions based on the MSA opcode. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201215225757.764263-20-f4bug@amsat.org> Reviewed-by: Jiaxun Yang Tested-by: Jiaxun Yang --- target/mips/translate.h | 3 +++ target/mips/msa32.decode | 24 ++++++++++++++++++++++++ target/mips/msa_translate.c | 36 ++++++++++++++++++++++++++++++++++++ target/mips/meson.build | 5 +++++ 4 files changed, 68 insertions(+) create mode 100644 target/mips/msa32.decode diff --git a/target/mips/translate.h b/target/mips/translate.h index c61c11978c2..858e47cf833 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -167,4 +167,7 @@ void msa_translate_init(void); void gen_msa(DisasContext *ctx); void gen_msa_branch(DisasContext *ctx, uint32_t op1); =20 +/* decodetree generated */ +bool decode_ase_msa(DisasContext *ctx, uint32_t insn); + #endif diff --git a/target/mips/msa32.decode b/target/mips/msa32.decode new file mode 100644 index 00000000000..d69675132b8 --- /dev/null +++ b/target/mips/msa32.decode @@ -0,0 +1,24 @@ +# MIPS SIMD Architecture Module instruction set +# +# Copyright (C) 2020 Philippe Mathieu-Daud=C3=A9 +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: +# MIPS Architecture for Programmers Volume IV-j +# The MIPS32 SIMD Architecture Module, Revision 1.12 +# (Document Number: MD00866-2B-MSA32-AFP-01.12) +# + +&msa_bz df wt s16 + +@bz ...... ... .. wt:5 s16:16 &msa_bz df=3D3 +@bz_df ...... ... df:2 wt:5 s16:16 &msa_bz + +BZ_V 010001 01011 ..... ................ @bz +BNZ_V 010001 01111 ..... ................ @bz + +BZ_x 010001 110 .. ..... ................ @bz_df +BNZ_x 010001 111 .. ..... ................ @bz_df + +MSA 011110 -------------------------- diff --git a/target/mips/msa_translate.c b/target/mips/msa_translate.c index 52bd428759a..5efb0a1fc8a 100644 --- a/target/mips/msa_translate.c +++ b/target/mips/msa_translate.c @@ -6,6 +6,7 @@ * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support) * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support) + * Copyright (c) 2020 Philippe Mathieu-Daud=C3=A9 * * SPDX-License-Identifier: LGPL-2.1-or-later */ @@ -16,6 +17,9 @@ #include "fpu_helper.h" #include "internal.h" =20 +/* Include the auto-generated decoder. */ +#include "decode-msa32.c.inc" + #define OPC_MSA (0x1E << 26) =20 #define MASK_MSA_MINOR(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) @@ -370,6 +374,16 @@ static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, i= nt s16, TCGCond cond) return true; } =20 +static bool trans_BZ_V(DisasContext *ctx, arg_msa_bz *a) +{ + return gen_msa_BxZ_V(ctx, a->wt, a->s16, TCG_COND_EQ); +} + +static bool trans_BNZ_V(DisasContext *ctx, arg_msa_bz *a) +{ + return gen_msa_BxZ_V(ctx, a->wt, a->s16, TCG_COND_NE); +} + static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool i= f_not) { check_msa_access(ctx); @@ -388,6 +402,16 @@ static bool gen_msa_BxZ(DisasContext *ctx, int df, int= wt, int s16, bool if_not) return true; } =20 +static bool trans_BZ_x(DisasContext *ctx, arg_msa_bz *a) +{ + return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, false); +} + +static bool trans_BNZ_x(DisasContext *ctx, arg_msa_bz *a) +{ + return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, true); +} + void gen_msa_branch(DisasContext *ctx, uint32_t op1) { uint8_t df =3D (ctx->opcode >> 21) & 0x3; @@ -2261,3 +2285,15 @@ void gen_msa(DisasContext *ctx) break; } } + +static bool trans_MSA(DisasContext *ctx, arg_MSA *a) +{ + gen_msa(ctx); + + return true; +} + +bool decode_ase_msa(DisasContext *ctx, uint32_t insn) +{ + return decode_msa32(ctx, insn); +} diff --git a/target/mips/meson.build b/target/mips/meson.build index 2aa4d81300b..e6285abd044 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -1,4 +1,9 @@ +gen =3D [ + decodetree.process('msa32.decode', extra_args: [ '--static-decode=3Ddeco= de_msa32' ]), +] + mips_ss =3D ss.source_set() +mips_ss.add(gen) mips_ss.add(files( 'cpu.c', 'gdbstub.c', --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) client-ip=216.205.24.124; envelope-from=libvir-list-bounces@redhat.com; helo=us-smtp-delivery-124.mimecast.com; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) smtp.mailfrom=libvir-list-bounces@redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1610058467; cv=none; d=zohomail.com; s=zohoarc; b=ALAilxSdFgHS+uzcZZCfOcQfFXbxW6dSce+Bv0i/ZXmoEU2U6m7nDRY0mK+32T/8wfl4J05fOcxF0RayxHaTY3Vq7/mW6QTqm5Jhbxe96n2x6f6Jnfrgt3c7aZd6C7Zn3H6zPHEZ8MSmb7HTLgWjwTXjDek05OUk4H2MfC/gjy0= ARC-Message-Signature: i=1; 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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id w189sm9557825wmg.31.2021.01.07.14.27.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:27:29 -0800 (PST) X-MC-Unique: xu7coz7FOr-AwHXC1qoV6Q-1 X-MC-Unique: hfPVKaEOOvycACSbx0PPiw-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=ohRDermR0mkMdvDegF26EL3fB4ZqSyCTCt3CGv8BgrM=; b=q9KKA/QEzELllj74252MLthkXz9V+oc/eJz/JxzTlm7Id3fZmCz6dkDgJ6LuHq4hWY BVcwfICUFGYt2ifenKvkI1kOtqLK7wXl2Uuy58cQFY9tJvHG3qBDkWkChIIMkui2BUKD Zxw1k1RBDuqqeIQO95PwbGF1LnyA8eLzr22EQ1t9e9zmfJ7+08CFVVQb1SPsh3SxfQ7f /JYSL/0rsgX/zv9sPAUai40XTmA11iNjRFUqiHpkOCu1GqP6okcWIpZ0i6Law2cFFI9W ml5yMqw48jzxT/FQuSJUQ645H5ntZZEmAKwzafLEq7Kv9Af3XGBFXEPt9oh8xg6z8AeD ovNQ== X-Gm-Message-State: AOAM532jtnW0KamoRUx2LPw+ZWzFthX/fN9MZ1MWV4Jbd+1QiZAr8L2Y 6gFDvc6nsnQErFF3W2ufZng= X-Google-Smtp-Source: ABdhPJzmlF9GZ/x2TYLqqOujsEGL9AtgxyOtqF9BsHqaARz0MImBXI7atAOgqyLObw3GtnMCJZgMtQ== X-Received: by 2002:a5d:4882:: with SMTP id g2mr650959wrq.273.1610058449889; Thu, 07 Jan 2021 14:27:29 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 53/66] target/mips: Use decode_ase_msa() generated from decodetree Date: Thu, 7 Jan 2021 23:22:40 +0100 Message-Id: <20210107222253.20382-54-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.78 on 10.11.54.6 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Now that we can decode the MSA ASE with decode_ase_msa(), use it and remove the previous code, now unreachable. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201215225757.764263-21-f4bug@amsat.org> Tested-by: Jiaxun Yang --- target/mips/translate.h | 12 ------------ target/mips/msa_translate.c | 29 +---------------------------- target/mips/translate.c | 32 ++++++++++---------------------- 3 files changed, 11 insertions(+), 62 deletions(-) diff --git a/target/mips/translate.h b/target/mips/translate.h index 858e47cf833..35e9c4cd135 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -82,8 +82,6 @@ enum { OPC_BC1 =3D (0x08 << 21) | OPC_CP1, /* bc */ OPC_BC1ANY2 =3D (0x09 << 21) | OPC_CP1, OPC_BC1ANY4 =3D (0x0A << 21) | OPC_CP1, - OPC_BZ_V =3D (0x0B << 21) | OPC_CP1, - OPC_BNZ_V =3D (0x0F << 21) | OPC_CP1, OPC_S_FMT =3D (FMT_S << 21) | OPC_CP1, OPC_D_FMT =3D (FMT_D << 21) | OPC_CP1, OPC_E_FMT =3D (FMT_E << 21) | OPC_CP1, @@ -93,14 +91,6 @@ enum { OPC_PS_FMT =3D (FMT_PS << 21) | OPC_CP1, OPC_BC1EQZ =3D (0x09 << 21) | OPC_CP1, OPC_BC1NEZ =3D (0x0D << 21) | OPC_CP1, - OPC_BZ_B =3D (0x18 << 21) | OPC_CP1, - OPC_BZ_H =3D (0x19 << 21) | OPC_CP1, - OPC_BZ_W =3D (0x1A << 21) | OPC_CP1, - OPC_BZ_D =3D (0x1B << 21) | OPC_CP1, - OPC_BNZ_B =3D (0x1C << 21) | OPC_CP1, - OPC_BNZ_H =3D (0x1D << 21) | OPC_CP1, - OPC_BNZ_W =3D (0x1E << 21) | OPC_CP1, - OPC_BNZ_D =3D (0x1F << 21) | OPC_CP1, }; =20 #define MASK_CP1_FUNC(op) (MASK_CP1(op) | (op & 0x3F)) @@ -164,8 +154,6 @@ extern TCGv bcond; =20 /* MSA */ void msa_translate_init(void); -void gen_msa(DisasContext *ctx); -void gen_msa_branch(DisasContext *ctx, uint32_t op1); =20 /* decodetree generated */ bool decode_ase_msa(DisasContext *ctx, uint32_t insn); diff --git a/target/mips/msa_translate.c b/target/mips/msa_translate.c index 5efb0a1fc8a..8a48f889aa2 100644 --- a/target/mips/msa_translate.c +++ b/target/mips/msa_translate.c @@ -412,33 +412,6 @@ static bool trans_BNZ_x(DisasContext *ctx, arg_msa_bz = *a) return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, true); } =20 -void gen_msa_branch(DisasContext *ctx, uint32_t op1) -{ - uint8_t df =3D (ctx->opcode >> 21) & 0x3; - uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; - int64_t s16 =3D (int16_t)ctx->opcode; - - switch (op1) { - case OPC_BZ_V: - case OPC_BNZ_V: - gen_msa_BxZ_V(ctx, wt, s16, (op1 =3D=3D OPC_BZ_V) ? - TCG_COND_EQ : TCG_COND_NE); - break; - case OPC_BZ_B: - case OPC_BZ_H: - case OPC_BZ_W: - case OPC_BZ_D: - gen_msa_BxZ(ctx, df, wt, s16, false); - break; - case OPC_BNZ_B: - case OPC_BNZ_H: - case OPC_BNZ_W: - case OPC_BNZ_D: - gen_msa_BxZ(ctx, df, wt, s16, true); - break; - } -} - static void gen_msa_i8(DisasContext *ctx) { #define MASK_MSA_I8(op) (MASK_MSA_MINOR(op) | (op & (0x03 << 24))) @@ -2188,7 +2161,7 @@ static void gen_msa_vec(DisasContext *ctx) } } =20 -void gen_msa(DisasContext *ctx) +static void gen_msa(DisasContext *ctx) { uint32_t opcode =3D ctx->opcode; =20 diff --git a/target/mips/translate.c b/target/mips/translate.c index 01fe4609c9d..3da12e31351 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -6,6 +6,7 @@ * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support) * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support) + * Copyright (c) 2020 Philippe Mathieu-Daud=C3=A9 * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public @@ -135,8 +136,6 @@ enum { OPC_JIALC =3D (0x3E << 26), /* MDMX ASE specific */ OPC_MDMX =3D (0x1E << 26), - /* MSA ASE, same as MDMX */ - OPC_MSA =3D OPC_MDMX, /* Cache and prefetch */ OPC_CACHE =3D (0x2F << 26), OPC_PREF =3D (0x33 << 26), @@ -28828,21 +28827,6 @@ static bool decode_opc_legacy(CPUMIPSState *env, D= isasContext *ctx) } break; } - case OPC_BZ_V: - case OPC_BNZ_V: - case OPC_BZ_B: - case OPC_BZ_H: - case OPC_BZ_W: - case OPC_BZ_D: - case OPC_BNZ_B: - case OPC_BNZ_H: - case OPC_BNZ_W: - case OPC_BNZ_D: - if (ase_msa_available(env)) { - gen_msa_branch(ctx, op1); - break; - } - /* fall through */ default: MIPS_INVAL("cp1"); gen_reserved_instruction(ctx); @@ -29024,16 +29008,13 @@ static bool decode_opc_legacy(CPUMIPSState *env, = DisasContext *ctx) gen_compute_branch(ctx, op, 4, rs, rt, offset, 4); } break; - case OPC_MSA: /* OPC_MDMX */ + case OPC_MDMX: /* MMI_OPC_LQ */ if (ctx->insn_flags & INSN_R5900) { #if defined(TARGET_MIPS64) - gen_mmi_lq(env, ctx); /* MMI_OPC_LQ */ + gen_mmi_lq(env, ctx); #endif } else { /* MDMX: Not implemented. */ - if (ase_msa_available(env)) { - gen_msa(ctx); - } } break; case OPC_PCREL: @@ -29066,6 +29047,13 @@ static void decode_opc(CPUMIPSState *env, DisasCon= text *ctx) gen_set_label(l1); } =20 + /* Transition to the auto-generated decoder. */ + + /* ISA extensions */ + if (ase_msa_available(env) && decode_ase_msa(ctx, ctx->opcode)) { + return; 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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id h16sm9920371wrq.29.2021.01.07.14.27.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:27:34 -0800 (PST) X-MC-Unique: u3pymeqQOu2KRdAp4hx1ZQ-1 X-MC-Unique: dWGp2WEgMZu2dfzyRgpFYA-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=ccUqeFnMhpxujrGGkccrptJlKtmDtdTT+pOY6u5+VKc=; b=FPaO8YuFPJRDjen1QF35BkEC2M6di3B1/rx6lMoDB0GLH++0WM+EWOhKzEpBQf9ULb LLlgLo5wZ0dW4+z2IohnhiOb4jGf+wgii6NkBE/v8bs09NkjAEmV9R7cSb7wu52dn+iJ euePJvVXCgohfo0LqLTCHYqgvypg0Z71Dzm9YYIcLQQj+m1Tg7azIX1NIVRg8T4Sne2r as1Xhpjjs2j8SNRgpy+RtrhUNqO24871By/YhghmOHA9NWYmFnY37qwYs6Fqix6z471F iW0+a5KoenqR6cppd6nu8HzkflgsRABnNDij+pGGu6ORDMKcyGyEMCh0otQfRklIAJNK 4mAQ== X-Gm-Message-State: AOAM532zKztfsb1VZCm6XHhcfJcZpkKtz48d6/6+/uhZ7Txzq5Asd6uz A7DQIW2FMiyNeZd99v4adSo= X-Google-Smtp-Source: ABdhPJxQWmRIx7MeLpcmbSI97z96a23zdfgCxvCqjxgZWoVHageDGrXX0id/exUl0a/Cule2yoD4TA== X-Received: by 2002:a5d:6cad:: with SMTP id a13mr639387wra.275.1610058454893; Thu, 07 Jan 2021 14:27:34 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 54/66] target/mips: Extract LSA/DLSA translation generators Date: Thu, 7 Jan 2021 23:22:41 +0100 Message-Id: <20210107222253.20382-55-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.78 on 10.11.54.4 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Extract gen_lsa() from translate.c and explode it as gen_LSA() and gen_DLSA(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201215225757.764263-22-f4bug@amsat.org> --- target/mips/translate.h | 6 +++ target/mips/translate.c | 35 ++--------------- target/mips/translate_addr_const.c | 61 ++++++++++++++++++++++++++++++ target/mips/meson.build | 1 + 4 files changed, 72 insertions(+), 31 deletions(-) create mode 100644 target/mips/translate_addr_const.c diff --git a/target/mips/translate.h b/target/mips/translate.h index 35e9c4cd135..50281c93369 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -129,6 +129,12 @@ void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int= reg); void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg); int get_fp_bit(int cc); =20 +/* + * Address Computation and Large Constant Instructions + */ +bool gen_LSA(DisasContext *ctx, int rd, int rt, int rs, int sa); +bool gen_DLSA(DisasContext *ctx, int rd, int rt, int rs, int sa); + extern TCGv cpu_gpr[32], cpu_PC; extern TCGv_i32 fpu_fcr0, fpu_fcr31; extern TCGv_i64 fpu_f64[32]; diff --git a/target/mips/translate.c b/target/mips/translate.c index 3da12e31351..e9730d95131 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -6616,31 +6616,6 @@ static void gen_bshfl(DisasContext *ctx, uint32_t op= 2, int rt, int rd) tcg_temp_free(t0); } =20 -static void gen_lsa(DisasContext *ctx, int opc, int rd, int rs, int rt, - int imm2) -{ - TCGv t0; - TCGv t1; - if (rd =3D=3D 0) { - /* Treat as NOP. */ - return; - } - t0 =3D tcg_temp_new(); - t1 =3D tcg_temp_new(); - gen_load_gpr(t0, rs); - gen_load_gpr(t1, rt); - tcg_gen_shli_tl(t0, t0, imm2 + 1); - tcg_gen_add_tl(cpu_gpr[rd], t0, t1); - if (opc =3D=3D OPC_LSA) { - tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); - } - - tcg_temp_free(t1); - tcg_temp_free(t0); - - return; -} - static void gen_align_bits(DisasContext *ctx, int wordsz, int rd, int rs, int rt, int bits) { @@ -16496,8 +16471,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) return; case LSA: check_insn(ctx, ISA_MIPS_R6); - gen_lsa(ctx, OPC_LSA, rd, rs, rt, - extract32(ctx->opcode, 9, 2)); + gen_LSA(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2)); break; case ALIGN: check_insn(ctx, ISA_MIPS_R6); @@ -21460,8 +21434,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) * amount, meaning that the supported shift values are in * the range 0 to 3 (instead of 1 to 4 in MIPSR6). */ - gen_lsa(ctx, OPC_LSA, rd, rs, rt, - extract32(ctx->opcode, 9, 2) - 1); + gen_LSA(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2) - 1); break; case NM_EXTW: gen_ext(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 6, 5)); @@ -24347,7 +24320,7 @@ static void decode_opc_special_r6(CPUMIPSState *env= , DisasContext *ctx) op1 =3D MASK_SPECIAL(ctx->opcode); switch (op1) { case OPC_LSA: - gen_lsa(ctx, op1, rd, rs, rt, extract32(ctx->opcode, 6, 2)); + gen_LSA(ctx, rd, rt, rs, extract32(ctx->opcode, 6, 2)); break; case OPC_MULT: case OPC_MULTU: @@ -24401,7 +24374,7 @@ static void decode_opc_special_r6(CPUMIPSState *env= , DisasContext *ctx) #if defined(TARGET_MIPS64) case OPC_DLSA: check_mips_64(ctx); - gen_lsa(ctx, op1, rd, rs, rt, extract32(ctx->opcode, 6, 2)); + gen_DLSA(ctx, rd, rt, rs, extract32(ctx->opcode, 6, 2)); break; case R6_OPC_DCLO: case R6_OPC_DCLZ: diff --git a/target/mips/translate_addr_const.c b/target/mips/translate_add= r_const.c new file mode 100644 index 00000000000..1c6f61c3dd2 --- /dev/null +++ b/target/mips/translate_addr_const.c @@ -0,0 +1,61 @@ +/* + * Address Computation and Large Constant Instructions + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * Copyright (c) 2006 Marius Groeger (FPU operations) + * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) + * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support) + * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support) + * Copyright (c) 2020 Philippe Mathieu-Daud=C3=A9 + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ +#include "qemu/osdep.h" +#include "tcg/tcg-op.h" +#include "translate.h" + +bool gen_LSA(DisasContext *ctx, int rd, int rt, int rs, int sa) +{ + TCGv t0; + TCGv t1; + + if (rd =3D=3D 0) { + /* Treat as NOP. */ + return true; + } + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + gen_load_gpr(t0, rs); + gen_load_gpr(t1, rt); + tcg_gen_shli_tl(t0, t0, sa + 1); + tcg_gen_add_tl(cpu_gpr[rd], t0, t1); + tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); + + tcg_temp_free(t1); + tcg_temp_free(t0); + + return true; +} + +bool gen_DLSA(DisasContext *ctx, int rd, int rt, int rs, int sa) +{ + TCGv t0; + TCGv t1; + + check_mips_64(ctx); + + if (rd =3D=3D 0) { + /* Treat as NOP. */ + return true; + } + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + gen_load_gpr(t0, rs); + gen_load_gpr(t1, rt); + tcg_gen_shli_tl(t0, t0, sa + 1); + tcg_gen_add_tl(cpu_gpr[rd], t0, t1); + tcg_temp_free(t1); + tcg_temp_free(t0); + + return true; +} diff --git a/target/mips/meson.build b/target/mips/meson.build index e6285abd044..9afee0ca955 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -17,6 +17,7 @@ 'op_helper.c', 'tlb_helper.c', 'translate.c', + 'translate_addr_const.c', )) mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) =20 --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) client-ip=216.205.24.124; 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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id w8sm10003601wrl.91.2021.01.07.14.27.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:27:39 -0800 (PST) X-MC-Unique: eHBmb6q2OrOkgfMheqophA-1 X-MC-Unique: AvOh1YPNOnOF8nnfRIE9Jg-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=fXnJoY5COKKqaViQrzHGXO3P7g2CyIkmu5oDvOAw7V8=; b=cVBp/Xt5I2q7XbkROARzOoUq35MeFgqmS/HdcqnGCw2eEKihdbsgnnaq7tnve/hwDX P7oYVJmcnrPjOasF2/kavgxYRm2so5L+IBL01psnRuc8Ss16Xa4ZJTILovODAyYFVU/N /n18CzXfwHrvA7wbNPgnhoU+bjhYtqYhoigxNfbyz20Y8DPtK4cXyz7a9dlU2CRLhwaz GLhtY9YNx65sSqH16sCAce1mGhNXynYQi+ATWbQjG26IJ2OJXs9RiZrv/USvTemyQiUh 3teRrswT/ynP2ydGRbZBqxGGkRrTrYH3VyRZPGOWWgnO0/jk9QbzVo3VvMDA2wv86uou R7ug== X-Gm-Message-State: AOAM532y2yRwo394mpP+mWssZ+gJ5ikbkKgIAK4ypk4rv5IYXbcX9YNb jvLxKS3TACW7iVP9GpzfEZ4= X-Google-Smtp-Source: ABdhPJx4Sw9YkvyMOSz1j6l4//C+swB7Ehawld7rbm9wWnEhdS49W2zJ3bBVSKrxYAHspGHLrfxgpA== X-Received: by 2002:a7b:c19a:: with SMTP id y26mr519327wmi.20.1610058459860; Thu, 07 Jan 2021 14:27:39 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 55/66] target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes Date: Thu, 7 Jan 2021 23:22:42 +0100 Message-Id: <20210107222253.20382-56-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.78 on 10.11.54.6 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Add the LSA opcode to the MSA32 decodetree config, add DLSA to a new config for the MSA64 ASE, and call decode_msa64() in the main decode_opc() loop. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201215225757.764263-23-f4bug@amsat.org> --- target/mips/msa32.decode | 4 ++++ target/mips/msa64.decode | 17 +++++++++++++++++ target/mips/msa_translate.c | 14 ++++++++++++++ target/mips/meson.build | 1 + 4 files changed, 36 insertions(+) create mode 100644 target/mips/msa64.decode diff --git a/target/mips/msa32.decode b/target/mips/msa32.decode index d69675132b8..0b2f0863251 100644 --- a/target/mips/msa32.decode +++ b/target/mips/msa32.decode @@ -10,11 +10,15 @@ # (Document Number: MD00866-2B-MSA32-AFP-01.12) # =20 +&lsa rd rt rs sa &msa_bz df wt s16 =20 +@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &lsa @bz ...... ... .. wt:5 s16:16 &msa_bz df=3D3 @bz_df ...... ... df:2 wt:5 s16:16 &msa_bz =20 +LSA 000000 ..... ..... ..... 000 .. 000101 @lsa + BZ_V 010001 01011 ..... ................ @bz BNZ_V 010001 01111 ..... ................ @bz =20 diff --git a/target/mips/msa64.decode b/target/mips/msa64.decode new file mode 100644 index 00000000000..8dcbbcd8538 --- /dev/null +++ b/target/mips/msa64.decode @@ -0,0 +1,17 @@ +# MIPS SIMD Architecture Module instruction set +# +# Copyright (C) 2020 Philippe Mathieu-Daud=C3=A9 +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: +# MIPS Architecture for Programmers Volume IV-j +# The MIPS64 SIMD Architecture Module, Revision 1.12 +# (Document Number: MD00868-1D-MSA64-AFP-01.12) +# + +&lsa rd rt rs sa !extern + +@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &lsa + +DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa diff --git a/target/mips/msa_translate.c b/target/mips/msa_translate.c index 8a48f889aa2..e97370e54c2 100644 --- a/target/mips/msa_translate.c +++ b/target/mips/msa_translate.c @@ -19,6 +19,7 @@ =20 /* Include the auto-generated decoder. */ #include "decode-msa32.c.inc" +#include "decode-msa64.c.inc" =20 #define OPC_MSA (0x1E << 26) =20 @@ -2266,7 +2267,20 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a) return true; } =20 +static bool trans_LSA(DisasContext *ctx, arg_LSA *a) +{ + return gen_LSA(ctx, a->rd, a->rt, a->rs, a->sa); +} + +static bool trans_DLSA(DisasContext *ctx, arg_LSA *a) +{ + return gen_DLSA(ctx, a->rd, a->rt, a->rs, a->sa); +} + bool decode_ase_msa(DisasContext *ctx, uint32_t insn) { + if (TARGET_LONG_BITS =3D=3D 64 && decode_msa64(ctx, insn)) { + return true; + } return decode_msa32(ctx, insn); } diff --git a/target/mips/meson.build b/target/mips/meson.build index 9afee0ca955..21b75254047 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -1,5 +1,6 @@ gen =3D [ decodetree.process('msa32.decode', extra_args: [ '--static-decode=3Ddeco= de_msa32' ]), + decodetree.process('msa64.decode', extra_args: [ '--static-decode=3Ddeco= de_msa64' ]), ] =20 mips_ss =3D ss.source_set() --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.45 as permitted sender) client-ip=209.85.221.45; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f45.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.45 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1610058466; cv=none; d=zohomail.com; s=zohoarc; b=ANFGCEO68HWplBF4dLMDWgZ1zVDVjEZ9OYDUmcj/qMNaKBOyqXXsanAsmWL4KRiO8KuBbvUiRp019D3OX0lbFcXYXHy1K0pSney3uoJZ6yDNNsNv344EMqt8TQdaYn81DgvFJ/Oh5cyyZEHxB8NPiZGoGn2QsH/rnAQnsL8/JkU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610058466; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6z86y274+C7xcqFi/N79ZkHJjYYrdiH8WHVp+WKoviw=; b=dC3W5R6M9yyLuD/d3/fQ1L2nHwhgOUlToCb4BHlck0dno01P/gWOSJ/6ljDjXC0eEv9y5xtOwi185OtW5Pzgzwtqnb/L9gHTHt87mY+kbVd/tLF8c9rrDV9iOCygAmCncuEAWHAL8d4fqgdVXa322eFc7HSfVHeMDrNfmzkYkzA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.45 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) by mx.zohomail.com with SMTPS id 1610058466824956.3024841094458; Thu, 7 Jan 2021 14:27:46 -0800 (PST) Received: by mail-wr1-f45.google.com with SMTP id 91so7131215wrj.7 for ; Thu, 07 Jan 2021 14:27:46 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (241.red-88-10-103.dynamicip.rima-tde.net. [88.10.103.241]) by smtp.gmail.com with ESMTPSA id m2sm9138739wml.34.2021.01.07.14.27.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:27:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6z86y274+C7xcqFi/N79ZkHJjYYrdiH8WHVp+WKoviw=; b=uAZJuAqMkllQrDsX4nqlkrU8Zg8x3UjM+OgNNBVR4QmmaHScOqdeMJekk7Ngsa5czr FLoqi6FvROm/AQm0m97Ha3v7RG2n07jsRrJ4YKJrhNJdvO8Fhj29/NEHBrr2FLPcKLhG KggXA8Z4oj9RArPyrxA/7nU6b+zKcGhpsP0y7m4aIIcH0iZQY84xPVrawno0eBsQ9qKL I3bI6dBJMzTZ4O+GWDjqPGRUWTCmRX03nCptX8NG8pJ62YCw8zHLyBz4/SEf1peBhRnr Uc9TnQj0chhf/il1UeibVhUwUP1dhjduUb6Yh8g1gGeygwQxvFBPESMWfAZQXAl5g6vf 6avw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=6z86y274+C7xcqFi/N79ZkHJjYYrdiH8WHVp+WKoviw=; b=BlmR31b1a/d0HXrcXLsC05WhZFVH5hGxSEvtrz4lseZ15dRFQNSYsSczto4jZJRCxP aiDVROaJL8z+CkMBBtM4busjLUirIWAYpMsTz2vtots877QaoSFVI1lZKizqktuWeB8T oyzV0ryuTQ+C9dqPfQVvG/NwmooZmMBnueFHruyP7bFxTdf0OcMEX65VjcqCGxDId/oP D2PpdR2afHfF3aNYBQc1SC8cjOo3DZJth38KsMMT2EcsHe8ySHFJavmz9mdEyTa6xVMq ys5Qqut0MkNaolB0WxlhfHReL2BUWP+7vyShmr4aIZjab1Sp0Os/bvSmdufmn+C2q4gy 4qJQ== X-Gm-Message-State: AOAM530JCjM2CNPZpcsF2Vloklp3fw14bRujQvfdKZVyJsr7P7H49rQc Q9UfuFs3cYFJ3Sz7XyuYUv0= X-Google-Smtp-Source: ABdhPJyL6kNVJRlZ5scQksDQQqnFk6VuaNfLcIavVG3srQbvSUfFrJCIe0JFD6edKv135PKwSec01w== X-Received: by 2002:a05:6000:1811:: with SMTP id m17mr660527wrh.67.1610058464943; Thu, 07 Jan 2021 14:27:44 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: libvir-list@redhat.com, Paolo Bonzini , Laurent Vivier , kvm@vger.kernel.org, Jiaxun Yang , Aurelien Jarno , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Paul Burton , Richard Henderson Subject: [PULL 56/66] target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodes Date: Thu, 7 Jan 2021 23:22:43 +0100 Message-Id: <20210107222253.20382-57-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) LSA and LDSA opcodes are also available with MIPS release 6. Introduce the decodetree config files and call the decode() helpers in the main decode_opc() loop. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201215225757.764263-24-f4bug@amsat.org> --- target/mips/translate.h | 1 + target/mips/mips32r6.decode | 17 +++++++++++++++++ target/mips/mips64r6.decode | 17 +++++++++++++++++ target/mips/rel6_translate.c | 37 ++++++++++++++++++++++++++++++++++++ target/mips/translate.c | 5 +++++ target/mips/meson.build | 3 +++ 6 files changed, 80 insertions(+) create mode 100644 target/mips/mips32r6.decode create mode 100644 target/mips/mips64r6.decode create mode 100644 target/mips/rel6_translate.c diff --git a/target/mips/translate.h b/target/mips/translate.h index 50281c93369..11730f5b2e6 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -162,6 +162,7 @@ extern TCGv bcond; void msa_translate_init(void); =20 /* decodetree generated */ +bool decode_isa_rel6(DisasContext *ctx, uint32_t insn); bool decode_ase_msa(DisasContext *ctx, uint32_t insn); =20 #endif diff --git a/target/mips/mips32r6.decode b/target/mips/mips32r6.decode new file mode 100644 index 00000000000..027585ee042 --- /dev/null +++ b/target/mips/mips32r6.decode @@ -0,0 +1,17 @@ +# MIPS32 Release 6 instruction set +# +# Copyright (C) 2020 Philippe Mathieu-Daud=C3=A9 +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: +# MIPS Architecture for Programmers Volume II-A +# The MIPS32 Instruction Set Reference Manual, Revision 6.06 +# (Document Number: MD00086-2B-MIPS32BIS-AFP-06.06) +# + +&lsa rd rt rs sa + +@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &lsa + +LSA 000000 ..... ..... ..... 000 .. 000101 @lsa diff --git a/target/mips/mips64r6.decode b/target/mips/mips64r6.decode new file mode 100644 index 00000000000..e812224341e --- /dev/null +++ b/target/mips/mips64r6.decode @@ -0,0 +1,17 @@ +# MIPS64 Release 6 instruction set +# +# Copyright (C) 2020 Philippe Mathieu-Daud=C3=A9 +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: +# MIPS Architecture for Programmers Volume II-A +# The MIPS64 Instruction Set Reference Manual, Revision 6.06 +# (Document Number: MD00087-2B-MIPS64BIS-AFP-6.06) +# + +&lsa rd rt rs sa !extern + +@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &lsa + +DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa diff --git a/target/mips/rel6_translate.c b/target/mips/rel6_translate.c new file mode 100644 index 00000000000..631d0b87748 --- /dev/null +++ b/target/mips/rel6_translate.c @@ -0,0 +1,37 @@ +/* + * MIPS emulation for QEMU - # Release 6 translation routines + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * Copyright (c) 2006 Marius Groeger (FPU operations) + * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) + * Copyright (c) 2020 Philippe Mathieu-Daud=C3=A9 + * + * This code is licensed under the GNU GPLv2 and later. + */ + +#include "qemu/osdep.h" +#include "tcg/tcg-op.h" +#include "exec/helper-gen.h" +#include "translate.h" + +/* Include the auto-generated decoder. */ +#include "decode-mips32r6.c.inc" +#include "decode-mips64r6.c.inc" + +static bool trans_LSA(DisasContext *ctx, arg_LSA *a) +{ + return gen_LSA(ctx, a->rd, a->rt, a->rs, a->sa); +} + +static bool trans_DLSA(DisasContext *ctx, arg_LSA *a) +{ + return gen_DLSA(ctx, a->rd, a->rt, a->rs, a->sa); +} + +bool decode_isa_rel6(DisasContext *ctx, uint32_t insn) +{ + if (TARGET_LONG_BITS =3D=3D 64 && decode_mips64r6(ctx, insn)) { + return true; + } + return decode_mips32r6(ctx, insn); +} diff --git a/target/mips/translate.c b/target/mips/translate.c index e9730d95131..cd34b06faae 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -29027,6 +29027,11 @@ static void decode_opc(CPUMIPSState *env, DisasCon= text *ctx) return; } =20 + /* ISA (from latest to oldest) */ + if (cpu_supports_isa(env, ISA_MIPS_R6) && decode_isa_rel6(ctx, ctx->op= code)) { + return; + } + if (!decode_opc_legacy(env, ctx)) { gen_reserved_instruction(ctx); } diff --git a/target/mips/meson.build b/target/mips/meson.build index 21b75254047..ab01123013a 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -1,4 +1,6 @@ gen =3D [ + decodetree.process('mips32r6.decode', extra_args: [ '--static-decode=3Dd= ecode_mips32r6' ]), + decodetree.process('mips64r6.decode', extra_args: [ '--static-decode=3Dd= ecode_mips64r6' ]), decodetree.process('msa32.decode', extra_args: [ '--static-decode=3Ddeco= de_msa32' ]), decodetree.process('msa64.decode', extra_args: [ '--static-decode=3Ddeco= de_msa64' ]), ] @@ -16,6 +18,7 @@ 'msa_helper.c', 'msa_translate.c', 'op_helper.c', + 'rel6_translate.c', 'tlb_helper.c', 'translate.c', 'translate_addr_const.c', --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.53 as permitted sender) client-ip=209.85.128.53; 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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id q15sm9908485wrw.75.2021.01.07.14.27.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:27:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YBRHf7wGs+dAQiqYFO87nWhgnylXmMhIKDrVpD+hV3A=; b=TfT4Z7pCtA5i/83DuHy+/X+0UCcP0xTOxo+I1mwEVwU+M20l6yIhDRkCEtsgku1mxg OTOHuJ1CSA2oI5iR4UItCm9Zq98N5ObcfAq/NeHOYHG1iOPXOhuR7aZONkGGyD/CWJCx lx/G28pauWvxempWaqg+vHX4fU7vMVobraeTcTA64+Fq+SYhp5da6zTmspmNxODUKM/h RCiuhDKko1A8a91re0MyhOerfAAILo67RVVXiKlLuRAJMGHfDk9EADcdIOAIhItLWj8v fTbieEJaxsTqcBHjhHiy33o+dIC1vo2Gk/hWylF01ybzxMyb16EvMw8lN/2NC59kiA0Z hriA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=YBRHf7wGs+dAQiqYFO87nWhgnylXmMhIKDrVpD+hV3A=; b=oWt/p2afJa7lTMyMzYOLcpjpH4Tjn60P0GLUUj8mBW4qtySj3LiA6ZUSS8hcswnmPx Q2vwUN8crmdY4rvnJmoN276D5RnZgqrRemomvOn9oPqthgnepkYSNNZJ2V4iKmyvXlTH 6XHz8Gd26z2dq6Xo0u+J8f7gocBV0iTOjgTSLV7hz/PB3C1zJtT/anzKF9D3h27doeqE W1SOn9bIwr9lEoVxwhTZcuPuIPzIBaAATLoU7mrh5+oMuZ5DQlbmUbpA8vOVqVTsF5In Ti2Okxm5i18CsFci3ZcveOCcYsL1icO20WrqBxGPDHbbo5Dnv5P88jumZh3X0aqxoyfT msBQ== X-Gm-Message-State: AOAM5330CUOEGViRrWU7OCS0b6JJ7C1ORaLZGFj9E0fFFjJ1XGyNutkB 9ojkSXTHFQ/QAM7JEzTkxlnV9R7tAK0= X-Google-Smtp-Source: ABdhPJy7oJ7BB8Xzb76xkAfOU8XnrPlDmrZ+GsFRHxXmMlUkKT7gC+Vy/DlK/QSONpgwK84Dr/EfGg== X-Received: by 2002:a1c:4c0a:: with SMTP id z10mr495077wmf.95.1610058470286; Thu, 07 Jan 2021 14:27:50 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: libvir-list@redhat.com, Paolo Bonzini , Laurent Vivier , kvm@vger.kernel.org, Jiaxun Yang , Aurelien Jarno , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Paul Burton , Richard Henderson Subject: [PULL 57/66] target/mips: Remove now unreachable LSA/DLSA opcodes code Date: Thu, 7 Jan 2021 23:22:44 +0100 Message-Id: <20210107222253.20382-58-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Since we switched to decodetree-generated processing, we can remove this now unreachable code. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201208203704.243704-6-f4bug@amsat.org> --- target/mips/translate.c | 29 +++++------------------------ 1 file changed, 5 insertions(+), 24 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index cd34b06faae..f4481afb8de 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -280,9 +280,6 @@ enum { R6_OPC_DCLZ =3D 0x12 | OPC_SPECIAL, R6_OPC_DCLO =3D 0x13 | OPC_SPECIAL, R6_OPC_SDBBP =3D 0x0e | OPC_SPECIAL, - - OPC_LSA =3D 0x05 | OPC_SPECIAL, - OPC_DLSA =3D 0x15 | OPC_SPECIAL, }; =20 /* Multiplication variants of the vr54xx. */ @@ -24319,9 +24316,6 @@ static void decode_opc_special_r6(CPUMIPSState *env= , DisasContext *ctx) =20 op1 =3D MASK_SPECIAL(ctx->opcode); switch (op1) { - case OPC_LSA: - gen_LSA(ctx, rd, rt, rs, extract32(ctx->opcode, 6, 2)); - break; case OPC_MULT: case OPC_MULTU: case OPC_DIV: @@ -24372,10 +24366,6 @@ static void decode_opc_special_r6(CPUMIPSState *en= v, DisasContext *ctx) } break; #if defined(TARGET_MIPS64) - case OPC_DLSA: - check_mips_64(ctx); - gen_DLSA(ctx, rd, rt, rs, extract32(ctx->opcode, 6, 2)); - break; case R6_OPC_DCLO: case R6_OPC_DCLZ: if (rt =3D=3D 0 && sa =3D=3D 1) { @@ -24637,18 +24627,14 @@ static void decode_opc_special(CPUMIPSState *env,= DisasContext *ctx) check_insn(ctx, ISA_MIPS2); gen_trap(ctx, op1, rs, rt, -1); break; - case OPC_LSA: /* OPC_PMON */ - if ((ctx->insn_flags & ISA_MIPS_R6) || ase_msa_available(env)) { - decode_opc_special_r6(env, ctx); - } else { - /* Pmon entry point, also R4010 selsl */ + case OPC_PMON: + /* Pmon entry point, also R4010 selsl */ #ifdef MIPS_STRICT_STANDARD - MIPS_INVAL("PMON / selsl"); - gen_reserved_instruction(ctx); + MIPS_INVAL("PMON / selsl"); + gen_reserved_instruction(ctx); #else - gen_helper_0e0i(pmon, sa); + gen_helper_0e0i(pmon, sa); #endif - } break; case OPC_SYSCALL: generate_exception_end(ctx, EXCP_SYSCALL); @@ -24739,11 +24725,6 @@ static void decode_opc_special(CPUMIPSState *env, = DisasContext *ctx) break; } break; - case OPC_DLSA: - if ((ctx->insn_flags & ISA_MIPS_R6) || ase_msa_available(env)) { - decode_opc_special_r6(env, ctx); - } - break; #endif default: if (ctx->insn_flags & ISA_MIPS_R6) { --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 170.10.133.124 as permitted sender) client-ip=170.10.133.124; envelope-from=libvir-list-bounces@redhat.com; helo=us-smtp-delivery-124.mimecast.com; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of redhat.com designates 170.10.133.124 as permitted sender) smtp.mailfrom=libvir-list-bounces@redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1610058494; cv=none; d=zohomail.com; s=zohoarc; b=lIEk9EvZNG/IF4DBtyDOZFt3/SqrGOxFlW8Zxzl84Wv3a/4etmBz0+CqwNgqdUB8x3eiS7L8WcLlMJ/aDoy1M2Z9+DoEDEmRm1XoGh4lgIXHswdUbcJMaNDmpsM2DEm9bKAEK2oFUt+5ZNgUfK7jBpKevzieIzq4UuTLJmlZ9Tw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id b83sm9675771wmd.48.2021.01.07.14.27.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:27:54 -0800 (PST) X-MC-Unique: ofGP0xJvNEGE5toOOKKeKw-1 X-MC-Unique: oHhTNB-mOPqn625lsuS2rg-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=2KMW1AHx+CcjcF6oy+EHrDBlKoWTeIJxR2dMpOZQe7U=; b=eEg+FgP9MuZe43G55kbKsYd9NuFX1lmIeWyPLgJY/PBRtmiX53tSu3DQP6GuwF6XUe 6AUfUm92gkMvmLBq+dMV0tIW+uDq8y2RrinXg2NR+/8mK/ldAmjIJ+uPWwYIpFmUfwoE RNBmb8z+UPMOcVPLXpeXawoN8ABYTKlYCFQCvoviL0VA+RPBh9Jy5uzF8wTndbtJViUN GycEvMz9J7z6ioktxbKf/q44u21UOu5aOYz7dPxDbyYlgJ84FmDdL7v7UwsSe8P2Mn6t GZa+in39u8wTQTdlIX886Zolk2zgCmVX6HUKQvt/UL1Q0xEXzyD+i1rHp6LgIGHGfG4Z iVBA== X-Gm-Message-State: AOAM531FM9AHeTxsKcbB3MQwlRmTG6aF7eCzyk2Y4GPkBjuDEI8MHBu7 rCF7UFFXB5NRMmOijqRTy6g= X-Google-Smtp-Source: ABdhPJwhlHkwhPGlw9CABxGJvzuyyJEPRsNT1YsTzkdqiwuDfohqGuCHk/Hb4esUZif9cgPQE9hFFQ== X-Received: by 2002:a1c:2b46:: with SMTP id r67mr521041wmr.162.1610058475322; Thu, 07 Jan 2021 14:27:55 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 58/66] target/mips: Convert Rel6 Special2 opcode to decodetree Date: Thu, 7 Jan 2021 23:22:45 +0100 Message-Id: <20210107222253.20382-59-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.79 on 10.11.54.5 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Special2 opcode have been removed from the Release 6. Add a single decodetree entry for all the opcode class, triggering Reserved Instruction if ever used. Remove unreachable check_insn_opc_removed() call. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201208203704.243704-7-f4bug@amsat.org> --- target/mips/mips32r6.decode | 2 ++ target/mips/rel6_translate.c | 7 +++++++ target/mips/translate.c | 2 -- 3 files changed, 9 insertions(+), 2 deletions(-) diff --git a/target/mips/mips32r6.decode b/target/mips/mips32r6.decode index 027585ee042..259bac612ab 100644 --- a/target/mips/mips32r6.decode +++ b/target/mips/mips32r6.decode @@ -15,3 +15,5 @@ @lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &lsa =20 LSA 000000 ..... ..... ..... 000 .. 000101 @lsa + +REMOVED 011100 ----- ----- ----- ----- ------ # SPECIAL2 diff --git a/target/mips/rel6_translate.c b/target/mips/rel6_translate.c index 631d0b87748..51264f0ce92 100644 --- a/target/mips/rel6_translate.c +++ b/target/mips/rel6_translate.c @@ -18,6 +18,13 @@ #include "decode-mips32r6.c.inc" #include "decode-mips64r6.c.inc" =20 +bool trans_REMOVED(DisasContext *ctx, arg_REMOVED *a) +{ + gen_reserved_instruction(ctx); + + return true; +} + static bool trans_LSA(DisasContext *ctx, arg_LSA *a) { return gen_LSA(ctx, a->rd, a->rt, a->rs, a->sa); diff --git a/target/mips/translate.c b/target/mips/translate.c index f4481afb8de..01c1ee546e2 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -27137,8 +27137,6 @@ static void decode_opc_special2_legacy(CPUMIPSState= *env, DisasContext *ctx) int rs, rt, rd; uint32_t op1; =20 - check_insn_opc_removed(ctx, ISA_MIPS_R6); - rs =3D (ctx->opcode >> 21) & 0x1f; rt =3D (ctx->opcode >> 16) & 0x1f; rd =3D (ctx->opcode >> 11) & 0x1f; --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.52 as permitted sender) client-ip=209.85.128.52; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f52.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1610058482; cv=none; d=zohomail.com; s=zohoarc; b=GHxLAr7uKLCbIn+OIJn5k2ojqdbUxnempiHERDle4ek+tPcUEmivyrr8BKTFvHCJ9wvYZCovEURwz10RseHeApmeKfOBjrn+UrYvbbgn6+wTVVozI/98bIKQbpv/f1wPc6jcLiarTijEZ8RADhEb0VFgICWRY2h6k2v/AgCckEk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610058482; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=85d5cVtyUsTX7S7LbQY+InlQNjjtHltMndZsoNBoSL4=; b=QDgmVbA5q6axEhoBFWvzqoev9Fw7z/WTevUS8sh9n/NFFQz2SujaEooLWqH/R1Po86MQDBuEggUsuyOteaKKyeQ8IBHWB8tqufmi2NhTgLNuP4yykxQvclTGz/Ob8kgRd6oVOdEyEeCP7wPLqavlcNEIyrRByZRCPti3mTUvZ0M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) by mx.zohomail.com with SMTPS id 1610058482122443.8307667004251; Thu, 7 Jan 2021 14:28:02 -0800 (PST) Received: by mail-wm1-f52.google.com with SMTP id v14so6369038wml.1 for ; Thu, 07 Jan 2021 14:28:01 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (241.red-88-10-103.dynamicip.rima-tde.net. [88.10.103.241]) by smtp.gmail.com with ESMTPSA id z6sm9175402wmi.15.2021.01.07.14.27.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:27:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=85d5cVtyUsTX7S7LbQY+InlQNjjtHltMndZsoNBoSL4=; b=nraN2mOVUcgRgNgyVYJJSc9AtepJctiYv3inK3boLA2ZJ5R3teD2lWbDuOhqftYs4K aljUHeg2H14Qv7vammJ9Idv6h05/oXhGAm9OtTOebDKiVNp+B+A8FEb5pABUCP7izrju g62dDfEKVKuTYpF0OhcN8edwK9PN3DtdyB3deImtoW60QwcUhY3+EiSnGamg8NL7rBhW Z/YmYr8RylFv1/efu4dPwZB07/1+dwV/0nrqEhqgSBMPpzKtxAdEZSXBSsOYeWXBjPrS WEh7NaVbWnHCmc3TwNp0JOMoM45wcZ9HK4/r1MqlKEvMueeHNT7Ln9Ln6y89nhQdsMmg 766Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=85d5cVtyUsTX7S7LbQY+InlQNjjtHltMndZsoNBoSL4=; b=JMuOf05zCpa/narO0UcrsJ32T2N7Osl1LCvTN2IPRnxB0PVgH8md/Ksf70qcE/4t81 BklxpDOuJnY8S157+HUBOTcENwEkHTBzGuDXUr4kPLGqTwZgofe7/FUL83ET0AIA1BTM TJyqSvRs4o34EetIs0cSEAvZYQsnDHrQ+SAJPZTMEipwlYWEYloXdtL1iMZ+HZjmV1x1 m1+NzArvRmRcw8QzlND8TecHdaUiP2yzR5w3LlyRgIKqO57qCj83SDeKE9XRC0FFxLFg KcVvLIWE3YeCbbN30N2JkF0JJ44N+5YKn+inoLvZFvH/hiUmwWGzmZfmDNUGiwRUtSnn K0bw== X-Gm-Message-State: AOAM532sP2G5cVdkkqZ/Y9h4y6+QFMJ22CqzW7zj+A932hQBaqFIadSV FZFWS6jNDXOt7pzewDbVrZQ= X-Google-Smtp-Source: ABdhPJy7r2Dm8szonCZjGKKtJ+ouK1+WaygeHI3YzUMw65d3dheae2KjeyNpEeIr7uKkwkIWUfRTXA== X-Received: by 2002:a1c:1fc2:: with SMTP id f185mr533619wmf.134.1610058480374; Thu, 07 Jan 2021 14:28:00 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: libvir-list@redhat.com, Paolo Bonzini , Laurent Vivier , kvm@vger.kernel.org, Jiaxun Yang , Aurelien Jarno , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Paul Burton , Richard Henderson Subject: [PULL 59/66] target/mips: Convert Rel6 COP1X opcode to decodetree Date: Thu, 7 Jan 2021 23:22:46 +0100 Message-Id: <20210107222253.20382-60-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) COP1x opcode has been removed from the Release 6. Add a single decodetree entry for it, triggering Reserved Instruction if ever used. Remove unreachable check_insn_opc_removed() call. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201208203704.243704-8-f4bug@amsat.org> --- target/mips/mips32r6.decode | 2 ++ target/mips/translate.c | 1 - 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/mips/mips32r6.decode b/target/mips/mips32r6.decode index 259bac612ab..7b12a1bff25 100644 --- a/target/mips/mips32r6.decode +++ b/target/mips/mips32r6.decode @@ -16,4 +16,6 @@ =20 LSA 000000 ..... ..... ..... 000 .. 000101 @lsa =20 +REMOVED 010011 ----- ----- ----- ----- ------ # COP1X (COP3) + REMOVED 011100 ----- ----- ----- ----- ------ # SPECIAL2 diff --git a/target/mips/translate.c b/target/mips/translate.c index 01c1ee546e2..52397bce84b 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28827,7 +28827,6 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) break; =20 case OPC_CP3: - check_insn_opc_removed(ctx, ISA_MIPS_R6); if (ctx->CP0_Config1 & (1 << CP0C1_FP)) { check_cp1_enabled(ctx); op1 =3D MASK_CP3(ctx->opcode); --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) client-ip=209.85.221.51; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f51.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1610058487; cv=none; d=zohomail.com; s=zohoarc; b=moWXqGzhljwAomAEcGe8AGMmn2MNBo/YPp+5qabzqLQwdXZvAPRp/bv2JzAbWf2+6JR7ofjs+WYu64IsOFFapBM5lCuj9KYgnwoC5MOmpq7xFtSyt+yMx+hl2/ku+uWM1HEnFKj6CJ6vh97pkcSsgr58/aVztMfhJZi+egS0nw4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610058487; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=3otSOREwspFZTGVmnwaLoO3N9uKJi1c7L45V7c+1Mcw=; b=LyjtQdAQIwfodVoL2AZd0lj7pthdmf562u7lSg7pqU3xggmuYlV2edN0hxkb900g0qGBBe3EPvfZ3+u44Pcg7hRF4SUc/Q3POPlCJtkEWb8FF4Qwcl6mnpZdLEasAX6YxWaYBOJtYTWOQ3skT0J9DeBksdcxM4hPCVH69L/xsUY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) by mx.zohomail.com with SMTPS id 1610058487232791.0555125487514; Thu, 7 Jan 2021 14:28:07 -0800 (PST) Received: by mail-wr1-f51.google.com with SMTP id t30so7157705wrb.0 for ; Thu, 07 Jan 2021 14:28:06 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (241.red-88-10-103.dynamicip.rima-tde.net. [88.10.103.241]) by smtp.gmail.com with ESMTPSA id r20sm9154498wmh.15.2021.01.07.14.28.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:28:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3otSOREwspFZTGVmnwaLoO3N9uKJi1c7L45V7c+1Mcw=; b=HT9D+afyPYopDhOH8xG1yMnVMl2R5yK8GjRTe7gP0CD+O/KURKNF3XELfGkuu+BszE HXttADITpCa74d+4/2TzIJtS27kpebkg7PEvXIAJvgCmsm3rULxeNFPDN9IkIc2OKA5l vu99Vo01PsCL3DPJEruDzh6k9Rdu08Dy7NApOWJ7HpvBBFUIdj/niEN8v6ySrjhScUV2 udCkWMHIyteQ3ewxG0k8s/F1R3V5BnO9/v5ZawlqXZrCWdyDfnVZbJ30/7WRxbFMnNSl qTcj3qmfoi3g16iLrF5bfmqAXcMKfQrwXjOizVJJ/vV5t8EgF64X9j/iQm38zOg+cNcl NJfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=3otSOREwspFZTGVmnwaLoO3N9uKJi1c7L45V7c+1Mcw=; b=m3c/WamihI/QX0rZMyHzm+I5VCjFOtRnzkGVQJHfaa6n6HpQrqIPfUkuLgcdiQm6Of 01FFDs41SbX6j4+5akmE5A9LAurofBwSyT91OMpDUosHjdNK9IO0Txd5q43QuhkyPCL/ mVOxeG2CH7ktsZkRY3HLdScef1umRNGBIkvV++pVn3Nwgo4nytyPJErVukQV7smqIEc7 MXBYZl+fkpWKCxC8/mOjHQ5awaHD48xPGsrI/iWx826wMbTVU1QTv5vGfNhBUhtRq/hF jn3lp3cFkPn7CQXq8sjkPjcFQ7kHgtWziuSDSEUshNY+VIxTAdRfnmyLlqhQZ3DStyEM wSuQ== X-Gm-Message-State: AOAM532H9AcABzbB6qk7fEZqcMqKAJkEg4QCiy9Cj797HAoo2XVB+Dsz jqPPqB/r+A1VPb2MU5xB6mk= X-Google-Smtp-Source: ABdhPJxtW3I/nOKsLXx6mQmay0VzhVUHJw1O3mSe8PkgVEl0dPlY1zMTbBvNRkTAatGVNp2b5SssbA== X-Received: by 2002:a5d:4905:: with SMTP id x5mr667882wrq.75.1610058485483; Thu, 07 Jan 2021 14:28:05 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: libvir-list@redhat.com, Paolo Bonzini , Laurent Vivier , kvm@vger.kernel.org, Jiaxun Yang , Aurelien Jarno , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Paul Burton , Richard Henderson Subject: [PULL 60/66] target/mips: Convert Rel6 CACHE/PREF opcodes to decodetree Date: Thu, 7 Jan 2021 23:22:47 +0100 Message-Id: <20210107222253.20382-61-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) CACHE/PREF opcodes have been removed from the Release 6. Add a single decodetree entry for the opcodes, triggering Reserved Instruction if ever used. Remove unreachable check_insn_opc_removed() calls. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201208203704.243704-9-f4bug@amsat.org> --- target/mips/mips32r6.decode | 3 +++ target/mips/translate.c | 2 -- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/mips/mips32r6.decode b/target/mips/mips32r6.decode index 7b12a1bff25..e3b3934539a 100644 --- a/target/mips/mips32r6.decode +++ b/target/mips/mips32r6.decode @@ -19,3 +19,6 @@ LSA 000000 ..... ..... ..... 000 .. 00010= 1 @lsa REMOVED 010011 ----- ----- ----- ----- ------ # COP1X (COP3) =20 REMOVED 011100 ----- ----- ----- ----- ------ # SPECIAL2 + +REMOVED 101111 ----- ----- ---------------- # CACHE +REMOVED 110011 ----- ----- ---------------- # PREF diff --git a/target/mips/translate.c b/target/mips/translate.c index 52397bce84b..e8389738c57 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28620,7 +28620,6 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) gen_st_cond(ctx, rt, rs, imm, MO_TESL, false); break; case OPC_CACHE: - check_insn_opc_removed(ctx, ISA_MIPS_R6); check_cp0_enabled(ctx); check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1); if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { @@ -28629,7 +28628,6 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) /* Treat as NOP. */ break; case OPC_PREF: - check_insn_opc_removed(ctx, ISA_MIPS_R6); if (ctx->insn_flags & INSN_R5900) { /* Treat as NOP. */ } else { --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) client-ip=216.205.24.124; envelope-from=libvir-list-bounces@redhat.com; helo=us-smtp-delivery-124.mimecast.com; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) smtp.mailfrom=libvir-list-bounces@redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1610058511; cv=none; d=zohomail.com; s=zohoarc; b=fNUvLHFZ5fZ081lP6njkMYSppSk88WdPMrzUP8IX19mqfHFQDCI9aSBnKwGaLioYXejJwBU10PsaNVA5edAzc6oGylyq4Jud2zdNP/oT4Nr1pBsCGPkTMMWOHN0ITw+RBTw4jZwZFBd3ueDL5FPmJhgYu+D0SRnsUB9m2DF1RQU= ARC-Message-Signature: i=1; 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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id d191sm9498068wmd.24.2021.01.07.14.28.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:28:09 -0800 (PST) X-MC-Unique: 6Q7JbRJIPOW4_v4Req3sqw-1 X-MC-Unique: lH2QPstUPii0wDa55T1b8g-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=jlfAUa3yzIuzGTG6Nw//8ZjnEqUFLfQ9i/y2dfj6avA=; b=YS6t50pF8BLOzbggvj4aGlKU21yDWCudx1dDAWjKF0Y7Yu4TjLECk6431oZh/c7N6T PhCaA+ob5ne6zG1Ne2jCoYDwAB/UAT2bbSh/NWokjEsRasep2NbjJNO/ZsXv09yc7uIu zTMkdKoYy8RyB6IjYdruOlEGSzRVKY5sC4SWpMdfIXoSUDx5jwfglo9MHNgiEpu/E2BK PoWcGsjhBYJNaTfe9miLnZSfmS5pSEVmO9AVbln4l5DckW4g+PosMG3uvSYJskjuEpte NQ3clMaGUGJAfhc9hrpmU/kpgTWoGfXx1ppoUXsLc+SaK/u4MYm0fIIiPCOxTfATtiRo W4HA== X-Gm-Message-State: AOAM533nk2FRvEDHpMclxHy5b6L5+9RcWv0cyfrjYL4I9tL0gxz+33A/ lvnDVyhHv9Gto9UjCp+CnNg= X-Google-Smtp-Source: ABdhPJxQ2uYbbyM0jNrN7Wau7cpOMcgEfAdSDonzO/lX6iY/F9AduoIVoTwOtu2AvYXchXHB30BTvw== X-Received: by 2002:adf:9d82:: with SMTP id p2mr691905wre.330.1610058490365; Thu, 07 Jan 2021 14:28:10 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 61/66] target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetree Date: Thu, 7 Jan 2021 23:22:48 +0100 Message-Id: <20210107222253.20382-62-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable LWL/LWR/SWL/SWR opcodes have been removed from the Release 6. Add a single decodetree entry for the opcodes, triggering Reserved Instruction if ever used. Remove unreachable check_insn_opc_removed() calls. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201208203704.243704-10-f4bug@amsat.org> --- target/mips/mips32r6.decode | 5 +++++ target/mips/translate.c | 5 +---- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/target/mips/mips32r6.decode b/target/mips/mips32r6.decode index e3b3934539a..89a0085fafd 100644 --- a/target/mips/mips32r6.decode +++ b/target/mips/mips32r6.decode @@ -20,5 +20,10 @@ REMOVED 010011 ----- ----- ----- ----- -----= - # COP1X (COP3) =20 REMOVED 011100 ----- ----- ----- ----- ------ # SPECIAL2 =20 +REMOVED 100010 ----- ----- ---------------- # LWL +REMOVED 100110 ----- ----- ---------------- # LWR +REMOVED 101010 ----- ----- ---------------- # SWL +REMOVED 101110 ----- ----- ---------------- # SWR + REMOVED 101111 ----- ----- ---------------- # CACHE REMOVED 110011 ----- ----- ---------------- # PREF diff --git a/target/mips/translate.c b/target/mips/translate.c index e8389738c57..0d729293f6b 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28589,11 +28589,10 @@ static bool decode_opc_legacy(CPUMIPSState *env, = DisasContext *ctx) if (ctx->insn_flags & INSN_R5900) { check_insn_opc_user_only(ctx, INSN_R5900); } + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* Fallthrough */ case OPC_LWL: case OPC_LWR: - check_insn_opc_removed(ctx, ISA_MIPS_R6); - /* Fallthrough */ case OPC_LB: case OPC_LH: case OPC_LW: @@ -28604,8 +28603,6 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) break; case OPC_SWL: case OPC_SWR: - check_insn_opc_removed(ctx, ISA_MIPS_R6); - /* fall through */ case OPC_SB: case OPC_SH: case OPC_SW: --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.54 as permitted sender) client-ip=209.85.128.54; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f54.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1610058497; cv=none; d=zohomail.com; s=zohoarc; b=LqNHiClhPX4/XZwUquHMi0ANCG1zPwBIc6sTsEbzwBk/4crRT6Wt+p9gzMPAWijV1bC4LAffJC9ojqHrPyfKgLJV8MqjY6DJOlFCwYe5zkeWsDNsrILs1JEOWaD31m6NFcxSeTk1qVPOrFPZ4mfS/An8v6vwIA+VIJgHL4qxcWA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610058497; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Yq3mxfTZKdf/fjKj8fFk3v2tF8q6uI5ug94fHU9oH8s=; b=Kg0n06JkyFYtXq31dusZPzEFKM87iAdoSMzQaOGOThn8wVSZU9LNipY1cApkIl0bl2/JyDS9HsecWA8n2pjADCE7O3o0BVHLBzDsCTR7Y4UCGuG/UocmELBOc72jA0JDAvtkRgI/yk5y6CKxwC0vdB290PLB3bC6YNbHbry5HkQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) by mx.zohomail.com with SMTPS id 1610058497135927.9552159772536; Thu, 7 Jan 2021 14:28:17 -0800 (PST) Received: by mail-wm1-f54.google.com with SMTP id r4so6808937wmh.5 for ; Thu, 07 Jan 2021 14:28:16 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (241.red-88-10-103.dynamicip.rima-tde.net. [88.10.103.241]) by smtp.gmail.com with ESMTPSA id m14sm10311543wrh.94.2021.01.07.14.28.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:28:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Yq3mxfTZKdf/fjKj8fFk3v2tF8q6uI5ug94fHU9oH8s=; b=Gd82pxS4+zzvVBDBN4HENJ44Mz7QxhZU8UloC1P6jP13F72cJ1g34MUWYAWomwmLeN 2/A/ouAET0qQIZ38QJbEmi1RMN3rf1WPjaSCpzvlBzTVdPI3Z4/TbI3S1LLx54yFTwFp 5ti2dy+nF9HmEr8DCSO4RtzQmHPOEF8iby5YeukNi9AlSJqS+3pKPdqGHnVpHNKOzOus P9QwZVrNPwz2VNdmmyINVxIEiQIyHv/dewREky1tgJyp3NaCaXh89mYxWSEAXQIAFnVw JQ2WyK9sDprS+omnTUjYMY3S0BevUtsCalHviNOwMRPGdurcSm8BPgTOGQzRhHiE/HLO P0aQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Yq3mxfTZKdf/fjKj8fFk3v2tF8q6uI5ug94fHU9oH8s=; b=rxlVI5oo4rvHd2NNHrYL9bFwL5sSE0ZxZoBxnxmJZEQiU+Yb6v2p+BB0DFkpAnA+Xz ivnoqMC70u5+in1JwOWW5Swirh88Y6e36NRtlWhOFvepqEbfSvv4C78MjTf4X94rvhIw CPJXgfwhGHirTNeCuWkjBp89eWjBS5ldlseANZZsPTsf2RiXHImvWqHMCk0sSoIcAv/B 7ZjQEDTOrL++oQ7DwK46bU8lZNJ3vUu95IA5KCs+i3lyX6IAMcBx+9Y5XUa8xN784CUa /mBgFpEnAK8lQIEdriQpB2jUTMyL+yQzX5GXN2uSUzShBa1+JPUDHgBSMbQKrrzuSWVl puGg== X-Gm-Message-State: AOAM530PHrWgCuEkxdcF6y3obUxQIKdGxVltfLvZG/LRv299RmKkkdDW HGQ2qiuV2gkyxn+pv1HyY0Y= X-Google-Smtp-Source: ABdhPJxD8yDTAfSjw1MvU0PUYHwY/6OzpFw719ayDQklkKKFRhWW9uo0SP6oCkINV8b+kAq1EiW3TA== X-Received: by 2002:a7b:c184:: with SMTP id y4mr534072wmi.92.1610058495363; Thu, 07 Jan 2021 14:28:15 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: libvir-list@redhat.com, Paolo Bonzini , Laurent Vivier , kvm@vger.kernel.org, Jiaxun Yang , Aurelien Jarno , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Paul Burton , Richard Henderson Subject: [PULL 62/66] target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetree Date: Thu, 7 Jan 2021 23:22:49 +0100 Message-Id: <20210107222253.20382-63-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) LWLE/LWRE/SWLE/SWRE (EVA) opcodes have been removed from the Release 6. Add a single decodetree entry for the opcodes, triggering Reserved Instruction if ever used. Remove unreachable check_insn_opc_removed() calls. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201208203704.243704-11-f4bug@amsat.org> --- target/mips/mips32r6.decode | 5 +++++ target/mips/translate.c | 4 ---- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/target/mips/mips32r6.decode b/target/mips/mips32r6.decode index 89a0085fafd..3ec50704cf2 100644 --- a/target/mips/mips32r6.decode +++ b/target/mips/mips32r6.decode @@ -20,6 +20,11 @@ REMOVED 010011 ----- ----- ----- ----- -----= - # COP1X (COP3) =20 REMOVED 011100 ----- ----- ----- ----- ------ # SPECIAL2 =20 +REMOVED 011111 ----- ----- ---------- 011001 # LWLE +REMOVED 011111 ----- ----- ---------- 011010 # LWRE +REMOVED 011111 ----- ----- ---------- 100001 # SWLE +REMOVED 011111 ----- ----- ---------- 100010 # SWRE + REMOVED 100010 ----- ----- ---------------- # LWL REMOVED 100110 ----- ----- ---------------- # LWR REMOVED 101010 ----- ----- ---------------- # SWL diff --git a/target/mips/translate.c b/target/mips/translate.c index 0d729293f6b..73efbd24585 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28122,8 +28122,6 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) switch (op1) { case OPC_LWLE: case OPC_LWRE: - check_insn_opc_removed(ctx, ISA_MIPS_R6); - /* fall through */ case OPC_LBUE: case OPC_LHUE: case OPC_LBE: @@ -28135,8 +28133,6 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) return; case OPC_SWLE: case OPC_SWRE: - check_insn_opc_removed(ctx, ISA_MIPS_R6); - /* fall through */ case OPC_SBE: case OPC_SHE: case OPC_SWE: --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) client-ip=209.85.221.44; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f44.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1610058502; cv=none; d=zohomail.com; s=zohoarc; b=USQoqWKwR6hcMqknK4BZrg/R718/nt8yL0BoUTQbymW9TDnugIij8dp6eZRNCw8WfoXlguDvCG94YfnJLwEVtnC0r5o0+OCSHASbp7m6ea3GeOl2cIIiJV1MYzwfhjUrU0sqgTaSp7uVHiA+Twst1P1MNiPmCa9NNiRz+cHWMgQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610058502; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ADeLjBIuNm8Db2lkSUMCJRDAVngCOHiUxA4Y6spWn0I=; b=F7ksxz1X2Ao+4Y/htC+flE4ZXQSS6qaSP6yk7GfaniosBNTzko1OJFO8rrRMosJuikzTAUQkMq4cK465RkqCtb1jOdaIdL9X9q3HaLZVrIwyY1QXPLxmR6a2z2w1dodyqaWL6nMTOKs0RvM8KLGZssD2yjg8rnN94fI58JsAggI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) by mx.zohomail.com with SMTPS id 16100585024221023.3668910212217; Thu, 7 Jan 2021 14:28:22 -0800 (PST) Received: by mail-wr1-f44.google.com with SMTP id c5so7112680wrp.6 for ; Thu, 07 Jan 2021 14:28:21 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (241.red-88-10-103.dynamicip.rima-tde.net. [88.10.103.241]) by smtp.gmail.com with ESMTPSA id m17sm11788101wrn.0.2021.01.07.14.28.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:28:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ADeLjBIuNm8Db2lkSUMCJRDAVngCOHiUxA4Y6spWn0I=; b=DsPiUBFgZubvxf2GePgfLlQAvIsVAdsSz4Pr9D3xFLnGnAV6kscnE/yLi/H5oybGLJ lf6RlFYc8SoacNkGAukiY77zsn/ei6qXWVMzAh0raYVJ+BZGXSc3gX+fw1NAah1cI+zw 8PgNNKqAdzIlWOklbEDv9+ZAVUtEE4XqP6XZUxNg7IYik2MvFnSkGbKXZH2iCmoneHUa wUTrY0iosyh0IdFd1OolVkHkDYyuWJHnSG47p28Wsmkh7VI+05X3pkbvPLTWqeme9Ypg IddKtUBE2yWH2SK57efV4dnc4mdZxos5u/NcrMP1Z8oJkPnAuAvXAt7NCZK8CIzc4U2w CjKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=ADeLjBIuNm8Db2lkSUMCJRDAVngCOHiUxA4Y6spWn0I=; b=akuOJyyeVgFbuKDH+dhSGFmQqnvYHp2UvEC6i/VF35b1ewbxohc2vDNKOpuyDSEBio hVOztnBs5djVpULYnkQ6m4naxnczlEpXsFq4PDeE0KjISNXrzbNywgUem8YQNQDFRDAh AGMvAlMm8/gJ043VQjlFrcz55HAsr6teld/Axt/w08/55oYk0LDOKmsfhrz26A3m2cMs SzQTghHaGh5/GVacgn183u2NwS1vz7K5zqTNEsu95QH4j0yTHAzMxCLBLPZ//fLpPR5C Utvk799jttFF3DYaOl2BTxTwC6zS7W6JsJkme2oX9GeJ9L6hgU8WgQGBJ/8dDPB92lT4 Cu+w== X-Gm-Message-State: AOAM532aWOFnwdb7lLx4jjRd6E/B+qZYdjbnbmojT5CsYr97dc5cEy+u 3qUfubplD5IuTncr4MZVj8w= X-Google-Smtp-Source: ABdhPJwmwG+IOuURAtgZfJZeyY0mGhHbK6Zox4gOBAU8vjb6V2st3D0j0ccmQnWMvuf9SjqNPgJ4VQ== X-Received: by 2002:a5d:684b:: with SMTP id o11mr667739wrw.157.1610058500527; Thu, 07 Jan 2021 14:28:20 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: libvir-list@redhat.com, Paolo Bonzini , Laurent Vivier , kvm@vger.kernel.org, Jiaxun Yang , Aurelien Jarno , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Paul Burton , Richard Henderson Subject: [PULL 63/66] target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree Date: Thu, 7 Jan 2021 23:22:50 +0100 Message-Id: <20210107222253.20382-64-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) LDL/LDR/SDL/SDR opcodes have been removed from the Release 6. Add a single decodetree entry for the opcodes, triggering Reserved Instruction if ever used. Remove unreachable check_insn_opc_removed() calls. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201208203704.243704-12-f4bug@amsat.org> --- target/mips/mips64r6.decode | 6 ++++++ target/mips/translate.c | 5 +---- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/target/mips/mips64r6.decode b/target/mips/mips64r6.decode index e812224341e..8c3fc5dae9c 100644 --- a/target/mips/mips64r6.decode +++ b/target/mips/mips64r6.decode @@ -10,8 +10,14 @@ # (Document Number: MD00087-2B-MIPS64BIS-AFP-6.06) # =20 +&REMOVED !extern &lsa rd rt rs sa !extern =20 @lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &lsa =20 DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa + +REMOVED 011010 ----- ----- ---------------- # LDL +REMOVED 011011 ----- ----- ---------------- # LDR +REMOVED 101100 ----- ----- ---------------- # SDL +REMOVED 101101 ----- ----- ---------------- # SDR diff --git a/target/mips/translate.c b/target/mips/translate.c index 73efbd24585..f46d7c5f80b 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28871,11 +28871,10 @@ static bool decode_opc_legacy(CPUMIPSState *env, = DisasContext *ctx) if (ctx->insn_flags & INSN_R5900) { check_insn_opc_user_only(ctx, INSN_R5900); } + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* fall through */ case OPC_LDL: case OPC_LDR: - check_insn_opc_removed(ctx, ISA_MIPS_R6); - /* fall through */ case OPC_LWU: case OPC_LD: check_insn(ctx, ISA_MIPS3); @@ -28884,8 +28883,6 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) break; case OPC_SDL: case OPC_SDR: - check_insn_opc_removed(ctx, ISA_MIPS_R6); - /* fall through */ case OPC_SD: check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 63.128.21.124 as permitted sender) client-ip=63.128.21.124; envelope-from=libvir-list-bounces@redhat.com; helo=us-smtp-delivery-124.mimecast.com; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of redhat.com designates 63.128.21.124 as permitted sender) smtp.mailfrom=libvir-list-bounces@redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1610058540; cv=none; d=zohomail.com; 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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id v20sm11076739wra.19.2021.01.07.14.28.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:28:24 -0800 (PST) X-MC-Unique: Ze-FJmQyMbeW2WyLOqU9dg-1 X-MC-Unique: o7TJYj_FMOyO7SUO5KfPQw-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=fdYSuYQvqNKVpq92aM/7Wd5ow52H+eR0/gXxomb4sjQ=; b=IqKLkFVSnfT3IdLa3ipWvAHmdsM6clGShxuMHMLdP6IgVODxrHVcRXb+mJ12Rpi8nR akvEkfpfVWpEmlcAZJ1f2lyFPKocvjhVCw29dxcoyTJI7alviNd9mFVNAzOr6hdtJLrn SXt+0KsJGB2uTr+F6VM3cR/IfgoE+mPloPvACZZT42is7L6meU1u1rcOd0wxorR/a0tj Y3LvykwmZsNNmh7wm+8bHnuSzfjZVdUvMLbMxZEaSwtAdA9sN3gOpmeE9cMPNTPP7FsC vsXUgBKf4yoQMAuPlez3nLOsBz8XrGizr+u1akuOYgXyyCLiyUTA70GlElbZUib2W1J5 PBeA== X-Gm-Message-State: AOAM531Iiw/4OMSc+w19nBYcpUsQv9Bayqb2aUzM3cn2q6xkcmr0sJUE yLNULKywUmztJuHCB+VIVWQ= X-Google-Smtp-Source: ABdhPJws5xak3FcT1HkGs0Ly6rut//3AP/lYHP4MA74T0CtSIKncybZuO1pBYPc0CUfac9oScLTv7A== X-Received: by 2002:a1c:e90b:: with SMTP id q11mr537869wmc.102.1610058505516; Thu, 07 Jan 2021 14:28:25 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 64/66] target/mips: Convert Rel6 LLD/SCD opcodes to decodetree Date: Thu, 7 Jan 2021 23:22:51 +0100 Message-Id: <20210107222253.20382-65-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable LLD/SCD opcodes have been removed from the Release 6. Add a single decodetree entry for the opcodes, triggering Reserved Instruction if ever used. Remove unreachable check_insn_opc_removed() calls. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201208203704.243704-13-f4bug@amsat.org> --- target/mips/mips64r6.decode | 3 +++ target/mips/translate.c | 2 -- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/mips/mips64r6.decode b/target/mips/mips64r6.decode index 8c3fc5dae9c..609b8958d25 100644 --- a/target/mips/mips64r6.decode +++ b/target/mips/mips64r6.decode @@ -21,3 +21,6 @@ REMOVED 011010 ----- ----- ---------------- = # LDL REMOVED 011011 ----- ----- ---------------- # LDR REMOVED 101100 ----- ----- ---------------- # SDL REMOVED 101101 ----- ----- ---------------- # SDR + +REMOVED 110100 ----- ----- ---------------- # LLD +REMOVED 111100 ----- ----- ---------------- # SCD diff --git a/target/mips/translate.c b/target/mips/translate.c index f46d7c5f80b..9f717aab287 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28871,7 +28871,6 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) if (ctx->insn_flags & INSN_R5900) { check_insn_opc_user_only(ctx, INSN_R5900); } - check_insn_opc_removed(ctx, ISA_MIPS_R6); /* fall through */ case OPC_LDL: case OPC_LDR: @@ -28889,7 +28888,6 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) gen_st(ctx, op, rt, rs, imm); break; case OPC_SCD: - check_insn_opc_removed(ctx, ISA_MIPS_R6); check_insn(ctx, ISA_MIPS3); if (ctx->insn_flags & INSN_R5900) { check_insn_opc_user_only(ctx, INSN_R5900); --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) client-ip=209.85.221.53; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f53.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1610058512; cv=none; d=zohomail.com; s=zohoarc; b=B0a7rAauTFlXtzWTkol1tH9+VC70X7DnXDlIwlrqESrkDOY5HQhnS8cN15rvG4acFtqwsZ8sn43l2BVD6BNn6aZbBdQCUJxk8ubV9mWHUdkhUg1ElwU4nGUfXBM95ZP3YnDyhHrVNIkCEgGWy72XIAQ5Nh7mq38kFPt1s1wa7wk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610058512; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=d4Gj//OkD5jKhI/4P4VQprZ7+6fnm/3amg1m9obP+eI=; b=F574O6PQ5qFhfmh15gDs6/UayQtNYQgRfNA+1/J27E4WdTbwYCOzVoJnhI5FKkl0MDcrXYviQ96uXHoG9Cb00lBo6EEcMkw3rNaHXpovAlk1POY71gPc6/7fJ8IWlGjFufFJXBPLYMQlhnP5SqOiJ2F+KjdJuJTFFtTVA/tT/hU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) by mx.zohomail.com with SMTPS id 1610058512540460.5036597372879; Thu, 7 Jan 2021 14:28:32 -0800 (PST) Received: by mail-wr1-f53.google.com with SMTP id c5so7113026wrp.6 for ; Thu, 07 Jan 2021 14:28:31 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (241.red-88-10-103.dynamicip.rima-tde.net. [88.10.103.241]) by smtp.gmail.com with ESMTPSA id c6sm10851358wrh.7.2021.01.07.14.28.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:28:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=d4Gj//OkD5jKhI/4P4VQprZ7+6fnm/3amg1m9obP+eI=; b=btSc1YFi2LkwM2+EAdgZ56w6Qe52rwg/g+fmeS/hD3F68F2fEFYUhlDqUxB33dh1gj xOYJ4UZ8CN/NTQcanjgvNXqtwdaLTVhDW8Sav3kCpJ7B0+ZIUqVWlQBhH0fEe8wc9OEV kK1dVmMJcIBi1TumZ7MxLX9shUchuLu0bnXJ4yeimJeC4gFUQK6rqLNVvsRForqedVnL 0d0CHDhdUFMjAaOtrL6QL2447KxIpU6h+WvZ6NdCoSVPcGrZK1u/EAqPzOJK8OHe4CWU woZXW1JsNZG8HEY2OaN964q8Y0N1/EIGnEX2OyllI3J+E99MYPhjmAi3xHJwUnt5A7mB 8Fcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=d4Gj//OkD5jKhI/4P4VQprZ7+6fnm/3amg1m9obP+eI=; b=qij1UG/uPpPEVBebe6SMRcZNjWsaMCm8xssfy4/7VhugTj68f+3KSmxNy8CqcnpH1G OGpL0bKubpavJMqUILJEgUJ3WtkZgmdxTNqzbIZQtqj6lQgPvoaYqtGNxNZqaAwgMlxD SaHuqnpo/16nxGg6yiK2pHdT0hpdi4dpIj3yAO7b+94u8DwQqXKbJFa1V6/Apb879iAK X0swVVUAGLNNsZ24JD3+gWjviu0yxO1iDhG46x0dZkTTkK7lnRIpRqjBcf+1GtMYEQ/I 6xp6z6dTv21jpzaLYIpTbDkYzrKqDP34K/DJ11atfuJgos0wa0Fb4LYgv3Ebd5bTzzPx K4JQ== X-Gm-Message-State: AOAM531nLgJ7UYN4rdO6ksQqs+SkR9aodshmeHuOmn4T8vs19bW8XDDu 0obYj3z6mpjmdthU2Rqqs2ABk7Aodt8= X-Google-Smtp-Source: ABdhPJyeb/1d59aZ9MSRmZedPlgjNOORpFfUrYpwLVOmJ2MAgpomcFip6GYr8+4/7KkvOopf0mTobA== X-Received: by 2002:a5d:5385:: with SMTP id d5mr677700wrv.384.1610058510668; Thu, 07 Jan 2021 14:28:30 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: libvir-list@redhat.com, Paolo Bonzini , Laurent Vivier , kvm@vger.kernel.org, Jiaxun Yang , Aurelien Jarno , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Paul Burton , Richard Henderson Subject: [PULL 65/66] target/mips: Convert Rel6 LL/SC opcodes to decodetree Date: Thu, 7 Jan 2021 23:22:52 +0100 Message-Id: <20210107222253.20382-66-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) LL/SC opcodes have been removed from the Release 6. Add a single decodetree entry for the opcodes, triggering Reserved Instruction if ever used. Remove unreachable check_insn_opc_removed() calls. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201208203704.243704-14-f4bug@amsat.org> --- target/mips/mips32r6.decode | 2 ++ target/mips/translate.c | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/mips/mips32r6.decode b/target/mips/mips32r6.decode index 3ec50704cf2..489c20aa4e9 100644 --- a/target/mips/mips32r6.decode +++ b/target/mips/mips32r6.decode @@ -31,4 +31,6 @@ REMOVED 101010 ----- ----- ---------------- = # SWL REMOVED 101110 ----- ----- ---------------- # SWR =20 REMOVED 101111 ----- ----- ---------------- # CACHE +REMOVED 110000 ----- ----- ---------------- # LL REMOVED 110011 ----- ----- ---------------- # PREF +REMOVED 111000 ----- ----- ---------------- # SC diff --git a/target/mips/translate.c b/target/mips/translate.c index 9f717aab287..b5b7706a7c2 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28585,7 +28585,6 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) if (ctx->insn_flags & INSN_R5900) { check_insn_opc_user_only(ctx, INSN_R5900); } - check_insn_opc_removed(ctx, ISA_MIPS_R6); /* Fallthrough */ case OPC_LWL: case OPC_LWR: @@ -28606,7 +28605,6 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) break; case OPC_SC: check_insn(ctx, ISA_MIPS2); - check_insn_opc_removed(ctx, ISA_MIPS_R6); if (ctx->insn_flags & INSN_R5900) { check_insn_opc_user_only(ctx, INSN_R5900); } --=20 2.26.2 From nobody Thu Apr 25 08:53:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) client-ip=216.205.24.124; envelope-from=libvir-list-bounces@redhat.com; helo=us-smtp-delivery-124.mimecast.com; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) smtp.mailfrom=libvir-list-bounces@redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1610058547; cv=none; d=zohomail.com; s=zohoarc; b=huQgYihxBrvUGNWXlyT5bBFkcchtPBnFRlUPokvlJAi9a69TzIQFdpv1lWucWDA7SiEqK+dnzJqSY/Rsj9MNTKMLzGUVvcdFzt3nxXkHrN6XDAjtpEIN98zpvMxO1gc1jeo3CWCs8Qdr6Z/bQk5Ikt6R7Hbjlfx1Th1R+ZG3qEQ= ARC-Message-Signature: i=1; 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[88.10.103.241]) by smtp.gmail.com with ESMTPSA id s13sm10723025wra.53.2021.01.07.14.28.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 14:28:35 -0800 (PST) X-MC-Unique: nVn5GC-UPCq0grQIfvg4KA-1 X-MC-Unique: bI7uwYvvMHueoOS66-75oQ-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=D0ZV7Tyr2j4fG9lWfj8Aj9YT0gOWwwyKM8Utajfqaqw=; b=ME5lr1NmvMbecn4XWv9et73qjZdRU6L/OF60bAi0T/BiooBwBRm7Ayovsc1j7B2gXO WbW9pG83aOZuDRYaSo1mtQFv7kukpAx+BBESq12XUmYZoKH27jakld/5gR225DMQp+nH OL7eyPwRklnScIhahWAoW+CYiV4esWFW+USZ6vo5v+oE1rmz1KbWATtsHm9Q1AliSN+/ iIrT1KQy91CLRQGLh2pErJ1Llh7+kHOgFN9UlWACmq09AXJuH7VS42ysXsnN8RJ+Mvpn 0lE9tTP03C3Y3WaBPZR9okYKAyMwcnPHUs4LhPC2v5EThgz/6oH8+4Q0L6IYbfULjcOt lbnA== X-Gm-Message-State: AOAM531UYUI4G2TLbM2ZY/8IuASLlQFKINYDA1f+UAMMWj2tt34BQTN6 2aeIFaOZWiAN+8ShQmmJPQI= X-Google-Smtp-Source: ABdhPJwTubkYm60fTqneKGYSwtRCJWkNzO9wICrkxUQL5Qd4H9Q/yF7YPiKn9A1Eda9+ks8qWYLV/A== X-Received: by 2002:a7b:c208:: with SMTP id x8mr491314wmi.179.1610058515651; Thu, 07 Jan 2021 14:28:35 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 66/66] docs/system: Remove deprecated 'fulong2e' machine alias Date: Thu, 7 Jan 2021 23:22:53 +0100 Message-Id: <20210107222253.20382-67-f4bug@amsat.org> In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org> References: <20210107222253.20382-1-f4bug@amsat.org> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Scanned-By: MIMEDefang 2.78 on 10.11.54.4 X-loop: libvir-list@redhat.com Cc: Aleksandar Rikalo , Paul Burton , kvm@vger.kernel.org, libvir-list@redhat.com, Huacai Chen , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Paolo Bonzini , Aurelien Jarno X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=libvir-list-bounces@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The 'fulong2e' machine alias has been marked as deprecated since QEMU v5.1 (commit c3a09ff68dd, the machine is renamed 'fuloong2e'). Time to remove it now. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Huacai Chen Reviewed-by: Thomas Huth Message-Id: <20210106184602.3771551-1-f4bug@amsat.org> --- docs/system/deprecated.rst | 5 ----- docs/system/removed-features.rst | 5 +++++ hw/mips/fuloong2e.c | 1 - 3 files changed, 5 insertions(+), 6 deletions(-) diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst index bacd76d7a58..e20bfcb17a4 100644 --- a/docs/system/deprecated.rst +++ b/docs/system/deprecated.rst @@ -309,11 +309,6 @@ The 'scsi-disk' device is deprecated. Users should use= 'scsi-hd' or System emulator machines ------------------------ =20 -mips ``fulong2e`` machine (since 5.1) -''''''''''''''''''''''''''''''''''''' - -This machine has been renamed ``fuloong2e``. - ``pc-1.0``, ``pc-1.1``, ``pc-1.2`` and ``pc-1.3`` (since 5.0) ''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' =20 diff --git a/docs/system/removed-features.rst b/docs/system/removed-feature= s.rst index 8b20d78a4d0..430fc33ca18 100644 --- a/docs/system/removed-features.rst +++ b/docs/system/removed-features.rst @@ -120,6 +120,11 @@ mips ``r4k`` platform (removed in 5.2) This machine type was very old and unmaintained. Users should use the ``ma= lta`` machine type instead. =20 +mips ``fulong2e`` machine alias (removed in 6.0) +'''''''''''''''''''''''''''''''''''''''''''''''' + +This machine has been renamed ``fuloong2e``. + Related binaries ---------------- =20 diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c index 29805242caa..bac2adbd5ae 100644 --- a/hw/mips/fuloong2e.c +++ b/hw/mips/fuloong2e.c @@ -383,7 +383,6 @@ static void mips_fuloong2e_init(MachineState *machine) static void mips_fuloong2e_machine_init(MachineClass *mc) { mc->desc =3D "Fuloong 2e mini pc"; - mc->alias =3D "fulong2e"; /* Incorrect name used up to QEM= U 4.2 */ mc->init =3D mips_fuloong2e_init; mc->block_default_type =3D IF_IDE; mc->default_cpu_type =3D MIPS_CPU_TYPE_NAME("Loongson-2E"); --=20 2.26.2