From nobody Tue Feb 10 04:13:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607000021; cv=none; d=zohomail.com; s=zohoarc; b=ZzZmEeGym5hU6uKthcaBBagCQGKdrhoXj4dlrl/H8MAqcgz8VPEBGbM7vQ1Oc21436CY24uvPfJgFo8yb395Mw9OlN5MqZZyNR87SSNqRnZ3fNSK7pPY58zUlKHAVa3XPLkzCcmLsNgBH6Jmist0LrxXdtc2cP+Z1Wm9PpqxSVM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607000021; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=rM/bFU7rHOPObrFrpceUwIwQKgpKa0lY3r5w1HicLsQ=; b=VWldyH2LjvF8PAUG12oM+6PG1MgdPCoC7H2JysvwH1av3eXv9MchU53/kz6uwzn7ptlTYWK//RvqmUJzGsHhGVW11y8XuEPo4cjFqVs+h78wt/hurCs1xDF/uS4GWX28nRkSxlH1KvKGvYK7pgYdglfg55gV+dwHawQgSOtpctQ= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607000021325730.9167438326116; Thu, 3 Dec 2020 04:53:41 -0800 (PST) Received: from localhost ([::1]:37338 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kko7A-0004vz-5q for importer@patchew.org; Thu, 03 Dec 2020 07:53:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45212) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kko1V-0004OI-Dv; Thu, 03 Dec 2020 07:47:49 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:2818) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kko1R-0006v2-Rv; Thu, 03 Dec 2020 07:47:49 -0500 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.58]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4CmwZz1wzSzkksF; Thu, 3 Dec 2020 20:47:07 +0800 (CST) Received: from huawei.com (10.174.186.236) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.487.0; Thu, 3 Dec 2020 20:47:34 +0800 From: Yifei Jiang To: , Subject: [PATCH RFC v4 10/15] target/riscv: Add kvm_riscv_get/put_regs_timer Date: Thu, 3 Dec 2020 20:46:58 +0800 Message-ID: <20201203124703.168-11-jiangyifei@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20201203124703.168-1-jiangyifei@huawei.com> References: <20201203124703.168-1-jiangyifei@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.186.236] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.190; envelope-from=jiangyifei@huawei.com; helo=szxga04-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: victor.zhangxiaofeng@huawei.com, sagark@eecs.berkeley.edu, kvm@vger.kernel.org, libvir-list@redhat.com, kbastian@mail.uni-paderborn.de, anup.patel@wdc.com, yinyipeng1@huawei.com, Alistair.Francis@wdc.com, Yifei Jiang , kvm-riscv@lists.infradead.org, palmer@dabbelt.com, dengkai1@huawei.com, wu.wubin@huawei.com, zhang.zhanghailiang@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Add kvm_riscv_get/put_regs_timer to synchronize virtual time context from KVM. To set register of RISCV_TIMER_REG(state) will occur a error from KVM on kvm_timer_state =3D=3D 0. It's better to adapt in KVM, but it doesn't ma= tter that adaping in QEMU. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/cpu.h | 6 ++++ target/riscv/kvm.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 78 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 4288898019..16d6050ead 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -237,6 +237,12 @@ struct CPURISCVState { =20 hwaddr kernel_addr; hwaddr fdt_addr; + + /* kvm timer */ + bool kvm_timer_dirty; + uint64_t kvm_timer_time; + uint64_t kvm_timer_compare; + uint64_t kvm_timer_state; }; =20 OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass, diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index afd99b3315..79228eb726 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -59,6 +59,9 @@ static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx) #define RISCV_CSR_REG(name) kvm_riscv_reg_id(KVM_REG_RISCV_CSR, \ KVM_REG_RISCV_CSR_REG(name)) =20 +#define RISCV_TIMER_REG(name) kvm_riscv_reg_id(KVM_REG_RISCV_TIMER, \ + KVM_REG_RISCV_TIMER_REG(name)) + #define RISCV_FP_F_REG(idx) kvm_riscv_reg_id(KVM_REG_RISCV_FP_F, idx) =20 #define RISCV_FP_D_REG(idx) kvm_riscv_reg_id(KVM_REG_RISCV_FP_D, idx) @@ -306,6 +309,75 @@ static int kvm_riscv_put_regs_fp(CPUState *cs) return ret; } =20 +static void kvm_riscv_get_regs_timer(CPUState *cs) +{ + int ret; + uint64_t reg; + CPURISCVState *env =3D &RISCV_CPU(cs)->env; + + if (env->kvm_timer_dirty) { + return; + } + + ret =3D kvm_get_one_reg(cs, RISCV_TIMER_REG(time), ®); + if (ret) { + abort(); + } + env->kvm_timer_time =3D reg; + + ret =3D kvm_get_one_reg(cs, RISCV_TIMER_REG(compare), ®); + if (ret) { + abort(); + } + env->kvm_timer_compare =3D reg; + + ret =3D kvm_get_one_reg(cs, RISCV_TIMER_REG(state), ®); + if (ret) { + abort(); + } + env->kvm_timer_state =3D reg; + + env->kvm_timer_dirty =3D true; +} + +static void kvm_riscv_put_regs_timer(CPUState *cs) +{ + int ret; + uint64_t reg; + CPURISCVState *env =3D &RISCV_CPU(cs)->env; + + if (!env->kvm_timer_dirty) { + return; + } + + reg =3D env->kvm_timer_time; + ret =3D kvm_set_one_reg(cs, RISCV_TIMER_REG(time), ®); + if (ret) { + abort(); + } + + reg =3D env->kvm_timer_compare; + ret =3D kvm_set_one_reg(cs, RISCV_TIMER_REG(compare), ®); + if (ret) { + abort(); + } + + /* + * To set register of RISCV_TIMER_REG(state) will occur a error from K= VM + * on env->kvm_timer_state =3D=3D 0, It's better to adapt in KVM, but = it + * doesn't matter that adaping in QEMU now. + * TODO If KVM changes, adapt here. + */ + if (env->kvm_timer_state) { + reg =3D env->kvm_timer_state; + ret =3D kvm_set_one_reg(cs, RISCV_TIMER_REG(state), ®); + if (ret) { + abort(); + } + } + + env->kvm_timer_dirty =3D false; +} =20 const KVMCapabilityInfo kvm_arch_required_capabilities[] =3D { KVM_CAP_LAST_INFO --=20 2.19.1