From nobody Mon Apr 29 12:29:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1598520232; cv=none; d=zohomail.com; s=zohoarc; b=c1vmBQKdReLhuXi8KgB8yzBuEW6/7OTAOHHtkLP1kRu7jhPSx0biKr6fPVeSLs7enOcqyUrMjl8Z+OlF0qZKvONjN77/vFDPVwV/wWlzBxA0wsujB0BSVbGIPLgnHEghZjYqWDkjghs88dv7W2d2O5pZG/xTxUmyIySo35OYBGI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598520232; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=C8nqvxeFaovylS/MXuVstaIj6Mt2qBGXJo94nO1LcZI=; b=Cv6NeUEnT30+kOAsayqL6XmK/vrg4hK/IHX30MztkQFY2Cohyv4truZXelnGinrKKxqDGxezMUpjnqIC/E+KFyx14RgapsHZMulfA2wESp50f9PhSP8ahG4JwvrjkU8CENmlfunc2BuXioMAanqeHzTqZCVIAW9Vl01K+rUrA0c= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598520232633353.7208032779323; Thu, 27 Aug 2020 02:23:52 -0700 (PDT) Received: from localhost ([::1]:55116 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBE8N-0004NR-9S for importer@patchew.org; Thu, 27 Aug 2020 05:23:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56930) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBE7K-0002el-LD; Thu, 27 Aug 2020 05:22:46 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:4273 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBE7I-0003FD-9N; Thu, 27 Aug 2020 05:22:46 -0400 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id DD3CB5AA9F2509329753; Thu, 27 Aug 2020 17:22:34 +0800 (CST) Received: from huawei.com (10.174.187.31) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.487.0; Thu, 27 Aug 2020 17:22:26 +0800 From: Yifei Jiang To: , Subject: [PATCH RFC v3 01/14] linux-header: Update linux/kvm.h Date: Thu, 27 Aug 2020 17:21:24 +0800 Message-ID: <20200827092137.479-2-jiangyifei@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20200827092137.479-1-jiangyifei@huawei.com> References: <20200827092137.479-1-jiangyifei@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.187.31] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.191; envelope-from=jiangyifei@huawei.com; helo=huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/27 02:09:23 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: victor.zhangxiaofeng@huawei.com, sagark@eecs.berkeley.edu, kvm@vger.kernel.org, libvir-list@redhat.com, kbastian@mail.uni-paderborn.de, anup.patel@wdc.com, yinyipeng1@huawei.com, Alistair.Francis@wdc.com, Yifei Jiang , kvm-riscv@lists.infradead.org, palmer@dabbelt.com, dengkai1@huawei.com, wu.wubin@huawei.com, zhang.zhanghailiang@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Update linux-headers/linux/kvm.h from https://github.com/kvm-riscv/linux. Only use this header file, so here do not update all linux headers by update-linux-headers.sh until above KVM series is accepted. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- linux-headers/linux/kvm.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h index a28c366737..b2d3721798 100644 --- a/linux-headers/linux/kvm.h +++ b/linux-headers/linux/kvm.h @@ -248,6 +248,7 @@ struct kvm_hyperv_exit { #define KVM_EXIT_IOAPIC_EOI 26 #define KVM_EXIT_HYPERV 27 #define KVM_EXIT_ARM_NISV 28 +#define KVM_EXIT_RISCV_SBI 28 =20 /* For KVM_EXIT_INTERNAL_ERROR */ /* Emulate instruction failed. */ @@ -412,6 +413,13 @@ struct kvm_run { __u64 esr_iss; __u64 fault_ipa; } arm_nisv; + /* KVM_EXIT_RISCV_SBI */ + struct { + unsigned long extension_id; + unsigned long function_id; + unsigned long args[6]; + unsigned long ret[2]; + } riscv_sbi; /* Fix the size of the union. */ char padding[256]; }; --=20 2.19.1 From nobody Mon Apr 29 12:29:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Thu, 27 Aug 2020 02:29:29 -0700 (PDT) Received: from localhost ([::1]:53232 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBEDn-0006Zi-RC for importer@patchew.org; Thu, 27 Aug 2020 05:29:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57074) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBE7Q-0002pk-1i; Thu, 27 Aug 2020 05:22:52 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:56370 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBE7J-0003Fd-76; Thu, 27 Aug 2020 05:22:51 -0400 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id C2B8CADD0F0E1E22CFC6; Thu, 27 Aug 2020 17:22:40 +0800 (CST) Received: from huawei.com (10.174.187.31) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.487.0; Thu, 27 Aug 2020 17:22:27 +0800 From: Yifei Jiang To: , Subject: [PATCH RFC v3 02/14] target/riscv: Add target/riscv/kvm.c to place the public kvm interface Date: Thu, 27 Aug 2020 17:21:25 +0800 Message-ID: <20200827092137.479-3-jiangyifei@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20200827092137.479-1-jiangyifei@huawei.com> References: <20200827092137.479-1-jiangyifei@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.187.31] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.35; envelope-from=jiangyifei@huawei.com; helo=huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/27 05:22:41 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: victor.zhangxiaofeng@huawei.com, sagark@eecs.berkeley.edu, kvm@vger.kernel.org, libvir-list@redhat.com, kbastian@mail.uni-paderborn.de, anup.patel@wdc.com, yinyipeng1@huawei.com, Alistair Francis , Yifei Jiang , kvm-riscv@lists.infradead.org, palmer@dabbelt.com, dengkai1@huawei.com, wu.wubin@huawei.com, zhang.zhanghailiang@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Add target/riscv/kvm.c to place kvm_arch_* function needed by kvm/kvm-all.c. Meanwhile, add kvm support in configure file. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin Reviewed-by: Alistair Francis --- configure | 1 + target/riscv/kvm.c | 128 +++++++++++++++++++++++++++++++++++++++ target/riscv/meson.build | 1 + 3 files changed, 130 insertions(+) create mode 100644 target/riscv/kvm.c diff --git a/configure b/configure index b8f5b81a67..f1fe4021d4 100755 --- a/configure +++ b/configure @@ -269,6 +269,7 @@ supported_kvm_target() { x86_64:i386 | x86_64:x86_64 | x86_64:x32 | \ mips:mips | mipsel:mips | mips64:mips | mips64el:mips | \ ppc:ppc | ppc64:ppc | ppc:ppc64 | ppc64:ppc64 | ppc64:ppc64le | \ + riscv32:riscv32 | riscv64:riscv64 | \ s390x:s390x) return 0 ;; diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c new file mode 100644 index 0000000000..8c386d9acf --- /dev/null +++ b/target/riscv/kvm.c @@ -0,0 +1,128 @@ +/* + * RISC-V implementation of KVM hooks + * + * Copyright (c) 2020 Huawei Technologies Co., Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include + +#include + +#include "qemu-common.h" +#include "qemu/timer.h" +#include "qemu/error-report.h" +#include "qemu/main-loop.h" +#include "sysemu/sysemu.h" +#include "sysemu/kvm.h" +#include "sysemu/kvm_int.h" +#include "cpu.h" +#include "trace.h" +#include "hw/pci/pci.h" +#include "exec/memattrs.h" +#include "exec/address-spaces.h" +#include "hw/boards.h" +#include "hw/irq.h" +#include "qemu/log.h" +#include "hw/loader.h" + +const KVMCapabilityInfo kvm_arch_required_capabilities[] =3D { + KVM_CAP_LAST_INFO +}; + +int kvm_arch_get_registers(CPUState *cs) +{ + return 0; +} + +int kvm_arch_put_registers(CPUState *cs, int level) +{ + return 0; +} + +int kvm_arch_release_virq_post(int virq) +{ + return 0; +} + +int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, + uint64_t address, uint32_t data, PCIDevice *d= ev) +{ + return 0; +} + +int kvm_arch_destroy_vcpu(CPUState *cs) +{ + return 0; +} + +unsigned long kvm_arch_vcpu_id(CPUState *cpu) +{ + return cpu->cpu_index; +} + +void kvm_arch_init_irq_routing(KVMState *s) +{ +} + +int kvm_arch_init_vcpu(CPUState *cs) +{ + return 0; +} + +int kvm_arch_msi_data_to_gsi(uint32_t data) +{ + abort(); +} + +int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, + int vector, PCIDevice *dev) +{ + return 0; +} + +int kvm_arch_init(MachineState *ms, KVMState *s) +{ + return 0; +} + +int kvm_arch_irqchip_create(KVMState *s) +{ + return 0; +} + +int kvm_arch_process_async_events(CPUState *cs) +{ + return 0; +} + +void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) +{ +} + +MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) +{ + return MEMTXATTRS_UNSPECIFIED; +} + +bool kvm_arch_stop_on_emulation_error(CPUState *cs) +{ + return true; +} + +int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) +{ + return 0; +} diff --git a/target/riscv/meson.build b/target/riscv/meson.build index abd647fea1..66d0dfd0c9 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -23,6 +23,7 @@ riscv_ss.add(files( 'vector_helper.c', 'translate.c', )) +riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) =20 riscv_softmmu_ss =3D ss.source_set() riscv_softmmu_ss.add(files( --=20 2.19.1 From nobody Mon Apr 29 12:29:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 27 Aug 2020 02:23:56 -0700 (PDT) Received: from localhost ([::1]:55062 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBE8P-0004MH-IC for importer@patchew.org; Thu, 27 Aug 2020 05:23:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56928) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBE7K-0002ej-HX; Thu, 27 Aug 2020 05:22:46 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:56312 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBE7I-0003FY-QF; Thu, 27 Aug 2020 05:22:46 -0400 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id BC985CB042D1FB3802F9; Thu, 27 Aug 2020 17:22:40 +0800 (CST) Received: from huawei.com (10.174.187.31) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.487.0; Thu, 27 Aug 2020 17:22:28 +0800 From: Yifei Jiang To: , Subject: [PATCH RFC v3 03/14] target/riscv: Implement function kvm_arch_init_vcpu Date: Thu, 27 Aug 2020 17:21:26 +0800 Message-ID: <20200827092137.479-4-jiangyifei@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20200827092137.479-1-jiangyifei@huawei.com> References: <20200827092137.479-1-jiangyifei@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.187.31] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Get isa info from kvm while kvm init. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/kvm.c | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 8c386d9acf..7983f43f3f 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -38,6 +38,18 @@ #include "qemu/log.h" #include "hw/loader.h" =20 +static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx) +{ + __u64 id =3D KVM_REG_RISCV | type | idx; + +#if defined(TARGET_RISCV32) + id |=3D KVM_REG_SIZE_U32; +#elif defined(TARGET_RISCV64) + id |=3D KVM_REG_SIZE_U64; +#endif + return id; +} + const KVMCapabilityInfo kvm_arch_required_capabilities[] =3D { KVM_CAP_LAST_INFO }; @@ -79,7 +91,19 @@ void kvm_arch_init_irq_routing(KVMState *s) =20 int kvm_arch_init_vcpu(CPUState *cs) { - return 0; + int ret =3D 0; + target_ulong isa; + RISCVCPU *cpu =3D RISCV_CPU(cs); + __u64 id; + + id =3D kvm_riscv_reg_id(KVM_REG_RISCV_CONFIG, KVM_REG_RISCV_CONFIG_REG= (isa)); + ret =3D kvm_get_one_reg(cs, id, &isa); + if (ret) { + return ret; + } + cpu->env.misa =3D isa; + + return ret; } =20 int kvm_arch_msi_data_to_gsi(uint32_t data) --=20 2.19.1 From nobody Mon Apr 29 12:29:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1598520350; cv=none; d=zohomail.com; s=zohoarc; b=VDIBSO/MVASI6OsU+NN08RlSSgzsS4A6wwzn/pKejRfC17ybsYw/ghJk3Kxb4xMIBupnrJiHAJre9rTA6s9ocx1jJ6cP3VbENHLrLIAitAHhrWqtFbqbHfB+rcyJo4WzOzFBHSCrPTcmKWgHZ1YKYN6DCwweXMHWYEeZJPT9MHU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598520350; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=rZOdB+ie6SG6Ft+9SR7PbacGNztr4hih+8nD/HDipRM=; b=Y2y7CL1NwbqgPMamlmQQPXPD+Yl/WR00pcl93HfDwaFkwtCb+pw7wvrZPeTbRw50SrgQxQIMhRcvL03cnbb4YoameMHkEKjOSwgqx3cdNiGvWcn/wjHVByPP5ocynrKHkiAggDJmLkrbrgJTa9Da/iMKC6KIpbByWY6KUHHUnfA= ARC-Authentication-Results: i=1; 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Thu, 27 Aug 2020 17:22:40 +0800 (CST) Received: from huawei.com (10.174.187.31) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.487.0; Thu, 27 Aug 2020 17:22:28 +0800 From: Yifei Jiang To: , Subject: [PATCH RFC v3 04/14] target/riscv: Implement kvm_arch_get_registers Date: Thu, 27 Aug 2020 17:21:27 +0800 Message-ID: <20200827092137.479-5-jiangyifei@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20200827092137.479-1-jiangyifei@huawei.com> References: <20200827092137.479-1-jiangyifei@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.187.31] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.35; envelope-from=jiangyifei@huawei.com; helo=huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/27 05:22:41 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: victor.zhangxiaofeng@huawei.com, sagark@eecs.berkeley.edu, kvm@vger.kernel.org, libvir-list@redhat.com, kbastian@mail.uni-paderborn.de, anup.patel@wdc.com, yinyipeng1@huawei.com, Alistair.Francis@wdc.com, Yifei Jiang , kvm-riscv@lists.infradead.org, palmer@dabbelt.com, dengkai1@huawei.com, wu.wubin@huawei.com, zhang.zhanghailiang@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Get GPR CSR and FP registers from kvm by KVM_GET_ONE_REG ioctl. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/kvm.c | 150 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 149 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 7983f43f3f..e91f505607 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -50,13 +50,161 @@ static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx) return id; } =20 +#define RISCV_CORE_REG(name) kvm_riscv_reg_id(KVM_REG_RISCV_CORE, \ + KVM_REG_RISCV_CORE_REG(name)) + +#define RISCV_CSR_REG(name) kvm_riscv_reg_id(KVM_REG_RISCV_CSR, \ + KVM_REG_RISCV_CSR_REG(name)) + +#define RISCV_FP_F_REG(idx) kvm_riscv_reg_id(KVM_REG_RISCV_FP_F, idx) + +#define RISCV_FP_D_REG(idx) kvm_riscv_reg_id(KVM_REG_RISCV_FP_D, idx) + +static int kvm_riscv_get_regs_core(CPUState *cs) +{ + int ret =3D 0; + int i; + target_ulong reg; + CPURISCVState *env =3D &RISCV_CPU(cs)->env; + + ret =3D kvm_get_one_reg(cs, RISCV_CORE_REG(regs.pc), ®); + if (ret) { + return ret; + } + env->pc =3D reg; + + for (i =3D 1; i < 32; i++) { + __u64 id =3D kvm_riscv_reg_id(KVM_REG_RISCV_CORE, i); + ret =3D kvm_get_one_reg(cs, id, ®); + if (ret) { + return ret; + } + env->gpr[i] =3D reg; + } + + return ret; +} + +static int kvm_riscv_get_regs_csr(CPUState *cs) +{ + int ret =3D 0; + target_ulong reg; + CPURISCVState *env =3D &RISCV_CPU(cs)->env; + + ret =3D kvm_get_one_reg(cs, RISCV_CSR_REG(sstatus), ®); + if (ret) { + return ret; + } + env->mstatus =3D reg; + + ret =3D kvm_get_one_reg(cs, RISCV_CSR_REG(sie), ®); + if (ret) { + return ret; + } + env->mie =3D reg; + + ret =3D kvm_get_one_reg(cs, RISCV_CSR_REG(stvec), ®); + if (ret) { + return ret; + } + env->stvec =3D reg; + + ret =3D kvm_get_one_reg(cs, RISCV_CSR_REG(sscratch), ®); + if (ret) { + return ret; + } + env->sscratch =3D reg; + + ret =3D kvm_get_one_reg(cs, RISCV_CSR_REG(sepc), ®); + if (ret) { + return ret; + } + env->sepc =3D reg; + + ret =3D kvm_get_one_reg(cs, RISCV_CSR_REG(scause), ®); + if (ret) { + return ret; + } + env->scause =3D reg; + + ret =3D kvm_get_one_reg(cs, RISCV_CSR_REG(stval), ®); + if (ret) { + return ret; + } + env->sbadaddr =3D reg; + + ret =3D kvm_get_one_reg(cs, RISCV_CSR_REG(sip), ®); + if (ret) { + return ret; + } + env->mip =3D reg; + + ret =3D kvm_get_one_reg(cs, RISCV_CSR_REG(satp), ®); + if (ret) { + return ret; + } + env->satp =3D reg; + + return ret; +} + +static int kvm_riscv_get_regs_fp(CPUState *cs) +{ + int ret =3D 0; + int i; + CPURISCVState *env =3D &RISCV_CPU(cs)->env; + + if (riscv_has_ext(env, RVD)) { + uint64_t reg; + for (i =3D 0; i < 32; i++) { + ret =3D kvm_get_one_reg(cs, RISCV_FP_D_REG(i), ®); + if (ret) { + return ret; + } + env->fpr[i] =3D reg; + } + return ret; + } + + if (riscv_has_ext(env, RVF)) { + uint32_t reg; + for (i =3D 0; i < 32; i++) { + ret =3D kvm_get_one_reg(cs, RISCV_FP_F_REG(i), ®); + if (ret) { + return ret; + } + env->fpr[i] =3D reg; + } + return ret; + } + + return ret; +} + const KVMCapabilityInfo kvm_arch_required_capabilities[] =3D { KVM_CAP_LAST_INFO }; =20 int kvm_arch_get_registers(CPUState *cs) { - return 0; + int ret =3D 0; + + ret =3D kvm_riscv_get_regs_core(cs); + if (ret) { + return ret; + } + + ret =3D kvm_riscv_get_regs_csr(cs); + if (ret) { + return ret; + } + + ret =3D kvm_riscv_get_regs_fp(cs); + if (ret) { + return ret; + } + + return ret; } =20 int kvm_arch_put_registers(CPUState *cs, int level) --=20 2.19.1 From nobody Mon Apr 29 12:29:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1598520351; cv=none; d=zohomail.com; s=zohoarc; b=Bf/CulFr4WV7Ez78kIvSgJ8mpzjQvBb3ql4COXR12C4HMy22kHTjN9DDxQSo/NppDdSC8uR5AKYw8qTdjgaYbmKiBjYuF7BvXmPyTEobPeR/44TofwgzcteyylGChi76dTF9HRJkDCiGy+Pud5u6oHaxBKInIO+xEa/KDpn3tdg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598520351; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Thu, 27 Aug 2020 05:22:47 -0400 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id AE79F31403EFD6C6DDBD; Thu, 27 Aug 2020 17:22:40 +0800 (CST) Received: from huawei.com (10.174.187.31) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.487.0; Thu, 27 Aug 2020 17:22:29 +0800 From: Yifei Jiang To: , Subject: [PATCH RFC v3 05/14] arget/riscv: Implement kvm_arch_put_registers Date: Thu, 27 Aug 2020 17:21:28 +0800 Message-ID: <20200827092137.479-6-jiangyifei@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20200827092137.479-1-jiangyifei@huawei.com> References: <20200827092137.479-1-jiangyifei@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.187.31] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Put GPR CSR and FP registers to kvm by KVM_SET_ONE_REG ioctl Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/kvm.c | 142 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 141 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index e91f505607..7afb4263e9 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -85,6 +85,31 @@ static int kvm_riscv_get_regs_core(CPUState *cs) return ret; } =20 +static int kvm_riscv_put_regs_core(CPUState *cs) +{ + int ret =3D 0; + int i; + target_ulong reg; + CPURISCVState *env =3D &RISCV_CPU(cs)->env; + + reg =3D env->pc; + ret =3D kvm_set_one_reg(cs, RISCV_CORE_REG(regs.pc), ®); + if (ret) { + return ret; + } + + for (i =3D 1; i < 32; i++) { + __u64 id =3D kvm_riscv_reg_id(KVM_REG_RISCV_CORE, i); + reg =3D env->gpr[i]; + ret =3D kvm_set_one_reg(cs, id, ®); + if (ret) { + return ret; + } + } + + return ret; +} + static int kvm_riscv_get_regs_csr(CPUState *cs) { int ret =3D 0; @@ -148,6 +173,70 @@ static int kvm_riscv_get_regs_csr(CPUState *cs) return ret; } =20 +static int kvm_riscv_put_regs_csr(CPUState *cs) +{ + int ret =3D 0; + target_ulong reg; + CPURISCVState *env =3D &RISCV_CPU(cs)->env; + + reg =3D env->mstatus; + ret =3D kvm_set_one_reg(cs, RISCV_CSR_REG(sstatus), ®); + if (ret) { + return ret; + } + + reg =3D env->mie; + ret =3D kvm_set_one_reg(cs, RISCV_CSR_REG(sie), ®); + if (ret) { + return ret; + } + + reg =3D env->stvec; + ret =3D kvm_set_one_reg(cs, RISCV_CSR_REG(stvec), ®); + if (ret) { + return ret; + } + + reg =3D env->sscratch; + ret =3D kvm_set_one_reg(cs, RISCV_CSR_REG(sscratch), ®); + if (ret) { + return ret; + } + + reg =3D env->sepc; + ret =3D kvm_set_one_reg(cs, RISCV_CSR_REG(sepc), ®); + if (ret) { + return ret; + } + + reg =3D env->scause; + ret =3D kvm_set_one_reg(cs, RISCV_CSR_REG(scause), ®); + if (ret) { + return ret; + } + + reg =3D env->sbadaddr; + ret =3D kvm_set_one_reg(cs, RISCV_CSR_REG(stval), ®); + if (ret) { + return ret; + } + + reg =3D env->mip; + ret =3D kvm_set_one_reg(cs, RISCV_CSR_REG(sip), ®); + if (ret) { + return ret; + } + + reg =3D env->satp; + ret =3D kvm_set_one_reg(cs, RISCV_CSR_REG(satp), ®); + if (ret) { + return ret; + } + + return ret; +} + + static int kvm_riscv_get_regs_fp(CPUState *cs) { int ret =3D 0; @@ -181,6 +270,40 @@ static int kvm_riscv_get_regs_fp(CPUState *cs) return ret; } =20 +static int kvm_riscv_put_regs_fp(CPUState *cs) +{ + int ret =3D 0; + int i; + CPURISCVState *env =3D &RISCV_CPU(cs)->env; + + if (riscv_has_ext(env, RVD)) { + uint64_t reg; + for (i =3D 0; i < 32; i++) { + reg =3D env->fpr[i]; + ret =3D kvm_set_one_reg(cs, RISCV_FP_D_REG(i), ®); + if (ret) { + return ret; + } + } + return ret; + } + + if (riscv_has_ext(env, RVF)) { + uint32_t reg; + for (i =3D 0; i < 32; i++) { + reg =3D env->fpr[i]; + ret =3D kvm_set_one_reg(cs, RISCV_FP_F_REG(i), ®); + if (ret) { + return ret; + } + } + return ret; + } + + return ret; +} + + const KVMCapabilityInfo kvm_arch_required_capabilities[] =3D { KVM_CAP_LAST_INFO }; @@ -209,7 +332,24 @@ int kvm_arch_get_registers(CPUState *cs) =20 int kvm_arch_put_registers(CPUState *cs, int level) { - return 0; + int ret =3D 0; + + ret =3D kvm_riscv_put_regs_core(cs); + if (ret) { + return ret; + } + + ret =3D kvm_riscv_put_regs_csr(cs); + if (ret) { + return ret; + } + + ret =3D kvm_riscv_put_regs_fp(cs); + if (ret) { + return ret; + } + + return ret; } =20 int kvm_arch_release_virq_post(int virq) --=20 2.19.1 From nobody Mon Apr 29 12:29:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1598520240; cv=none; d=zohomail.com; s=zohoarc; b=cl6OGkeGTk8MwXkEIn0aUL1FNisv33mnH3HEqmsv1OqOigDgGQDqC7diUfTAiheCnt4a0mHGWSD+oLDnpS7oWX6XnqCHSiMQnVx2V7lu1DwxB7rQVzL0e6uLR/9BCc7S+jEJIBV1ixsVmnXr1hy/k3k14yyNPEg5okSXQgM9GeE= ARC-Message-Signature: i=1; a=rsa-sha256; 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Thu, 27 Aug 2020 05:23:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56994) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBE7M-0002fZ-AD; Thu, 27 Aug 2020 05:22:48 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:56348 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBE7I-0003FZ-TX; Thu, 27 Aug 2020 05:22:48 -0400 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id B558FEA7BFE0E03DBA3A; Thu, 27 Aug 2020 17:22:40 +0800 (CST) Received: from huawei.com (10.174.187.31) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.487.0; Thu, 27 Aug 2020 17:22:30 +0800 From: Yifei Jiang To: , Subject: [PATCH RFC v3 06/14] target/riscv: Support start kernel directly by KVM Date: Thu, 27 Aug 2020 17:21:29 +0800 Message-ID: <20200827092137.479-7-jiangyifei@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20200827092137.479-1-jiangyifei@huawei.com> References: <20200827092137.479-1-jiangyifei@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.187.31] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.35; envelope-from=jiangyifei@huawei.com; helo=huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/27 05:22:41 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: victor.zhangxiaofeng@huawei.com, sagark@eecs.berkeley.edu, kvm@vger.kernel.org, libvir-list@redhat.com, kbastian@mail.uni-paderborn.de, anup.patel@wdc.com, yinyipeng1@huawei.com, Alistair.Francis@wdc.com, Yifei Jiang , kvm-riscv@lists.infradead.org, palmer@dabbelt.com, dengkai1@huawei.com, wu.wubin@huawei.com, zhang.zhanghailiang@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Get kernel and fdt start address in virt.c, and pass them to KVM when cpu reset. In addition, add kvm_riscv.h to place riscv specific interface. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- hw/riscv/virt.c | 8 ++++++++ target/riscv/cpu.c | 4 ++++ target/riscv/cpu.h | 3 +++ target/riscv/kvm.c | 14 ++++++++++++++ target/riscv/kvm_riscv.h | 24 ++++++++++++++++++++++++ 5 files changed, 53 insertions(+) create mode 100644 target/riscv/kvm_riscv.h diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 6e91cf129e..e3336522bf 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -41,6 +41,7 @@ #include "sysemu/sysemu.h" #include "hw/pci/pci.h" #include "hw/pci-host/gpex.h" +#include "sysemu/kvm.h" =20 #if defined(TARGET_RISCV32) # define BIOS_FILENAME "opensbi-riscv32-generic-fw_dynamic.bin" @@ -482,6 +483,7 @@ static void virt_machine_init(MachineState *machine) uint64_t kernel_entry; int i; unsigned int smp_cpus =3D machine->smp.cpus; + CPUState *cs; =20 /* Initialize SOC */ object_initialize_child(OBJECT(machine), "soc", &s->soc, @@ -547,6 +549,12 @@ static void virt_machine_init(MachineState *machine) virt_memmap[VIRT_MROM].size, kernel_entry, fdt_load_addr, s->fdt); =20 + for (cs =3D first_cpu; cs; cs =3D CPU_NEXT(cs)) { + RISCVCPU *riscv_cpu =3D RISCV_CPU(cs); + riscv_cpu->env.kernel_addr =3D kernel_entry; + riscv_cpu->env.fdt_addr =3D fdt_load_addr; + } + /* create PLIC hart topology configuration string */ plic_hart_config_len =3D (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpu= s; plic_hart_config =3D g_malloc0(plic_hart_config_len); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 228b9bdb5d..266e70cc47 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -28,6 +28,7 @@ #include "hw/qdev-properties.h" #include "migration/vmstate.h" #include "fpu/softfloat-helpers.h" +#include "kvm_riscv.h" =20 /* RISC-V CPU definitions */ =20 @@ -321,6 +322,9 @@ static void riscv_cpu_reset(DeviceState *dev) cs->exception_index =3D EXCP_NONE; env->load_res =3D -1; set_default_nan_mode(1, &env->fp_status); +#ifdef CONFIG_KVM + kvm_riscv_reset_vcpu(cpu); +#endif } =20 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a804a5d0ba..d4cafe37e1 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -229,6 +229,9 @@ struct CPURISCVState { =20 /* Fields from here on are preserved across CPU reset. */ QEMUTimer *timer; /* Internal timer */ + + hwaddr kernel_addr; + hwaddr fdt_addr; }; =20 #define RISCV_CPU_CLASS(klass) \ diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 7afb4263e9..69217add16 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -37,6 +37,7 @@ #include "hw/irq.h" #include "qemu/log.h" #include "hw/loader.h" +#include "kvm_riscv.h" =20 static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx) { @@ -438,3 +439,16 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run = *run) { return 0; } + +void kvm_riscv_reset_vcpu(RISCVCPU *cpu) +{ + CPURISCVState *env =3D &cpu->env; + + if (!kvm_enabled()) { + return; + } + env->pc =3D cpu->env.kernel_addr; + env->gpr[10] =3D kvm_arch_vcpu_id(CPU(cpu)); /* a0 */ + env->gpr[11] =3D cpu->env.fdt_addr; /* a1 */ +} + diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h new file mode 100644 index 0000000000..f38c82bf59 --- /dev/null +++ b/target/riscv/kvm_riscv.h @@ -0,0 +1,24 @@ +/* + * QEMU KVM support -- RISC-V specific functions. + * + * Copyright (c) 2020 Huawei Technologies Co., Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef QEMU_KVM_RISCV_H +#define QEMU_KVM_RISCV_H + +void kvm_riscv_reset_vcpu(RISCVCPU *cpu); + +#endif --=20 2.19.1 From nobody Mon Apr 29 12:29:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1598520436; cv=none; d=zohomail.com; s=zohoarc; b=g1SY+TkTwiugnwJYWUhqS1/Qu9vVpo9inbBJZ1Z5ahkJ0JpLIy3ZiO3DKXvgrhx0ogez/4AGAw0TQ6MykKydz2Huw2NRLKqUSxQ2kN13Rgxi6G1SVSvPA3GXN4Y8UrAtWjTUPg5GRjcg1jY0Wx7lKP0gU/x1TUpgxA3kH1kLXe8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598520436; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=mRdRCp0940lIUJ0w9zFw7DntoWN9xm1eHIL40kNEz+8=; b=dza+z4FZCs38V7iK0mmPLBdDEoq9MtnwycH22d2io8ZBs7bKyUvdXqd754nFUChrZnI7vvU7t6fMe5+Imj2+E65hLDSAvORI4eL33vFetAP0iaAC9Tg1Qq3mqwSypq+or6UGQITzF3f22wQVm3zeOiGUHGHPn+hFzthg5gib2GM= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15985204366731001.5666730046054; Thu, 27 Aug 2020 02:27:16 -0700 (PDT) Received: from localhost ([::1]:44218 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBEBf-0002xz-C9 for importer@patchew.org; Thu, 27 Aug 2020 05:27:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56986) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBE7M-0002fF-30; Thu, 27 Aug 2020 05:22:48 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:56304 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBE7I-0003FX-Td; Thu, 27 Aug 2020 05:22:47 -0400 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id A7D9F68216606540F837; Thu, 27 Aug 2020 17:22:40 +0800 (CST) Received: from huawei.com (10.174.187.31) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.487.0; Thu, 27 Aug 2020 17:22:31 +0800 From: Yifei Jiang To: , Subject: [PATCH RFC v3 07/14] hw/riscv: PLIC update external interrupt by KVM when kvm enabled Date: Thu, 27 Aug 2020 17:21:30 +0800 Message-ID: <20200827092137.479-8-jiangyifei@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20200827092137.479-1-jiangyifei@huawei.com> References: <20200827092137.479-1-jiangyifei@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.187.31] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.35; envelope-from=jiangyifei@huawei.com; helo=huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/27 05:22:41 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: victor.zhangxiaofeng@huawei.com, sagark@eecs.berkeley.edu, kvm@vger.kernel.org, libvir-list@redhat.com, kbastian@mail.uni-paderborn.de, anup.patel@wdc.com, yinyipeng1@huawei.com, Alistair.Francis@wdc.com, Yifei Jiang , kvm-riscv@lists.infradead.org, palmer@dabbelt.com, dengkai1@huawei.com, wu.wubin@huawei.com, zhang.zhanghailiang@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Only support supervisor external interrupt currently. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- hw/riscv/sifive_plic.c | 31 ++++++++++++++++++++++--------- target/riscv/kvm.c | 19 +++++++++++++++++++ target/riscv/kvm_riscv.h | 1 + 3 files changed, 42 insertions(+), 9 deletions(-) diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c index c20c192034..9c5a131e0f 100644 --- a/hw/riscv/sifive_plic.c +++ b/hw/riscv/sifive_plic.c @@ -30,6 +30,8 @@ #include "target/riscv/cpu.h" #include "sysemu/sysemu.h" #include "hw/riscv/sifive_plic.h" +#include "sysemu/kvm.h" +#include "kvm_riscv.h" =20 #define RISCV_DEBUG_PLIC 0 =20 @@ -146,15 +148,26 @@ static void sifive_plic_update(SiFivePLICState *plic) continue; } int level =3D sifive_plic_irqs_pending(plic, addrid); - switch (mode) { - case PLICMode_M: - riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP, BOOL_TO_MASK(le= vel)); - break; - case PLICMode_S: - riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP, BOOL_TO_MASK(le= vel)); - break; - default: - break; + if (kvm_enabled()) { + if (mode =3D=3D PLICMode_M) { + continue; + } +#ifdef CONFIG_KVM + kvm_riscv_set_irq(RISCV_CPU(cpu), IRQ_S_EXT, level); +#endif + } else { + switch (mode) { + case PLICMode_M: + riscv_cpu_update_mip(RISCV_CPU(cpu), + MIP_MEIP, BOOL_TO_MASK(level)); + break; + case PLICMode_S: + riscv_cpu_update_mip(RISCV_CPU(cpu), + MIP_SEIP, BOOL_TO_MASK(level)); + break; + default: + break; + } } } =20 diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 69217add16..d510d23da1 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -452,3 +452,22 @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu) env->gpr[11] =3D cpu->env.fdt_addr; /* a1 */ } =20 +void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) +{ + int ret; + unsigned virq =3D level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET; + + if (irq !=3D IRQ_S_EXT) { + return; + } + + if (!kvm_enabled()) { + return; + } + + ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); + if (ret < 0) { + perror("Set irq failed"); + abort(); + } +} diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h index f38c82bf59..ed281bdce0 100644 --- a/target/riscv/kvm_riscv.h +++ b/target/riscv/kvm_riscv.h @@ -20,5 +20,6 @@ #define QEMU_KVM_RISCV_H =20 void kvm_riscv_reset_vcpu(RISCVCPU *cpu); +void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level); =20 #endif --=20 2.19.1 From nobody Mon Apr 29 12:29:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1598520631; cv=none; d=zohomail.com; s=zohoarc; b=ETeyt/HUqCp8UsduLGZkZdVC9BMvlIla8FibDx0YfxmYwlcBll6lTi5mDaiyZdIUTpWTaF//KcKsfep3WuE4zPBZBvNskj8RHdNv2309g5tt59P3Nugdvad1UrcQLu/fVHRarTq+oJpmtqiq9ZzDiR+P+RHpvV/XOPl5tTnR+xo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598520631; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HIeZNSuqwpRepXB7ILpLSimzK8ey2g/sz7Ylo1hL3CM=; b=Pb7nhcVlulTD7lvUTxmwUnf+Poe7Pt+3CRHSF/j32e2jAOWP7VHZaY0PLxL7iMV06CYqRWY+/6VIaN6tVyCk3pqJdzQ1fMvDr24PU0BMv0SPuD7feaWSzO+4HArLSYyLP6PXRjMIIhjPmh4bfXKtVLLiiIjfhlCb3E3p5eJmCtY= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598520631808596.5181157882056; Thu, 27 Aug 2020 02:30:31 -0700 (PDT) Received: from localhost ([::1]:58412 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kBEEo-0000El-Hi for importer@patchew.org; Thu, 27 Aug 2020 05:30:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57066) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBE7P-0002nW-79; Thu, 27 Aug 2020 05:22:51 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:34552 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBE7L-0003GB-LB; Thu, 27 Aug 2020 05:22:50 -0400 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 0A16A5BD47C6198FEF0F; Thu, 27 Aug 2020 17:22:43 +0800 (CST) Received: from huawei.com (10.174.187.31) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.487.0; Thu, 27 Aug 2020 17:22:32 +0800 From: Yifei Jiang To: , Subject: [PATCH RFC v3 08/14] target/riscv: Handler KVM_EXIT_RISCV_SBI exit Date: Thu, 27 Aug 2020 17:21:31 +0800 Message-ID: <20200827092137.479-9-jiangyifei@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20200827092137.479-1-jiangyifei@huawei.com> References: <20200827092137.479-1-jiangyifei@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.187.31] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.32; envelope-from=jiangyifei@huawei.com; helo=huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/27 02:28:14 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: victor.zhangxiaofeng@huawei.com, sagark@eecs.berkeley.edu, kvm@vger.kernel.org, libvir-list@redhat.com, kbastian@mail.uni-paderborn.de, anup.patel@wdc.com, yinyipeng1@huawei.com, Alistair.Francis@wdc.com, Yifei Jiang , kvm-riscv@lists.infradead.org, palmer@dabbelt.com, dengkai1@huawei.com, wu.wubin@huawei.com, zhang.zhanghailiang@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Use char-fe handler console sbi call, which implement early console io while apply 'earlycon=3Dsbi' into kernel parameters. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/kvm.c | 42 ++++++++++++++++- target/riscv/sbi_ecall_interface.h | 72 ++++++++++++++++++++++++++++++ 2 files changed, 113 insertions(+), 1 deletion(-) create mode 100644 target/riscv/sbi_ecall_interface.h diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index d510d23da1..b49df6dd9c 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -38,6 +38,8 @@ #include "qemu/log.h" #include "hw/loader.h" #include "kvm_riscv.h" +#include "sbi_ecall_interface.h" +#include "chardev/char-fe.h" =20 static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx) { @@ -435,9 +437,47 @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs) return true; } =20 +static int kvm_riscv_handle_sbi(struct kvm_run *run) +{ + int ret =3D 0; + unsigned char ch; + switch (run->riscv_sbi.extension_id) { + case SBI_EXT_0_1_CONSOLE_PUTCHAR: + ch =3D run->riscv_sbi.args[0]; + qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch)); + break; + case SBI_EXT_0_1_CONSOLE_GETCHAR: + ret =3D qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch)); + if (ret =3D=3D sizeof(ch)) { + run->riscv_sbi.args[0] =3D ch; + } else { + run->riscv_sbi.args[0] =3D -1; + } + break; + default: + qemu_log_mask(LOG_UNIMP, + "%s: un-handled SBI EXIT, specific reasons is %lu\n", + __func__, run->riscv_sbi.extension_id); + ret =3D -1; + break; + } + return ret; +} + int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) { - return 0; + int ret =3D 0; + switch (run->exit_reason) { + case KVM_EXIT_RISCV_SBI: + ret =3D kvm_riscv_handle_sbi(run); + break; + default: + qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n", + __func__, run->exit_reason); + ret =3D -1; + break; + } + return ret; } =20 void kvm_riscv_reset_vcpu(RISCVCPU *cpu) diff --git a/target/riscv/sbi_ecall_interface.h b/target/riscv/sbi_ecall_in= terface.h new file mode 100644 index 0000000000..fb1a3fa8f2 --- /dev/null +++ b/target/riscv/sbi_ecall_interface.h @@ -0,0 +1,72 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Anup Patel + */ + +#ifndef __SBI_ECALL_INTERFACE_H__ +#define __SBI_ECALL_INTERFACE_H__ + +/* clang-format off */ + +/* SBI Extension IDs */ +#define SBI_EXT_0_1_SET_TIMER 0x0 +#define SBI_EXT_0_1_CONSOLE_PUTCHAR 0x1 +#define SBI_EXT_0_1_CONSOLE_GETCHAR 0x2 +#define SBI_EXT_0_1_CLEAR_IPI 0x3 +#define SBI_EXT_0_1_SEND_IPI 0x4 +#define SBI_EXT_0_1_REMOTE_FENCE_I 0x5 +#define SBI_EXT_0_1_REMOTE_SFENCE_VMA 0x6 +#define SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID 0x7 +#define SBI_EXT_0_1_SHUTDOWN 0x8 +#define SBI_EXT_BASE 0x10 +#define SBI_EXT_TIME 0x54494D45 +#define SBI_EXT_IPI 0x735049 +#define SBI_EXT_RFENCE 0x52464E43 +#define SBI_EXT_HSM 0x48534D + +/* SBI function IDs for BASE extension*/ +#define SBI_EXT_BASE_GET_SPEC_VERSION 0x0 +#define SBI_EXT_BASE_GET_IMP_ID 0x1 +#define SBI_EXT_BASE_GET_IMP_VERSION 0x2 +#define SBI_EXT_BASE_PROBE_EXT 0x3 +#define SBI_EXT_BASE_GET_MVENDORID 0x4 +#define SBI_EXT_BASE_GET_MARCHID 0x5 +#define SBI_EXT_BASE_GET_MIMPID 0x6 + +/* SBI function IDs for TIME extension*/ +#define SBI_EXT_TIME_SET_TIMER 0x0 + +/* SBI function IDs for IPI extension*/ +#define SBI_EXT_IPI_SEND_IPI 0x0 + +/* SBI function IDs for RFENCE extension*/ +#define SBI_EXT_RFENCE_REMOTE_FENCE_I 0x0 +#define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA 0x1 +#define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID 0x2 +#define SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA 0x3 +#define SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID 0x4 +#define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA 0x5 +#define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID 0x6 + +/* SBI function IDs for HSM extension */ +#define SBI_EXT_HSM_HART_START 0x0 +#define SBI_EXT_HSM_HART_STOP 0x1 +#define SBI_EXT_HSM_HART_GET_STATUS 0x2 + +#define SBI_HSM_HART_STATUS_STARTED 0x0 +#define SBI_HSM_HART_STATUS_STOPPED 0x1 +#define SBI_HSM_HART_STATUS_START_PENDING 0x2 +#define SBI_HSM_HART_STATUS_STOP_PENDING 0x3 + +#define SBI_SPEC_VERSION_MAJOR_OFFSET 24 +#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f +#define SBI_SPEC_VERSION_MINOR_MASK 0xffffff +#define SBI_EXT_VENDOR_START 0x09000000 +#define SBI_EXT_VENDOR_END 0x09FFFFFF +/* clang-format on */ + +#endif --=20 2.19.1 From nobody Mon Apr 29 12:29:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Currently, host cpu is inherited simply. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/cpu.c | 6 ++++++ target/riscv/cpu.h | 1 + 2 files changed, 7 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 266e70cc47..d8c32a8f84 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -179,6 +179,10 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) =20 #endif =20 +static void riscv_host_cpu_init(Object *obj) +{ +} + static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) { ObjectClass *oc; @@ -635,10 +639,12 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rvxx_sifive_e_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init= ), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rvxx_sifive_u_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), #elif defined(TARGET_RISCV64) DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rvxx_sifive_e_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rvxx_sifive_u_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), #endif }; =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d4cafe37e1..7795e7ae13 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -42,6 +42,7 @@ #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") +#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") =20 #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) --=20 2.19.1 From nobody Mon Apr 29 12:29:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1598520438; cv=none; d=zohomail.com; s=zohoarc; b=lkYL2WVrENEmDnsK01tWj9QrqOxluN+RnszOCT9P0cbi8S7syirK9wyXBabLEjAbxkdhKlCtBPNXj72AZmlUYZJXanFXyQb2x4wNAhPqgkfYV9RLpRJdsdywL+oBC1UOoHylvF9/hZWi6GxpjKgjolZne1mmsny+a3QDOuKj1yM= ARC-Message-Signature: i=1; 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Thu, 27 Aug 2020 05:27:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57052) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBE7O-0002m0-Qm; Thu, 27 Aug 2020 05:22:50 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:4658 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kBE7L-0003G6-C9; Thu, 27 Aug 2020 05:22:50 -0400 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id B6E1D77AE83A698E6BD4; Thu, 27 Aug 2020 17:22:42 +0800 (CST) Received: from huawei.com (10.174.187.31) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.487.0; Thu, 27 Aug 2020 17:22:33 +0800 From: Yifei Jiang To: , Subject: [PATCH RFC v3 10/14] target/riscv: Add sifive_plic vmstate Date: Thu, 27 Aug 2020 17:21:33 +0800 Message-ID: <20200827092137.479-11-jiangyifei@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20200827092137.479-1-jiangyifei@huawei.com> References: <20200827092137.479-1-jiangyifei@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.187.31] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Add sifive_plic vmstate for supporting sifive_plic migration. Current vmstate framework only supports one structure parameter as num field to describe variable length arrays, so introduce num_enables. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- hw/riscv/sifive_plic.c | 24 +++++++++++++++++++++++- include/hw/riscv/sifive_plic.h | 1 + 2 files changed, 24 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c index 9c5a131e0f..897dc289a0 100644 --- a/hw/riscv/sifive_plic.c +++ b/hw/riscv/sifive_plic.c @@ -32,6 +32,7 @@ #include "hw/riscv/sifive_plic.h" #include "sysemu/kvm.h" #include "kvm_riscv.h" +#include "migration/vmstate.h" =20 #define RISCV_DEBUG_PLIC 0 =20 @@ -460,11 +461,12 @@ static void sifive_plic_realize(DeviceState *dev, Err= or **errp) TYPE_SIFIVE_PLIC, plic->aperture_size); parse_hart_config(plic); plic->bitfield_words =3D (plic->num_sources + 31) >> 5; + plic->num_enables =3D plic->bitfield_words * plic->num_addrs; plic->source_priority =3D g_new0(uint32_t, plic->num_sources); plic->target_priority =3D g_new(uint32_t, plic->num_addrs); plic->pending =3D g_new0(uint32_t, plic->bitfield_words); plic->claimed =3D g_new0(uint32_t, plic->bitfield_words); - plic->enable =3D g_new0(uint32_t, plic->bitfield_words * plic->num_add= rs); + plic->enable =3D g_new0(uint32_t, plic->num_enables); sysbus_init_mmio(SYS_BUS_DEVICE(dev), &plic->mmio); qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources); =20 @@ -484,12 +486,32 @@ static void sifive_plic_realize(DeviceState *dev, Err= or **errp) msi_nonbroken =3D true; } =20 +static const VMStateDescription vmstate_sifive_plic =3D { + .name =3D "riscv_sifive_plic", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_VARRAY_UINT32(source_priority, SiFivePLICState, num_so= urces, 0, + vmstate_info_uint32, uint32_t), + VMSTATE_VARRAY_UINT32(target_priority, SiFivePLICState, num_ad= drs, 0, + vmstate_info_uint32, uint32_t), + VMSTATE_VARRAY_UINT32(pending, SiFivePLICState, bitfield_words= , 0, + vmstate_info_uint32, uint32_t), + VMSTATE_VARRAY_UINT32(claimed, SiFivePLICState, bitfield_words= , 0, + vmstate_info_uint32, uint32_t), + VMSTATE_VARRAY_UINT32(enable, SiFivePLICState, num_enables, 0, + vmstate_info_uint32, uint32_t), + VMSTATE_END_OF_LIST() + } +}; + static void sifive_plic_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 device_class_set_props(dc, sifive_plic_properties); dc->realize =3D sifive_plic_realize; + dc->vmsd =3D &vmstate_sifive_plic; } =20 static const TypeInfo sifive_plic_info =3D { diff --git a/include/hw/riscv/sifive_plic.h b/include/hw/riscv/sifive_plic.h index 4421e81249..130df0cf1c 100644 --- a/include/hw/riscv/sifive_plic.h +++ b/include/hw/riscv/sifive_plic.h @@ -49,6 +49,7 @@ typedef struct SiFivePLICState { MemoryRegion mmio; uint32_t num_addrs; uint32_t bitfield_words; + uint32_t num_enables; PLICAddr *addr_config; uint32_t *source_priority; uint32_t *target_priority; --=20 2.19.1 From nobody Mon Apr 29 12:29:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; 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charset="utf-8" Describe gpr, fpr and csr in vmstate_riscv_cpu. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/cpu.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d8c32a8f84..b698f4adbb 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -26,7 +26,7 @@ #include "qapi/error.h" #include "qemu/error-report.h" #include "hw/qdev-properties.h" -#include "migration/vmstate.h" +#include "migration/cpu.h" #include "fpu/softfloat-helpers.h" #include "kvm_riscv.h" =20 @@ -499,7 +499,23 @@ static void riscv_cpu_init(Object *obj) #ifndef CONFIG_USER_ONLY static const VMStateDescription vmstate_riscv_cpu =3D { .name =3D "cpu", - .unmigratable =3D 1, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), + VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32), + VMSTATE_UINTTL(env.pc, RISCVCPU), + VMSTATE_UINTTL(env.mstatus, RISCVCPU), + VMSTATE_UINTTL(env.mie, RISCVCPU), + VMSTATE_UINTTL(env.stvec, RISCVCPU), + VMSTATE_UINTTL(env.sscratch, RISCVCPU), + VMSTATE_UINTTL(env.sepc, RISCVCPU), + VMSTATE_UINTTL(env.scause, RISCVCPU), + VMSTATE_UINTTL(env.sbadaddr, RISCVCPU), + VMSTATE_UINTTL(env.mip, RISCVCPU), + VMSTATE_UINTTL(env.satp, RISCVCPU), + VMSTATE_END_OF_LIST() + } }; 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Thu, 27 Aug 2020 17:22:42 +0800 (CST) Received: from huawei.com (10.174.187.31) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.487.0; Thu, 27 Aug 2020 17:22:35 +0800 From: Yifei Jiang To: , Subject: [PATCH RFC v3 12/14] target/riscv: Add kvm_riscv_get/put_regs_timer Date: Thu, 27 Aug 2020 17:21:35 +0800 Message-ID: <20200827092137.479-13-jiangyifei@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20200827092137.479-1-jiangyifei@huawei.com> References: <20200827092137.479-1-jiangyifei@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.187.31] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.32; envelope-from=jiangyifei@huawei.com; helo=huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/27 02:28:14 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: victor.zhangxiaofeng@huawei.com, sagark@eecs.berkeley.edu, kvm@vger.kernel.org, libvir-list@redhat.com, kbastian@mail.uni-paderborn.de, anup.patel@wdc.com, yinyipeng1@huawei.com, Alistair.Francis@wdc.com, Yifei Jiang , kvm-riscv@lists.infradead.org, palmer@dabbelt.com, dengkai1@huawei.com, wu.wubin@huawei.com, zhang.zhanghailiang@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Add kvm_riscv_get/put_regs_timer to synchronize virtual time context from KVM. The frequency of virtual time is not supported by KVM_SET_ONE_REG, So it's useless to synchronize the frequency of virtual time. To set register of RISCV_TIMER_REG(state) will occur a error from KVM on kvm_timer_state =3D=3D 0. It's better to adapt in KVM, but it doesn't ma= tter that adaping in QEMU. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/cpu.h | 6 ++++ target/riscv/kvm.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 78 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7795e7ae13..b735258f27 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -233,6 +233,12 @@ struct CPURISCVState { =20 hwaddr kernel_addr; hwaddr fdt_addr; + + /* kvm timer */ + bool kvm_timer_dirty; + uint64_t kvm_timer_time; + uint64_t kvm_timer_compare; + uint64_t kvm_timer_state; }; =20 #define RISCV_CPU_CLASS(klass) \ diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index b49df6dd9c..59c537b1cb 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -59,6 +59,9 @@ static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx) #define RISCV_CSR_REG(name) kvm_riscv_reg_id(KVM_REG_RISCV_CSR, \ KVM_REG_RISCV_CSR_REG(name)) =20 +#define RISCV_TIMER_REG(name) kvm_riscv_reg_id(KVM_REG_RISCV_TIMER, \ + KVM_REG_RISCV_TIMER_REG(name)) + #define RISCV_FP_F_REG(idx) kvm_riscv_reg_id(KVM_REG_RISCV_FP_F, idx) =20 #define RISCV_FP_D_REG(idx) kvm_riscv_reg_id(KVM_REG_RISCV_FP_D, idx) @@ -306,6 +309,75 @@ static int kvm_riscv_put_regs_fp(CPUState *cs) return ret; } =20 +static void kvm_riscv_get_regs_timer(CPUState *cs) +{ + int ret; + uint64_t reg; + CPURISCVState *env =3D &RISCV_CPU(cs)->env; + + if (env->kvm_timer_dirty) { + return; + } + + ret =3D kvm_get_one_reg(cs, RISCV_TIMER_REG(time), ®); + if (ret) { + abort(); + } + env->kvm_timer_time =3D reg; + + ret =3D kvm_get_one_reg(cs, RISCV_TIMER_REG(compare), ®); + if (ret) { + abort(); + } + env->kvm_timer_compare =3D reg; + + ret =3D kvm_get_one_reg(cs, RISCV_TIMER_REG(state), ®); + if (ret) { + abort(); + } + env->kvm_timer_state =3D reg; + + env->kvm_timer_dirty =3D true; +} + +static void kvm_riscv_put_regs_timer(CPUState *cs) +{ + int ret; + uint64_t reg; + CPURISCVState *env =3D &RISCV_CPU(cs)->env; + + if (!env->kvm_timer_dirty) { + return; + } + + reg =3D env->kvm_timer_time; + ret =3D kvm_set_one_reg(cs, RISCV_TIMER_REG(time), ®); + if (ret) { + abort(); + } + + reg =3D env->kvm_timer_compare; + ret =3D kvm_set_one_reg(cs, RISCV_TIMER_REG(compare), ®); + if (ret) { + abort(); + } + + /* + * To set register of RISCV_TIMER_REG(state) will occur a error from K= VM + * on env->kvm_timer_state =3D=3D 0, It's better to adapt in KVM, but = it + * doesn't matter that adaping in QEMU now. + * TODO If KVM changes, adapt here. + */ + if (env->kvm_timer_state) { + reg =3D env->kvm_timer_state; + ret =3D kvm_set_one_reg(cs, RISCV_TIMER_REG(state), ®); + if (ret) { + abort(); + } + } + + env->kvm_timer_dirty =3D false; +} =20 const KVMCapabilityInfo kvm_arch_required_capabilities[] =3D { KVM_CAP_LAST_INFO --=20 2.19.1 From nobody Mon Apr 29 12:29:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1598520354; cv=none; d=zohomail.com; s=zohoarc; b=D/YKvIowzbp1PgfMfnZoqPPT5xRcETGpcioWSl8jZTxi8RM1tWMjsIYhe4D4BcbiNiBbbETbpUK+/alEstOjLWSlluDnff/KAY1s/Jkj/UkuVLMHamZ3+9Gi1eDJnrG2xpIJ0JTnv2eONHwku9dDCzNp60rhoSpdgpIVvcnc/xk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598520354; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Thu, 27 Aug 2020 05:22:50 -0400 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id A2193869D6D927573166; Thu, 27 Aug 2020 17:22:42 +0800 (CST) Received: from huawei.com (10.174.187.31) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.487.0; Thu, 27 Aug 2020 17:22:35 +0800 From: Yifei Jiang To: , Subject: [PATCH RFC v3 13/14] target/riscv: Implement virtual time adjusting with vm state changing Date: Thu, 27 Aug 2020 17:21:36 +0800 Message-ID: <20200827092137.479-14-jiangyifei@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20200827092137.479-1-jiangyifei@huawei.com> References: <20200827092137.479-1-jiangyifei@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.187.31] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" We hope that virtual time adjusts with vm state changing. When a vm is stopped, guest virtual time should stop counting and kvm_timer should be stopped. When the vm is resumed, guest virtual time should continue to count and kvm_timer should be restored. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/kvm.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 59c537b1cb..943d733539 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -40,6 +40,7 @@ #include "kvm_riscv.h" #include "sbi_ecall_interface.h" #include "chardev/char-fe.h" +#include "sysemu/runstate.h" =20 static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx) { @@ -448,6 +449,17 @@ unsigned long kvm_arch_vcpu_id(CPUState *cpu) return cpu->cpu_index; } =20 +static void kvm_riscv_vm_state_change(void *opaque, int running, RunState = state) +{ + CPUState *cs =3D opaque; + + if (running) { + kvm_riscv_put_regs_timer(cs); + } else { + kvm_riscv_get_regs_timer(cs); + } +} + void kvm_arch_init_irq_routing(KVMState *s) { } @@ -459,6 +471,8 @@ int kvm_arch_init_vcpu(CPUState *cs) RISCVCPU *cpu =3D RISCV_CPU(cs); __u64 id; =20 + qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change, cs); + id =3D kvm_riscv_reg_id(KVM_REG_RISCV_CONFIG, KVM_REG_RISCV_CONFIG_REG= (isa)); ret =3D kvm_get_one_reg(cs, id, &isa); if (ret) { --=20 2.19.1 From nobody Mon Apr 29 12:29:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1598520353; cv=none; d=zohomail.com; s=zohoarc; b=ax8avTFdK+Ssom1QJlCCAWGdOwbB0x7XZudXh9aORieiyGa1Wy1pd6tgUcK7WR7EgKBIni1ZmyuSaYYg0hMV1pOmYsb0oTlvdD3LnMBDci5J2UpFh1DyRTA+yzRB9mCmZ3eZ00ZR+lIW2MA7jEeEnPYLchI6qXeIlTnTb00U614= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598520353; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Dz48i5FcJJnN4GBtYkDubwWMpvCGY97WptXG8Na/9oM=; b=EQ/qhA2XL0dxAElBKjl5BmOmKPEExesCk06CnqEz0kPgTdFYGSyt33WPvfxbj/k2XnR1CcjvU/I68NLgp5W1/0bBO/vuWBIVanewWN9nxLVaPPG4I2s2/L7aKnwiO7adaxa5CXx3NcD2hVX5AoeSfJrKQyZMfAsNy086S6OkxJo= ARC-Authentication-Results: i=1; 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charset="utf-8" Add virtual time context description to vmstate_riscv_cpu. After cpu being loaded, virtual time context is updated to KVM. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/cpu.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b698f4adbb..c6b207d201 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -496,11 +496,19 @@ static void riscv_cpu_init(Object *obj) cpu_set_cpustate_pointers(cpu); } =20 +static int cpu_post_load(void *opaque, int version_id) +{ + RISCVCPU *cpu =3D opaque; + cpu->env.kvm_timer_dirty =3D true; + return 0; +} + #ifndef CONFIG_USER_ONLY static const VMStateDescription vmstate_riscv_cpu =3D { .name =3D "cpu", .version_id =3D 1, .minimum_version_id =3D 1, + .post_load =3D cpu_post_load, .fields =3D (VMStateField[]) { VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32), @@ -514,6 +522,9 @@ static const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINTTL(env.sbadaddr, RISCVCPU), VMSTATE_UINTTL(env.mip, RISCVCPU), VMSTATE_UINTTL(env.satp, RISCVCPU), + VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU), + VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU), + VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU), VMSTATE_END_OF_LIST() } }; --=20 2.19.1