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Fri, 6 Mar 2020 08:41:50 +0000 (UTC) Received: from youngberry.canonical.com (youngberry.canonical.com [91.189.89.112]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-66-E9V_SKyPMC29_lqLI7RajQ-1; Fri, 06 Mar 2020 03:41:48 -0500 Received: from 2.general.paelzer.uk.vpn ([10.172.196.173] helo=localhost.localdomain) by youngberry.canonical.com with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1jA8YE-0002Nk-HM; Fri, 06 Mar 2020 08:41:46 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1583484171; h=from:from:sender:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding:list-id:list-help: list-unsubscribe:list-subscribe:list-post; bh=7C25lqRL2CCZ+2Feu7VCtk8Khoh+qlx65AySraRFR+o=; b=bfq6YubHObrG4eXvxlqz5+ZIfJsc+uyGMTQlHDrHQYGXRL19pkThXj7hMOfRjgtelJZb1a CIu0htylBbqx7lqKTEcQMYv1AmsQTyAv76ekdv/sprY/juWgHiYZRZY7xx405tL0g7JTDr qMCbU+1TY8Lwi6ROUX2NuG3GW4hLoW0= X-MC-Unique: LHb6IxSHMIioqoBv083a9A-1 X-MC-Unique: E9V_SKyPMC29_lqLI7RajQ-1 From: Christian Ehrhardt To: libvir-list@redhat.com Subject: [PATCH] cpu_map: Add more -noTSX x86 CPU models Date: Fri, 6 Mar 2020 09:41:43 +0100 Message-Id: <20200306084143.2759-1-christian.ehrhardt@canonical.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-MIME-Autoconverted: from quoted-printable to 8bit by lists01.pubmisc.prod.ext.phx2.redhat.com id 0268frQc006220 X-loop: libvir-list@redhat.com Cc: Jiri Denemark , Eduardo Habkost , Christian Ehrhardt X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.12 Precedence: junk List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: libvir-list-bounces@redhat.com Errors-To: libvir-list-bounces@redhat.com X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @redhat.com) Content-Type: text/plain; charset="utf-8" One of the mitigation methods for TAA[1] is to disable TSX support on the host system. Linux added a mechanism to disable TSX globally through the kernel command line, and many Linux distributions now default to tsx=3Doff. This makes existing CPU models that have HLE and RTM enabled not usable anymore. Add new versions of all CPU models that have the HLE and RTM features enabled, that can be used when TSX is disabled in the host system. On systems disabling the features without those types defined in cpu-maps users end up without modern CPU types in the list of usable CPUs to use in the likes of virsh domcapabilities or tools higher in the stack like virt-manager. This adds: -Cascadelake-Server-noTSX -Icelake-Client-noTSX -Icelake-Server-noTSX -Skylake-Server-noTSX-IBRS -Skylake-Client-noTSX-IBRS Introduced in QEMU by commit v4.2.0-rc2-3-g9ab2237f19 (function) and commit v4.2.0-rc2-4-g02fa60d101 (names) References: [1] TAA, TSX asynchronous Abort: https://software.intel.com/security-software-guidance/insights/deep= -dive-intel-transactional-synchronization-extensions-intel-tsx-asynchronous= -abort https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_asyn= c_abort.html Fixes: https://bugs.launchpad.net/ubuntu/+source/libvirt/+bug/1853200 Signed-off-by: Christian Ehrhardt --- src/cpu_map/Makefile.inc.am | 5 ++ src/cpu_map/index.xml | 5 ++ src/cpu_map/x86_Cascadelake-Server-noTSX.xml | 78 ++++++++++++++++ src/cpu_map/x86_Icelake-Client-noTSX.xml | 81 +++++++++++++++++ src/cpu_map/x86_Icelake-Server-noTSX.xml | 90 +++++++++++++++++++ src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml | 73 +++++++++++++++ src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml | 75 ++++++++++++++++ 7 files changed, 407 insertions(+) create mode 100644 src/cpu_map/x86_Cascadelake-Server-noTSX.xml create mode 100644 src/cpu_map/x86_Icelake-Client-noTSX.xml create mode 100644 src/cpu_map/x86_Icelake-Server-noTSX.xml create mode 100644 src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml create mode 100644 src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml diff --git a/src/cpu_map/Makefile.inc.am b/src/cpu_map/Makefile.inc.am index e935178304..be64c9a0d4 100644 --- a/src/cpu_map/Makefile.inc.am +++ b/src/cpu_map/Makefile.inc.am @@ -20,6 +20,7 @@ cpumap_DATA =3D \ cpu_map/x86_Broadwell-noTSX.xml \ cpu_map/x86_Broadwell-noTSX-IBRS.xml \ cpu_map/x86_Cascadelake-Server.xml \ + cpu_map/x86_Cascadelake-Server-noTSX.xml \ cpu_map/x86_Conroe.xml \ cpu_map/x86_core2duo.xml \ cpu_map/x86_coreduo.xml \ @@ -33,7 +34,9 @@ cpumap_DATA =3D \ cpu_map/x86_Haswell-noTSX.xml \ cpu_map/x86_Haswell-noTSX-IBRS.xml \ cpu_map/x86_Icelake-Client.xml \ + cpu_map/x86_Icelake-Client-noTSX.xml \ cpu_map/x86_Icelake-Server.xml \ + cpu_map/x86_Icelake-Server-noTSX.xml \ cpu_map/x86_IvyBridge.xml \ cpu_map/x86_IvyBridge-IBRS.xml \ cpu_map/x86_kvm32.xml \ @@ -58,8 +61,10 @@ cpumap_DATA =3D \ cpu_map/x86_SandyBridge-IBRS.xml \ cpu_map/x86_Skylake-Client.xml \ cpu_map/x86_Skylake-Client-IBRS.xml \ + cpu_map/x86_Skylake-Client-noTSX-IBRS.xml \ cpu_map/x86_Skylake-Server.xml \ cpu_map/x86_Skylake-Server-IBRS.xml \ + cpu_map/x86_Skylake-Server-noTSX-IBRS.xml \ cpu_map/x86_Westmere.xml \ cpu_map/x86_Westmere-IBRS.xml \ $(NULL) diff --git a/src/cpu_map/index.xml b/src/cpu_map/index.xml index ffb2f6fe1b..50b030de29 100644 --- a/src/cpu_map/index.xml +++ b/src/cpu_map/index.xml @@ -44,11 +44,16 @@ + + + + + =20 diff --git a/src/cpu_map/x86_Cascadelake-Server-noTSX.xml b/src/cpu_map/x86= _Cascadelake-Server-noTSX.xml new file mode 100644 index 0000000000..4a979739e2 --- /dev/null +++ b/src/cpu_map/x86_Cascadelake-Server-noTSX.xml @@ -0,0 +1,78 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/src/cpu_map/x86_Icelake-Client-noTSX.xml b/src/cpu_map/x86_Ice= lake-Client-noTSX.xml new file mode 100644 index 0000000000..4feb9cef2d --- /dev/null +++ b/src/cpu_map/x86_Icelake-Client-noTSX.xml @@ -0,0 +1,81 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/src/cpu_map/x86_Icelake-Server-noTSX.xml b/src/cpu_map/x86_Ice= lake-Server-noTSX.xml new file mode 100644 index 0000000000..76ae713a4d --- /dev/null +++ b/src/cpu_map/x86_Icelake-Server-noTSX.xml @@ -0,0 +1,90 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml b/src/cpu_map/x8= 6_Skylake-Client-noTSX-IBRS.xml new file mode 100644 index 0000000000..5fa4a733c6 --- /dev/null +++ b/src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml @@ -0,0 +1,73 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml b/src/cpu_map/x8= 6_Skylake-Server-noTSX-IBRS.xml new file mode 100644 index 0000000000..cb65474767 --- /dev/null +++ b/src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml @@ -0,0 +1,75 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + --=20 2.25.1