From nobody Mon Feb 9 05:48:08 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.libvirt.org designates 8.43.85.245 as permitted sender) client-ip=8.43.85.245; envelope-from=devel-bounces@lists.libvirt.org; helo=lists.libvirt.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of lists.libvirt.org designates 8.43.85.245 as permitted sender) smtp.mailfrom=devel-bounces@lists.libvirt.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.libvirt.org (lists.libvirt.org [8.43.85.245]) by mx.zohomail.com with SMTPS id 1728383431495653.5587451377319; Tue, 8 Oct 2024 03:30:31 -0700 (PDT) Received: by lists.libvirt.org (Postfix, from userid 996) id 779CD1577; Tue, 8 Oct 2024 06:30:30 -0400 (EDT) Received: from lists.libvirt.org (localhost [IPv6:::1]) by lists.libvirt.org (Postfix) with ESMTP id A05CA150A; Tue, 8 Oct 2024 06:27:23 -0400 (EDT) Received: by lists.libvirt.org (Postfix, from userid 996) id 3754815FC; Tue, 8 Oct 2024 06:27:19 -0400 (EDT) Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.libvirt.org (Postfix) with ESMTPS id 7890114EF for ; Tue, 8 Oct 2024 06:27:03 -0400 (EDT) Received: from mx-prod-mc-02.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-319-e5P9upRgNcKLtPQuiBknVQ-1; Tue, 08 Oct 2024 06:27:01 -0400 Received: from mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.12]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-02.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 3584F1955EEA for ; Tue, 8 Oct 2024 10:27:01 +0000 (UTC) Received: from orkuz (unknown [10.43.3.115]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id B81D919560A2 for ; Tue, 8 Oct 2024 10:27:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on lists.libvirt.org X-Spam-Level: X-Spam-Status: No, score=-0.5 required=5.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED,SPF_HELO_NONE autolearn=unavailable autolearn_force=no version=3.4.4 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1728383223; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=c+f63xBMsdlx1R0rKfqEnxNSfH+l7ntQ+kh1J4Gy5mk=; b=eFsWx/KKxFXn9CWqIEFvL/D5XIdtZ0vQAKk1xJOoBYOXe84CPotp9bMTAK2JixYzOY3oxw HJK0A6P7dCK98oaUHNMKf6chrWK+z5YBjTk0IdXjVhdvN1rl2kp1K9Jx+IC19RSdUF963j QCH/MqkiSFb8sVqDyNUQiBHnuj4yzqI= X-MC-Unique: e5P9upRgNcKLtPQuiBknVQ-1 From: Jiri Denemark To: devel@lists.libvirt.org Subject: [PATCH 6/7] cpu_map: Drop vmx-ept-{uc,wb} features from CPU models Date: Tue, 8 Oct 2024 12:26:45 +0200 Message-ID: <16834b8addd7a34bdd15ecd454aec86c9fe51770.1728383133.git.jdenemar@redhat.com> In-Reply-To: References: MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Message-ID-Hash: DDGCGBQ7XBHOLLLMRIWMBO3AQLJ3SUZB X-Message-ID-Hash: DDGCGBQ7XBHOLLLMRIWMBO3AQLJ3SUZB X-MailFrom: jdenemar@redhat.com X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-config-1; header-match-config-2; header-match-config-3; header-match-devel.lists.libvirt.org-0; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; suspicious-header X-Mailman-Version: 3.2.2 Precedence: list List-Id: Development discussions about the libvirt library & tools Archived-At: List-Archive: List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1728383433781116600 Content-Type: text/plain; charset="utf-8" Although QEMU knows and enables the corresponding MSR bits, it does not allow users to configure them (there are no names attached to them). They should have never been added to the CPU map and definitely not to CPU models as the features will always be considered disabled regardless on their actual state as QEMU will not report them. While we cannot drop them completely for backward compatibility, we can at least remove them from all CPU models. This is effectively no change for CPU models where the features were marked with added=3D'yes' because migration source would always remove the features from domain XML so not adding them to the live XML does not hurt. On the other side the destination could not ever be surprised by the features being suddenly enabled as QEMU never reports them, which means libvirt considers them disabled all the time. GraniteRapids CPU model is the only one which contains the feature ever since it was introduced in libvirt, but it was never possible to migrate a domain with such CPU. The source would always mark vmx-ept-wb as disabled and the destination without the fixes in this series would drop the feature from the XML completely as it is unsupported by QEMU and disabled, but when probing for the actual CPU created by QEMU libvirt would expect the feature to be enabled (as it is included in the CPU model and not explicitly mentioned in the domain definition) and fail the migration. There's nothing the source could do to workaround the behavior on the destination and migration to older libvirt will still be broken. But it's possible to migrate a domain with GraniteRapids to a destination with this series applied from both old and new source. Signed-off-by: Jiri Denemark --- src/cpu_map/sync_qemu_features_i386.py | 2 -- src/cpu_map/sync_qemu_models_i386.py | 3 +-- src/cpu_map/x86_Broadwell-IBRS.xml | 1 - src/cpu_map/x86_Broadwell-noTSX-IBRS.xml | 1 - src/cpu_map/x86_Broadwell-noTSX.xml | 1 - src/cpu_map/x86_Broadwell.xml | 1 - src/cpu_map/x86_Cascadelake-Server-noTSX.xml | 1 - src/cpu_map/x86_Cascadelake-Server.xml | 1 - src/cpu_map/x86_Cooperlake.xml | 1 - src/cpu_map/x86_GraniteRapids.xml | 1 - src/cpu_map/x86_Haswell-IBRS.xml | 1 - src/cpu_map/x86_Haswell-noTSX-IBRS.xml | 1 - src/cpu_map/x86_Haswell-noTSX.xml | 1 - src/cpu_map/x86_Haswell.xml | 1 - src/cpu_map/x86_Icelake-Server-noTSX.xml | 1 - src/cpu_map/x86_Icelake-Server.xml | 1 - src/cpu_map/x86_IvyBridge-IBRS.xml | 1 - src/cpu_map/x86_IvyBridge.xml | 1 - src/cpu_map/x86_Nehalem-IBRS.xml | 1 - src/cpu_map/x86_Nehalem.xml | 1 - src/cpu_map/x86_SandyBridge-IBRS.xml | 1 - src/cpu_map/x86_SandyBridge.xml | 1 - src/cpu_map/x86_SapphireRapids.xml | 1 - src/cpu_map/x86_Skylake-Client-IBRS.xml | 1 - src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml | 1 - src/cpu_map/x86_Skylake-Client.xml | 1 - src/cpu_map/x86_Skylake-Server-IBRS.xml | 1 - src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml | 1 - src/cpu_map/x86_Skylake-Server.xml | 1 - src/cpu_map/x86_Snowridge.xml | 1 - src/cpu_map/x86_Westmere-IBRS.xml | 1 - src/cpu_map/x86_Westmere.xml | 1 - src/qemu/qemu_capabilities.c | 1 + 33 files changed, 2 insertions(+), 34 deletions(-) diff --git a/src/cpu_map/sync_qemu_features_i386.py b/src/cpu_map/sync_qemu= _features_i386.py index 21df37e9d6..c78c0b2ac9 100755 --- a/src/cpu_map/sync_qemu_features_i386.py +++ b/src/cpu_map/sync_qemu_features_i386.py @@ -70,8 +70,6 @@ FEATURES_EXTRA =3D { 18: "cvt16", }, (0x0000048c,): { - 8: "vmx-ept-uc", - 14: "vmx-ept-wb", 41: "vmx-invvpid-single-context", # wrong name in qe= mu 43: "vmx-invvpid-single-context-noglobals", # wrong name in qe= mu } diff --git a/src/cpu_map/sync_qemu_models_i386.py b/src/cpu_map/sync_qemu_m= odels_i386.py index 06a8837b0a..408e07911e 100755 --- a/src/cpu_map/sync_qemu_models_i386.py +++ b/src/cpu_map/sync_qemu_models_i386.py @@ -278,8 +278,6 @@ def translate_feature(name): "MSR_VMX_EPT_EXECONLY": "vmx-ept-execonly", "MSR_VMX_EPT_PAGE_WALK_LENGTH_4": "vmx-page-walk-4", "MSR_VMX_EPT_PAGE_WALK_LENGTH_5": "vmx-page-walk-5", - "MSR_VMX_EPT_UC": "vmx-ept-uc", - "MSR_VMX_EPT_WB": "vmx-ept-wb", "MSR_VMX_EPT_2MB": "vmx-ept-2mb", "MSR_VMX_EPT_1GB": "vmx-ept-1gb", "MSR_VMX_EPT_INVEPT": "vmx-invept", @@ -307,6 +305,7 @@ def translate_feature(name): name in ("CPUID_EXT_MONITOR", "monitor"), name in ("MSR_VMX_BASIC_DUAL_MONITOR", "dual-monitor"), name in ("CPUID_EXT3_TOPOEXT", "topoext"), + name in ("MSR_VMX_EPT_UC", "MSR_VMX_EPT_WB"), ]) =20 if ignore: diff --git a/src/cpu_map/x86_Broadwell-IBRS.xml b/src/cpu_map/x86_Broadwell= -IBRS.xml index 1484903298..e87f54a102 100644 --- a/src/cpu_map/x86_Broadwell-IBRS.xml +++ b/src/cpu_map/x86_Broadwell-IBRS.xml @@ -78,7 +78,6 @@ - diff --git a/src/cpu_map/x86_Broadwell-noTSX-IBRS.xml b/src/cpu_map/x86_Bro= adwell-noTSX-IBRS.xml index 13f08435b7..59c2c08937 100644 --- a/src/cpu_map/x86_Broadwell-noTSX-IBRS.xml +++ b/src/cpu_map/x86_Broadwell-noTSX-IBRS.xml @@ -76,7 +76,6 @@ - diff --git a/src/cpu_map/x86_Broadwell-noTSX.xml b/src/cpu_map/x86_Broadwel= l-noTSX.xml index 4293b3aeee..b9b25d6b6c 100644 --- a/src/cpu_map/x86_Broadwell-noTSX.xml +++ b/src/cpu_map/x86_Broadwell-noTSX.xml @@ -75,7 +75,6 @@ - diff --git a/src/cpu_map/x86_Broadwell.xml b/src/cpu_map/x86_Broadwell.xml index 37dd1dabcf..2845a620ac 100644 --- a/src/cpu_map/x86_Broadwell.xml +++ b/src/cpu_map/x86_Broadwell.xml @@ -77,7 +77,6 @@ - diff --git a/src/cpu_map/x86_Cascadelake-Server-noTSX.xml b/src/cpu_map/x86= _Cascadelake-Server-noTSX.xml index 8c4cbf9c9a..a3b332c9c1 100644 --- a/src/cpu_map/x86_Cascadelake-Server-noTSX.xml +++ b/src/cpu_map/x86_Cascadelake-Server-noTSX.xml @@ -89,7 +89,6 @@ - diff --git a/src/cpu_map/x86_Cascadelake-Server.xml b/src/cpu_map/x86_Casca= delake-Server.xml index c7c4f6412f..9faad320e6 100644 --- a/src/cpu_map/x86_Cascadelake-Server.xml +++ b/src/cpu_map/x86_Cascadelake-Server.xml @@ -91,7 +91,6 @@ - diff --git a/src/cpu_map/x86_Cooperlake.xml b/src/cpu_map/x86_Cooperlake.xml index af428f2781..caccfc048c 100644 --- a/src/cpu_map/x86_Cooperlake.xml +++ b/src/cpu_map/x86_Cooperlake.xml @@ -100,7 +100,6 @@ - diff --git a/src/cpu_map/x86_GraniteRapids.xml b/src/cpu_map/x86_GraniteRap= ids.xml index 6f7030ce39..6dab7d7b09 100644 --- a/src/cpu_map/x86_GraniteRapids.xml +++ b/src/cpu_map/x86_GraniteRapids.xml @@ -129,7 +129,6 @@ - diff --git a/src/cpu_map/x86_Haswell-IBRS.xml b/src/cpu_map/x86_Haswell-IBR= S.xml index 57b980d14f..e2e3ce6b51 100644 --- a/src/cpu_map/x86_Haswell-IBRS.xml +++ b/src/cpu_map/x86_Haswell-IBRS.xml @@ -74,7 +74,6 @@ - diff --git a/src/cpu_map/x86_Haswell-noTSX-IBRS.xml b/src/cpu_map/x86_Haswe= ll-noTSX-IBRS.xml index fcae023ffb..c8d050b8d3 100644 --- a/src/cpu_map/x86_Haswell-noTSX-IBRS.xml +++ b/src/cpu_map/x86_Haswell-noTSX-IBRS.xml @@ -72,7 +72,6 @@ - diff --git a/src/cpu_map/x86_Haswell-noTSX.xml b/src/cpu_map/x86_Haswell-no= TSX.xml index 7404052065..d714ce5858 100644 --- a/src/cpu_map/x86_Haswell-noTSX.xml +++ b/src/cpu_map/x86_Haswell-noTSX.xml @@ -71,7 +71,6 @@ - diff --git a/src/cpu_map/x86_Haswell.xml b/src/cpu_map/x86_Haswell.xml index 99986c5c45..583649dbab 100644 --- a/src/cpu_map/x86_Haswell.xml +++ b/src/cpu_map/x86_Haswell.xml @@ -73,7 +73,6 @@ - diff --git a/src/cpu_map/x86_Icelake-Server-noTSX.xml b/src/cpu_map/x86_Ice= lake-Server-noTSX.xml index caba24ab35..8515b6518c 100644 --- a/src/cpu_map/x86_Icelake-Server-noTSX.xml +++ b/src/cpu_map/x86_Icelake-Server-noTSX.xml @@ -99,7 +99,6 @@ - diff --git a/src/cpu_map/x86_Icelake-Server.xml b/src/cpu_map/x86_Icelake-S= erver.xml index 5a864b2fad..9d0cc254c0 100644 --- a/src/cpu_map/x86_Icelake-Server.xml +++ b/src/cpu_map/x86_Icelake-Server.xml @@ -101,7 +101,6 @@ - diff --git a/src/cpu_map/x86_IvyBridge-IBRS.xml b/src/cpu_map/x86_IvyBridge= -IBRS.xml index 27d85d86c4..4822b546e9 100644 --- a/src/cpu_map/x86_IvyBridge-IBRS.xml +++ b/src/cpu_map/x86_IvyBridge-IBRS.xml @@ -66,7 +66,6 @@ - diff --git a/src/cpu_map/x86_IvyBridge.xml b/src/cpu_map/x86_IvyBridge.xml index 72031cfdc6..93edca17ca 100644 --- a/src/cpu_map/x86_IvyBridge.xml +++ b/src/cpu_map/x86_IvyBridge.xml @@ -65,7 +65,6 @@ - diff --git a/src/cpu_map/x86_Nehalem-IBRS.xml b/src/cpu_map/x86_Nehalem-IBR= S.xml index 0cfee14c0f..a6510aa99f 100644 --- a/src/cpu_map/x86_Nehalem-IBRS.xml +++ b/src/cpu_map/x86_Nehalem-IBRS.xml @@ -55,7 +55,6 @@ - diff --git a/src/cpu_map/x86_Nehalem.xml b/src/cpu_map/x86_Nehalem.xml index 74ee64ce1c..6c0dfba451 100644 --- a/src/cpu_map/x86_Nehalem.xml +++ b/src/cpu_map/x86_Nehalem.xml @@ -54,7 +54,6 @@ - diff --git a/src/cpu_map/x86_SandyBridge-IBRS.xml b/src/cpu_map/x86_SandyBr= idge-IBRS.xml index 297eea8e88..6d2b5028ee 100644 --- a/src/cpu_map/x86_SandyBridge-IBRS.xml +++ b/src/cpu_map/x86_SandyBridge-IBRS.xml @@ -58,7 +58,6 @@ - diff --git a/src/cpu_map/x86_SandyBridge.xml b/src/cpu_map/x86_SandyBridge.= xml index 20ea378c47..de3ad60e3d 100644 --- a/src/cpu_map/x86_SandyBridge.xml +++ b/src/cpu_map/x86_SandyBridge.xml @@ -57,7 +57,6 @@ - diff --git a/src/cpu_map/x86_SapphireRapids.xml b/src/cpu_map/x86_SapphireR= apids.xml index 40164a47e2..6321dd36d9 100644 --- a/src/cpu_map/x86_SapphireRapids.xml +++ b/src/cpu_map/x86_SapphireRapids.xml @@ -122,7 +122,6 @@ - diff --git a/src/cpu_map/x86_Skylake-Client-IBRS.xml b/src/cpu_map/x86_Skyl= ake-Client-IBRS.xml index f36a8bd210..7d0d3c7114 100644 --- a/src/cpu_map/x86_Skylake-Client-IBRS.xml +++ b/src/cpu_map/x86_Skylake-Client-IBRS.xml @@ -83,7 +83,6 @@ - diff --git a/src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml b/src/cpu_map/x8= 6_Skylake-Client-noTSX-IBRS.xml index 5150117db4..383270f5f9 100644 --- a/src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml +++ b/src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml @@ -81,7 +81,6 @@ - diff --git a/src/cpu_map/x86_Skylake-Client.xml b/src/cpu_map/x86_Skylake-C= lient.xml index 061c0dfaec..84789d642a 100644 --- a/src/cpu_map/x86_Skylake-Client.xml +++ b/src/cpu_map/x86_Skylake-Client.xml @@ -82,7 +82,6 @@ - diff --git a/src/cpu_map/x86_Skylake-Server-IBRS.xml b/src/cpu_map/x86_Skyl= ake-Server-IBRS.xml index bbd3c8998e..8cd25a2df4 100644 --- a/src/cpu_map/x86_Skylake-Server-IBRS.xml +++ b/src/cpu_map/x86_Skylake-Server-IBRS.xml @@ -88,7 +88,6 @@ - diff --git a/src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml b/src/cpu_map/x8= 6_Skylake-Server-noTSX-IBRS.xml index ee0d2a2fa3..f3877bfbec 100644 --- a/src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml +++ b/src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml @@ -86,7 +86,6 @@ - diff --git a/src/cpu_map/x86_Skylake-Server.xml b/src/cpu_map/x86_Skylake-S= erver.xml index 9d9d112d40..78bd727357 100644 --- a/src/cpu_map/x86_Skylake-Server.xml +++ b/src/cpu_map/x86_Skylake-Server.xml @@ -87,7 +87,6 @@ - diff --git a/src/cpu_map/x86_Snowridge.xml b/src/cpu_map/x86_Snowridge.xml index bc410bd8f8..b31ce6f9f5 100644 --- a/src/cpu_map/x86_Snowridge.xml +++ b/src/cpu_map/x86_Snowridge.xml @@ -81,7 +81,6 @@ - diff --git a/src/cpu_map/x86_Westmere-IBRS.xml b/src/cpu_map/x86_Westmere-I= BRS.xml index a5abe8a1e1..534c752ed9 100644 --- a/src/cpu_map/x86_Westmere-IBRS.xml +++ b/src/cpu_map/x86_Westmere-IBRS.xml @@ -53,7 +53,6 @@ - diff --git a/src/cpu_map/x86_Westmere.xml b/src/cpu_map/x86_Westmere.xml index 161f1a078e..4edc5b3839 100644 --- a/src/cpu_map/x86_Westmere.xml +++ b/src/cpu_map/x86_Westmere.xml @@ -54,7 +54,6 @@ - diff --git a/src/qemu/qemu_capabilities.c b/src/qemu/qemu_capabilities.c index f930ad2acf..45565326a5 100644 --- a/src/qemu/qemu_capabilities.c +++ b/src/qemu/qemu_capabilities.c @@ -3534,6 +3534,7 @@ virQEMUCapsProbeQMPSGXCapabilities(virQEMUCaps *qemuC= aps, const char *ignoredFeatures[] =3D { "cmt", "mbm_total", "mbm_local", /* never supported by QEMU */ "osxsave", "ospke", /* dropped from QEMU */ + "vmx-ept-uc", "vmx-ept-wb", /* never supported by QEMU */ }; =20 bool --=20 2.46.2