From nobody Fri May 17 11:58:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+109057+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+109057+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1695694605; cv=none; d=zohomail.com; s=zohoarc; b=ijL8je8DIdOt+H0EWik0dZWP4Nb/ggUFZZDOcFjkGGaF+XoCA2Exubkelv2NFDfBbRNayLPMm2cdVYES/5vk8TunQxVRkrYAV+722kRuIoCSPrqZLZaIcK/fuOWaZCklV2o5MNu2vDF6Ty/wAtt461n213hcIcYTdIyHm6guc+w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695694605; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; bh=gYbCaqdGJWS51ztL/yxycRQe16MMhSlyeU5bwCn0cmk=; b=Slp478Ql1DaG0RPfV8yZsSNIm2+YHiXD9J7XuahwY7ccdID1uYMN6luJ2mETbebAVxrhjABkiaR8tYiJk79JDhr0F+RNkqVgqDJI4ed4OXM6orUmExae8Hd0wNqMmRUKh2oL6XIRFkDsnaYxFaX12fVuP4BiLA0cz/HnnanhNvA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+109057+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1695694605370910.0618402593335; Mon, 25 Sep 2023 19:16:45 -0700 (PDT) Return-Path: DKIM-Signature: a=rsa-sha256; bh=yuE198rlrE6hTv667CEYIXafuWk3tP360jUpPcrafuw=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1695694605; v=1; b=B3k/nLWO9Lh0VgwEU5nCQkG8YG92fqszDTiMo+KZAQ3UhAdjfoBlbG4pHcxhh8ZKfR9fEdJH ugWAvUUSEJbAHRkjDqa6ACng4KTIJmHfKi2GXSd5OY2cQ9lPGptaUDnyttniXcztBBaSgvmeRLs YVfg2oOeA9YyXUNp/9FyT4WA= X-Received: by 127.0.0.2 with SMTP id L19KYY1788612x00KxJrIxOb; Mon, 25 Sep 2023 19:16:45 -0700 X-Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web10.10247.1695694604311708239 for ; Mon, 25 Sep 2023 19:16:44 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10843"; a="385311082" X-IronPort-AV: E=Sophos;i="6.03,176,1694761200"; d="scan'208";a="385311082" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Sep 2023 19:16:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10843"; a="777941485" X-IronPort-AV: E=Sophos;i="6.03,176,1694761200"; d="scan'208";a="777941485" X-Received: from gaocheng-desk.ccr.corp.intel.com ([10.239.154.170]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Sep 2023 19:16:41 -0700 From: "Gao" To: devel@edk2.groups.io Cc: Gao Cheng , Hao A Wu , Ray Ni , Jian J Wang , Liming Gao Subject: [edk2-devel] [PATCH] MdeModulePkg/Xhci: Skip size round up for TRB during address translation Date: Tue, 26 Sep 2023 10:12:12 +0800 Message-ID: MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,gao.cheng@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: CUNViMwLtifKTdUqGA4AgF8zx1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1695694606786100001 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D4560 TRB Template is 16 bytes. When boundary checking is 64 bytes for xHCI device/host memory address, it may exceed xHCI host memory pool and cause unwanted DXE_ASSERT. Introduce a new input parameter to indicate whether to enforce 64byte size alignment and round up. For TRB case, should set it to FALSE to skip the size round up. Signed-off-by: Gao Cheng Cc: Hao A Wu Cc: Ray Ni Cc: Jian J Wang Cc: Liming Gao --- MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c | 20 +++++++-- MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.h | 8 +++- MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c | 54 +++++++++++++----------- MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.c | 20 +++++++-- MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.h | 8 +++- MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c | 48 +++++++++++---------- 6 files changed, 99 insertions(+), 59 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c b/MdeModulePkg/Bus/Pci= /XhciDxe/UsbHcMem.c index d0ad1582e4..8fea441fbc 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c +++ b/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c @@ -226,6 +226,7 @@ UsbHcAllocMemFromBlock ( @param Pool The memory pool of the host controller. @param Mem The pointer to host memory. @param Size The size of the memory region. + @param Alignment Alignment the size to USBHC_MEM_UNIT bytes. =20 @return The pci memory address =20 @@ -234,7 +235,8 @@ EFI_PHYSICAL_ADDRESS UsbHcGetPciAddrForHostAddr ( IN USBHC_MEM_POOL *Pool, IN VOID *Mem, - IN UINTN Size + IN UINTN Size, + IN BOOLEAN Alignment ) { USBHC_MEM_BLOCK *Head; @@ -244,7 +246,11 @@ UsbHcGetPciAddrForHostAddr ( UINTN Offset; =20 Head =3D Pool->Head; - AllocSize =3D USBHC_MEM_ROUND (Size); + if (Alignment) { + AllocSize =3D USBHC_MEM_ROUND (Size); + } else { + AllocSize =3D Size; + } =20 if (Mem =3D=3D NULL) { return 0; @@ -275,6 +281,7 @@ UsbHcGetPciAddrForHostAddr ( @param Pool The memory pool of the host controller. @param Mem The pointer to pci memory. @param Size The size of the memory region. + @param Alignment Alignment the size to USBHC_MEM_UNIT bytes. =20 @return The host memory address =20 @@ -283,7 +290,8 @@ EFI_PHYSICAL_ADDRESS UsbHcGetHostAddrForPciAddr ( IN USBHC_MEM_POOL *Pool, IN VOID *Mem, - IN UINTN Size + IN UINTN Size, + IN BOOLEAN Alignment ) { USBHC_MEM_BLOCK *Head; @@ -293,7 +301,11 @@ UsbHcGetHostAddrForPciAddr ( UINTN Offset; =20 Head =3D Pool->Head; - AllocSize =3D USBHC_MEM_ROUND (Size); + if (Alignment) { + AllocSize =3D USBHC_MEM_ROUND (Size); + } else { + AllocSize =3D Size; + } =20 if (Mem =3D=3D NULL) { return 0; diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.h b/MdeModulePkg/Bus/Pci= /XhciDxe/UsbHcMem.h index c85b0b919f..b21bf9da3e 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.h +++ b/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.h @@ -129,6 +129,7 @@ UsbHcFreeMem ( @param Pool The memory pool of the host controller. @param Mem The pointer to host memory. @param Size The size of the memory region. + @param Alignment Alignment the size to USBHC_MEM_UNIT bytes. =20 @return The pci memory address =20 @@ -137,7 +138,8 @@ EFI_PHYSICAL_ADDRESS UsbHcGetPciAddrForHostAddr ( IN USBHC_MEM_POOL *Pool, IN VOID *Mem, - IN UINTN Size + IN UINTN Size, + IN BOOLEAN Alignment ); =20 /** @@ -146,6 +148,7 @@ UsbHcGetPciAddrForHostAddr ( @param Pool The memory pool of the host controller. @param Mem The pointer to pci memory. @param Size The size of the memory region. + @param Alignment Alignment the size to USBHC_MEM_UNIT bytes. =20 @return The host memory address =20 @@ -154,7 +157,8 @@ EFI_PHYSICAL_ADDRESS UsbHcGetHostAddrForPciAddr ( IN USBHC_MEM_POOL *Pool, IN VOID *Mem, - IN UINTN Size + IN UINTN Size, + IN BOOLEAN Alignment ); =20 /** diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c b/MdeModulePkg/Bus/Pc= i/XhciDxe/XhciSched.c index 53421e64a8..c2be171780 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c @@ -588,7 +588,7 @@ XhcInitSched ( // Some 3rd party XHCI external cards don't support single 64-bytes widt= h register access, // So divide it to two 32-bytes width register access. // - DcbaaPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Dcbaa, Entries); + DcbaaPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Dcbaa, Entries, T= RUE); XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET, XHC_LOW_32BIT (DcbaaPhy)); XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET + 4, XHC_HIGH_32BIT (DcbaaPhy)); =20 @@ -607,7 +607,7 @@ XhcInitSched ( // So we set RCS as inverted PCS init value to let Command Ring empty // CmdRing =3D (UINT64)(UINTN)Xhc->CmdRing.RingSeg0; - CmdRingPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, (VOID *)(UINTN)= CmdRing, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER); + CmdRingPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, (VOID *)(UINTN)= CmdRing, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER, TRUE); ASSERT ((CmdRingPhy & 0x3F) =3D=3D 0); CmdRingPhy |=3D XHC_CRCR_RCS; // @@ -809,7 +809,7 @@ CreateEventRing ( EventRing->EventRingDequeue =3D (TRB_TEMPLATE *)EventRing->EventRingSeg0; EventRing->EventRingEnqueue =3D (TRB_TEMPLATE *)EventRing->EventRingSeg0; =20 - DequeuePhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size); + DequeuePhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size, TRUE= ); =20 // // Software maintains an Event Ring Consumer Cycle State (CCS) bit, init= ializing it to '1' @@ -829,7 +829,7 @@ CreateEventRing ( ERSTBase->PtrHi =3D XHC_HIGH_32BIT (DequeuePhy); ERSTBase->RingTrbSize =3D EVENT_RING_TRB_NUMBER; =20 - ERSTPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, ERSTBase, Size); + ERSTPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, ERSTBase, Size, TR= UE); =20 // // Program the Interrupter Event Ring Segment Table Size (ERSTSZ) regist= er (5.5.2.3.1) @@ -913,7 +913,7 @@ CreateTransferRing ( // EndTrb =3D (LINK_TRB *)((UINTN)Buf + sizeof (TRB_TEMPLATE) * (Trb= Num - 1)); EndTrb->Type =3D TRB_TYPE_LINK; - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, sizeof = (TRB_TEMPLATE) * TrbNum); + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, sizeof = (TRB_TEMPLATE) * TrbNum, TRUE); EndTrb->PtrLo =3D XHC_LOW_32BIT (PhyAddr); EndTrb->PtrHi =3D XHC_HIGH_32BIT (PhyAddr); // @@ -1045,7 +1045,7 @@ IsTransferRingTrb ( if (CheckedTrb->Type =3D=3D TRB_TYPE_LINK) { LinkTrb =3D (LINK_TRB *)CheckedTrb; PhyAddr =3D (EFI_PHYSICAL_ADDRESS)(LinkTrb->PtrLo | LShiftU64 ((U= INT64)LinkTrb->PtrHi, 32)); - CheckedTrb =3D (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xh= c->MemPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE)); + CheckedTrb =3D (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xh= c->MemPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE), FALSE); ASSERT (CheckedTrb =3D=3D Urb->Ring->RingSeg0); } } @@ -1154,7 +1154,7 @@ XhcCheckUrbResult ( // Need convert pci device address to host address // PhyAddr =3D (EFI_PHYSICAL_ADDRESS)(EvtTrb->TRBPtrLo | LShiftU64 ((UINT= 64)EvtTrb->TRBPtrHi, 32)); - TRBPtr =3D (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xhc->Me= mPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE)); + TRBPtr =3D (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xhc->Me= mPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE), FALSE); =20 // // Update the status of URB including the pending URB, the URB that is= currently checked, @@ -1259,7 +1259,7 @@ EXIT: High =3D XhcReadRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4); XhcDequeue =3D (UINT64)(LShiftU64 ((UINT64)High, 32) | Low); =20 - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->EventRing.Eve= ntRingDequeue, sizeof (TRB_TEMPLATE)); + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->EventRing.Eve= ntRingDequeue, sizeof (TRB_TEMPLATE), FALSE); =20 if ((XhcDequeue & (~0x0F)) !=3D (PhyAddr & (~0x0F))) { // @@ -2280,7 +2280,8 @@ XhcInitializeDeviceSlot ( PhyAddr =3D UsbHcGetPciAddrForHostAddr ( Xhc->MemPool, ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].Endpoint= TransferRing[0])->RingSeg0, - sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER + sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER, + TRUE ); InputContext->EP[0].PtrLo =3D XHC_LOW_32BIT (PhyAddr) | BIT0; InputContext->EP[0].PtrHi =3D XHC_HIGH_32BIT (PhyAddr); @@ -2298,7 +2299,7 @@ XhcInitializeDeviceSlot ( // 7) Load the appropriate (Device Slot ID) entry in the Device Context = Base Address Array (5.4.6) with // a pointer to the Output Device Context data structure (6.2.1). // - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, siz= eof (DEVICE_CONTEXT)); + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, siz= eof (DEVICE_CONTEXT), TRUE); // // Fill DCBAA with PCI device address // @@ -2313,7 +2314,7 @@ XhcInitializeDeviceSlot ( // gBS->Stall (XHC_RESET_RECOVERY_DELAY); ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr)); - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->U= sbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT)); + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->U= sbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT), TRUE); CmdTrbAddr.PtrLo =3D XHC_LOW_32BIT (PhyAddr); CmdTrbAddr.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); CmdTrbAddr.CycleBit =3D 1; @@ -2496,7 +2497,8 @@ XhcInitializeDeviceSlot64 ( PhyAddr =3D UsbHcGetPciAddrForHostAddr ( Xhc->MemPool, ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].Endpoint= TransferRing[0])->RingSeg0, - sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER + sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER, + TRUE ); InputContext->EP[0].PtrLo =3D XHC_LOW_32BIT (PhyAddr) | BIT0; InputContext->EP[0].PtrHi =3D XHC_HIGH_32BIT (PhyAddr); @@ -2514,7 +2516,7 @@ XhcInitializeDeviceSlot64 ( // 7) Load the appropriate (Device Slot ID) entry in the Device Context = Base Address Array (5.4.6) with // a pointer to the Output Device Context data structure (6.2.1). // - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, siz= eof (DEVICE_CONTEXT_64)); + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, siz= eof (DEVICE_CONTEXT_64), TRUE); // // Fill DCBAA with PCI device address // @@ -2529,7 +2531,7 @@ XhcInitializeDeviceSlot64 ( // gBS->Stall (XHC_RESET_RECOVERY_DELAY); ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr)); - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->U= sbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64)); + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->U= sbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64), TRUE); CmdTrbAddr.PtrLo =3D XHC_LOW_32BIT (PhyAddr); CmdTrbAddr.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); CmdTrbAddr.CycleBit =3D 1; @@ -2964,7 +2966,8 @@ XhcInitializeEndpointContext ( PhyAddr =3D UsbHcGetPciAddrForHostAddr ( Xhc->MemPool, ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].Endpoi= ntTransferRing[Dci-1])->RingSeg0, - sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER + sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER, + TRUE ); PhyAddr &=3D ~((EFI_PHYSICAL_ADDRESS)0x0F); PhyAddr |=3D (EFI_PHYSICAL_ADDRESS)((TRANSFER_RIN= G *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS; @@ -3166,7 +3169,8 @@ XhcInitializeEndpointContext64 ( PhyAddr =3D UsbHcGetPciAddrForHostAddr ( Xhc->MemPool, ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].Endpoi= ntTransferRing[Dci-1])->RingSeg0, - sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER + sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER, + TRUE ); PhyAddr &=3D ~((EFI_PHYSICAL_ADDRESS)0x0F); PhyAddr |=3D (EFI_PHYSICAL_ADDRESS)((TRANSFER_RIN= G *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS; @@ -3248,7 +3252,7 @@ XhcSetConfigCmd ( // configure endpoint // ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT)); + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT), TRUE); CmdTrbCfgEP.PtrLo =3D XHC_LOW_32BIT (PhyAddr); CmdTrbCfgEP.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); CmdTrbCfgEP.CycleBit =3D 1; @@ -3339,7 +3343,7 @@ XhcSetConfigCmd64 ( // configure endpoint // ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT_64)); + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT_64), TRUE); CmdTrbCfgEP.PtrLo =3D XHC_LOW_32BIT (PhyAddr); CmdTrbCfgEP.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); CmdTrbCfgEP.CycleBit =3D 1; @@ -3513,7 +3517,7 @@ XhcSetTrDequeuePointer ( // Send stop endpoint command to transit Endpoint from running to stop s= tate // ZeroMem (&CmdSetTRDeq, sizeof (CmdSetTRDeq)); - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->= Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER)); + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->= Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER), TRUE); CmdSetTRDeq.PtrLo =3D XHC_LOW_32BIT (PhyAddr) | Urb->Ring->RingPCS; CmdSetTRDeq.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); CmdSetTRDeq.CycleBit =3D 1; @@ -3713,7 +3717,7 @@ XhcSetInterface ( // 5) Issue and successfully complete a Configure Endpoint Command. // ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Inp= utContext, sizeof (INPUT_CONTEXT)); + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Inp= utContext, sizeof (INPUT_CONTEXT), TRUE); CmdTrbCfgEP.PtrLo =3D XHC_LOW_32BIT (PhyAddr); CmdTrbCfgEP.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); CmdTrbCfgEP.CycleBit =3D 1; @@ -3919,7 +3923,7 @@ XhcSetInterface64 ( // 5) Issue and successfully complete a Configure Endpoint Command. // ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Inp= utContext, sizeof (INPUT_CONTEXT_64)); + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Inp= utContext, sizeof (INPUT_CONTEXT_64), TRUE); CmdTrbCfgEP.PtrLo =3D XHC_LOW_32BIT (PhyAddr); CmdTrbCfgEP.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); CmdTrbCfgEP.CycleBit =3D 1; @@ -3986,7 +3990,7 @@ XhcEvaluateContext ( InputContext->EP[0].EPState =3D 0; =20 ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu)); - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT)); + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT), TRUE); CmdTrbEvalu.PtrLo =3D XHC_LOW_32BIT (PhyAddr); CmdTrbEvalu.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); CmdTrbEvalu.CycleBit =3D 1; @@ -4047,7 +4051,7 @@ XhcEvaluateContext64 ( InputContext->EP[0].EPState =3D 0; =20 ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu)); - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT_64)); + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT_64), TRUE); CmdTrbEvalu.PtrLo =3D XHC_LOW_32BIT (PhyAddr); CmdTrbEvalu.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); CmdTrbEvalu.CycleBit =3D 1; @@ -4116,7 +4120,7 @@ XhcConfigHubContext ( InputContext->Slot.MTT =3D MTT; =20 ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT)); + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT), TRUE); CmdTrbCfgEP.PtrLo =3D XHC_LOW_32BIT (PhyAddr); CmdTrbCfgEP.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); CmdTrbCfgEP.CycleBit =3D 1; @@ -4185,7 +4189,7 @@ XhcConfigHubContext64 ( InputContext->Slot.MTT =3D MTT; =20 ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT_64)); + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT_64), TRUE); CmdTrbCfgEP.PtrLo =3D XHC_LOW_32BIT (PhyAddr); CmdTrbCfgEP.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); CmdTrbCfgEP.CycleBit =3D 1; diff --git a/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.c b/MdeModulePkg/Bus/Pci= /XhciPei/UsbHcMem.c index e779a31138..e9cf53b122 100644 --- a/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.c +++ b/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.c @@ -190,6 +190,7 @@ UsbHcAllocMemFromBlock ( @param Pool The memory pool of the host controller. @param Mem The pointer to host memory. @param Size The size of the memory region. + @param Alignment Alignment the size to USBHC_MEM_UNIT bytes. =20 @return The pci memory address =20 @@ -198,7 +199,8 @@ EFI_PHYSICAL_ADDRESS UsbHcGetPciAddrForHostAddr ( IN USBHC_MEM_POOL *Pool, IN VOID *Mem, - IN UINTN Size + IN UINTN Size, + IN BOOLEAN Alignment ) { USBHC_MEM_BLOCK *Head; @@ -208,7 +210,11 @@ UsbHcGetPciAddrForHostAddr ( UINTN Offset; =20 Head =3D Pool->Head; - AllocSize =3D USBHC_MEM_ROUND (Size); + if (Alignment) { + AllocSize =3D USBHC_MEM_ROUND (Size); + } else { + AllocSize =3D Size; + } =20 if (Mem =3D=3D NULL) { return 0; @@ -239,6 +245,7 @@ UsbHcGetPciAddrForHostAddr ( @param Pool The memory pool of the host controller. @param Mem The pointer to pci memory. @param Size The size of the memory region. + @param Alignment Alignment the size to USBHC_MEM_UNIT bytes. =20 @return The host memory address =20 @@ -247,7 +254,8 @@ EFI_PHYSICAL_ADDRESS UsbHcGetHostAddrForPciAddr ( IN USBHC_MEM_POOL *Pool, IN VOID *Mem, - IN UINTN Size + IN UINTN Size, + IN BOOLEAN Alignment ) { USBHC_MEM_BLOCK *Head; @@ -257,7 +265,11 @@ UsbHcGetHostAddrForPciAddr ( UINTN Offset; =20 Head =3D Pool->Head; - AllocSize =3D USBHC_MEM_ROUND (Size); + if (Alignment) { + AllocSize =3D USBHC_MEM_ROUND (Size); + } else { + AllocSize =3D Size; + } =20 if (Mem =3D=3D NULL) { return 0; diff --git a/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.h b/MdeModulePkg/Bus/Pci= /XhciPei/UsbHcMem.h index 2b4c8b19fc..8f760e084e 100644 --- a/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.h +++ b/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.h @@ -68,6 +68,7 @@ typedef struct _USBHC_MEM_POOL { @param Pool The memory pool of the host controller. @param Mem The pointer to host memory. @param Size The size of the memory region. + @param Alignment Alignment the size to USBHC_MEM_UNIT bytes. =20 @return The pci memory address =20 @@ -76,7 +77,8 @@ EFI_PHYSICAL_ADDRESS UsbHcGetPciAddrForHostAddr ( IN USBHC_MEM_POOL *Pool, IN VOID *Mem, - IN UINTN Size + IN UINTN Size, + IN BOOLEAN Alignment ); =20 /** @@ -85,6 +87,7 @@ UsbHcGetPciAddrForHostAddr ( @param Pool The memory pool of the host controller. @param Mem The pointer to pci memory. @param Size The size of the memory region. + @param Alignment Alignment the size to USBHC_MEM_UNIT bytes. =20 @return The host memory address =20 @@ -93,7 +96,8 @@ EFI_PHYSICAL_ADDRESS UsbHcGetHostAddrForPciAddr ( IN USBHC_MEM_POOL *Pool, IN VOID *Mem, - IN UINTN Size + IN UINTN Size, + IN BOOLEAN Alignment ); =20 /** diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c b/MdeModulePkg/Bus/Pc= i/XhciPei/XhciSched.c index 8400c90f7a..53272f62dd 100644 --- a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c +++ b/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c @@ -675,7 +675,7 @@ XhcPeiCheckUrbResult ( // Need convert pci device address to host address // PhyAddr =3D (EFI_PHYSICAL_ADDRESS)(EvtTrb->TRBPtrLo | LShiftU64 ((UINT= 64)EvtTrb->TRBPtrHi, 32)); - TRBPtr =3D (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xhc->Me= mPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE)); + TRBPtr =3D (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xhc->Me= mPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE), FALSE); =20 // // Update the status of Urb according to the finished event regardless= of whether @@ -766,7 +766,7 @@ EXIT: High =3D XhcPeiReadRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4); XhcDequeue =3D (UINT64)(LShiftU64 ((UINT64)High, 32) | Low); =20 - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->EventRing.Eve= ntRingDequeue, sizeof (TRB_TEMPLATE)); + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->EventRing.Eve= ntRingDequeue, sizeof (TRB_TEMPLATE), FALSE); =20 if ((XhcDequeue & (~0x0F)) !=3D (PhyAddr & (~0x0F))) { // @@ -1213,7 +1213,8 @@ XhcPeiInitializeDeviceSlot ( PhyAddr =3D UsbHcGetPciAddrForHostAddr ( Xhc->MemPool, ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].Endpoint= TransferRing[0])->RingSeg0, - sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER + sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER, + TRUE ); InputContext->EP[0].PtrLo =3D XHC_LOW_32BIT (PhyAddr) | BIT0; InputContext->EP[0].PtrHi =3D XHC_HIGH_32BIT (PhyAddr); @@ -1231,7 +1232,7 @@ XhcPeiInitializeDeviceSlot ( // 7) Load the appropriate (Device Slot ID) entry in the Device Context = Base Address Array (5.4.6) with // a pointer to the Output Device Context data structure (6.2.1). // - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, siz= eof (DEVICE_CONTEXT)); + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, siz= eof (DEVICE_CONTEXT), TRUE); // // Fill DCBAA with PCI device address // @@ -1246,7 +1247,7 @@ XhcPeiInitializeDeviceSlot ( // MicroSecondDelay (XHC_RESET_RECOVERY_DELAY); ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr)); - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->U= sbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT)); + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->U= sbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT), TRUE); CmdTrbAddr.PtrLo =3D XHC_LOW_32BIT (PhyAddr); CmdTrbAddr.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); CmdTrbAddr.CycleBit =3D 1; @@ -1427,7 +1428,8 @@ XhcPeiInitializeDeviceSlot64 ( PhyAddr =3D UsbHcGetPciAddrForHostAddr ( Xhc->MemPool, ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].Endpoint= TransferRing[0])->RingSeg0, - sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER + sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER, + TRUE ); InputContext->EP[0].PtrLo =3D XHC_LOW_32BIT (PhyAddr) | BIT0; InputContext->EP[0].PtrHi =3D XHC_HIGH_32BIT (PhyAddr); @@ -1445,7 +1447,7 @@ XhcPeiInitializeDeviceSlot64 ( // 7) Load the appropriate (Device Slot ID) entry in the Device Context = Base Address Array (5.4.6) with // a pointer to the Output Device Context data structure (6.2.1). // - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, siz= eof (DEVICE_CONTEXT_64)); + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, siz= eof (DEVICE_CONTEXT_64), TRUE); // // Fill DCBAA with PCI device address // @@ -1460,7 +1462,7 @@ XhcPeiInitializeDeviceSlot64 ( // MicroSecondDelay (XHC_RESET_RECOVERY_DELAY); ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr)); - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->U= sbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64)); + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->U= sbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64), TRUE); CmdTrbAddr.PtrLo =3D XHC_LOW_32BIT (PhyAddr); CmdTrbAddr.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); CmdTrbAddr.CycleBit =3D 1; @@ -1882,7 +1884,8 @@ XhcPeiSetConfigCmd ( PhyAddr =3D UsbHcGetPciAddrForHostAddr ( Xhc->MemPool, ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].Endp= ointTransferRing[Dci-1])->RingSeg0, - sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER + sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER, + TRUE ); PhyAddr &=3D ~((EFI_PHYSICAL_ADDRESS)0x0F); PhyAddr |=3D (EFI_PHYSICAL_ADDRESS)((TRANSFER_R= ING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingP= CS; @@ -1901,7 +1904,7 @@ XhcPeiSetConfigCmd ( // configure endpoint // ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT)); + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT), TRUE); CmdTrbCfgEP.PtrLo =3D XHC_LOW_32BIT (PhyAddr); CmdTrbCfgEP.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); CmdTrbCfgEP.CycleBit =3D 1; @@ -2108,7 +2111,8 @@ XhcPeiSetConfigCmd64 ( PhyAddr =3D UsbHcGetPciAddrForHostAddr ( Xhc->MemPool, ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].Endp= ointTransferRing[Dci-1])->RingSeg0, - sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER + sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER, + TRUE ); =20 PhyAddr &=3D ~((EFI_PHYSICAL_ADDRESS)0x0F); @@ -2129,7 +2133,7 @@ XhcPeiSetConfigCmd64 ( // configure endpoint // ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT_64)); + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT_64), TRUE); CmdTrbCfgEP.PtrLo =3D XHC_LOW_32BIT (PhyAddr); CmdTrbCfgEP.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); CmdTrbCfgEP.CycleBit =3D 1; @@ -2184,7 +2188,7 @@ XhcPeiEvaluateContext ( InputContext->EP[0].MaxPacketSize =3D MaxPacketSize; =20 ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu)); - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT)); + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT), TRUE); CmdTrbEvalu.PtrLo =3D XHC_LOW_32BIT (PhyAddr); CmdTrbEvalu.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); CmdTrbEvalu.CycleBit =3D 1; @@ -2239,7 +2243,7 @@ XhcPeiEvaluateContext64 ( InputContext->EP[0].MaxPacketSize =3D MaxPacketSize; =20 ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu)); - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT_64)); + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT_64), TRUE); CmdTrbEvalu.PtrLo =3D XHC_LOW_32BIT (PhyAddr); CmdTrbEvalu.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); CmdTrbEvalu.CycleBit =3D 1; @@ -2308,7 +2312,7 @@ XhcPeiConfigHubContext ( InputContext->Slot.MTT =3D MTT; =20 ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT)); + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT), TRUE); CmdTrbCfgEP.PtrLo =3D XHC_LOW_32BIT (PhyAddr); CmdTrbCfgEP.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); CmdTrbCfgEP.CycleBit =3D 1; @@ -2377,7 +2381,7 @@ XhcPeiConfigHubContext64 ( InputContext->Slot.MTT =3D MTT; =20 ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT_64)); + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT_64), TRUE); CmdTrbCfgEP.PtrLo =3D XHC_LOW_32BIT (PhyAddr); CmdTrbCfgEP.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); CmdTrbCfgEP.CycleBit =3D 1; @@ -2522,7 +2526,7 @@ XhcPeiSetTrDequeuePointer ( // Send stop endpoint command to transit Endpoint from running to stop s= tate // ZeroMem (&CmdSetTRDeq, sizeof (CmdSetTRDeq)); - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->= Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER)); + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->= Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER), TRUE); CmdSetTRDeq.PtrLo =3D XHC_LOW_32BIT (PhyAddr) | Urb->Ring->RingPCS; CmdSetTRDeq.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); CmdSetTRDeq.CycleBit =3D 1; @@ -2682,7 +2686,7 @@ XhcPeiCreateEventRing ( ASSERT (((UINTN)Buf & 0x3F) =3D=3D 0); ZeroMem (Buf, Size); =20 - DequeuePhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size); + DequeuePhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size, TRUE= ); =20 EventRing->EventRingSeg0 =3D Buf; EventRing->TrbNumber =3D EVENT_RING_TRB_NUMBER; @@ -2707,7 +2711,7 @@ XhcPeiCreateEventRing ( ERSTBase->PtrHi =3D XHC_HIGH_32BIT (DequeuePhy); ERSTBase->RingTrbSize =3D EVENT_RING_TRB_NUMBER; =20 - ERSTPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size); + ERSTPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size, TRUE); =20 // // Program the Interrupter Event Ring Segment Table Size (ERSTSZ) regist= er (5.5.2.3.1) @@ -2855,7 +2859,7 @@ XhcPeiCreateTransferRing ( // EndTrb =3D (LINK_TRB *)((UINTN)Buf + sizeof (TRB_TEMPLATE) * (Trb= Num - 1)); EndTrb->Type =3D TRB_TYPE_LINK; - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, sizeof = (TRB_TEMPLATE) * TrbNum); + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, sizeof = (TRB_TEMPLATE) * TrbNum, TRUE); EndTrb->PtrLo =3D XHC_LOW_32BIT (PhyAddr); EndTrb->PtrHi =3D XHC_HIGH_32BIT (PhyAddr); // @@ -2988,7 +2992,7 @@ XhcPeiInitSched ( // Some 3rd party XHCI external cards don't support single 64-bytes widt= h register access, // So divide it to two 32-bytes width register access. // - DcbaaPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Dcbaa, Size); + DcbaaPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Dcbaa, Size, TRUE= ); XhcPeiWriteOpReg (Xhc, XHC_DCBAAP_OFFSET, XHC_LOW_32BIT (DcbaaPhy)); XhcPeiWriteOpReg (Xhc, XHC_DCBAAP_OFFSET + 4, XHC_HIGH_32BIT (DcbaaPhy)); =20 @@ -3006,7 +3010,7 @@ XhcPeiInitSched ( // Transfer Ring it checks for a Cycle bit transition. If a transition d= etected, the ring is empty. // So we set RCS as inverted PCS init value to let Command Ring empty // - CmdRingPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->CmdRing.Ri= ngSeg0, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER); + CmdRingPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->CmdRing.Ri= ngSeg0, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER, TRUE); ASSERT ((CmdRingPhy & 0x3F) =3D=3D 0); CmdRingPhy |=3D XHC_CRCR_RCS; // --=20 2.42.0.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#109057): https://edk2.groups.io/g/devel/message/109057 Mute This Topic: https://groups.io/mt/101588610/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-