From nobody Thu Apr 25 19:36:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+89692+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+89692+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1652334338; cv=none; d=zohomail.com; s=zohoarc; b=CJXpqTe+U+SHOTwA3ctMMijD09FPgEIfs+F7VCNYluHo44vC/pH4lWUC7uh1iV07vU/lQQ6TT3ouAJi9bCckFS1JMqBhc2urnXzbejuynt5Va7Bp9Knvf/OZ9og/Ws9rSGQeYXGIi68Zhs3/xfIYtTakWHZB5PyiRXODyaRog20= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652334338; h=Content-Transfer-Encoding:Date:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; bh=4W2+iXw3OdNJBo4Gba6Ds+Cjpz3L2HXa3cNibfpqn+s=; b=ZoOw7sdkxlwgGi1z/yrLIEhIgLBFovll6OZU020PEZy1hb4AdhG83LEx/r+kHemetsKDRlcNrdv89xNwQqXzINWwC8GTCdEVqBj4SAm+DzpYqJTnqdk7MOuGjVviAvvPe9R/jSN6GvzQ7LmRs2hO90JN1w12dEVAngxCELQtHyA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+89692+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 165233433801448.76470485581308; Wed, 11 May 2022 22:45:38 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 0Dv4YY1788612xhvyl5Z1DwN; Wed, 11 May 2022 22:45:37 -0700 X-Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mx.groups.io with SMTP id smtpd.web08.929.1652334335731142201 for ; Wed, 11 May 2022 22:45:36 -0700 X-IronPort-AV: E=McAfee;i="6400,9594,10344"; a="249793357" X-IronPort-AV: E=Sophos;i="5.91,218,1647327600"; d="scan'208";a="249793357" X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2022 22:45:34 -0700 X-IronPort-AV: E=Sophos;i="5.91,218,1647327600"; d="scan'208";a="553627549" X-Received: from cbduggap-mobl1.gar.corp.intel.com ([10.215.202.133]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2022 22:45:33 -0700 From: "cbduggap" To: devel@edk2.groups.io Subject: [edk2-devel] [PATCH] FSP_TEMP_RAM_INIT API call must follow X64 Calling Convention Date: Thu, 12 May 2022 11:14:59 +0530 Message-Id: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chinni.b.duggapu@intel.com X-Gm-Message-State: GEJronKjAwWjI86CflWgBPo7x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1652334337; bh=TvQc7JF2Q4Vj2xaVSdNg5NQUDecm5kU3PwguQu7k8cs=; h=Date:From:Reply-To:Subject:To; b=fG3Q/WEftkMhSCrjBnBXdkl3AN0liiCHSG0aB/S186xJLQnX6tB0Lcc//1IRnn0EC4N E/vcMAUp4Oq1XL2EH3tiNM6/F1cfrBmowL8BTzlyNRitm8y70Voiu62LZ8Ri4aQm6Jk45 bexabCtvjCzHkybCiy+AT4gDRGf4/GUrstg= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1652334338792100003 Content-Type: text/plain; charset="utf-8" This API accept one parameter using RCX and this is consumed in mutiple sub functions. Signed-off-by: cbduggap --- IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 23 +++--- .../Include/SaveRestoreSseAvxNasm.inc | 82 +++++++++++++++++++ 2 files changed, 95 insertions(+), 10 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm b/IntelFsp2Pkg/F= spSecCore/X64/FspApiEntryT.nasm index a9f5f28ed7..4add0ef3fd 100644 --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm @@ -130,10 +130,9 @@ ASM_PFX(LoadMicrocodeDefault): =20 cmp rsp, 0 jz ParamError - mov eax, dword [rsp + 8] ; Parameter pointer - cmp eax, 0 + cmp ecx, 0 jz ParamError - mov esp, eax + mov esp, ecx =20 ; skip loading Microcode if the MicrocodeCodeSize is zero ; and report error if size is less than 2k @@ -321,8 +320,7 @@ ASM_PFX(EstablishStackFsp): ; ; Save parameter pointer in rdx ; - mov rdx, qword [rsp + 8] - + mov rdx, rcx ; ; Enable FSP STACK ; @@ -418,9 +416,12 @@ ASM_PFX(TempRamInitApi): ; ; Ensure both SSE and AVX are enabled ; - ENABLE_SSE + ENABLE_SSE_X64 ENABLE_AVX - + ; + ; Save Input Parameter in YMM10 + ; + SAVE_RCX ; ; Save RBP, RBX, RSI, RDI and RSP in YMM7, YMM8 and YMM6 ; @@ -442,9 +443,8 @@ ASM_PFX(TempRamInitApi): ; ; Check Parameter ; - mov rax, qword [rsp + 8] - cmp rax, 0 - mov rax, 08000000000000002h + cmp rcx, 0 + mov rcx, 08000000000000002h jz TempRamInitExit =20 ; @@ -456,17 +456,20 @@ ASM_PFX(TempRamInitApi): =20 ; Load microcode LOAD_RSP + LOAD_RCX CALL_YMM ASM_PFX(LoadMicrocodeDefault) SAVE_UCODE_STATUS rax ; Save microcode return status in SLOT= 0 in YMM9 (upper 128bits). ; @note If return value rax is not 0, microcode did not load, but contin= ue and attempt to boot. =20 ; Call Sec CAR Init LOAD_RSP + LOAD_RCX CALL_YMM ASM_PFX(SecCarInit) cmp rax, 0 jnz TempRamInitExit =20 LOAD_RSP + LOAD_RCX CALL_YMM ASM_PFX(EstablishStackFsp) cmp rax, 0 jnz TempRamInitExit diff --git a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc b/IntelFsp2Pkg/= Include/SaveRestoreSseAvxNasm.inc index e8bd91669d..fb6df2a18b 100644 --- a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc +++ b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc @@ -177,6 +177,30 @@ LXMMN xmm5, %1, 1 %endmacro =20 +; +; Upper half of YMM10 to save/restore RCX +; +; +; Save RCX to YMM10[128:191] +; Modified: XMM5 and YMM10 +; + +%macro SAVE_RCX 0 + LYMMN ymm10, xmm5, 1 + SXMMN xmm5, 0, rcx + SYMMN ymm10, 1, xmm5 + %endmacro + +; +; Restore RCX from YMM10[128:191] +; Modified: XMM5 and RCX +; + +%macro LOAD_RCX 0 + LYMMN ymm10, xmm5, 1 + movq rcx, xmm5 + %endmacro + ; ; YMM7[128:191] for calling stack ; arg 1:Entry @@ -258,6 +282,7 @@ NextAddress: %endmacro =20 %macro ENABLE_AVX 0 + mov r10, rcx mov eax, 1 cpuid and ecx, 10000000h @@ -280,5 +305,62 @@ EnableAvx: xgetbv ; result in edx:eax or eax, 00000006h ; Set XCR0 bit #1 and bit #2 to enable = SSE state and AVX state xsetbv + mov rcx, r10 %endmacro =20 +%macro ENABLE_SSE_X64 0 + ; + ; Initialize floating point units + ; + jmp NextAddress +align 4 + ; + ; Float control word initial value: + ; all exceptions masked, double-precision, round-to-nearest + ; +FpuControlWord DW 027Fh + ; + ; Multimedia-extensions control word: + ; all exceptions masked, round-to-nearest, flush to zero for m= asked underflow + ; +MmxControlWord DQ 01F80h +SseError: + ; + ; Processor has to support SSE + ; + jmp SseError +NextAddress: + finit + mov rax, FpuControlWord + fldcw [rax] + + ; + ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] =3D 1) to t= est + ; whether the processor supports SSE instruction. + ; + mov r10, rcx + mov rax, 1 + cpuid + bt rdx, 25 + jnc SseError + + ; + ; SSE 4.1 support + ; + bt ecx, 19 + jnc SseError + mov rcx, r10 + ; + ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10) + ; + mov rax, cr4 + or rax, 00000600h + mov cr4, rax + + ; + ; The processor should support SSE instruction and we can use + ; ldmxcsr instruction + ; + mov rax, MmxControlWord + ldmxcsr [rax] + %endmacro \ No newline at end of file --=20 2.36.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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