From: caiyuqing379 <202235273@mail.sdu.edu.cn>
This module supports Sophgo SG2042 EVB platform. It uses the
PEI less design. Add this module in SG2042Pkg leveraging the
one from OvmfPkg/RiscVVirt.
Signed-off-by: caiyuqing379 <202235273@mail.sdu.edu.cn>
Co-authored-by: USER0FISH <libing1202@outlook.com>
Cc: dahogn <dahogn@hotmail.com>
Cc: meng-cz <mengcz1126@gmail.com>
Cc: yli147 <yong.li@intel.com>
Cc: ChaiEvan <evan.chai@intel.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
---
Silicon/Sophgo/SG2042Pkg/Sec/SecMain.inf | 68 +++++
Silicon/Sophgo/SG2042Pkg/Sec/SecMain.h | 104 +++++++
Silicon/Sophgo/SG2042Pkg/Sec/Cpu.c | 29 ++
Silicon/Sophgo/SG2042Pkg/Sec/Memory.c | 347 +++++++++++++++++++++++
Silicon/Sophgo/SG2042Pkg/Sec/Platform.c | 130 +++++++++
Silicon/Sophgo/SG2042Pkg/Sec/SecMain.c | 115 ++++++++
Silicon/Sophgo/SG2042Pkg/Sec/SecEntry.S | 18 ++
7 files changed, 811 insertions(+)
create mode 100644 Silicon/Sophgo/SG2042Pkg/Sec/SecMain.inf
create mode 100644 Silicon/Sophgo/SG2042Pkg/Sec/SecMain.h
create mode 100644 Silicon/Sophgo/SG2042Pkg/Sec/Cpu.c
create mode 100644 Silicon/Sophgo/SG2042Pkg/Sec/Memory.c
create mode 100644 Silicon/Sophgo/SG2042Pkg/Sec/Platform.c
create mode 100644 Silicon/Sophgo/SG2042Pkg/Sec/SecMain.c
create mode 100644 Silicon/Sophgo/SG2042Pkg/Sec/SecEntry.S
diff --git a/Silicon/Sophgo/SG2042Pkg/Sec/SecMain.inf b/Silicon/Sophgo/SG2042Pkg/Sec/SecMain.inf
new file mode 100644
index 000000000000..3b4d6d6b86bc
--- /dev/null
+++ b/Silicon/Sophgo/SG2042Pkg/Sec/SecMain.inf
@@ -0,0 +1,68 @@
+## @file
+# SEC Driver for RISC-V
+#
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
+# Copyright (c) 2023, Academy of Intelligent Innovation, Shandong Universiy, China.P.R. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = SecMainRiscV64
+ FILE_GUID = 125E1236-9D4F-457B-BF7E-6311C88A1621
+ MODULE_TYPE = SEC
+ VERSION_STRING = 1.0
+ ENTRY_POINT = SecMain
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ SecEntry.S
+ SecMain.c
+ SecMain.h
+ Cpu.c
+ Memory.c
+ Platform.c
+
+[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+ Silicon/Sophgo/SG2042Pkg/SG2042Pkg.dec
+ Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ PcdLib
+ IoLib
+ PeCoffLib
+ LzmaDecompressLib
+ RiscVSbiLib
+ PrePiLib
+ FdtLib
+ MemoryAllocationLib
+ HobLib
+ SerialPortLib
+
+[FixedPcd]
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase ## CONSUMES
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize ## CONSUMES
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress ## CONSUMES
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize ## CONSUMES
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES
+
+[Guids]
+ gFdtHobGuid ## PRODUCES
+
+[BuildOptions]
+ GCC:*_*_*_PP_FLAGS = -D__ASSEMBLY__
+
diff --git a/Silicon/Sophgo/SG2042Pkg/Sec/SecMain.h b/Silicon/Sophgo/SG2042Pkg/Sec/SecMain.h
new file mode 100644
index 000000000000..9d615e9fa6a1
--- /dev/null
+++ b/Silicon/Sophgo/SG2042Pkg/Sec/SecMain.h
@@ -0,0 +1,104 @@
+/** @file
+ Master header file for SecCore.
+
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
+ Copyright (c) 2023, Academy of Intelligent Innovation, Shandong Universiy, China.P.R. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef SEC_MAIN_H_
+#define SEC_MAIN_H_
+
+#include <PiPei.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugAgentLib.h>
+#include <Library/DebugLib.h>
+#include <Library/ExtractGuidedSectionLib.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PeCoffExtraActionLib.h>
+#include <Library/PeCoffGetEntryPointLib.h>
+#include <Library/PeCoffLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PeiServicesTablePointerLib.h>
+#include <Library/DebugPrintErrorLevelLib.h>
+#include <Library/PrintLib.h>
+#include <Library/BaseRiscVSbiLib.h>
+#include <Library/PrePiLib.h>
+#include <Library/PrePiHobListPointerLib.h>
+#include <Library/SerialPortLib.h>
+#include <Register/RiscV64/RiscVImpl.h>
+
+/**
+ Entry point to the C language phase of SEC. After the SEC assembly
+ code has initialized some temporary memory and set up the stack,
+ the control is transferred to this function.
+
+ @param SizeOfRam Size of the temporary memory available for use.
+ @param TempRamBase Base address of temporary ram
+ @param BootFirmwareVolume Base address of the Boot Firmware Volume.
+**/
+VOID
+NORETURN
+EFIAPI
+SecStartup (
+ IN UINTN BootHartId,
+ IN VOID *DeviceTreeAddress
+ );
+
+/**
+ Auto-generated function that calls the library constructors for all of the module's
+ dependent libraries. This function must be called by the SEC Core once a stack has
+ been established.
+
+**/
+VOID
+EFIAPI
+ProcessLibraryConstructorList (
+ VOID
+ );
+
+/**
+ Perform Platform PEIM initialization.
+
+ @return EFI_SUCCESS The platform initialized successfully.
+ @retval Others - As the error code indicates
+
+**/
+EFI_STATUS
+EFIAPI
+PlatformPeimInitialization (
+ IN VOID *DeviceTreeAddress
+ );
+
+/**
+ Perform Memory PEIM initialization.
+
+ @param DeviceTreeAddress Pointer to FDT.
+ @return EFI_SUCCESS The platform initialized successfully.
+ @retval Others - As the error code indicates
+
+**/
+EFI_STATUS
+EFIAPI
+MemoryPeimInitialization (
+ IN VOID *DeviceTreeAddress
+ );
+
+/**
+ Perform CPU PEIM initialization.
+
+ @return EFI_SUCCESS The platform initialized successfully.
+ @retval Others - As the error code indicates
+
+**/
+EFI_STATUS
+EFIAPI
+CpuPeimInitialization (
+ VOID
+ );
+
+#endif
diff --git a/Silicon/Sophgo/SG2042Pkg/Sec/Cpu.c b/Silicon/Sophgo/SG2042Pkg/Sec/Cpu.c
new file mode 100644
index 000000000000..c72bafdcc478
--- /dev/null
+++ b/Silicon/Sophgo/SG2042Pkg/Sec/Cpu.c
@@ -0,0 +1,29 @@
+/** @file
+The library call to pass the device tree to DXE via HOB.
+
+Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+
+/**
+ Cpu Peim initialization.
+
+**/
+EFI_STATUS
+CpuPeimInitialization (
+ VOID
+ )
+{
+ //
+ // for MMU type >= sv39
+ //
+ BuildCpuHob (40, 39);
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Sophgo/SG2042Pkg/Sec/Memory.c b/Silicon/Sophgo/SG2042Pkg/Sec/Memory.c
new file mode 100644
index 000000000000..3fa4df148ad2
--- /dev/null
+++ b/Silicon/Sophgo/SG2042Pkg/Sec/Memory.c
@@ -0,0 +1,347 @@
+/** @file
+ Memory Detection for SG2042 EVB.
+
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2023, Academy of Intelligent Innovation, Shandong Universiy, China.P.R. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+Module Name:
+
+ MemDetect.c
+
+**/
+
+#include <PiPei.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PeimEntryPoint.h>
+#include <Library/ResourcePublicationLib.h>
+#include <Register/RiscV64/RiscVEncoding.h>
+#include <Library/PrePiLib.h>
+#include <libfdt.h>
+#include <Guid/FdtHob.h>
+
+VOID
+BuildMemoryTypeInformationHob (
+ VOID
+ );
+
+/**
+ Create memory range resource HOB using the memory base
+ address and size.
+
+ @param MemoryBase Memory range base address.
+ @param MemorySize Memory range size.
+
+**/
+STATIC
+VOID
+AddMemoryBaseSizeHob (
+ IN EFI_PHYSICAL_ADDRESS MemoryBase,
+ IN UINT64 MemorySize
+ )
+{
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED,
+ MemoryBase,
+ MemorySize
+ );
+}
+
+/**
+ Create memory range resource HOB using memory base
+ address and top address of the memory range.
+
+ @param MemoryBase Memory range base address.
+ @param MemoryLimit Memory range size.
+
+**/
+STATIC
+VOID
+AddMemoryRangeHob (
+ IN EFI_PHYSICAL_ADDRESS MemoryBase,
+ IN EFI_PHYSICAL_ADDRESS MemoryLimit
+ )
+{
+ AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
+}
+
+/**
+ Publish system RAM and reserve memory regions.
+
+**/
+STATIC
+VOID
+InitializeRamRegions (
+ IN EFI_PHYSICAL_ADDRESS SystemMemoryBase,
+ IN UINT64 SystemMemorySize
+ )
+{
+ AddMemoryRangeHob (
+ SystemMemoryBase,
+ SystemMemoryBase + SystemMemorySize
+ );
+}
+
+/** Get the number of cells for a given property
+
+ @param[in] Fdt Pointer to Device Tree (DTB)
+ @param[in] Node Node
+ @param[in] Name Name of the property
+
+ @return Number of cells.
+**/
+STATIC
+INT32
+GetNumCells (
+ IN VOID *Fdt,
+ IN INT32 Node,
+ IN CONST CHAR8 *Name
+ )
+{
+ CONST INT32 *Prop;
+ INT32 Len;
+ UINT32 Val;
+
+ Prop = fdt_getprop (Fdt, Node, Name, &Len);
+ if (Prop == NULL) {
+ return Len;
+ }
+
+ if (Len != sizeof (*Prop)) {
+ return -FDT_ERR_BADNCELLS;
+ }
+
+ Val = fdt32_to_cpu (*Prop);
+ if (Val > FDT_MAX_NCELLS) {
+ return -FDT_ERR_BADNCELLS;
+ }
+
+ return (INT32)Val;
+}
+
+/** Mark reserved memory ranges in the EFI memory map
+
+ * As per DT spec v0.4 Section 3.5.4,
+ * "Reserved regions with the no-map property must be listed in the
+ * memory map with type EfiReservedMemoryType. All other reserved
+ * regions must be listed with type EfiBootServicesData."
+
+ @param FdtPointer Pointer to FDT
+
+**/
+STATIC
+VOID
+AddReservedMemoryMap (
+ IN VOID *FdtPointer
+ )
+{
+ CONST INT32 *RegProp;
+ INT32 Node;
+ INT32 SubNode;
+ INT32 Len;
+ EFI_PHYSICAL_ADDRESS Addr;
+ UINT64 Size;
+ INTN NumRsv, i;
+ INT32 NumAddrCells, NumSizeCells;
+
+ NumRsv = fdt_num_mem_rsv (FdtPointer);
+
+ /* Look for an existing entry and add it to the efi mem map. */
+ for (i = 0; i < NumRsv; i++) {
+ if (fdt_get_mem_rsv (FdtPointer, i, &Addr, &Size) != 0) {
+ continue;
+ }
+
+ BuildMemoryAllocationHob (
+ Addr,
+ Size,
+ EfiReservedMemoryType
+ );
+ }
+
+ /* process reserved-memory */
+ Node = fdt_subnode_offset (FdtPointer, 0, "reserved-memory");
+ if (Node >= 0) {
+ NumAddrCells = GetNumCells (FdtPointer, Node, "#address-cells");
+ if (NumAddrCells <= 0) {
+ return;
+ }
+
+ NumSizeCells = GetNumCells (FdtPointer, Node, "#size-cells");
+ if (NumSizeCells <= 0) {
+ return;
+ }
+
+ fdt_for_each_subnode (SubNode, FdtPointer, Node) {
+ RegProp = fdt_getprop (FdtPointer, SubNode, "reg", &Len);
+
+ if ((RegProp != 0) && (Len == ((NumAddrCells + NumSizeCells) * sizeof (INT32)))) {
+ Addr = fdt32_to_cpu (RegProp[0]);
+
+ if (NumAddrCells > 1) {
+ Addr = (Addr << 32) | fdt32_to_cpu (RegProp[1]);
+ }
+
+ RegProp += NumAddrCells;
+ Size = fdt32_to_cpu (RegProp[0]);
+
+ if (NumSizeCells > 1) {
+ Size = (Size << 32) | fdt32_to_cpu (RegProp[1]);
+ }
+
+ DEBUG ((
+ DEBUG_INFO,
+ "%a: Adding Reserved Memory Addr = 0x%llx, Size = 0x%llx\n",
+ __func__,
+ Addr,
+ Size
+ ));
+
+ if (fdt_getprop (FdtPointer, SubNode, "no-map", &Len)) {
+ BuildMemoryAllocationHob (
+ Addr,
+ Size,
+ EfiReservedMemoryType
+ );
+ } else {
+ BuildMemoryAllocationHob (
+ Addr,
+ Size,
+ EfiBootServicesData
+ );
+ }
+ }
+ }
+ }
+}
+
+/**
+ Initialize memory hob based on the DTB information.
+
+ NOTE: The memory space size of SG2042 EVB is determined by the number
+ and size of DDRs inserted on the board. There is an error with initializing
+ the system ram space of each memory node separately using InitializeRamRegions,
+ so InitializeRamRegions is only called once for total system ram initialization.
+
+ @param DeviceTreeAddress Pointer to FDT.
+ @return EFI_SUCCESS The memory hob added successfully.
+
+**/
+EFI_STATUS
+MemoryPeimInitialization (
+ IN VOID *DeviceTreeAddress
+ )
+{
+ CONST UINT64 *RegProp;
+ CONST CHAR8 *Type;
+ UINT64 UefiMemoryBase;
+ UINT64 CurBase;
+ UINT64 CurSize;
+ UINT64 LongestStart;
+ UINT64 LongestLength;
+ UINT64 PrevEnd;
+ UINT64 CurStart;
+ UINT64 CurLength;
+ UINT64 MaxLength;
+ INT32 Node;
+ INT32 Prev;
+ INT32 Len;
+
+ UefiMemoryBase = (UINT64)FixedPcdGet32 (PcdTemporaryRamBase) + FixedPcdGet32 (PcdTemporaryRamSize) - SIZE_32MB;
+ LongestStart = 0;
+ LongestLength = 0;
+ PrevEnd = 0;
+ CurStart = 0;
+ CurLength = 0;
+ MaxLength = 0;
+
+ // Look for the lowest memory node
+ for (Prev = 0; ; Prev = Node) {
+ Node = fdt_next_node (DeviceTreeAddress, Prev, NULL);
+ if (Node < 0) {
+ break;
+ }
+
+ // Check for memory node
+ Type = fdt_getprop (DeviceTreeAddress, Node, "device_type", &Len);
+ if (Type && (AsciiStrnCmp (Type, "memory", Len) == 0)) {
+ // Get the 'reg' property of this node. For now, we will assume
+ // two 8 byte quantities for base and size, respectively.
+ RegProp = fdt_getprop (DeviceTreeAddress, Node, "reg", &Len);
+ if ((RegProp != 0) && (Len == (2 * sizeof (UINT64)))) {
+ CurBase = fdt64_to_cpu (ReadUnaligned64 (RegProp));
+ CurSize = fdt64_to_cpu (ReadUnaligned64 (RegProp + 1));
+
+ DEBUG ((
+ DEBUG_INFO,
+ "%a: System RAM @ 0x%lx - 0x%lx\n",
+ __func__,
+ CurBase,
+ CurBase + CurSize - 1
+ ));
+
+ if (PrevEnd == 0 || CurBase == PrevEnd) {
+ if (CurLength == 0) {
+ CurStart = CurBase;
+ }
+ CurLength += CurSize;
+
+ if (CurLength > MaxLength) {
+ MaxLength = CurLength;
+ LongestStart = CurStart;
+ LongestLength = MaxLength;
+ }
+ } else {
+ CurStart = CurBase;
+ CurLength = CurSize;
+ }
+
+ PrevEnd = CurBase + CurSize;
+
+ } else {
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: Failed to parse FDT memory node\n",
+ __func__
+ ));
+ }
+ }
+ }
+
+ if (UefiMemoryBase > LongestStart) {
+ LongestStart = UefiMemoryBase;
+ LongestLength -= UefiMemoryBase;
+ }
+
+ DEBUG ((
+ DEBUG_INFO,
+ "%a: Total System RAM @ 0x%lx - 0x%lx\n",
+ __func__,
+ LongestStart,
+ LongestStart + LongestLength - 1
+ ));
+
+ InitializeRamRegions (LongestStart, LongestLength);
+
+ AddReservedMemoryMap (DeviceTreeAddress);
+
+ /* Make sure SEC is booting with bare mode */
+ ASSERT ((RiscVGetSupervisorAddressTranslationRegister () & SATP64_MODE) == (SATP_MODE_OFF << SATP64_MODE_SHIFT));
+
+ BuildMemoryTypeInformationHob ();
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Sophgo/SG2042Pkg/Sec/Platform.c b/Silicon/Sophgo/SG2042Pkg/Sec/Platform.c
new file mode 100644
index 000000000000..21885a956088
--- /dev/null
+++ b/Silicon/Sophgo/SG2042Pkg/Sec/Platform.c
@@ -0,0 +1,130 @@
+/** @file
+The library call to pass the device tree to DXE via HOB.
+
+Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Include/Library/PrePiLib.h>
+#include <libfdt.h>
+#include <Guid/FdtHob.h>
+
+/**
+ Build memory map I/O range resource HOB using the
+ base address and size.
+
+ @param MemoryBase Memory map I/O base.
+ @param MemorySize Memory map I/O size.
+
+**/
+STATIC
+VOID
+AddIoMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ )
+{
+ /* Align to EFI_PAGE_SIZE */
+ MemorySize = ALIGN_VALUE (MemorySize, EFI_PAGE_SIZE);
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_MEMORY_MAPPED_IO,
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED,
+ MemoryBase,
+ MemorySize
+ );
+}
+
+/**
+ Populate IO resources from FDT that not added to GCD by its
+ driver in the DXE phase.
+
+ @param FdtBase Fdt base address
+ @param Compatible Compatible string
+
+**/
+STATIC
+VOID
+PopulateIoResources (
+ VOID *FdtBase,
+ CONST CHAR8 *Compatible
+ )
+{
+ UINT64 *Reg;
+ INT32 Node, LenP;
+
+ Node = fdt_node_offset_by_compatible (FdtBase, -1, Compatible);
+ while (Node != -FDT_ERR_NOTFOUND) {
+ Reg = (UINT64 *)fdt_getprop (FdtBase, Node, "reg", &LenP);
+ if (Reg) {
+ ASSERT (LenP == (2 * sizeof (UINT64)));
+ AddIoMemoryBaseSizeHob (SwapBytes64 (Reg[0]), SwapBytes64 (Reg[1]));
+ }
+
+ Node = fdt_node_offset_by_compatible (FdtBase, Node, Compatible);
+ }
+}
+
+/**
+ @param DeviceTreeAddress Pointer to FDT.
+ @retval EFI_SUCCESS The address of FDT is passed in HOB.
+ EFI_UNSUPPORTED Can't locate FDT.
+**/
+EFI_STATUS
+EFIAPI
+PlatformPeimInitialization (
+ IN VOID *DeviceTreeAddress
+ )
+{
+ VOID *Base;
+ VOID *NewBase;
+ UINTN FdtSize;
+ UINTN FdtPages;
+ UINT64 *FdtHobData;
+
+ if (DeviceTreeAddress == NULL) {
+ DEBUG ((DEBUG_ERROR, "%a: Invalid FDT pointer\n", __func__));
+ return EFI_UNSUPPORTED;
+ }
+
+ DEBUG ((DEBUG_INFO, "%a: Build FDT HOB - FDT at address: 0x%x \n", __func__, DeviceTreeAddress));
+ Base = DeviceTreeAddress;
+ if (fdt_check_header (Base) != 0) {
+ DEBUG ((DEBUG_ERROR, "%a: Corrupted DTB\n", __func__));
+ return EFI_UNSUPPORTED;
+ }
+
+ FdtSize = fdt_totalsize (Base);
+ FdtPages = EFI_SIZE_TO_PAGES (FdtSize);
+ NewBase = AllocatePages (FdtPages);
+ if (NewBase == NULL) {
+ DEBUG ((DEBUG_ERROR, "%a: Could not allocate memory for DTB\n", __func__));
+ return EFI_UNSUPPORTED;
+ }
+
+ fdt_open_into (Base, NewBase, EFI_PAGES_TO_SIZE (FdtPages));
+
+ FdtHobData = BuildGuidHob (&gFdtHobGuid, sizeof *FdtHobData);
+ if (FdtHobData == NULL) {
+ DEBUG ((DEBUG_ERROR, "%a: Could not build FDT Hob\n", __func__));
+ return EFI_UNSUPPORTED;
+ }
+
+ *FdtHobData = (UINTN)NewBase;
+
+ BuildFvHob (PcdGet32 (PcdRiscVDxeFvBase), PcdGet32 (PcdRiscVDxeFvSize));
+
+ PopulateIoResources (Base, "bitmain,bm-sd");
+ PopulateIoResources (Base, "snps,dw-apb-uart");
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Sophgo/SG2042Pkg/Sec/SecMain.c b/Silicon/Sophgo/SG2042Pkg/Sec/SecMain.c
new file mode 100644
index 000000000000..a75b8b819737
--- /dev/null
+++ b/Silicon/Sophgo/SG2042Pkg/Sec/SecMain.c
@@ -0,0 +1,115 @@
+/** @file
+ RISC-V SEC phase module for SG2042 EVB.
+
+ Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
+ Copyright (c) 2023, Academy of Intelligent Innovation, Shandong Universiy, China.P.R. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "SecMain.h"
+
+/**
+ Initialize the memory and CPU, setting the boot mode, and platform
+ initialization. It also builds the core information HOB.
+
+ @return EFI_SUCCESS Status.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+SecInitializePlatform (
+ IN VOID *DeviceTreeAddress
+ )
+{
+ EFI_STATUS Status;
+
+ MemoryPeimInitialization (DeviceTreeAddress);
+
+ CpuPeimInitialization ();
+
+ // Set the Boot Mode
+ SetBootMode (BOOT_WITH_FULL_CONFIGURATION);
+
+ Status = PlatformPeimInitialization (DeviceTreeAddress);
+ ASSERT_EFI_ERROR (Status);
+
+ return EFI_SUCCESS;
+}
+
+/**
+
+ Entry point to the C language phase of SEC. After the SEC assembly
+ code has initialized some temporary memory and set up the stack,
+ the control is transferred to this function.
+
+
+ @param[in] BootHartId Hardware thread ID of boot hart.
+ @param[in] DeviceTreeAddress Pointer to Device Tree (DTB)
+**/
+VOID
+NORETURN
+EFIAPI
+SecStartup (
+ IN UINTN BootHartId,
+ IN VOID *DeviceTreeAddress
+ )
+{
+ EFI_HOB_HANDOFF_INFO_TABLE *HobList;
+ EFI_RISCV_FIRMWARE_CONTEXT FirmwareContext;
+ EFI_STATUS Status;
+ UINT64 UefiMemoryBase;
+ UINT64 StackBase;
+ UINT32 StackSize;
+
+ SerialPortInitialize ();
+
+ //
+ // Report Status Code to indicate entering SEC core
+ //
+ DEBUG ((
+ DEBUG_INFO,
+ "%a() BootHartId: 0x%x, DeviceTreeAddress=0x%x\n",
+ __func__,
+ BootHartId,
+ DeviceTreeAddress
+ ));
+
+ FirmwareContext.BootHartId = BootHartId;
+ SetFirmwareContextPointer (&FirmwareContext);
+
+ StackBase = (UINT64)FixedPcdGet32 (PcdTemporaryRamBase);
+ StackSize = FixedPcdGet32 (PcdTemporaryRamSize);
+ UefiMemoryBase = StackBase + StackSize - SIZE_32MB;
+
+ // Declare the PI/UEFI memory region
+ HobList = HobConstructor (
+ (VOID *)UefiMemoryBase,
+ SIZE_32MB,
+ (VOID *)UefiMemoryBase,
+ (VOID *)StackBase // The top of the UEFI Memory is reserved for the stacks
+ );
+ PrePeiSetHobList (HobList);
+
+ SecInitializePlatform (DeviceTreeAddress);
+
+ BuildStackHob (StackBase, StackSize);
+
+ //
+ // Process all libraries constructor function linked to SecMain.
+ //
+ ProcessLibraryConstructorList ();
+
+ // Assume the FV that contains the SEC (our code) also contains a compressed FV.
+ Status = DecompressFirstFv ();
+ ASSERT_EFI_ERROR (Status);
+
+ // Load the DXE Core and transfer control to it
+ Status = LoadDxeCoreFromFv (NULL, 0);
+ ASSERT_EFI_ERROR (Status);
+ //
+ // Should not come here.
+ //
+ UNREACHABLE ();
+}
diff --git a/Silicon/Sophgo/SG2042Pkg/Sec/SecEntry.S b/Silicon/Sophgo/SG2042Pkg/Sec/SecEntry.S
new file mode 100644
index 000000000000..ee02317a6bc8
--- /dev/null
+++ b/Silicon/Sophgo/SG2042Pkg/Sec/SecEntry.S
@@ -0,0 +1,18 @@
+/*
+ Copyright (c) 2022 Ventana Micro Systems Inc.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ */
+
+#include "SecMain.h"
+
+ASM_FUNC (_ModuleEntryPoint)
+ /* Use Temp memory as the stack for calling to C code */
+ li a4, FixedPcdGet32 (PcdTemporaryRamBase)
+ li a5, FixedPcdGet32 (PcdTemporaryRamSize)
+
+ /* Use Temp memory as the stack for calling to C code */
+ add sp, a4, a5
+
+ call SecStartup
--
2.34.1
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-=-=-=-=-=-=-=-=-=-=-=-On Thu, Sep 07, 2023 at 06:25:48PM +0800, caiyuqing_hz@163.com wrote:
> From: caiyuqing379 <202235273@mail.sdu.edu.cn>
>
> This module supports Sophgo SG2042 EVB platform. It uses the
> PEI less design. Add this module in SG2042Pkg leveraging the
> one from OvmfPkg/RiscVVirt.
>
> Signed-off-by: caiyuqing379 <202235273@mail.sdu.edu.cn>
> Co-authored-by: USER0FISH <libing1202@outlook.com>
> Cc: dahogn <dahogn@hotmail.com>
> Cc: meng-cz <mengcz1126@gmail.com>
> Cc: yli147 <yong.li@intel.com>
> Cc: ChaiEvan <evan.chai@intel.com>
> Cc: Sunil V L <sunilvl@ventanamicro.com>
> Cc: Leif Lindholm <quic_llindhol@quicinc.com>
> ---
> Silicon/Sophgo/SG2042Pkg/Sec/SecMain.inf | 68 +++++
> Silicon/Sophgo/SG2042Pkg/Sec/SecMain.h | 104 +++++++
> Silicon/Sophgo/SG2042Pkg/Sec/Cpu.c | 29 ++
> Silicon/Sophgo/SG2042Pkg/Sec/Memory.c | 347 +++++++++++++++++++++++
> Silicon/Sophgo/SG2042Pkg/Sec/Platform.c | 130 +++++++++
> Silicon/Sophgo/SG2042Pkg/Sec/SecMain.c | 115 ++++++++
> Silicon/Sophgo/SG2042Pkg/Sec/SecEntry.S | 18 ++
> 7 files changed, 811 insertions(+)
> create mode 100644 Silicon/Sophgo/SG2042Pkg/Sec/SecMain.inf
> create mode 100644 Silicon/Sophgo/SG2042Pkg/Sec/SecMain.h
> create mode 100644 Silicon/Sophgo/SG2042Pkg/Sec/Cpu.c
> create mode 100644 Silicon/Sophgo/SG2042Pkg/Sec/Memory.c
> create mode 100644 Silicon/Sophgo/SG2042Pkg/Sec/Platform.c
> create mode 100644 Silicon/Sophgo/SG2042Pkg/Sec/SecMain.c
> create mode 100644 Silicon/Sophgo/SG2042Pkg/Sec/SecEntry.S
>
> diff --git a/Silicon/Sophgo/SG2042Pkg/Sec/SecMain.inf b/Silicon/Sophgo/SG2042Pkg/Sec/SecMain.inf
> new file mode 100644
> index 000000000000..3b4d6d6b86bc
> --- /dev/null
> +++ b/Silicon/Sophgo/SG2042Pkg/Sec/SecMain.inf
> @@ -0,0 +1,68 @@
> +## @file
> +# SEC Driver for RISC-V
> +#
> +# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
> +# Copyright (c) 2023, Academy of Intelligent Innovation, Shandong Universiy, China.P.R. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x0001001B
> + BASE_NAME = SecMainRiscV64
> + FILE_GUID = 125E1236-9D4F-457B-BF7E-6311C88A1621
> + MODULE_TYPE = SEC
> + VERSION_STRING = 1.0
> + ENTRY_POINT = SecMain
> +
> +#
> +# The following information is for reference only and not required by the build tools.
> +#
> +# VALID_ARCHITECTURES = RISCV64
> +#
> +
> +[Sources]
> + SecEntry.S
> + SecMain.c
> + SecMain.h
> + Cpu.c
> + Memory.c
> + Platform.c
> +
> +[Packages]
> + EmbeddedPkg/EmbeddedPkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + MdePkg/MdePkg.dec
> + UefiCpuPkg/UefiCpuPkg.dec
> + Silicon/Sophgo/SG2042Pkg/SG2042Pkg.dec
> + Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
> +
> +[LibraryClasses]
> + BaseLib
> + DebugLib
> + PcdLib
> + IoLib
> + PeCoffLib
> + LzmaDecompressLib
> + RiscVSbiLib
> + PrePiLib
> + FdtLib
> + MemoryAllocationLib
> + HobLib
> + SerialPortLib
> +
> +[FixedPcd]
> + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase ## CONSUMES
> + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize ## CONSUMES
> + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress ## CONSUMES
> + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize ## CONSUMES
> + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES
> + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES
> +
> +[Guids]
> + gFdtHobGuid ## PRODUCES
> +
> +[BuildOptions]
> + GCC:*_*_*_PP_FLAGS = -D__ASSEMBLY__
> +
> diff --git a/Silicon/Sophgo/SG2042Pkg/Sec/SecMain.h b/Silicon/Sophgo/SG2042Pkg/Sec/SecMain.h
> new file mode 100644
> index 000000000000..9d615e9fa6a1
> --- /dev/null
> +++ b/Silicon/Sophgo/SG2042Pkg/Sec/SecMain.h
> @@ -0,0 +1,104 @@
> +/** @file
> + Master header file for SecCore.
> +
> + Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
> + Copyright (c) 2023, Academy of Intelligent Innovation, Shandong Universiy, China.P.R. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef SEC_MAIN_H_
> +#define SEC_MAIN_H_
> +
> +#include <PiPei.h>
> +#include <Library/BaseLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/DebugAgentLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/ExtractGuidedSectionLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/HobLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/PeCoffExtraActionLib.h>
> +#include <Library/PeCoffGetEntryPointLib.h>
> +#include <Library/PeCoffLib.h>
> +#include <Library/PeiServicesLib.h>
> +#include <Library/PeiServicesTablePointerLib.h>
> +#include <Library/DebugPrintErrorLevelLib.h>
> +#include <Library/PrintLib.h>
> +#include <Library/BaseRiscVSbiLib.h>
> +#include <Library/PrePiLib.h>
> +#include <Library/PrePiHobListPointerLib.h>
> +#include <Library/SerialPortLib.h>
> +#include <Register/RiscV64/RiscVImpl.h>
> +
> +/**
> + Entry point to the C language phase of SEC. After the SEC assembly
> + code has initialized some temporary memory and set up the stack,
> + the control is transferred to this function.
> +
> + @param SizeOfRam Size of the temporary memory available for use.
> + @param TempRamBase Base address of temporary ram
> + @param BootFirmwareVolume Base address of the Boot Firmware Volume.
> +**/
> +VOID
> +NORETURN
> +EFIAPI
> +SecStartup (
> + IN UINTN BootHartId,
> + IN VOID *DeviceTreeAddress
> + );
> +
> +/**
> + Auto-generated function that calls the library constructors for all of the module's
> + dependent libraries. This function must be called by the SEC Core once a stack has
> + been established.
> +
> +**/
> +VOID
> +EFIAPI
> +ProcessLibraryConstructorList (
> + VOID
> + );
> +
> +/**
> + Perform Platform PEIM initialization.
> +
> + @return EFI_SUCCESS The platform initialized successfully.
> + @retval Others - As the error code indicates
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +PlatformPeimInitialization (
> + IN VOID *DeviceTreeAddress
> + );
> +
> +/**
> + Perform Memory PEIM initialization.
> +
> + @param DeviceTreeAddress Pointer to FDT.
> + @return EFI_SUCCESS The platform initialized successfully.
> + @retval Others - As the error code indicates
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +MemoryPeimInitialization (
> + IN VOID *DeviceTreeAddress
> + );
> +
> +/**
> + Perform CPU PEIM initialization.
> +
> + @return EFI_SUCCESS The platform initialized successfully.
> + @retval Others - As the error code indicates
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +CpuPeimInitialization (
> + VOID
> + );
> +
> +#endif
> diff --git a/Silicon/Sophgo/SG2042Pkg/Sec/Cpu.c b/Silicon/Sophgo/SG2042Pkg/Sec/Cpu.c
> new file mode 100644
> index 000000000000..c72bafdcc478
> --- /dev/null
> +++ b/Silicon/Sophgo/SG2042Pkg/Sec/Cpu.c
> @@ -0,0 +1,29 @@
> +/** @file
> +The library call to pass the device tree to DXE via HOB.
> +
> +Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <PiPei.h>
> +#include <Library/DebugLib.h>
> +#include <Library/HobLib.h>
> +
> +/**
> + Cpu Peim initialization.
> +
> +**/
> +EFI_STATUS
> +CpuPeimInitialization (
> + VOID
> + )
> +{
> + //
> + // for MMU type >= sv39
> + //
> + BuildCpuHob (40, 39);
> +
> + return EFI_SUCCESS;
> +}
> diff --git a/Silicon/Sophgo/SG2042Pkg/Sec/Memory.c b/Silicon/Sophgo/SG2042Pkg/Sec/Memory.c
> new file mode 100644
> index 000000000000..3fa4df148ad2
> --- /dev/null
> +++ b/Silicon/Sophgo/SG2042Pkg/Sec/Memory.c
> @@ -0,0 +1,347 @@
> +/** @file
> + Memory Detection for SG2042 EVB.
> +
> + Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> + Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
> + Copyright (c) 2023, Academy of Intelligent Innovation, Shandong Universiy, China.P.R. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +Module Name:
> +
> + MemDetect.c
> +
> +**/
> +
> +#include <PiPei.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/HobLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/PeimEntryPoint.h>
> +#include <Library/ResourcePublicationLib.h>
> +#include <Register/RiscV64/RiscVEncoding.h>
> +#include <Library/PrePiLib.h>
> +#include <libfdt.h>
> +#include <Guid/FdtHob.h>
> +
> +VOID
> +BuildMemoryTypeInformationHob (
> + VOID
> + );
> +
> +/**
> + Create memory range resource HOB using the memory base
> + address and size.
> +
> + @param MemoryBase Memory range base address.
> + @param MemorySize Memory range size.
> +
> +**/
> +STATIC
> +VOID
> +AddMemoryBaseSizeHob (
> + IN EFI_PHYSICAL_ADDRESS MemoryBase,
> + IN UINT64 MemorySize
> + )
> +{
> + BuildResourceDescriptorHob (
> + EFI_RESOURCE_SYSTEM_MEMORY,
> + EFI_RESOURCE_ATTRIBUTE_PRESENT |
> + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
> + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
> + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
> + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
> + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
> + EFI_RESOURCE_ATTRIBUTE_TESTED,
> + MemoryBase,
> + MemorySize
> + );
> +}
> +
> +/**
> + Create memory range resource HOB using memory base
> + address and top address of the memory range.
> +
> + @param MemoryBase Memory range base address.
> + @param MemoryLimit Memory range size.
> +
> +**/
> +STATIC
> +VOID
> +AddMemoryRangeHob (
> + IN EFI_PHYSICAL_ADDRESS MemoryBase,
> + IN EFI_PHYSICAL_ADDRESS MemoryLimit
> + )
> +{
> + AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
> +}
> +
> +/**
> + Publish system RAM and reserve memory regions.
> +
> +**/
> +STATIC
> +VOID
> +InitializeRamRegions (
> + IN EFI_PHYSICAL_ADDRESS SystemMemoryBase,
> + IN UINT64 SystemMemorySize
> + )
> +{
> + AddMemoryRangeHob (
> + SystemMemoryBase,
> + SystemMemoryBase + SystemMemorySize
> + );
> +}
> +
> +/** Get the number of cells for a given property
> +
> + @param[in] Fdt Pointer to Device Tree (DTB)
> + @param[in] Node Node
> + @param[in] Name Name of the property
> +
> + @return Number of cells.
> +**/
> +STATIC
> +INT32
> +GetNumCells (
> + IN VOID *Fdt,
> + IN INT32 Node,
> + IN CONST CHAR8 *Name
> + )
> +{
> + CONST INT32 *Prop;
> + INT32 Len;
> + UINT32 Val;
> +
> + Prop = fdt_getprop (Fdt, Node, Name, &Len);
> + if (Prop == NULL) {
> + return Len;
> + }
> +
> + if (Len != sizeof (*Prop)) {
> + return -FDT_ERR_BADNCELLS;
> + }
> +
> + Val = fdt32_to_cpu (*Prop);
> + if (Val > FDT_MAX_NCELLS) {
> + return -FDT_ERR_BADNCELLS;
> + }
> +
> + return (INT32)Val;
> +}
> +
> +/** Mark reserved memory ranges in the EFI memory map
> +
> + * As per DT spec v0.4 Section 3.5.4,
> + * "Reserved regions with the no-map property must be listed in the
> + * memory map with type EfiReservedMemoryType. All other reserved
> + * regions must be listed with type EfiBootServicesData."
> +
> + @param FdtPointer Pointer to FDT
> +
> +**/
> +STATIC
> +VOID
> +AddReservedMemoryMap (
> + IN VOID *FdtPointer
> + )
> +{
> + CONST INT32 *RegProp;
> + INT32 Node;
> + INT32 SubNode;
> + INT32 Len;
> + EFI_PHYSICAL_ADDRESS Addr;
> + UINT64 Size;
> + INTN NumRsv, i;
> + INT32 NumAddrCells, NumSizeCells;
> +
> + NumRsv = fdt_num_mem_rsv (FdtPointer);
> +
> + /* Look for an existing entry and add it to the efi mem map. */
> + for (i = 0; i < NumRsv; i++) {
> + if (fdt_get_mem_rsv (FdtPointer, i, &Addr, &Size) != 0) {
> + continue;
> + }
> +
> + BuildMemoryAllocationHob (
> + Addr,
> + Size,
> + EfiReservedMemoryType
> + );
> + }
> +
> + /* process reserved-memory */
> + Node = fdt_subnode_offset (FdtPointer, 0, "reserved-memory");
> + if (Node >= 0) {
> + NumAddrCells = GetNumCells (FdtPointer, Node, "#address-cells");
> + if (NumAddrCells <= 0) {
> + return;
> + }
> +
> + NumSizeCells = GetNumCells (FdtPointer, Node, "#size-cells");
> + if (NumSizeCells <= 0) {
> + return;
> + }
> +
> + fdt_for_each_subnode (SubNode, FdtPointer, Node) {
> + RegProp = fdt_getprop (FdtPointer, SubNode, "reg", &Len);
> +
> + if ((RegProp != 0) && (Len == ((NumAddrCells + NumSizeCells) * sizeof (INT32)))) {
> + Addr = fdt32_to_cpu (RegProp[0]);
> +
> + if (NumAddrCells > 1) {
> + Addr = (Addr << 32) | fdt32_to_cpu (RegProp[1]);
> + }
> +
> + RegProp += NumAddrCells;
> + Size = fdt32_to_cpu (RegProp[0]);
> +
> + if (NumSizeCells > 1) {
> + Size = (Size << 32) | fdt32_to_cpu (RegProp[1]);
> + }
> +
> + DEBUG ((
> + DEBUG_INFO,
> + "%a: Adding Reserved Memory Addr = 0x%llx, Size = 0x%llx\n",
> + __func__,
> + Addr,
> + Size
> + ));
> +
> + if (fdt_getprop (FdtPointer, SubNode, "no-map", &Len)) {
Ensure you document that OpenSBI 1.3/1.3.1 should be used which fixed
its no-map issue. Otherwise, you can get into some issues in linux
kernel.
Acked-by: Sunil V L <sunilvl@ventanamicro.com>
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