From: caiyuqing379 <202235273@mail.sdu.edu.cn> Signed-off-by: caiyuqing379 <202235273@mail.sdu.edu.cn> Co-authored-by: USER0FISH <libing1202@outlook.com> Cc: dahogn <dahogn@hotmail.com> Cc: meng-cz <mengcz1126@gmail.com> Cc: yli147 <yong.li@intel.com> Cc: ChaiEvan <evan.chai@intel.com> Cc: Sunil V L <sunilvl@ventanamicro.com> *** BLURB HERE *** caiyuqing379 (8): Sophgo/SG2042Pkg: Add SmbiosPlatformDxe module. Sophgo/SG2042Pkg: Add PlatformUpdateMmuDxe module. Sophgo/SG2042Pkg: Add Sophgo SDHCI driver. Sophgo/SG2042Pkg: Add base MMC driver. Sophgo/SG2042Pkg: Add SEC module. SG2042Pkg/SG2042_EVB_Board: Add Sophgo SG2042 platform. Sophgo/SG2042Pkg: Add SG2042Pkg. Sophgo/SG2042Pkg: Add platform readme and document. Platform/Sophgo/SG2042Pkg/SG2042Pkg.dec | 35 + .../SG2042Pkg/SG2042_EVB_Board/SG2042.dec | 19 + .../SG2042Pkg/SG2042_EVB_Board/SG2042.dsc | 548 +++++++++++ .../SG2042Pkg/SG2042_EVB_Board/SG2042.fdf | 247 +++++ Platform/Sophgo/SG2042Pkg/Sec/SecMain.inf | 68 ++ .../SG2042Pkg/Universal/Dxe/MmcDxe/MmcDxe.inf | 46 + .../PlatformUpdateMmuDxe.inf | 34 + .../Universal/Dxe/SdHostDxe/SdHostDxe.inf | 47 + .../SmbiosPlatformDxe/SmbiosPlatformDxe.inf | 39 + Platform/Sophgo/SG2042Pkg/Include/MmcHost.h | 225 +++++ Platform/Sophgo/SG2042Pkg/Sec/SecMain.h | 103 ++ .../SG2042Pkg/Universal/Dxe/MmcDxe/Mmc.h | 513 ++++++++++ .../SG2042Pkg/Universal/Dxe/SdHostDxe/SdHci.h | 309 ++++++ Platform/Sophgo/SG2042Pkg/Sec/Cpu.c | 29 + Platform/Sophgo/SG2042Pkg/Sec/Memory.c | 363 +++++++ Platform/Sophgo/SG2042Pkg/Sec/Platform.c | 141 +++ Platform/Sophgo/SG2042Pkg/Sec/SecMain.c | 116 +++ .../Universal/Dxe/MmcDxe/ComponentName.c | 156 +++ .../Universal/Dxe/MmcDxe/Diagnostics.c | 323 ++++++ .../SG2042Pkg/Universal/Dxe/MmcDxe/Mmc.c | 527 ++++++++++ .../Universal/Dxe/MmcDxe/MmcBlockIo.c | 643 ++++++++++++ .../SG2042Pkg/Universal/Dxe/MmcDxe/MmcDebug.c | 194 ++++ .../Universal/Dxe/MmcDxe/MmcIdentification.c | 719 ++++++++++++++ .../PlatformUpdateMmuDxe.c | 591 +++++++++++ .../SG2042Pkg/Universal/Dxe/SdHostDxe/SdHci.c | 929 ++++++++++++++++++ .../Universal/Dxe/SdHostDxe/SdHostDxe.c | 450 +++++++++ .../Dxe/SmbiosPlatformDxe/SmbiosPlatformDxe.c | 805 +++++++++++++++ .../Sophgo/SG2042Pkg/About_Sophgo_platform.md | 39 + .../Documents/Media/EDK2_SDU_Programme.png | Bin 0 -> 59830 bytes .../SG2042Pkg/Documents/Media/SG2042_CPU.png | Bin 0 -> 806062 bytes .../Documents/Media/Sophgo_SG2042_EVB.png | Bin 0 -> 1445528 bytes Platform/Sophgo/SG2042Pkg/Maintainers.md | 107 ++ Platform/Sophgo/SG2042Pkg/Readme.md | 79 ++ Platform/Sophgo/SG2042Pkg/SG2042Pkg.uni | 13 + Platform/Sophgo/SG2042Pkg/SG2042PkgExtra.uni | 12 + .../SG2042Pkg/SG2042_EVB_Board/SG2042.fdf.inc | 62 ++ .../SG2042_EVB_Board/VarStore.fdf.inc | 77 ++ Platform/Sophgo/SG2042Pkg/Sec/SecEntry.S | 18 + 38 files changed, 8626 insertions(+) create mode 100644 Platform/Sophgo/SG2042Pkg/SG2042Pkg.dec create mode 100644 Platform/Sophgo/SG2042Pkg/SG2042_EVB_Board/SG2042.dec create mode 100644 Platform/Sophgo/SG2042Pkg/SG2042_EVB_Board/SG2042.dsc create mode 100644 Platform/Sophgo/SG2042Pkg/SG2042_EVB_Board/SG2042.fdf create mode 100644 Platform/Sophgo/SG2042Pkg/Sec/SecMain.inf create mode 100644 Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/MmcDxe.inf create mode 100644 Platform/Sophgo/SG2042Pkg/Universal/Dxe/PlatformUpdateMmuDxe/PlatformUpdateMmuDxe.inf create mode 100644 Platform/Sophgo/SG2042Pkg/Universal/Dxe/SdHostDxe/SdHostDxe.inf create mode 100644 Platform/Sophgo/SG2042Pkg/Universal/Dxe/SmbiosPlatformDxe/SmbiosPlatformDxe.inf create mode 100644 Platform/Sophgo/SG2042Pkg/Include/MmcHost.h create mode 100644 Platform/Sophgo/SG2042Pkg/Sec/SecMain.h create mode 100644 Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/Mmc.h create mode 100644 Platform/Sophgo/SG2042Pkg/Universal/Dxe/SdHostDxe/SdHci.h create mode 100644 Platform/Sophgo/SG2042Pkg/Sec/Cpu.c create mode 100644 Platform/Sophgo/SG2042Pkg/Sec/Memory.c create mode 100644 Platform/Sophgo/SG2042Pkg/Sec/Platform.c create mode 100644 Platform/Sophgo/SG2042Pkg/Sec/SecMain.c create mode 100644 Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/ComponentName.c create mode 100644 Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/Diagnostics.c create mode 100644 Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/Mmc.c create mode 100644 Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/MmcBlockIo.c create mode 100644 Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/MmcDebug.c create mode 100644 Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/MmcIdentification.c create mode 100644 Platform/Sophgo/SG2042Pkg/Universal/Dxe/PlatformUpdateMmuDxe/PlatformUpdateMmuDxe.c create mode 100755 Platform/Sophgo/SG2042Pkg/Universal/Dxe/SdHostDxe/SdHci.c create mode 100644 Platform/Sophgo/SG2042Pkg/Universal/Dxe/SdHostDxe/SdHostDxe.c create mode 100644 Platform/Sophgo/SG2042Pkg/Universal/Dxe/SmbiosPlatformDxe/SmbiosPlatformDxe.c create mode 100644 Platform/Sophgo/SG2042Pkg/About_Sophgo_platform.md create mode 100644 Platform/Sophgo/SG2042Pkg/Documents/Media/EDK2_SDU_Programme.png create mode 100644 Platform/Sophgo/SG2042Pkg/Documents/Media/SG2042_CPU.png create mode 100644 Platform/Sophgo/SG2042Pkg/Documents/Media/Sophgo_SG2042_EVB.png create mode 100644 Platform/Sophgo/SG2042Pkg/Maintainers.md create mode 100644 Platform/Sophgo/SG2042Pkg/Readme.md create mode 100644 Platform/Sophgo/SG2042Pkg/SG2042Pkg.uni create mode 100644 Platform/Sophgo/SG2042Pkg/SG2042PkgExtra.uni create mode 100644 Platform/Sophgo/SG2042Pkg/SG2042_EVB_Board/SG2042.fdf.inc create mode 100644 Platform/Sophgo/SG2042Pkg/SG2042_EVB_Board/VarStore.fdf.inc create mode 100644 Platform/Sophgo/SG2042Pkg/Sec/SecEntry.S -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#108216): https://edk2.groups.io/g/devel/message/108216 Mute This Topic: https://groups.io/mt/101084028/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=- From: caiyuqing379 <202235273@mail.sdu.edu.cn> This driver installs SMBIOS information for SG2042. Install hardware information by creating an SMBIOS table which includes BIOS version, system manufacturer, product name, processor, memory, slots, storage, and other. Signed-off-by: caiyuqing379 <202235273@mail.sdu.edu.cn> Co-authored-by: USER0FISH <libing1202@outlook.com> Cc: dahogn <dahogn@hotmail.com> Cc: meng-cz <mengcz1126@gmail.com> Cc: yli147 <yong.li@intel.com> Cc: ChaiEvan <evan.chai@intel.com> Cc: Sunil V L <sunilvl@ventanamicro.com> --- .../SmbiosPlatformDxe/SmbiosPlatformDxe.inf | 39 + .../Dxe/SmbiosPlatformDxe/SmbiosPlatformDxe.c | 805 ++++++++++++++++++ 2 files changed, 844 insertions(+) create mode 100644 Platform/Sophgo/SG2042Pkg/Universal/Dxe/SmbiosPlatformDxe/SmbiosPlatformDxe.inf create mode 100644 Platform/Sophgo/SG2042Pkg/Universal/Dxe/SmbiosPlatformDxe/SmbiosPlatformDxe.c diff --git a/Platform/Sophgo/SG2042Pkg/Universal/Dxe/SmbiosPlatformDxe/SmbiosPlatformDxe.inf b/Platform/Sophgo/SG2042Pkg/Universal/Dxe/SmbiosPlatformDxe/SmbiosPlatformDxe.inf new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/Sophgo/SG2042Pkg/Universal/Dxe/SmbiosPlatformDxe/SmbiosPlatformDxe.inf @@ -XXX,XX +XXX,XX @@ +#/** @file +# SMBIOS Table for RISC-V Sophgo SG2042 platform +# +# Copyright (c) 2013, Linaro Ltd. All rights reserved.<BR> +# Copyright (c) 2023, Academy of Intelligent Innovation, Shandong Universiy, China.P.R. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001B + BASE_NAME = SmbiosPlatformDxe + FILE_GUID = 1CAFAAC3-C386-BF0B-7DD1-7EEE514A91B1 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = SmbiosPlatformDriverEntryPoint + +[Sources] + SmbiosPlatformDxe.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + HobLib + PcdLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[Protocols] + gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED + +[Depex] + gEfiSmbiosProtocolGuid diff --git a/Platform/Sophgo/SG2042Pkg/Universal/Dxe/SmbiosPlatformDxe/SmbiosPlatformDxe.c b/Platform/Sophgo/SG2042Pkg/Universal/Dxe/SmbiosPlatformDxe/SmbiosPlatformDxe.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/Sophgo/SG2042Pkg/Universal/Dxe/SmbiosPlatformDxe/SmbiosPlatformDxe.c @@ -XXX,XX +XXX,XX @@ +/** @file + This driver installs SMBIOS information for Sophgo SG2042EVB platforms + + Copyright (c) 2015-2020, Arm Limited. All rights reserved.<BR> + Copyright (c) 2023, Academy of Intelligent Innovation, Shandong Universiy, China.P.R. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include <Library/BaseLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/DebugLib.h> +#include <Library/HobLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/PcdLib.h> +#include <Library/UefiBootServicesTableLib.h> + +#include <Protocol/Smbios.h> + +#include <IndustryStandard/SmBios.h> + +// +// SMBIOS tables often reference each other using +// fixed constants, define a list of these constants +// for our hardcoded tables +// +enum SMBIOS_REFRENCE_HANDLES { + SMBIOS_HANDLE_L1I = 0x1000, + SMBIOS_HANDLE_L1D, + SMBIOS_HANDLE_L2, + SMBIOS_HANDLE_L3, + SMBIOS_HANDLE_MOTHERBOARD, + SMBIOS_HANDLE_CHASSIS, + SMBIOS_HANDLE_CLUSTER, + SMBIOS_HANDLE_MEMORY, + SMBIOS_HANDLE_DIMM +}; + +// +// Type definition and contents of the default SMBIOS table. +// This table covers only the minimum structures required by +// the SMBIOS specification (section 6.2, version 3.0) +// + +// BIOS information (section 7.1) +STATIC SMBIOS_TABLE_TYPE0 mSG2042EVBType0 = { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_BIOS_INFORMATION, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE0), // UINT8 Length + SMBIOS_HANDLE_PI_RESERVED, + }, + 1, // SMBIOS_TABLE_STRING Vendor + 2, // SMBIOS_TABLE_STRING BiosVersion + 0xE800, // UINT16 BiosSegment + 3, // SMBIOS_TABLE_STRING BiosReleaseDate + 0, // UINT8 BiosSize + { // BiosCharacteristics + 0, // Reserved :2 + 0, // Unknown :1 + 0, // BiosCharacteristicsNotSupported :1 + 0, // IsaIsSupported :1 + 0, // McaIsSupported :1 + 0, // EisaIsSupported :1 + 1, // PciIsSupported :1 + 0, // PcmciaIsSupported :1 + 0, // PlugAndPlayIsSupported :1 + 0, // ApmIsSupported :1 + 1, // BiosIsUpgradable :1 + 0, // BiosShadowingAllowed :1 + 0, // VlVesaIsSupported :1 + 0, // EscdSupportIsAvailable :1 + 1, // BootFromCdIsSupported :1 + 1, // SelectableBootIsSupported :1 + 0, // RomBiosIsSocketed :1 + 0, // BootFromPcmciaIsSupported :1 + 0, // EDDSpecificationIsSupported :1 + 0, // JapaneseNecFloppyIsSupported :1 + 0, // JapaneseToshibaFloppyIsSupported :1 + 0, // Floppy525_360IsSupported :1 + 0, // Floppy525_12IsSupported :1 + 0, // Floppy35_720IsSupported :1 + 0, // Floppy35_288IsSupported :1 + 0, // PrintScreenIsSupported :1 + 0, // Keyboard8042IsSupported :1 + 0, // SerialIsSupported :1 + 0, // PrinterIsSupported :1 + 0, // CgaMonoIsSupported :1 + 0, // NecPc98 :1 + 0 // ReservedForVendor :3 + }, + { + 0x3, // BIOSCharacteristicsExtensionBytes[0] + 0xC, // BIOSCharacteristicsExtensionBytes[1] + }, + 0xFF, // UINT8 SystemBiosMajorRelease + 0xFF, // UINT8 SystemBiosMinorRelease + 0xFF, // UINT8 EmbeddedControllerFirmwareMajorRelease + 0xFF, // UINT8 EmbeddedControllerFirmwareMinorRelease +}; + +STATIC CHAR8 CONST *mSG2042EVBType0Strings[] = { + "EFI Development Kit II / Sophgo\0", /* Vendor */ + "V1.0\0", /* BiosVersion */ + __DATE__"\0", /* BiosReleaseDate */ + NULL +}; + + +// System information (section 7.2) +STATIC SMBIOS_TABLE_TYPE1 mSG2042EVBType1 = { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_SYSTEM_INFORMATION, + sizeof (SMBIOS_TABLE_TYPE1), + SMBIOS_HANDLE_PI_RESERVED, + }, + 1, // Manufacturer + 2, // Product Name + 3, // Version + 4, // Serial + { 0x9987FD42, 0x907E, 0x5446, { 0x1D,0x7D,0x7D,0xA0,0x10,0x9F,0x60,0xA1 }}, //UUID + 6, //Wakeup type + 0, //SKU + 0, //Family +}; + +STATIC CHAR8 CONST *mSG2042EVBType1Strings[] = { + "SOPHGO\0", /* Manufacturer */ + "Sophgo SG2042 EVB Board\0", /* Product Name */ + "None\0", /* Version */ + "Not Set\0", /* Serial */ + NULL +}; + + +// Baseboard (section 7.3) +STATIC SMBIOS_TABLE_TYPE2 mSG2042EVBType2 = { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_BASEBOARD_INFORMATION, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE2), // UINT8 Length + SMBIOS_HANDLE_MOTHERBOARD, + }, + 1, // Manufacturer + 2, // Product Name + 3, // Version + 4, // Serial + 0, // Asset tag + {1}, // motherboard, not replaceable + 5, // location of board + SMBIOS_HANDLE_CHASSIS, + BaseBoardTypeMotherBoard, + 1, + {SMBIOS_HANDLE_CLUSTER}, +}; + +STATIC CHAR8 CONST *mSG2042EVBType2Strings[] = { + "SOPHGO\0", /* Manufacturer */ + "Sophgo SG2042 EVB Board\0", /* Product Name */ + "None\0", /* Version */ + "Not Set\0", /* Serial */ + "Not Set\0", /* BaseBoardAssetTag */ + "Not Set\0", /* BaseBoardChassisLocation */ + NULL +}; + + +// Enclosure +STATIC SMBIOS_TABLE_TYPE3 mSG2042EVBType3 = { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE3), // UINT8 Length + SMBIOS_HANDLE_CHASSIS, + }, + 1, // Manufacturer + 2, // enclosure type + 2, // version + 3, // serial + 0, // asset tag + ChassisStateUnknown, // boot chassis state + ChassisStateSafe, // power supply state + ChassisStateSafe, // thermal state + ChassisSecurityStatusNone, // security state + {0,0,0,0,}, // OEM defined + 1, // 1U height + 1, // number of power cords + 0, // no contained elements +}; + +STATIC CHAR8 CONST *mSG2042EVBType3Strings[] = { + "SOPHGO\0", /* Manufacturer */ + "None\0", /* Version */ + "Not Set\0", /* Serial */ + "Not Set\0", /* AssetTag */ + NULL +}; + + +// Processor +STATIC SMBIOS_TABLE_TYPE4 mSG2042EVBType4 = { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE4), // UINT8 Length + SMBIOS_HANDLE_CLUSTER, + }, + 1, // socket type + 3, // processor type CPU + ProcessorFamilyIndicatorFamily2, // processor family, acquire from field2 + 2, // manufactuer + {{0,},{0.}}, // processor id + 3, // version + {0,0,0,0,0,1}, // voltage + 0, // external clock + 2200, // max speed + 0, // current speed - requires update + 0x41, // status + ProcessorUpgradeOther, + SMBIOS_HANDLE_L1I, // l1 cache handle + SMBIOS_HANDLE_L2, // l2 cache handle + SMBIOS_HANDLE_L3, // l3 cache handle + 0, // serial not set + 0, // asset not set + 4, // part number + 64, // core count in socket + 64, // enabled core count in socket + 64, // threads per socket + 0xEC, // processor characteristics + ProcessorFamilyRiscVRV64, // RISC-V core + 0, // CoreCount2; + 0, // EnabledCoreCount2; + 0, // ThreadCount2; +}; + +STATIC CHAR8 CONST *mSG2042EVBType4Strings[] = { + "Socket type unknown\0", /* Socket type placeholder */ + "SOPHGO\0", /* manufactuer */ + "SG2042\0", /* processor description */ + "Not Set\0", /* SerialNumber */ + NULL +}; + +// Cache +STATIC SMBIOS_TABLE_TYPE7 mSG2042EVBType7_l1i = { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length + SMBIOS_HANDLE_L1I, + }, + 1, + 0x380, // L1 enabled, unknown WB + 48, // 48k I-cache max + 48, // 48k installed + {0,1}, // SRAM type + {0,1}, // SRAM type + 0, // speed unknown + CacheErrorParity, // parity checking + CacheTypeInstruction, // instruction cache + CacheAssociativityOther, // three way + // SMBIOS 3.1.0 fields + 48, //48k I-cache max + 48, //48k installed +}; + +STATIC SMBIOS_TABLE_TYPE7 mSG2042EVBType7_l1d = { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length + SMBIOS_HANDLE_L1D, + }, + 2, + 0x380, // L1 enabled, unknown WB + 32, // 32k D-cache max + 32, // 32k installed + {0,1}, // SRAM type + {0,1}, // SRAM type + 0, // speed unknown + CacheErrorSingleBit, // ECC checking + CacheTypeData, // data cache + CacheAssociativity2Way, // two way + // SMBIOS 3.1.0 fields + 32, // 32k D-cache max + 32, // 32k installed +}; + +STATIC SMBIOS_TABLE_TYPE7 mSG2042EVBType7_l2 = { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length + SMBIOS_HANDLE_L2, + }, + 3, + 0x181, // L2 enabled, WB + 512, // 512k D-cache max + 512, // 512k installed + {0,1}, // SRAM type + {0,1}, // SRAM type + 0, // speed unknown + CacheErrorSingleBit, // ECC checking + CacheTypeUnified, // instruction cache + CacheAssociativity16Way, // 16 way associative + // SMBIOS 3.1.0 fields + 512, // 512k D-cache max + 512, // 512k installed +}; + +STATIC SMBIOS_TABLE_TYPE7 mSG2042EVBType7_l3 = { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length + SMBIOS_HANDLE_L3, + }, + 4, + 0x182, // L3 enabled, WB + 1024, // 1M cache max + 1024, // 1M installed + {0,1}, // SRAM type + {0,1}, // SRAM type + 0, // speed unknown + CacheErrorSingleBit, // ECC checking + CacheTypeUnified, // instruction cache + CacheAssociativity8Way, // 8 way associative + // SMBIOS 3.1.0 fields + 1024, // 1M cache max + 1024, // 1M installed +}; + +STATIC CONST CHAR8 *mSG2042EVBType7Strings[] = { + "L1 Instruction\0", /* L1I */ + "L1 Data\0", /* L1D */ + "L2\0", /* L2 */ + "L3\0", /* L3 */ + NULL +}; + +// Slots +STATIC SMBIOS_TABLE_TYPE9 mSG2042EVBType9_0 = { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_INACTIVE, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length + SMBIOS_HANDLE_PI_RESERVED, + }, + 1, + SlotTypePciExpressX16, + SlotDataBusWidth16X, + SlotUsageUnknown, + SlotLengthLong, + 0, + {1}, // Unknown + {1,0,1}, // PME and SMBUS + 0, + 0, + 1, +}; + +STATIC SMBIOS_TABLE_TYPE9 mSG2042EVBType9_1 = { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_INACTIVE, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length + SMBIOS_HANDLE_PI_RESERVED, + }, + 2, + SlotTypePciExpressGen2X8, + SlotDataBusWidth8X, + SlotUsageUnknown, + SlotLengthLong, + 0, + {1}, + {1,0,1}, // PME and SMBUS + 0, + 0, + 2, +}; + +STATIC SMBIOS_TABLE_TYPE9 mSG2042EVBType9_2 = { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_INACTIVE, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length + SMBIOS_HANDLE_PI_RESERVED, + }, + 3, + SlotTypePciExpressGen2X8, + SlotDataBusWidth8X, + SlotUsageUnknown, + SlotLengthLong, + 0, + {1}, + {1,0,1}, // PME and SMBUS + 0, + 0, + 3, +}; + +STATIC CHAR8 CONST *mSG2042EVBType9Strings[] = { + "PCIE0 ExpressX16 \0",/* Slot0 */ + "PCIE1 ExpressGen2X8 \0",/* Slot1 */ + "PCIE1 ExpressGen2X8 \0",/* Slot2 */ + NULL +}; + +// Memory array +STATIC SMBIOS_TABLE_TYPE16 mSG2042EVBType16 = { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE16), // UINT8 Length + SMBIOS_HANDLE_MEMORY, + }, + MemoryArrayLocationSystemBoard, // on motherboard + MemoryArrayUseSystemMemory, // system RAM + MemoryErrorCorrectionNone, // ECC RAM + 0x1000000, // 16GB + 0xFFFE, // No error information structure + 0x1, // soldered memory +}; + +STATIC CHAR8 CONST *mSG2042EVBType16Strings[] = { + NULL +}; + +// Memory device +STATIC SMBIOS_TABLE_TYPE17 mSG2042EVBType17 = { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_MEMORY_DEVICE, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE17), // UINT8 Length + SMBIOS_HANDLE_DIMM, + }, + SMBIOS_HANDLE_MEMORY, // array to which this module belongs + 0xFFFE, // no errors + 64, // single DIMM, no ECC is 64bits (for ecc this would be 72) + 32, // data width of this device (32-bits) + 0, // Memory size obtained dynamically + MemoryFormFactorRowOfChips, // Memory factor + 0, // Not part of a set + 1, // Location + 2, // Bank 0 + MemoryTypeDdr4, // DDR4 + {0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, // unbuffered + 0, // DRAM speed - requires update + 0, // varies between diffrent production runs + 0, // serial + 0, // asset tag + 0, // part number + 0, // rank + 0, // ExtendedSize; (since Size < 32GB-1) + 0, // ConfiguredMemoryClockSpeed - initialized at runtime + 0, // MinimumVoltage; (unknown) + 0, // MaximumVoltage; (unknown) + 0, // ConfiguredVoltage; (unknown) + MemoryTechnologyDram, // MemoryTechnology + {{ // MemoryOperatingModeCapability + 0, // Reserved :1; + 0, // Other :1; + 0, // Unknown :1; + 1, // VolatileMemory :1; + 0, // ByteAccessiblePersistentMemory :1; + 0, // BlockAccessiblePersistentMemory :1; + 0 // Reserved :10; + }}, + 0, // FirwareVersion + 0, // ModuleManufacturerID (unknown) + 0, // ModuleProductID (unknown) + 0, // MemorySubsystemControllerManufacturerID (unknown) + 0, // MemorySubsystemControllerProductID (unknown) + 0, // NonVolatileSize + 0, // VolatileSize - initialized at runtime + 0, // CacheSize + 0, // LogicalSize + 0, // ExtendedSpeed, + 0 // ExtendedConfiguredMemorySpeed +}; + +STATIC CHAR8 CONST *mSG2042EVBType17Strings[] = { + "DIMM SLOT\0", /* location */ + "BANK 0\0", /* bank description */ + NULL +}; + +// +// Memory array mapped address, this structure +// is overridden by SmbiosInstallMemoryStructure. +// +STATIC SMBIOS_TABLE_TYPE19 mSG2042EVBType19 = { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE19), // UINT8 Length + SMBIOS_HANDLE_PI_RESERVED, + }, + 0xFFFFFFFF, // invalid, look at extended addr field + 0xFFFFFFFF, + SMBIOS_HANDLE_DIMM, // handle + 1, + 0x080000000, // starting addr of first 2GB + 0x100000000, // ending addr of first 2GB +}; + +// System boot infomSG2042EVBType4. +STATIC SMBIOS_TABLE_TYPE32 mSG2042EVBType32 = { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE32), // UINT8 Length + SMBIOS_HANDLE_PI_RESERVED, + }, + {0, 0, 0, 0, 0, 0}, // reserved + BootInformationStatusNoError, +}; + +STATIC CHAR8 CONST *mSG2042EVBType32Strings[] = { + NULL +}; + +STATIC CONST VOID *DefaultCommonTables[][2] = +{ + { &mSG2042EVBType0, mSG2042EVBType0Strings }, + { &mSG2042EVBType1, mSG2042EVBType1Strings }, + { &mSG2042EVBType2, mSG2042EVBType2Strings }, + { &mSG2042EVBType3, mSG2042EVBType3Strings }, + { &mSG2042EVBType4, mSG2042EVBType4Strings }, + { &mSG2042EVBType7_l1i, mSG2042EVBType7Strings }, + { &mSG2042EVBType7_l1d, mSG2042EVBType7Strings }, + { &mSG2042EVBType7_l2, mSG2042EVBType7Strings }, + { &mSG2042EVBType7_l3, mSG2042EVBType7Strings }, + { &mSG2042EVBType9_0, mSG2042EVBType9Strings }, + { &mSG2042EVBType9_1, mSG2042EVBType9Strings }, + { &mSG2042EVBType9_2, mSG2042EVBType9Strings }, + { &mSG2042EVBType16, mSG2042EVBType16Strings }, + { &mSG2042EVBType17, mSG2042EVBType17Strings }, + { &mSG2042EVBType32, mSG2042EVBType32Strings }, + { NULL, NULL }, +}; + +/** + + Create SMBIOS record. + + Converts a fixed SMBIOS structure and an array of pointers to strings into + an SMBIOS record where the strings are cat'ed on the end of the fixed record + and terminated via a double NULL and add to SMBIOS table. + + SMBIOS_TABLE_TYPE32 gSmbiosType12 = { + { EFI_SMBIOS_TYPE_SYSTEM_CONFIGURATION_OPTIONS, sizeof (SMBIOS_TABLE_TYPE12), 0 }, + 1 // StringCount + }; + + CHAR8 *gSmbiosType12Strings[] = { + "Not Found", + NULL + }; + + ... + + LogSmbiosData ( + (EFI_SMBIOS_TABLE_HEADER*)&gSmbiosType12, + gSmbiosType12Strings + ); + + @param Smbios SMBIOS protocol + @param Template Fixed SMBIOS structure, required. + @param StringArray Array of strings to convert to an SMBIOS string pack. + NULL is OK. +**/ +STATIC +EFI_STATUS +EFIAPI +LogSmbiosData ( + IN EFI_SMBIOS_PROTOCOL *Smbios, + IN EFI_SMBIOS_TABLE_HEADER *Template, + IN CONST CHAR8 * CONST *StringArray + ) +{ + EFI_STATUS Status; + EFI_SMBIOS_TABLE_HEADER *Record; + UINTN Index; + UINTN StringSize; + UINTN Size; + CHAR8 *Str; + + + // Calculate the size of the fixed record and optional string pack + Size = Template->Length; + if (StringArray == NULL) { + // At least a double null is required + Size += 1; + } else { + for (Index = 0; StringArray[Index] != NULL; Index++) { + StringSize = AsciiStrSize (StringArray[Index]); + Size += StringSize; + } + if (StringArray[0] == NULL) { + // At least a double null is required + Size += 1; + } + + // Don't forget the terminating double null + Size += 1; + } + + // Copy over Template + Record = (EFI_SMBIOS_TABLE_HEADER *)AllocateZeroPool (Size); + if (Record == NULL) { + return EFI_OUT_OF_RESOURCES; + } + CopyMem (Record, Template, Template->Length); + + // Append string pack + Str = (CHAR8*)((UINTN)Record + Record->Length); + for (Index = 0; StringArray[Index] != NULL; Index++) { + StringSize = AsciiStrSize (StringArray[Index]); + CopyMem (Str, StringArray[Index], StringSize); + Str += StringSize; + } + *Str = 0; + + Status = Smbios->Add (Smbios, + NULL, + &Record->Handle, + Record); + ASSERT_EFI_ERROR (Status); + + FreePool (Record); + + return Status; +} + +/** + Installs a memory descriptor (type19) for the given address range + + @param Smbios SMBIOS protocol. + @param StartingAddress Start address of the memory chunk. + @param RegionLength Memory chunk size. + +**/ +EFI_STATUS +SmbiosInstallMemoryStructure ( + IN EFI_SMBIOS_PROTOCOL *Smbios, + IN UINT64 StartingAddress, + IN UINT64 RegionLength + ) +{ + EFI_SMBIOS_HANDLE SmbiosHandle; + SMBIOS_TABLE_TYPE19 MemoryDescriptor; + EFI_STATUS Status; + + Status = EFI_SUCCESS; + + CopyMem (&MemoryDescriptor, + &mSG2042EVBType19, + sizeof (SMBIOS_TABLE_TYPE19)); + + MemoryDescriptor.ExtendedStartingAddress = StartingAddress; + MemoryDescriptor.ExtendedEndingAddress = StartingAddress + RegionLength; + SmbiosHandle = MemoryDescriptor.Hdr.Handle; + + Status = Smbios->Add (Smbios, + NULL, + &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER*) &MemoryDescriptor); + + return Status; +} + +/** + Install a whole table worth of structructures + + @param Smbios SMBIOS protocol. + @param DefaultTables A pointer to the default SMBIOS table structure. + +**/ +EFI_STATUS +SmbiosInstallStructures ( + IN EFI_SMBIOS_PROTOCOL *Smbios, + IN CONST VOID *DefaultTables[][2] + ) +{ + EFI_STATUS Status; + INTN TableEntry; + + Status = EFI_SUCCESS; + + for (TableEntry = 0; DefaultTables[TableEntry][0] != NULL; TableEntry++) { + // Omit disabled tables + if (((EFI_SMBIOS_TABLE_HEADER *)DefaultTables[TableEntry][0])->Type == + EFI_SMBIOS_TYPE_INACTIVE) { + continue; + } + + Status = LogSmbiosData (Smbios, + ((EFI_SMBIOS_TABLE_HEADER *)DefaultTables[TableEntry][0]), + DefaultTables[TableEntry][1]); + if (EFI_ERROR (Status)) + break; + } + + return Status; +} + +/** + Update memory information basing on the HOB list. + + @param Smbios SMBIOS protocol + +**/ +STATIC +EFI_STATUS +SmbiosMemoryInstall ( + IN EFI_SMBIOS_PROTOCOL *Smbios + ) +{ + EFI_PEI_HOB_POINTERS Hob; + UINT64 MemorySize; + EFI_STATUS Status; + + MemorySize = 0; + + // + // Get the HOB list for processing + // + Hob.Raw = GetHobList (); + + // + // Collect memory ranges + // + while (!END_OF_HOB_LIST (Hob)) { + if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { + if (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) { + MemorySize += (UINT64)(Hob.ResourceDescriptor->ResourceLength); + + Status = SmbiosInstallMemoryStructure (Smbios, + Hob.ResourceDescriptor->PhysicalStart, + Hob.ResourceDescriptor->ResourceLength); + if (EFI_ERROR(Status)) { + return Status; + } + } + } + Hob.Raw = GET_NEXT_HOB (Hob); + } + + // + // Update TYPE17 memory size fields + // + mSG2042EVBType17.Size = (UINT16)(MemorySize >> 20); + mSG2042EVBType17.VolatileSize = MemorySize; + + return EFI_SUCCESS; +} + +/** + Install all structures from the DefaultTables structure + + @param Smbios SMBIOS protocol + +**/ +EFI_STATUS +SmbiosInstallAllStructures ( + IN EFI_SMBIOS_PROTOCOL *Smbios + ) +{ + EFI_STATUS Status; + + // + // Generate memory descriptors. + // + Status = SmbiosMemoryInstall (Smbios); + ASSERT_EFI_ERROR (Status); + + // + // Install all tables. + // + Status = SmbiosInstallStructures (Smbios, DefaultCommonTables); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} + +/** + Installs SMBIOS information for SG2042EVB platforms + + @param ImageHandle Module's image handle + @param SystemTable Pointer of EFI_SYSTEM_TABLE + + @retval EFI_SUCCESS Smbios data successfully installed + @retval Other Smbios data was not installed + +**/ +EFI_STATUS +EFIAPI +SmbiosPlatformDriverEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_SMBIOS_PROTOCOL *Smbios; + + // + // Find the SMBIOS protocol + // + Status = gBS->LocateProtocol (&gEfiSmbiosProtocolGuid, + NULL, + (VOID **)&Smbios); + if (EFI_ERROR (Status)) { + return Status; + } + + Status = SmbiosInstallAllStructures (Smbios); + + return Status; +} -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#108210): https://edk2.groups.io/g/devel/message/108210 Mute This Topic: https://groups.io/mt/101084022/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=- From: caiyuqing379 <202235273@mail.sdu.edu.cn> SG2042 (Xuantie C920) MMU can be enabled in SV39 mode. C920 has five customizable page properties that control whether the page is Strong order(SO), Cacheable(C), Bufferable(B), Shareable(SH), Trustable(Sec). This driver modifies the page table attributes to avoid exceptions based on the memory attributes of the C920. Introduces a PCD variable PcdForceNoMMU to disable MMU configuration. Currently, enabling MMU results in a timeout for reading data blocks from the SD card. Signed-off-by: caiyuqing379 <202235273@mail.sdu.edu.cn> Co-authored-by: USER0FISH <libing1202@outlook.com> Cc: dahogn <dahogn@hotmail.com> Cc: meng-cz <mengcz1126@gmail.com> Cc: yli147 <yong.li@intel.com> Cc: ChaiEvan <evan.chai@intel.com> Cc: Sunil V L <sunilvl@ventanamicro.com> --- .../PlatformUpdateMmuDxe.inf | 34 + .../PlatformUpdateMmuDxe.c | 591 ++++++++++++++++++ 2 files changed, 625 insertions(+) create mode 100644 Platform/Sophgo/SG2042Pkg/Universal/Dxe/PlatformUpdateMmuDxe/PlatformUpdateMmuDxe.inf create mode 100644 Platform/Sophgo/SG2042Pkg/Universal/Dxe/PlatformUpdateMmuDxe/PlatformUpdateMmuDxe.c diff --git a/Platform/Sophgo/SG2042Pkg/Universal/Dxe/PlatformUpdateMmuDxe/PlatformUpdateMmuDxe.inf b/Platform/Sophgo/SG2042Pkg/Universal/Dxe/PlatformUpdateMmuDxe/PlatformUpdateMmuDxe.inf new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/Sophgo/SG2042Pkg/Universal/Dxe/PlatformUpdateMmuDxe/PlatformUpdateMmuDxe.inf @@ -XXX,XX +XXX,XX @@ +## @file +# This driver modifies the page table attribute based on the memory attribute of the C920. +# +# Copyright (c) 2023, Academy of Intelligent Innovation, Shandong Universiy, China.P.R. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001b + BASE_NAME = PlatformUpdateMmuDxe + FILE_GUID = 9d1dd27f-6d7f-427b-aec4-b62f6279c2f1 + MODULE_TYPE = UEFI_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = PlatformUpdateMmu + +[Sources] + PlatformUpdateMmuDxe.c + +[Packages] + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + Platform/Sophgo/SG2042Pkg/SG2042Pkg.dec + +[LibraryClasses] + BaseLib + UefiLib + UefiDriverEntryPoint + RiscVMmuLib + DxeServicesTableLib + +[FixedPcd] + gSophgoSG2042PlatformPkgTokenSpaceGuid.PcdForceNoMMU ## CONSUMES diff --git a/Platform/Sophgo/SG2042Pkg/Universal/Dxe/PlatformUpdateMmuDxe/PlatformUpdateMmuDxe.c b/Platform/Sophgo/SG2042Pkg/Universal/Dxe/PlatformUpdateMmuDxe/PlatformUpdateMmuDxe.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/Sophgo/SG2042Pkg/Universal/Dxe/PlatformUpdateMmuDxe/PlatformUpdateMmuDxe.c @@ -XXX,XX +XXX,XX @@ +/** @file + This driver modifies the page table attribute based on the memory attribute of the C920. + C920 has five customizable page properties that control whether the page is Strong order, + Cacheable, Bufferable, Shareable,Trustable. + + Copyright (c) 2011-2020, ARM Limited. All rights reserved. + Copyright (c) 2016, Linaro Limited. All rights reserved. + Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> + Copyright (c) 2023, Ventana Micro Systems Inc. All Rights Reserved.<BR> + Copyright (c) 2023, Academy of Intelligent Innovation, Shandong Universiy, China.P.R. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <PiDxe.h> +#include <Uefi.h> +#include <Library/BaseLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/BaseRiscVMmuLib.h> +#include <Library/CacheMaintenanceLib.h> +#include <Library/DebugLib.h> +#include <Library/DxeServicesTableLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/PcdLib.h> +#include <Register/RiscV64/RiscVEncoding.h> + +#define RISCV_PG_V BIT0 +#define RISCV_PG_R BIT1 +#define RISCV_PG_W BIT2 +#define RISCV_PG_X BIT3 +#define RISCV_PG_G BIT5 +#define RISCV_PG_A BIT6 +#define RISCV_PG_D BIT7 +#define RISCV_PG_SH BIT60 +#define RISCV_PG_B BIT61 +#define RISCV_PG_C BIT62 +#define RISCV_PG_SO BIT63 +#define PTE_ATTRIBUTES_MASK 0xE + +#define PTE_PPN_MASK 0x3FFFFFFFFFFC00ULL +#define PTE_PPN_SHIFT 10 +#define RISCV_MMU_PAGE_SHIFT 12 + +STATIC UINTN mMaxRootTableLevel; +STATIC UINTN mBitPerLevel; +STATIC UINTN mTableEntryCount; + +/** + Determine if the MMU enabled or not. + + @retval TRUE The MMU already enabled. + @retval FALSE The MMU not enabled. + +**/ +STATIC +VOID +RiscVMmuDisabled ( + VOID + ) +{ + RiscVSetSupervisorAddressTranslationRegister (SATP_MODE_OFF << SATP64_MODE_SHIFT); +} + +/** + Determine if the MMU enabled or not. + + @retval TRUE The MMU already enabled. + @retval FALSE The MMU not enabled. + +**/ +STATIC +BOOLEAN +RiscVMmuEnabled ( + VOID + ) +{ + return ((RiscVGetSupervisorAddressTranslationRegister () & + SATP64_MODE) != (SATP_MODE_OFF << SATP64_MODE_SHIFT)); +} + +/** + Retrieve the root translate table. + + @return The root translate table. + +**/ +STATIC +UINTN +RiscVGetRootTranslateTable ( + VOID + ) +{ + return (RiscVGetSupervisorAddressTranslationRegister () & SATP64_PPN) << + RISCV_MMU_PAGE_SHIFT; +} + +/** + Determine if an entry is valid pte. + + @param Entry The entry value. + + @retval TRUE The entry is a valid pte. + @retval FALSE The entry is not a valid pte. + +**/ +STATIC +BOOLEAN +IsValidPte ( + IN UINTN Entry + ) +{ + if (((Entry & RISCV_PG_V) == 0) || + (((Entry & (RISCV_PG_R | RISCV_PG_W)) == RISCV_PG_W))) + { + return FALSE; + } + + return TRUE; +} + +/** + Set an entry to be a valid pte. + + @param Entry The entry value. + + @return The entry value. + +**/ +STATIC +UINTN +SetValidPte ( + IN UINTN Entry + ) +{ + /* Set Valid and Global mapping bits */ + return Entry | RISCV_PG_G | RISCV_PG_V; +} + +/** + Determine if an entry is a block pte. + + @param Entry The entry value. + + @retval TRUE The entry is a block pte. + @retval FALSE The entry is not a block pte. + +**/ +STATIC +BOOLEAN +IsBlockEntry ( + IN UINTN Entry + ) +{ + return IsValidPte (Entry) && + (Entry & (RISCV_PG_X | RISCV_PG_R)); +} + +/** + Determine if an entry is a table pte. + + @param Entry The entry value. + + @retval TRUE The entry is a table pte. + @retval FALSE The entry is not a table pte. + +**/ +STATIC +BOOLEAN +IsTableEntry ( + IN UINTN Entry + ) +{ + return IsValidPte (Entry) && + !IsBlockEntry (Entry); +} + +/** + Set an entry to be a table pte. + + @param Entry The entry value. + + @return The entry value. + +**/ +STATIC +UINTN +SetTableEntry ( + IN UINTN Entry + ) +{ + Entry = SetValidPte (Entry); + Entry &= ~(RISCV_PG_X | RISCV_PG_W | RISCV_PG_R); + + return Entry; +} + +/** + Replace an existing entry with new value. + + @param Entry The entry pointer. + @param Value The new entry value. + @param RegionStart The start of region that new value affects. + @param IsLiveBlockMapping TRUE if this is live update, FALSE otherwise. + +**/ +STATIC +VOID +ReplaceTableEntry ( + IN UINTN *Entry, + IN UINTN Value, + IN UINTN RegionStart, + IN BOOLEAN IsLiveBlockMapping + ) +{ + *Entry = Value; + + if (IsLiveBlockMapping && RiscVMmuEnabled ()) { + RiscVLocalTlbFlush (RegionStart); + } +} + +/** + Get an ppn value from an entry. + + @param Entry The entry value. + + @return The ppn value. + +**/ +STATIC +UINTN +GetPpnfromPte ( + IN UINTN Entry + ) +{ + return ((Entry & PTE_PPN_MASK) >> PTE_PPN_SHIFT); +} + +/** + Set an ppn value to a entry. + + @param Entry The entry value. + @param Address The address. + + @return The new entry value. + +**/ +STATIC +UINTN +SetPpnToPte ( + UINTN Entry, + UINTN Address + ) +{ + UINTN Ppn; + + Ppn = ((Address >> RISCV_MMU_PAGE_SHIFT) << PTE_PPN_SHIFT); + ASSERT (~(Ppn & ~PTE_PPN_MASK)); + Entry &= ~PTE_PPN_MASK; + return Entry | Ppn; +} + +/** + Free resources of translation table recursively. + + @param TranslationTable The pointer of table. + @param Level The current level. + +**/ +STATIC +VOID +FreePageTablesRecursive ( + IN UINTN *TranslationTable, + IN UINTN Level + ) +{ + UINTN Index; + + if (Level < mMaxRootTableLevel - 1) { + for (Index = 0; Index < mTableEntryCount; Index++) { + if (IsTableEntry (TranslationTable[Index])) { + FreePageTablesRecursive ( + (UINTN *)(GetPpnfromPte ((TranslationTable[Index])) << + RISCV_MMU_PAGE_SHIFT), + Level + 1 + ); + } + } + } + + FreePages (TranslationTable, 1); +} + +/** + Update region mapping recursively. + + @param RegionStart The start address of the region. + @param RegionEnd The end address of the region. + @param AttributeSetMask The attribute mask to be set. + @param AttributeClearMask The attribute mask to be clear. + @param PageTable The pointer of current page table. + @param Level The current level. + @param TableIsLive TRUE if this is live update, FALSE otherwise. + + @retval EFI_OUT_OF_RESOURCES Not enough resource. + @retval EFI_SUCCESS The operation succesfully. + +**/ +STATIC +EFI_STATUS +UpdateRegionMappingRecursive ( + IN UINTN RegionStart, + IN UINTN RegionEnd, + IN UINTN AttributeSetMask, + IN UINTN AttributeClearMask, + IN UINTN *PageTable, + IN UINTN Level, + IN BOOLEAN TableIsLive + ) +{ + EFI_STATUS Status; + UINTN BlockShift; + UINTN BlockMask; + UINTN BlockEnd; + UINTN *Entry; + UINTN EntryValue; + UINTN *TranslationTable; + BOOLEAN NextTableIsLive; + + ASSERT (Level < mMaxRootTableLevel); + ASSERT (((RegionStart | RegionEnd) & EFI_PAGE_MASK) == 0); + + BlockShift = (mMaxRootTableLevel - Level - 1) * mBitPerLevel + RISCV_MMU_PAGE_SHIFT; + BlockMask = MAX_ADDRESS >> (64 - BlockShift); + + DEBUG ( + ( + DEBUG_VERBOSE, + "%a(%d): %llx - %llx set %lx clr %lx\n", + __func__, + Level, + RegionStart, + RegionEnd, + AttributeSetMask, + AttributeClearMask + ) + ); + + for ( ; RegionStart < RegionEnd; RegionStart = BlockEnd) { + BlockEnd = MIN (RegionEnd, (RegionStart | BlockMask) + 1); + Entry = &PageTable[(RegionStart >> BlockShift) & (mTableEntryCount - 1)]; + + // + // If RegionStart or BlockEnd is not aligned to the block size at this + // level, we will have to create a table mapping in order to map less + // than a block, and recurse to create the block or page entries at + // the next level. No block mappings are allowed at all at level 0, + // so in that case, we have to recurse unconditionally. + // + if ((Level == 0) || + (((RegionStart | BlockEnd) & BlockMask) != 0) || IsTableEntry (*Entry)) + { + ASSERT (Level < mMaxRootTableLevel - 1); + if (!IsTableEntry (*Entry)) { + // + // No table entry exists yet, so we need to allocate a page table + // for the next level. + // + TranslationTable = AllocatePages (1); + if (TranslationTable == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + ZeroMem (TranslationTable, EFI_PAGE_SIZE); + + if (IsBlockEntry (*Entry)) { + // + // We are splitting an existing block entry, so we have to populate + // the new table with the attributes of the block entry it replaces. + // + Status = UpdateRegionMappingRecursive ( + RegionStart & ~BlockMask, + (RegionStart | BlockMask) + 1, + *Entry & PTE_ATTRIBUTES_MASK, + PTE_ATTRIBUTES_MASK, + TranslationTable, + Level + 1, + FALSE + ); + if (EFI_ERROR (Status)) { + // + // The range we passed to UpdateRegionMappingRecursive () is block + // aligned, so it is guaranteed that no further pages were allocated + // by it, and so we only have to free the page we allocated here. + // + FreePages (TranslationTable, 1); + return Status; + } + } + + NextTableIsLive = FALSE; + } else { + TranslationTable = (UINTN *)(GetPpnfromPte (*Entry) << RISCV_MMU_PAGE_SHIFT); + NextTableIsLive = TableIsLive; + } + + // + // Recurse to the next level + // + Status = UpdateRegionMappingRecursive ( + RegionStart, + BlockEnd, + AttributeSetMask, + AttributeClearMask, + TranslationTable, + Level + 1, + NextTableIsLive + ); + if (EFI_ERROR (Status)) { + if (!IsTableEntry (*Entry)) { + // + // We are creating a new table entry, so on failure, we can free all + // allocations we made recursively, given that the whole subhierarchy + // has not been wired into the live page tables yet. (This is not + // possible for existing table entries, since we cannot revert the + // modifications we made to the subhierarchy it represents.) + // + FreePageTablesRecursive (TranslationTable, Level + 1); + } + + return Status; + } + + if (!IsTableEntry (*Entry)) { + EntryValue = SetPpnToPte (0, (UINTN)TranslationTable); + EntryValue = SetTableEntry (EntryValue); + ReplaceTableEntry ( + Entry, + EntryValue, + RegionStart, + TableIsLive + ); + } + } else { + EntryValue = (*Entry & ~AttributeClearMask) | AttributeSetMask; + // + // We don't have page fault exception handler when a virtual page is accessed and + // the A bit is clear, or is written and the D bit is clear. + // So just set A for read and D for write permission. + // + if ((AttributeSetMask & RISCV_PG_R) != 0) { + EntryValue |= RISCV_PG_A; + } + + if ((AttributeSetMask & RISCV_PG_W) != 0) { + EntryValue |= RISCV_PG_D; + } + + EntryValue = SetPpnToPte (EntryValue, RegionStart); + EntryValue = SetValidPte (EntryValue); + ReplaceTableEntry (Entry, EntryValue, RegionStart, TableIsLive); + } + } + + return EFI_SUCCESS; +} + +/** + Update region mapping at root table. + + @param RegionStart The start address of the region. + @param RegionLength The length of the region. + @param AttributeSetMask The attribute mask to be set. + @param AttributeClearMask The attribute mask to be clear. + @param RootTable The pointer of root table. + @param TableIsLive TRUE if this is live update, FALSE otherwise. + + @retval EFI_INVALID_PARAMETER The RegionStart or RegionLength was not valid. + @retval EFI_OUT_OF_RESOURCES Not enough resource. + @retval EFI_SUCCESS The operation succesfully. + +**/ +STATIC +EFI_STATUS +UpdateRegionMapping ( + IN UINTN RegionStart, + IN UINTN RegionLength, + IN UINTN AttributeSetMask, + IN UINTN AttributeClearMask, + IN UINTN *RootTable, + IN BOOLEAN TableIsLive + ) +{ + if (((RegionStart | RegionLength) & EFI_PAGE_MASK) != 0) { + return EFI_INVALID_PARAMETER; + } + + return UpdateRegionMappingRecursive ( + RegionStart, + RegionStart + RegionLength, + AttributeSetMask, + AttributeClearMask, + RootTable, + 0, + TableIsLive + ); +} + +/** + The API to configure and enable RISC-V MMU with the highest mode supported. + + @retval EFI_OUT_OF_RESOURCES Not enough resource. + @retval EFI_SUCCESS The operation succesfully. + +**/ +EFI_STATUS +EFIAPI +PlatformUpdateMmu ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemoryMap; + UINTN NumberOfDescriptors; + UINTN Index; + EFI_STATUS Status; + + Status = EFI_SUCCESS; + + if(RiscVMmuEnabled () && PcdGetBool (PcdForceNoMMU)){ + RiscVMmuDisabled (); + DEBUG (( + DEBUG_INFO, + "%a: SG2042 MMU disabled\n", + __func__ + )); + + FreePageTablesRecursive ((UINTN *)RiscVGetRootTranslateTable (), 0); + return Status; + } + + if (RiscVMmuEnabled ()) { + mMaxRootTableLevel = 3; + mBitPerLevel = 9; + mTableEntryCount = 512; + + NumberOfDescriptors = 0; + MemoryMap = NULL; + Status = gDS->GetMemorySpaceMap ( + &NumberOfDescriptors, + &MemoryMap + ); + ASSERT_EFI_ERROR (Status); + + for (Index = 0; Index < NumberOfDescriptors; Index++) { + if (MemoryMap[Index].GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo) { + // Update Read/Write/Strong Order attribute for memory mapped IO + UpdateRegionMapping ( + MemoryMap[Index].BaseAddress, + MemoryMap[Index].Length, + RISCV_PG_R | RISCV_PG_W | RISCV_PG_SO, + PTE_ATTRIBUTES_MASK, + (UINTN *)RiscVGetRootTranslateTable (), + TRUE + ); + } else if (MemoryMap[Index].GcdMemoryType == EfiGcdMemoryTypeSystemMemory) { + // Update Read/Write/Execute/Sharable/Cacheable attribute for system memory + UpdateRegionMapping ( + MemoryMap[Index].BaseAddress, + MemoryMap[Index].Length, + RISCV_PG_R | RISCV_PG_W | RISCV_PG_X | RISCV_PG_SH | RISCV_PG_C, + PTE_ATTRIBUTES_MASK, + (UINTN *)RiscVGetRootTranslateTable (), + TRUE + ); + } + } + + DEBUG (( + DEBUG_INFO, + "%a: SG2042 Update memory attribute\n", + __func__ + )); + + FreePool ((VOID *)MemoryMap); + } + + return Status; +} -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#108213): https://edk2.groups.io/g/devel/message/108213 Mute This Topic: https://groups.io/mt/101084025/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=- From: caiyuqing379 <202235273@mail.sdu.edu.cn> This driver implements Sophgo SDHCI controller, which provides the necessary interfaces for handling communication and data transfer with SD cards. Signed-off-by: caiyuqing379 <202235273@mail.sdu.edu.cn> Co-authored-by: USER0FISH <libing1202@outlook.com> Cc: dahogn <dahogn@hotmail.com> Cc: meng-cz <mengcz1126@gmail.com> Cc: yli147 <yong.li@intel.com> Cc: ChaiEvan <evan.chai@intel.com> Cc: Sunil V L <sunilvl@ventanamicro.com> --- .../Universal/Dxe/SdHostDxe/SdHostDxe.inf | 47 + .../SG2042Pkg/Universal/Dxe/SdHostDxe/SdHci.h | 309 ++++++ .../SG2042Pkg/Universal/Dxe/SdHostDxe/SdHci.c | 929 ++++++++++++++++++ .../Universal/Dxe/SdHostDxe/SdHostDxe.c | 450 +++++++++ 4 files changed, 1735 insertions(+) create mode 100644 Platform/Sophgo/SG2042Pkg/Universal/Dxe/SdHostDxe/SdHostDxe.inf create mode 100644 Platform/Sophgo/SG2042Pkg/Universal/Dxe/SdHostDxe/SdHci.h create mode 100755 Platform/Sophgo/SG2042Pkg/Universal/Dxe/SdHostDxe/SdHci.c create mode 100644 Platform/Sophgo/SG2042Pkg/Universal/Dxe/SdHostDxe/SdHostDxe.c diff --git a/Platform/Sophgo/SG2042Pkg/Universal/Dxe/SdHostDxe/SdHostDxe.inf b/Platform/Sophgo/SG2042Pkg/Universal/Dxe/SdHostDxe/SdHostDxe.inf new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/Sophgo/SG2042Pkg/Universal/Dxe/SdHostDxe/SdHostDxe.inf @@ -XXX,XX +XXX,XX @@ +## @file +# Component description file for the SD Host Controller DXE driver module. +# +# Copyright (c) 2019, ARM Limited. All rights reserved. +# Copyright (c) 2017, Andrei Warkentin <andrey.warkentin@gmail.com> +# Copyright (c) Microsoft Corporation. All rights reserved. +# Copyright (c) 2023, Academy of Intelligent Innovation, Shandong Universiy, China.P.R. All rights reserved.<BR> +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = SdHostDxe + FILE_GUID = 11322596-DD4F-47FA-9E6C-CE787E11E4B1 + MODULE_TYPE = UEFI_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = SdHostInitialize + +[Sources] + SdHci.c + SdHci.h + SdHostDxe.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Platform/Sophgo/SG2042Pkg/SG2042Pkg.dec + +[LibraryClasses] + BaseLib + DebugLib + IoLib + MemoryAllocationLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiLib + UefiRuntimeServicesTableLib + +[Protocols] + gSophgoMmcHostProtocolGuid ## PRODUCES + +[FixedPcd] + gSophgoSG2042PlatformPkgTokenSpaceGuid.PcdSG2042SDIOBase ## CONSUMES + gSophgoSG2042PlatformPkgTokenSpaceGuid.PcdForceNoMMU ## CONSUMES diff --git a/Platform/Sophgo/SG2042Pkg/Universal/Dxe/SdHostDxe/SdHci.h b/Platform/Sophgo/SG2042Pkg/Universal/Dxe/SdHostDxe/SdHci.h new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/Sophgo/SG2042Pkg/Universal/Dxe/SdHostDxe/SdHci.h @@ -XXX,XX +XXX,XX @@ +/** @file + The header file that provides definitions and function declarations + related to the SD Host Controller Interface (SDHCI) for SD card host controllers. + + Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + Copyright (c) 2023, Academy of Intelligent Innovation, Shandong Universiy, China.P.R. All rights reserved.<BR> + SPDX-License-Identifier: BSD-3-Clause + +**/ + +#ifndef _SD_HCI_H_ +#define _SD_HCI_H_ + +#define SDIO_BASE (FixedPcdGet64(PcdSG2042SDIOBase)) +#define SDHCI_DMA_ADDRESS 0x00 +#define SDHCI_BLOCK_SIZE 0x04 +#define SDHCI_MAKE_BLKSZ(dma, blksz) ((((dma) & 0x7) << 12) | ((blksz) & 0xFFF)) +#define SDHCI_BLOCK_COUNT 0x06 +#define SDHCI_ARGUMENT 0x08 +#define SDHCI_TRANSFER_MODE 0x0C +#define SDHCI_TRNS_DMA BIT0 +#define SDHCI_TRNS_BLK_CNT_EN BIT1 +#define SDHCI_TRNS_ACMD12 BIT2 +#define SDHCI_TRNS_READ BIT4 +#define SDHCI_TRNS_MULTI BIT5 +#define SDHCI_TRNS_RESP_INT BIT8 +#define SDHCI_COMMAND 0x0E +#define SDHCI_CMD_RESP_MASK 0x03 +#define SDHCI_CMD_CRC 0x08 +#define SDHCI_CMD_INDEX 0x10 +#define SDHCI_CMD_DATA 0x20 +#define SDHCI_CMD_ABORTCMD 0xC0 +#define SDHCI_CMD_RESP_NONE 0x00 +#define SDHCI_CMD_RESP_LONG 0x01 +#define SDHCI_CMD_RESP_SHORT 0x02 +#define SDHCI_CMD_RESP_SHORT_BUSY 0x03 +#define SDHCI_MAKE_CMD(c, f) ((((c) & 0xff) << 8) | ((f) & 0xff)) +#define SDHCI_RESPONSE_01 0x10 +#define SDHCI_RESPONSE_23 0x14 +#define SDHCI_RESPONSE_45 0x18 +#define SDHCI_RESPONSE_67 0x1C +#define SDHCI_PSTATE 0x24 +#define SDHCI_CMD_INHIBIT BIT0 +#define SDHCI_CMD_INHIBIT_DAT BIT1 +#define SDHCI_BUF_WR_ENABLE BIT10 +#define SDHCI_BUF_RD_ENABLE BIT11 +#define SDHCI_CARD_INSERTED BIT16 +#define SDHCI_HOST_CONTROL 0x28 +#define SDHCI_DAT_XFER_WIDTH BIT1 +#define SDHCI_EXT_DAT_XFER BIT5 +#define SDHCI_CTRL_DMA_MASK 0x18 +#define SDHCI_CTRL_SDMA 0x00 +#define SDHCI_PWR_CONTROL 0x29 +#define SDHCI_BUS_VOL_VDD1_1_8V 0xC +#define SDHCI_BUS_VOL_VDD1_3_0V 0xE +#define SDHCI_BUF_DATA_R 0x20 +#define SDHCI_BLOCK_GAP_CONTROL 0x2A +#define SDHCI_CLK_CTRL 0x2C +#define SDHCI_TOUT_CTRL 0x2E +#define SDHCI_SOFTWARE_RESET 0x2F +#define SDHCI_RESET_CMD 0x02 +#define SDHCI_RESET_DATA 0x04 +#define SDHCI_INT_STATUS 0x30 +#define SDHCI_ERR_INT_STATUS 0x32 +#define SDHCI_INT_CMD_COMPLETE BIT0 +#define SDHCI_INT_XFER_COMPLETE BIT1 +#define SDHCI_INT_DMA_END BIT3 +#define SDHCI_INT_BUF_WR_READY BIT4 +#define SDHCI_INT_BUF_RD_READY BIT5 +#define SDHCI_INT_ERROR BIT15 +#define SDHCI_INT_STATUS_EN 0x34 +#define SDHCI_ERR_INT_STATUS_EN 0x36 +#define SDHCI_INT_CMD_COMPLETE_EN BIT0 +#define SDHCI_INT_XFER_COMPLETE_EN BIT1 +#define SDHCI_INT_DMA_END_EN BIT3 +#define SDHCI_INT_CARD_INSERTION_EN BIT6 +#define SDHCI_INT_ERROR_EN BIT15 +#define SDHCI_SIGNAL_ENABLE 0x38 +#define SDHCI_HOST_CONTROL2 0x3E +#define SDHCI_HOST_VER4_ENABLE BIT12 +#define SDHCI_CAPABILITIES1 0x40 +#define SDHCI_CAPABILITIES2 0x44 +#define SDHCI_ADMA_SA_LOW 0x58 +#define SDHCI_ADMA_SA_HIGH 0x5C +#define SDHCI_HOST_CNTRL_VERS 0xFE +#define SDHCI_UHS_2_TIMER_CNTRL 0xC2 + +#define P_VENDOR_SPECIFIC_AREA 0xE8 +#define P_VENDOR2_SPECIFIC_AREA 0xEA +#define VENDOR_SD_CTRL 0x2C + +#define SDHCI_PHY_R_OFFSET 0x300 + +#define SDHCI_P_PHY_CNFG (SDHCI_PHY_R_OFFSET + 0x00) +#define SDHCI_P_CMDPAD_CNFG (SDHCI_PHY_R_OFFSET + 0x04) +#define SDHCI_P_DATPAD_CNFG (SDHCI_PHY_R_OFFSET + 0x06) +#define SDHCI_P_CLKPAD_CNFG (SDHCI_PHY_R_OFFSET + 0x08) +#define SDHCI_P_STBPAD_CNFG (SDHCI_PHY_R_OFFSET + 0x0A) +#define SDHCI_P_RSTNPAD_CNFG (SDHCI_PHY_R_OFFSET + 0x0C) +#define SDHCI_P_PADTEST_CNFG (SDHCI_PHY_R_OFFSET + 0x0E) +#define SDHCI_P_PADTEST_OUT (SDHCI_PHY_R_OFFSET + 0x10) +#define SDHCI_P_PADTEST_IN (SDHCI_PHY_R_OFFSET + 0x12) +#define SDHCI_P_COMMDL_CNFG (SDHCI_PHY_R_OFFSET + 0x1C) +#define SDHCI_P_SDCLKDL_CNFG (SDHCI_PHY_R_OFFSET + 0x1D) +#define SDHCI_P_SDCLKDL_DC (SDHCI_PHY_R_OFFSET + 0x1E) +#define SDHCI_P_SMPLDL_CNFG (SDHCI_PHY_R_OFFSET + 0x20) +#define SDHCI_P_ATDL_CNFG (SDHCI_PHY_R_OFFSET + 0x21) +#define SDHCI_P_DLL_CTRL (SDHCI_PHY_R_OFFSET + 0x24) +#define SDHCI_P_DLL_CNFG1 (SDHCI_PHY_R_OFFSET + 0x25) +#define SDHCI_P_DLL_CNFG2 (SDHCI_PHY_R_OFFSET + 0x26) +#define SDHCI_P_DLLDL_CNFG (SDHCI_PHY_R_OFFSET + 0x28) +#define SDHCI_P_DLL_OFFST (SDHCI_PHY_R_OFFSET + 0x29) +#define SDHCI_P_DLLMST_TSTDC (SDHCI_PHY_R_OFFSET + 0x2A) +#define SDHCI_P_DLLLBT_CNFG (SDHCI_PHY_R_OFFSET + 0x2C) +#define SDHCI_P_DLL_STATUS (SDHCI_PHY_R_OFFSET + 0x2E) +#define SDHCI_P_DLLDBG_MLKDC (SDHCI_PHY_R_OFFSET + 0x30) +#define SDHCI_P_DLLDBG_SLKDC (SDHCI_PHY_R_OFFSET + 0x32) + +#define PHY_CNFG_PHY_RSTN 0 +#define PHY_CNFG_PHY_PWRGOOD 1 +#define PHY_CNFG_PAD_SP 16 +#define PHY_CNFG_PAD_SP_MSK 0xf +#define PHY_CNFG_PAD_SN 20 +#define PHY_CNFG_PAD_SN_MSK 0xf + +#define PAD_CNFG_RXSEL 0 +#define PAD_CNFG_RXSEL_MSK 0x7 +#define PAD_CNFG_WEAKPULL_EN 3 +#define PAD_CNFG_WEAKPULL_EN_MSK 0x3 +#define PAD_CNFG_TXSLEW_CTRL_P 5 +#define PAD_CNFG_TXSLEW_CTRL_P_MSK 0xf +#define PAD_CNFG_TXSLEW_CTRL_N 9 +#define PAD_CNFG_TXSLEW_CTRL_N_MSK 0xf + +#define COMMDL_CNFG_DLSTEP_SEL 0 +#define COMMDL_CNFG_DLOUT_EN 1 + +#define SDCLKDL_CNFG_EXTDLY_EN 0 +#define SDCLKDL_CNFG_BYPASS_EN 1 +#define SDCLKDL_CNFG_INPSEL_CNFG 2 +#define SDCLKDL_CNFG_INPSEL_CNFG_MSK 0x3 +#define SDCLKDL_CNFG_UPDATE_DC 4 + +#define SMPLDL_CNFG_EXTDLY_EN 0 +#define SMPLDL_CNFG_BYPASS_EN 1 +#define SMPLDL_CNFG_INPSEL_CNFG 2 +#define SMPLDL_CNFG_INPSEL_CNFG_MSK 0x3 +#define SMPLDL_CNFG_INPSEL_OVERRIDE 4 + +#define ATDL_CNFG_EXTDLY_EN 0 +#define ATDL_CNFG_BYPASS_EN 1 +#define ATDL_CNFG_INPSEL_CNFG 2 +#define ATDL_CNFG_INPSEL_CNFG_MSK 0x3 + +#define SD_USE_PIO 0x1 + +/** + card detect status + -1: haven't check the card detect register + 0 : no card detected + 1 : card detected +**/ +#define SDCARD_STATUS_UNKNOWN (-1) +#define SDCARD_STATUS_INSERTED (1) +#define SDCARD_STATUS_NOT_INSERTED (0) + +typedef struct { + UINT32 CmdIdx; + UINT32 CmdArg; + UINT32 ResponseType; + UINT32 Response[4]; +} MMC_CMD; + +typedef struct { + UINTN RegBase; + UINTN VendorBase; + UINTN DescBase; + UINTN DescSize; + INT32 ClkRate; + INT32 BusWidth; + UINT32 Flags; + INT32 CardIn; +} BM_SD_PARAMS; + +extern BM_SD_PARAMS BmParams; + +/** + SD card sends command. + + @param[in] Idx Command ID. + @param[in] Arg Command argument. + @param[in] RespType Type of response data. + @param[out] Response Response data. + + @retval EFI_SUCCESS The command was sent successfully. + @retval EFI_DEVICE_ERROR There was an error during the command transmission or response handling. + @retval EFI_TIMEOUT The command transmission or response handling timed out. + +**/ +EFI_STATUS +EFIAPI +BmSdSendCmd ( + IN UINT32 Idx, + IN UINT32 Arg, + IN UINT32 RespType, + OUT UINT32 *Response + ); + +/** + Detect the status of the SD card. + + @return The status of the SD card: + - SDCARD_STATUS_INSERTED: The SD card is inserted. + - SDCARD_STATUS_NOT_INSERTED: The SD card is not inserted. + - SDCARD_STATUS_UNKNOWN: The status of the SD card is unknown. + +**/ +INT32 +BmSdCardDetect ( + VOID + ); + +/** + Set the input/output settings for the SD card. + + @param[in] Clk The clock frequency for the SD card. + @param[in] Width The bus width for data transfer. + + @retval EFI_SUCCESS The input/output settings were set successfully. + @retval EFI_UNSUPPORTED The specified bus width is not supported. + +**/ +EFI_STATUS +BmSdSetIos ( + IN UINT32 Clk, + IN UINT32 Width + ); + +/** + Prepare the SD card for data transfer. + Set the number and size of data blocks before sending IO commands to the SD card. + + @param[in] Lba Logical Block Address. + @param[in] Buf Buffer Address. + @param[in] Size Size of Data Blocks. + + @retval EFI_SUCCESS The SD card was prepared successfully. + @retval Other An error occurred during the preparation of the SD card. + +**/ +EFI_STATUS +BmSdPrepare ( + IN INT32 Lba, + IN UINTN Buf, + IN UINTN Size + ); + +/** + SD card sends command to read data blocks. + + @param[in] Lba Logical Block Address. + @param[in] Buf Buffer Address. + @param[in] Size Size of Data Blocks. + + @retval EFI_SUCCESS The command to read data blocks was sent successfully. + @retval EFI_TIMEOUT The command transmission or data transfer timed out. + +**/ +EFI_STATUS +BmSdRead ( + IN INT32 Lba, + IN UINT32* Buf, + IN UINTN Size + ); + +/** + SD card sends commands to write data blocks. + + @param[in] Lba Logical Block Address. + @param[in] Buf Buffer Address. + @param[in] Size Size of Data Blocks. + + @retval EFI_SUCCESS The command to write data blocks was sent successfully. + @retval EFI_TIMEOUT The command transmission or data transfer timed out. + +**/ +EFI_STATUS +BmSdWrite ( + IN INT32 Lba, + IN UINT32* Buf, + IN UINTN Size + ); + +/** + Initialize the SD card. + + This function performs the initialization of the SD card hardware and settings. + + @param[in] Flags Initialization flags. + + @retval EFI_SUCCESS The SD card was initialized successfully. + +**/ +EFI_STATUS +SdInit ( + IN UINT32 flags + ); + +#endif diff --git a/Platform/Sophgo/SG2042Pkg/Universal/Dxe/SdHostDxe/SdHci.c b/Platform/Sophgo/SG2042Pkg/Universal/Dxe/SdHostDxe/SdHci.c new file mode 100755 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/Sophgo/SG2042Pkg/Universal/Dxe/SdHostDxe/SdHci.c @@ -XXX,XX +XXX,XX @@ +/** @file + The implementation for handling SD card operations using the SD Host Controller Interface (SDHCI). + + Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + Copyright (c) 2023, Academy of Intelligent Innovation, Shandong Universiy, China.P.R. All rights reserved.<BR> + SPDX-License-Identifier: BSD-3-Clause + +**/ + +#include <Uefi.h> +#include <Base.h> +#include <Library/BaseLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/PcdLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/BaseMemoryLib.h> +#include <Include/MmcHost.h> + +#include "SdHci.h" + +#define SDCARD_INIT_FREQ (200 * 1000) +#define SDCARD_TRAN_FREQ (6 * 1000 * 1000) + +/** + Return the clock rate of SD card. + + @retval the clock rate of SD card. + +**/ +INT32 +BmGetSdClk ( + VOID + ) +{ + return 100*1000*1000; +} + +/** + SD card sends command with response block data. + + @param Cmd Command sent by SD card. + + @retval EFI_SUCCESS The command with response block data was sent successfully. + @retval EFI_DEVICE_ERROR There was an error during the command transmission or response handling. + @retval EFI_TIMEOUT The command transmission or response handling timed out. + +**/ +STATIC +EFI_STATUS +SdSendCmdWithData ( + IN OUT MMC_CMD *Cmd + ) +{ + UINTN Base; + UINT32 Mode; + UINT32 State; + UINT32 DmaAddr; + UINT32 Flags; + UINT32 Timeout; + + Base = BmParams.RegBase; + Mode = 0; + Flags = 0; + + // Make sure Cmd line is clear + while (1) { + if (!(MmioRead32 (Base + SDHCI_PSTATE) & SDHCI_CMD_INHIBIT)) + break; + } + + switch (Cmd->CmdIdx) { + case MMC_CMD17: + case MMC_CMD18: + case MMC_ACMD51: + Mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI | SDHCI_TRNS_READ; + if (!(BmParams.Flags & SD_USE_PIO)) + Mode |= SDHCI_TRNS_DMA; + break; + case MMC_CMD24: + case MMC_CMD25: + Mode = (SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI) & ~SDHCI_TRNS_READ; + if (!(BmParams.Flags & SD_USE_PIO)) + Mode |= SDHCI_TRNS_DMA; + break; + default: + ASSERT(0); + } + + MmioWrite16 (Base + SDHCI_TRANSFER_MODE, Mode); + MmioWrite32 (Base + SDHCI_ARGUMENT, Cmd->CmdArg); + + // set Cmd Flags + if (Cmd->CmdIdx == MMC_CMD0) + Flags |= SDHCI_CMD_RESP_NONE; + else { + if (Cmd->ResponseType & MMC_RSP_136) + Flags |= SDHCI_CMD_RESP_LONG; + else + Flags |= SDHCI_CMD_RESP_SHORT; + if (Cmd->ResponseType & MMC_RSP_CRC) + Flags |= SDHCI_CMD_CRC; + if (Cmd->ResponseType & MMC_RSP_CMD_IDX) + Flags |= SDHCI_CMD_INDEX; + } + + Flags |= SDHCI_CMD_DATA; + + // issue the Cmd + MmioWrite16 (Base + SDHCI_COMMAND, SDHCI_MAKE_CMD(Cmd->CmdIdx, Flags)); + + // check Cmd complete if necessary + if ((MmioRead16 (Base + SDHCI_TRANSFER_MODE) & SDHCI_TRNS_RESP_INT) == 0) { + Timeout = 100000; + while (1) { + State = MmioRead16 (Base + SDHCI_INT_STATUS); + if (State & SDHCI_INT_ERROR) { + DEBUG ((DEBUG_ERROR, "%a: interrupt error: 0x%x 0x%x\n", __func__, MmioRead16 (Base + SDHCI_INT_STATUS), + MmioRead16 (Base + SDHCI_ERR_INT_STATUS))); + return EFI_DEVICE_ERROR; + } + if (State & SDHCI_INT_CMD_COMPLETE) { + MmioWrite16 (Base + SDHCI_INT_STATUS, State | SDHCI_INT_CMD_COMPLETE); + break; + } + + gBS->Stall (1); + if (!Timeout--) { + DEBUG ((DEBUG_ERROR, "%a: Timeout!\n", __func__)); + return EFI_TIMEOUT; + } + } + + // get Cmd respond + if (Flags != SDHCI_CMD_RESP_NONE) + Cmd->Response[0] = MmioRead32 (Base + SDHCI_RESPONSE_01); + if (Flags & SDHCI_CMD_RESP_LONG) { + Cmd->Response[1] = MmioRead32 (Base + SDHCI_RESPONSE_23); + Cmd->Response[2] = MmioRead32 (Base + SDHCI_RESPONSE_45); + Cmd->Response[3] = MmioRead32 (Base + SDHCI_RESPONSE_67); + } + } + + // check dma/transfer complete + if (!(BmParams.Flags & SD_USE_PIO)) { + while (1) { + State = MmioRead16 (Base + SDHCI_INT_STATUS); + if (State & SDHCI_INT_ERROR) { + DEBUG ((DEBUG_ERROR, "%a: interrupt error: 0x%x 0x%x\n", __func__, MmioRead16 (Base + SDHCI_INT_STATUS), + MmioRead16 (Base + SDHCI_ERR_INT_STATUS))); + return EFI_DEVICE_ERROR; + } + + if (State & SDHCI_INT_XFER_COMPLETE) { + MmioWrite16 (Base + SDHCI_INT_STATUS, State); + break; + } + + if (State & SDHCI_INT_DMA_END) { + MmioWrite16 (Base + SDHCI_INT_STATUS, State); + if (MmioRead16 (Base + SDHCI_HOST_CONTROL2) & SDHCI_HOST_VER4_ENABLE) { + DmaAddr = MmioRead32 (Base + SDHCI_ADMA_SA_LOW); + MmioWrite32 (Base + SDHCI_ADMA_SA_LOW, DmaAddr); + MmioWrite32 (Base + SDHCI_ADMA_SA_HIGH, 0); + } else { + DmaAddr = MmioRead32 (Base + SDHCI_DMA_ADDRESS); + MmioWrite32 (Base + SDHCI_DMA_ADDRESS, DmaAddr); + } + } + + } + } + + return EFI_SUCCESS; +} + +/** + SD card sends command without response block data. + + @param Cmd Command sent by SD card. + + @retval EFI_SUCCESS The command without response block data was sent successfully. + @retval EFI_DEVICE_ERROR There was an error during the command transmission or response handling. + @retval EFI_TIMEOUT The command transmission or response handling timed out. + +**/ +STATIC +EFI_STATUS +SdSendCmdWithoutData ( + IN OUT MMC_CMD *Cmd + ) +{ + UINTN Base; + UINT32 State; + UINT32 Flags; + UINT32 Timeout; + + Base = BmParams.RegBase; + Flags = 0x0; + Timeout = 10000; + + // make sure Cmd line is clear + while (1) { + if (!(MmioRead32 (Base + SDHCI_PSTATE) & SDHCI_CMD_INHIBIT)) + break; + } + + // set Cmd Flags + if (Cmd->CmdIdx == MMC_CMD0) + Flags |= SDHCI_CMD_RESP_NONE; + else if (Cmd->CmdIdx == MMC_CMD1) + Flags |= SDHCI_CMD_RESP_SHORT; + else if (Cmd->CmdIdx == MMC_ACMD41) + Flags |= SDHCI_CMD_RESP_SHORT; + else { + if (Cmd->ResponseType & MMC_RSP_136) + Flags |= SDHCI_CMD_RESP_LONG; + else + Flags |= SDHCI_CMD_RESP_SHORT; + if (Cmd->ResponseType & MMC_RSP_CRC) + Flags |= SDHCI_CMD_CRC; + if (Cmd->ResponseType & MMC_RSP_CMD_IDX) + Flags |= SDHCI_CMD_INDEX; + } + + // make sure dat line is clear if necessary + if (Flags != SDHCI_CMD_RESP_NONE) { + while (1) { + if (!(MmioRead32 (Base + SDHCI_PSTATE) & SDHCI_CMD_INHIBIT_DAT)) + break; + } + } + + // issue the Cmd + MmioWrite32 (Base + SDHCI_ARGUMENT, Cmd->CmdArg); + MmioWrite16 (Base + SDHCI_COMMAND, SDHCI_MAKE_CMD(Cmd->CmdIdx, Flags)); + + // check Cmd complete + Timeout = 100000; + while (1) { + State = MmioRead16 (Base + SDHCI_INT_STATUS); + if (State & SDHCI_INT_ERROR) { + DEBUG ((DEBUG_ERROR, "%a: interrupt error: 0x%x 0x%x\n", __func__, MmioRead16 (Base + SDHCI_INT_STATUS), + MmioRead16 (Base + SDHCI_ERR_INT_STATUS))); + return EFI_DEVICE_ERROR; + } + if (State & SDHCI_INT_CMD_COMPLETE) { + MmioWrite16 (Base + SDHCI_INT_STATUS, State | SDHCI_INT_CMD_COMPLETE); + break; + } + + gBS->Stall (1); + if (!Timeout--) { + DEBUG ((DEBUG_ERROR, "%a: Timeout!\n", __func__)); + return EFI_TIMEOUT; + } + } + + // get Cmd respond + if (!(Flags & SDHCI_CMD_RESP_NONE)) + Cmd->Response[0] = MmioRead32 (Base + SDHCI_RESPONSE_01); + if (Flags & SDHCI_CMD_RESP_LONG) { + Cmd->Response[1] = MmioRead32 (Base + SDHCI_RESPONSE_23); + Cmd->Response[2] = MmioRead32 (Base + SDHCI_RESPONSE_45); + Cmd->Response[3] = MmioRead32 (Base + SDHCI_RESPONSE_67); + } + + return EFI_SUCCESS; +} + +/** + SD card sends command. + + @param[in] Idx Command ID. + @param[in] Arg Command argument. + @param[in] RespType Type of response data. + @param[out] Response Response data. + + @retval EFI_SUCCESS The command was sent successfully. + @retval EFI_DEVICE_ERROR There was an error during the command transmission or response handling. + @retval EFI_TIMEOUT The command transmission or response handling timed out. + +**/ +EFI_STATUS +EFIAPI +BmSdSendCmd ( + IN UINT32 Idx, + IN UINT32 Arg, + IN UINT32 RespType, + OUT UINT32 *Response + ) +{ + EFI_STATUS Status; + MMC_CMD Cmd; + + // DEBUG ((DEBUG_INFO, "%a: SDHCI Cmd, Idx=%d, Arg=0x%x, ResponseType=0x%x\n", __func__, Idx, Arg, RespType)); + + ZeroMem(&Cmd,sizeof(MMC_CMD)); + + Cmd.CmdIdx = Idx; + Cmd.CmdArg = Arg; + Cmd.ResponseType = RespType; + + switch (Cmd.CmdIdx) { + case MMC_CMD17: + case MMC_CMD18: + case MMC_CMD24: + case MMC_CMD25: + case MMC_ACMD51: + Status = SdSendCmdWithData(&Cmd); + break; + default: + Status = SdSendCmdWithoutData(&Cmd); + } + + if ((Status == EFI_SUCCESS) && (Response != NULL)) { + for (INT32 I = 0; I < 4; I++) { + *Response = Cmd.Response[I]; + Response++; + } + } + return Status; +} + +/** + Set clock frequency of SD card. + + @param[in] Clk The clock frequency of SD card. + +**/ +VOID +SdSetClk ( + IN INT32 Clk + ) +{ + INT32 I; + INT32 Div; + UINTN Base; + + ASSERT (Clk > 0); + + if (BmParams.ClkRate <= Clk) { + Div = 0; + } else { + for (Div = 0x1; Div < 0xFF; Div++) { + if (BmParams.ClkRate / (2 * Div) <= Clk) + break; + } + } + ASSERT (Div <= 0xFF); + + Base = BmParams.RegBase; + if (MmioRead16 (Base + SDHCI_HOST_CONTROL2) & (1 << 15)) { + //verbose("Use SDCLK Preset Value\n"); + } else { + //verbose("Set SDCLK by driver. Div=0x%x(%d)\n", Div, Div); + MmioWrite16 (Base + SDHCI_CLK_CTRL, + MmioRead16 (Base + SDHCI_CLK_CTRL) & ~0x9); // disable INTERNAL_CLK_EN and PLL_ENABLE + MmioWrite16 (Base + SDHCI_CLK_CTRL, + (MmioRead16 (Base + SDHCI_CLK_CTRL) & 0xDF) | Div << 8); // set Clk Div + MmioWrite16 (Base + SDHCI_CLK_CTRL, + MmioRead16 (Base + SDHCI_CLK_CTRL) | 0x1); // set INTERNAL_CLK_EN + + for (I = 0; I <= 150000; I += 100) { + if (MmioRead16 (Base + SDHCI_CLK_CTRL) & 0x2) + break; + gBS->Stall (100); + } + + if (I > 150000) { + DEBUG ((DEBUG_ERROR, "%a: SD INTERNAL_CLK_EN setting FAILED!\n", __func__)); + ASSERT(0); + } + + MmioWrite16 (Base + SDHCI_CLK_CTRL, MmioRead16 (Base + SDHCI_CLK_CTRL) | 0x8); // set PLL_ENABLE + + for (I = 0; I <= 150000; I += 100) { + if (MmioRead16 (Base + SDHCI_CLK_CTRL) & 0x2) + return; + gBS->Stall (100); + } + } + + DEBUG ((DEBUG_INFO, "%a: SD PLL setting FAILED!\n", __func__)); +} + +/** + Change clock frequency of SD card. + + @param[in] Clk The clock frequency of SD card. + +**/ +VOID +SdChangeClk ( + IN INT32 Clk + ) +{ + INT32 I; + INT32 Div; + UINTN Base; + + ASSERT (Clk > 0); + + if (BmParams.ClkRate <= Clk) { + Div = 0; + } else { + for (Div = 0x1; Div < 0xFF; Div++) { + if (BmParams.ClkRate / (2 * Div) <= Clk) + break; + } + } + ASSERT (Div <= 0xFF); + + Base = BmParams.RegBase; + + MmioWrite16 (Base + SDHCI_CLK_CTRL, + MmioRead16 (Base + SDHCI_CLK_CTRL) & ~(0x1 << 2)); // stop SD clock + + MmioWrite16 (Base + SDHCI_CLK_CTRL, + MmioRead16 (Base + SDHCI_CLK_CTRL) & ~0x8); // disable PLL_ENABLE + + if (MmioRead16 (Base + SDHCI_HOST_CONTROL2) & (1 << 15)) { + MmioWrite16 (Base + SDHCI_HOST_CONTROL2, + MmioRead16 (Base + SDHCI_HOST_CONTROL2) & ~0x7); // clr UHS_MODE_SEL + } else { + MmioWrite16 (Base + SDHCI_CLK_CTRL, + (MmioRead16 (Base + SDHCI_CLK_CTRL) & 0xDF) | Div << 8); // set Clk Div + MmioWrite16 (Base + SDHCI_CLK_CTRL, + MmioRead16 (Base + SDHCI_CLK_CTRL) & ~(0x1 << 5)); // CLK_GEN_SELECT + } + + MmioWrite16 (Base + SDHCI_CLK_CTRL, + MmioRead16 (Base + SDHCI_CLK_CTRL) | 0xc); // enable PLL_ENABLE + + for (I = 0; I <= 150000; I += 100) { + if (MmioRead16 (Base + SDHCI_CLK_CTRL) & 0x2) + return; + gBS->Stall (100); + } + + DEBUG ((DEBUG_INFO, "%a: SD PLL setting FAILED!\n", __func__)); +} + +/** + Detect the status of the SD card. + + @return The status of the SD card: + - SDCARD_STATUS_INSERTED: The SD card is inserted. + - SDCARD_STATUS_NOT_INSERTED: The SD card is not inserted. + - SDCARD_STATUS_UNKNOWN: The status of the SD card is unknown. + +**/ +INT32 +BmSdCardDetect ( + VOID + ) +{ + UINTN Base; + UINTN Reg; + + Base = BmParams.RegBase; + + if (BmParams.CardIn != SDCARD_STATUS_UNKNOWN) + return BmParams.CardIn; + + MmioWrite16 (Base + SDHCI_INT_STATUS_EN, + MmioRead16 (Base + SDHCI_INT_STATUS_EN) | SDHCI_INT_CARD_INSERTION_EN); + + Reg = MmioRead32 (Base + SDHCI_PSTATE); + + if (Reg & SDHCI_CARD_INSERTED) + BmParams.CardIn = SDCARD_STATUS_INSERTED; + else + BmParams.CardIn = SDCARD_STATUS_NOT_INSERTED; + + return BmParams.CardIn; +} + +/** + SD card hardware initialization. + +**/ +STATIC +VOID +SdHwInit ( + VOID + ) +{ + UINTN Base; + + Base = BmParams.RegBase; + BmParams.VendorBase = Base + (MmioRead16 (Base + P_VENDOR_SPECIFIC_AREA) & ((1 << 12) - 1)); + + // deasset reset of phy + MmioWrite32 (Base + SDHCI_P_PHY_CNFG, MmioRead32 (Base + SDHCI_P_PHY_CNFG) | (1 << PHY_CNFG_PHY_RSTN)); + + // reset data & Cmd + MmioWrite8 (Base + SDHCI_SOFTWARE_RESET, 0x6); + + // init common parameters + MmioWrite8 (Base + SDHCI_PWR_CONTROL, (0x7 << 1)); + MmioWrite8 (Base + SDHCI_TOUT_CTRL, 0xe); // for TMCLK 50Khz + MmioWrite16 (Base + SDHCI_HOST_CONTROL2, + MmioRead16 (Base + SDHCI_HOST_CONTROL2) | 1 << 11); // set cmd23 support + MmioWrite16 (Base + SDHCI_CLK_CTRL, MmioRead16 (Base + SDHCI_CLK_CTRL) & ~(0x1 << 5)); // divided clock Mode + + // set host version 4 parameters + MmioWrite16 (Base + SDHCI_HOST_CONTROL2, + MmioRead16 (Base + SDHCI_HOST_CONTROL2) | (1 << 12)); // set HOST_VER4_ENABLE + if (MmioRead32 (Base + SDHCI_CAPABILITIES1) & (0x1 << 27)) { + MmioWrite16 (Base + SDHCI_HOST_CONTROL2, + MmioRead16 (Base + SDHCI_HOST_CONTROL2) | 0x1 << 13); // set 64bit addressing + } + + // if support asynchronous int + if (MmioRead32 (Base + SDHCI_CAPABILITIES1) & (0x1 << 29)) + MmioWrite16 (Base + SDHCI_HOST_CONTROL2, + MmioRead16 (Base + SDHCI_HOST_CONTROL2) | (0x1 << 14)); // enable async int + // give some time to power down card + gBS->Stall (20000); + + MmioWrite16 (Base + SDHCI_HOST_CONTROL2, + MmioRead16 (Base + SDHCI_HOST_CONTROL2) & ~(0x1 << 8)); // clr UHS2_IF_ENABLE + MmioWrite8 (Base + SDHCI_PWR_CONTROL, + MmioRead8 (Base + SDHCI_PWR_CONTROL) | 0x1); // set SD_BUS_PWR_VDD1 + MmioWrite16 (Base + SDHCI_HOST_CONTROL2, + MmioRead16 (Base + SDHCI_HOST_CONTROL2) & ~0x7); // clr UHS_MODE_SEL + SdSetClk (SDCARD_INIT_FREQ); + gBS->Stall (50000); + + MmioWrite16 (Base + SDHCI_CLK_CTRL, + MmioRead16 (Base + SDHCI_CLK_CTRL) | (0x1 << 2)); // supply SD clock + gBS->Stall (400); // wait for voltage ramp up time at least 74 cycle, 400us is 80 cycles for 200Khz + + MmioWrite16 (Base + SDHCI_INT_STATUS, MmioRead16 (Base + SDHCI_INT_STATUS) | (0x1 << 6)); + + // we enable all interrupt Status here for testing + MmioWrite16 (Base + SDHCI_INT_STATUS_EN, MmioRead16 (Base + SDHCI_INT_STATUS_EN) | 0xFFFF); + MmioWrite16 (Base + SDHCI_ERR_INT_STATUS_EN, MmioRead16 (Base + SDHCI_ERR_INT_STATUS_EN) | 0xFFFF); + + //verbose("SD init done\n"); +} + +/** + Set the input/output settings for the SD card. + + @param[in] Clk The clock frequency for the SD card. + @param[in] Width The bus width for data transfer. + + @retval EFI_SUCCESS The input/output settings were set successfully. + @retval EFI_UNSUPPORTED The specified bus width is not supported. + +**/ +EFI_STATUS +BmSdSetIos ( + IN UINT32 Clk, + IN UINT32 Width + ) +{ + switch (Width) { + case MMC_BUS_WIDTH_1: + MmioWrite8 (BmParams.RegBase + SDHCI_HOST_CONTROL, + MmioRead8 (BmParams.RegBase + SDHCI_HOST_CONTROL) & + ~SDHCI_DAT_XFER_WIDTH); + break; + case MMC_BUS_WIDTH_4: + MmioWrite8 (BmParams.RegBase + SDHCI_HOST_CONTROL, + MmioRead8 (BmParams.RegBase + SDHCI_HOST_CONTROL) | + SDHCI_DAT_XFER_WIDTH); + break; + default: + ASSERT (0); + } + + SdChangeClk (Clk); + + return EFI_SUCCESS; +} + +/** + Prepare the SD card for data transfer. + Set the number and size of data blocks before sending IO commands to the SD card. + + @param[in] Lba Logical Block Address. + @param[in] Buf Buffer Address. + @param[in] Size Size of Data Blocks. + + @retval EFI_SUCCESS The SD card was prepared successfully. + @retval Other An error occurred during the preparation of the SD card. + +**/ +EFI_STATUS +BmSdPrepare ( + IN INT32 Lba, + IN UINTN Buf, + IN UINTN Size + ) +{ + UINTN LoadAddr; + UINTN Base; + UINT32 BlockCnt; + UINT32 BlockSize; + UINT8 Tmp; + + LoadAddr = Buf; + + if (Size >= MMC_BLOCK_SIZE) { + // CMD17, 18, 24, 25 + // ASSERT (((LoadAddr & MMC_BLOCK_MASK) == 0) && ((Size % MMC_BLOCK_SIZE) == 0)); + BlockSize = MMC_BLOCK_SIZE; + BlockCnt = Size / MMC_BLOCK_SIZE; + } else { + // ACMD51 + ASSERT (((LoadAddr & 8) == 0) && ((Size % 8) == 0)); + BlockSize = 8; + BlockCnt = Size / 8; + } + + Base = BmParams.RegBase; + + if (!(BmParams.Flags & SD_USE_PIO)) { + if (MmioRead16 (Base + SDHCI_HOST_CONTROL2) & SDHCI_HOST_VER4_ENABLE) { + MmioWrite32 (Base + SDHCI_ADMA_SA_LOW, LoadAddr); + MmioWrite32 (Base + SDHCI_ADMA_SA_HIGH, (LoadAddr >> 32)); + MmioWrite32 (Base + SDHCI_DMA_ADDRESS, BlockCnt); + MmioWrite16 (Base + SDHCI_BLOCK_COUNT, 0); + } else { + ASSERT((LoadAddr >> 32) == 0); + MmioWrite32 (Base + SDHCI_DMA_ADDRESS, LoadAddr); + MmioWrite16 (Base + SDHCI_BLOCK_COUNT, BlockCnt); + } + + // 512K bytes SDMA buffer boundary + MmioWrite16 (Base + SDHCI_BLOCK_SIZE, SDHCI_MAKE_BLKSZ(7, BlockSize)); + + // select SDMA + Tmp = MmioRead8 (Base + SDHCI_HOST_CONTROL); + Tmp &= ~SDHCI_CTRL_DMA_MASK; + Tmp |= SDHCI_CTRL_SDMA; + MmioWrite8 (Base + SDHCI_HOST_CONTROL, Tmp); + } else { + MmioWrite16 (Base + SDHCI_BLOCK_SIZE, BlockSize); + MmioWrite16 (Base + SDHCI_BLOCK_COUNT, BlockCnt); + } + + return EFI_SUCCESS; +} + +/** + SD card sends command to read data blocks. + + @param[in] Lba Logical Block Address. + @param[in] Buf Buffer Address. + @param[in] Size Size of Data Blocks. + + @retval EFI_SUCCESS The command to read data blocks was sent successfully. + @retval EFI_TIMEOUT The command transmission or data transfer timed out. + +**/ +EFI_STATUS +BmSdRead ( + IN INT32 Lba, + IN UINT32* Buf, + IN UINTN Size + ) +{ + UINT32 Timeout; + UINTN Base; + UINT32 *Data; + UINT32 BlockSize; + UINT32 BlockCnt; + UINT32 Status; + + Timeout = 0; + Base = BmParams.RegBase; + Data = Buf; + BlockSize = 0; + BlockCnt = 0; + Status = 0; + + if (BmParams.Flags & SD_USE_PIO) { + BlockSize = MmioRead16 (Base + SDHCI_BLOCK_SIZE); + BlockCnt = Size / BlockSize; + BlockSize /= 4; + + for (INT32 I = 0; I < BlockCnt; ) { + Status = MmioRead16 (Base + SDHCI_INT_STATUS); + if ((Status & SDHCI_INT_BUF_RD_READY) && + (MmioRead32 (Base + SDHCI_PSTATE) & SDHCI_BUF_RD_ENABLE)) { + MmioWrite16 (Base + SDHCI_INT_STATUS, SDHCI_INT_BUF_RD_READY); + for (INT32 j = 0; j < BlockSize; j++) { + *(Data++) = MmioRead32 (Base + SDHCI_BUF_DATA_R); + } + + Timeout = 0; + I++; + } else { + gBS->Stall (1); + Timeout++; + } + + if (Timeout >= 10000) { + DEBUG ((DEBUG_INFO, "%a: sdhci read data Timeout\n", __func__)); + goto Timeout; + } + } + + Timeout = 0; + while (1) { + Status = MmioRead16 (Base + SDHCI_INT_STATUS); + if (Status & SDHCI_INT_XFER_COMPLETE) { + MmioWrite16 (Base + SDHCI_INT_STATUS, + Status | SDHCI_INT_XFER_COMPLETE); + + return EFI_SUCCESS; + } else { + gBS->Stall (1); + Timeout++; + } + + if (Timeout >= 10000) { + DEBUG ((DEBUG_INFO, "%a:wait xfer complete Timeout\n", __func__)); + goto Timeout; + } + } + } else { + return EFI_SUCCESS; + } + +Timeout: + return EFI_TIMEOUT; + +} + +/** + SD card sends commands to write data blocks. + + @param[in] Lba Logical Block Address. + @param[in] Buf Buffer Address. + @param[in] Size Size of Data Blocks. + + @retval EFI_SUCCESS The command to write data blocks was sent successfully. + @retval EFI_TIMEOUT The command transmission or data transfer timed out. + +**/ +EFI_STATUS +BmSdWrite ( + IN INT32 Lba, + IN UINT32* Buf, + IN UINTN Size + ) +{ + UINT32 Timeout; + UINTN Base; + UINT32 *Data; + UINT32 BlockSize; + UINT32 BlockCnt; + UINT32 Status; + + Timeout = 0; + Base = BmParams.RegBase; + Data = Buf; + BlockSize = 0; + BlockCnt = 0; + Status = 0; + + if (BmParams.Flags & SD_USE_PIO) { + BlockSize = MmioRead16 (Base + SDHCI_BLOCK_SIZE); + BlockCnt = Size / BlockSize; + BlockSize /= 4; + + for (INT32 j = 0; j < BlockSize; j++) { + MmioWrite32 (Base + SDHCI_BUF_DATA_R, *(Data++)); + } + + for (INT32 I = 0; I < BlockCnt-1; ) { + Status = MmioRead16 (Base + SDHCI_INT_STATUS); + if ((Status & SDHCI_INT_BUF_WR_READY) && + (MmioRead32 (Base + SDHCI_PSTATE) & + SDHCI_BUF_WR_ENABLE)) { + MmioWrite16 (Base + SDHCI_INT_STATUS, SDHCI_INT_BUF_WR_READY); + for (INT32 j = 0; j < BlockSize; j++) { + MmioWrite32 (Base + SDHCI_BUF_DATA_R, *(Data++)); + } + + Timeout = 0; + I++; + } else { + gBS->Stall (1); + Timeout++; + } + + if (Timeout >= 10000000) { + DEBUG ((DEBUG_INFO, "%a:sdhci write data Timeout\n", __func__)); + goto Timeout; + } + } + + Timeout = 0; + while (1) { + Status = MmioRead16 (Base + SDHCI_INT_STATUS); + if (Status & SDHCI_INT_XFER_COMPLETE) { + MmioWrite16 (Base + SDHCI_INT_STATUS, + Status | SDHCI_INT_XFER_COMPLETE); + + return EFI_SUCCESS; + } else { + gBS->Stall (1); + Timeout++; + } + + if (Timeout >= 10000) { + DEBUG ((DEBUG_INFO, "%a:wait xfer complete Timeout\n", __func__)); + goto Timeout; + } + } + } else + return EFI_SUCCESS; + +Timeout: + return EFI_TIMEOUT; +} + +/** + Initialize the SD PHY. + + This function performs the initialization of the SD PHY hardware. + +**/ +VOID +SdPhyInit ( + VOID + ) +{ + UINTN Base; + INT32 RetryCount; + + Base = BmParams.RegBase; + RetryCount = 100; + + // reset hardware + MmioWrite8 (Base + SDHCI_SOFTWARE_RESET, 0x7); + while (MmioRead8 (Base + SDHCI_SOFTWARE_RESET)) { + if (RetryCount-- > 0) + gBS->Stall (10000); + else + break; + } + + // Wait for the PHY power on ready + RetryCount = 100; + while (!(MmioRead32 (Base + SDHCI_P_PHY_CNFG) & (1 << PHY_CNFG_PHY_PWRGOOD))) { + if (RetryCount-- > 0) + gBS->Stall (10000); + else + break; + } + + // Asset reset of phy + MmioAnd32 (Base + SDHCI_P_PHY_CNFG, ~(1 << PHY_CNFG_PHY_RSTN)); + + // Set PAD_SN PAD_SP + MmioWrite32 (Base + SDHCI_P_PHY_CNFG, + (1 << PHY_CNFG_PHY_PWRGOOD) | (0x9 << PHY_CNFG_PAD_SP) | (0x8 << PHY_CNFG_PAD_SN)); + + // Set CMDPAD + MmioWrite16 (Base + SDHCI_P_CMDPAD_CNFG, + (0x2 << PAD_CNFG_RXSEL) | (1 << PAD_CNFG_WEAKPULL_EN) | + (0x3 << PAD_CNFG_TXSLEW_CTRL_P) | (0x2 << PAD_CNFG_TXSLEW_CTRL_N)); + + // Set DATAPAD + MmioWrite16 (Base + SDHCI_P_DATPAD_CNFG, + (0x2 << PAD_CNFG_RXSEL) | (1 << PAD_CNFG_WEAKPULL_EN) | + (0x3 << PAD_CNFG_TXSLEW_CTRL_P) | (0x2 << PAD_CNFG_TXSLEW_CTRL_N)); + + // Set CLKPAD + MmioWrite16 (Base + SDHCI_P_CLKPAD_CNFG, + (0x2 << PAD_CNFG_RXSEL) | (0x3 << PAD_CNFG_TXSLEW_CTRL_P) | (0x2 << PAD_CNFG_TXSLEW_CTRL_N)); + + // Set STB_PAD + MmioWrite16 (Base + SDHCI_P_STBPAD_CNFG, + (0x2 << PAD_CNFG_RXSEL) | (0x2 << PAD_CNFG_WEAKPULL_EN) | + (0x3 << PAD_CNFG_TXSLEW_CTRL_P) | (0x2 << PAD_CNFG_TXSLEW_CTRL_N)); + + // Set RSTPAD + MmioWrite16 (Base + SDHCI_P_RSTNPAD_CNFG, + (0x2 << PAD_CNFG_RXSEL) | (1 << PAD_CNFG_WEAKPULL_EN) | + (0x3 << PAD_CNFG_TXSLEW_CTRL_P) | (0x2 << PAD_CNFG_TXSLEW_CTRL_N)); + + // Set SDCLKDL_CNFG, EXTDLY_EN = 1, fix delay + MmioWrite8 (Base + SDHCI_P_SDCLKDL_CNFG, (1 << SDCLKDL_CNFG_EXTDLY_EN)); + + // Set SMPLDL_CNFG, Bypass + MmioWrite8 (Base + SDHCI_P_SMPLDL_CNFG, (1 << SMPLDL_CNFG_BYPASS_EN)); + + // Set ATDL_CNFG, tuning Clk not use for init + MmioWrite8 (Base + SDHCI_P_ATDL_CNFG, (2 << ATDL_CNFG_INPSEL_CNFG)); + + return; +} + +/** + Initialize the SD card. + + This function performs the initialization of the SD card hardware and settings. + + @param[in] Flags Initialization flags. + + @retval EFI_SUCCESS The SD card was initialized successfully. + +**/ +EFI_STATUS +SdInit ( + IN UINT32 Flags +) +{ + BmParams.ClkRate = BmGetSdClk (); + + DEBUG ((DEBUG_INFO, "SD initializing %dHz\n", BmParams.ClkRate)); + + BmParams.Flags = Flags; + + SdPhyInit (); + + SdHwInit (); + + return EFI_SUCCESS; +} diff --git a/Platform/Sophgo/SG2042Pkg/Universal/Dxe/SdHostDxe/SdHostDxe.c b/Platform/Sophgo/SG2042Pkg/Universal/Dxe/SdHostDxe/SdHostDxe.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/Sophgo/SG2042Pkg/Universal/Dxe/SdHostDxe/SdHostDxe.c @@ -XXX,XX +XXX,XX @@ +/** @file + This file implements the SD host controller driver for UEFI systems. + The file contains the implementation of the EFI_MMC_HOST_PROTOCOL, which provides + the necessary interfaces for handling communication and data transfer with SD cards. + + Copyright (c) 2017, Andrei Warkentin <andrey.warkentin@gmail.com> + Copyright (c) Microsoft Corporation. All rights reserved. + Copyright (c) 2023, Academy of Intelligent Innovation, Shandong Universiy, China.P.R. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <Uefi.h> +#include <Library/BaseLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/DebugLib.h> +#include <Library/DevicePathLib.h> +#include <Library/IoLib.h> +#include <Library/PcdLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/DmaLib.h> +#include <Library/TimerLib.h> + +#include <Protocol/EmbeddedExternalDevice.h> +#include <Protocol/BlockIo.h> +#include <Protocol/DevicePath.h> +#include <Include/MmcHost.h> + +#include "SdHci.h" + +#define SDHOST_BLOCK_BYTE_LENGTH 512 + +#define DEBUG_MMCHOST_SD DEBUG_VERBOSE +#define DEBUG_MMCHOST_SD_INFO DEBUG_INFO +#define DEBUG_MMCHOST_SD_ERROR DEBUG_ERROR + +STATIC BOOLEAN mCardIsPresent = FALSE; +STATIC CARD_DETECT_STATE mCardDetectState = CardDetectRequired; +BM_SD_PARAMS BmParams; + +/** + Check if the SD card is read-only. + + @param[in] This Pointer to the EFI_MMC_HOST_PROTOCOL instance. + + @retval FALSE The SD card is not read-only. + +**/ +STATIC +BOOLEAN +SdIsReadOnly ( + IN EFI_MMC_HOST_PROTOCOL *This + ) +{ + return FALSE; +} + +/** + Build the device path for the SD card. + + @param[in] This Pointer to the EFI_MMC_HOST_PROTOCOL instance. + @param[out] DevicePath Pointer to the location to store the newly created device path. + + @retval EFI_SUCCESS The device path is built successfully. + +**/ +STATIC +EFI_STATUS +SdBuildDevicePath ( + IN EFI_MMC_HOST_PROTOCOL *This, + OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath + ) +{ + EFI_DEVICE_PATH_PROTOCOL *NewDevicePathNode; + EFI_GUID DevicePathGuid = EFI_CALLER_ID_GUID; + + DEBUG ((DEBUG_MMCHOST_SD, "SdHost: SdBuildDevicePath ()\n")); + + NewDevicePathNode = CreateDeviceNode (HARDWARE_DEVICE_PATH, HW_VENDOR_DP, sizeof (VENDOR_DEVICE_PATH)); + CopyGuid (&((VENDOR_DEVICE_PATH*)NewDevicePathNode)->Guid, &DevicePathGuid); + *DevicePath = NewDevicePathNode; + + return EFI_SUCCESS; +} + +/** + Send a command to the SD card. + + @param[in] This Pointer to the EFI_MMC_HOST_PROTOCOL instance. + @param[in] MmcCmd The MMC command to send. + @param[in] Argument The argument for the command. + @param[in] Type The type of response expected. + @param[in] Buffer Pointer to the buffer to store the response. + + @retval EFI_SUCCESS The command was sent successfully and the response was retrieved. + @retval Other An error occurred while sending a command. +**/ +STATIC +EFI_STATUS +SdSendCommand ( + IN EFI_MMC_HOST_PROTOCOL *This, + IN MMC_IDX MmcCmd, + IN UINT32 Argument, + IN MMC_RESPONSE_TYPE Type, + IN UINT32* Buffer + ) +{ + EFI_STATUS Status; + + Status = BmSdSendCmd (MmcCmd, Argument, Type, Buffer); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_MMCHOST_SD_ERROR, "SdSendCommand Error, Status=%r.\n", Status)); + return Status; + } + + return EFI_SUCCESS; +} + +/** + Read block data from an SD card. + + @param[in] This Pointer to the EFI_MMC_HOST_PROTOCOL instance. + @param[in] Lba Logical Block Address of the starting block to read. + @param[in] Length Number of blocks to read. + @param[in] Buffer Pointer to the buffer to store the read data. + + @retval EFI_SUCCESS The operation completed successfully. + @retval Other The operation failed. + +**/ +STATIC +EFI_STATUS +SdReadBlockData ( + IN EFI_MMC_HOST_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Length, + OUT UINT32* Buffer + ) +{ + EFI_STATUS Status; + + ASSERT (Buffer != NULL); + ASSERT (Length % 4 == 0); + + Status = BmSdRead (Lba, Buffer, Length); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_MMCHOST_SD_ERROR, "SdReadBlockData Error, Status=%r.\n", Status)); + return Status; + } + + return EFI_SUCCESS; +} + +/** + Write block data to an SD card. + + @param[in] This Pointer to the EFI_MMC_HOST_PROTOCOL instance. + @param[in] Lba Logical Block Address of the starting block to write. + @param[in] Length Number of blocks to write. + @param[in] Buffer Pointer to the buffer containing the data to be written. + + @retval EFI_SUCCESS The operation completed successfully. + @retval Other The operation failed. + +**/ +STATIC +EFI_STATUS +SdWriteBlockData ( + IN EFI_MMC_HOST_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Length, + IN UINT32* Buffer + ) +{ + EFI_STATUS Status; + + DEBUG ((DEBUG_MMCHOST_SD, "SdHost: SdWriteBlockData(LBA: 0x%x, Length: 0x%x, Buffer: 0x%x)\n",(UINT32)Lba, Length, Buffer)); + + ASSERT (Buffer != NULL); + ASSERT (Length % SDHOST_BLOCK_BYTE_LENGTH == 0); + + Status = BmSdWrite (Lba, Buffer, Length); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_MMCHOST_SD_ERROR, "SdWriteBlockData Error, Status=%r.\n", Status)); + return Status; + } + + return EFI_SUCCESS; +} + +/** + Set the I/O settings for an SD card. + + @param[in] This Pointer to the EFI_MMC_HOST_PROTOCOL instance. + @param[in] BusClockFreq Bus clock frequency in Hz. + @param[in] BusWidth Bus width setting. + + @retval EFI_SUCCESS The operation completed successfully. + @retval Other The operation failed. + +**/ +STATIC +EFI_STATUS +SdSetIos ( + IN EFI_MMC_HOST_PROTOCOL *This, + IN UINT32 BusClockFreq, + IN UINT32 BusWidth + ) +{ + EFI_STATUS Status; + + DEBUG ((DEBUG_MMCHOST_SD_INFO, "%a: Setting Freq %u Hz\n", __func__, BusClockFreq)); + DEBUG ((DEBUG_MMCHOST_SD_INFO, "%a: Setting BusWidth %u\n", __func__, BusWidth)); + + Status = BmSdSetIos (BusClockFreq,BusWidth); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_MMCHOST_SD_ERROR, "SdSetIos Error, Status=%r.\n", Status)); + return Status; + } + + return EFI_SUCCESS; +} + +/** + Prepare the SD card for data transfer. + + @param[in] This Pointer to the EFI_MMC_HOST_PROTOCOL instance. + @param[in] Lba Logical Block Address of the starting block to prepare. + @param[in] Length Number of blocks to prepare. + @param[in] Buffer Buffer containing the data to be prepared. + + @retval EFI_SUCCESS The operation completed successfully. + @retval Other The operation failed. + +**/ +STATIC +EFI_STATUS +SdPrepare ( + IN EFI_MMC_HOST_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Length, + IN UINTN Buffer + ) +{ + EFI_STATUS Status; + + Status = BmSdPrepare (Lba, Buffer, Length); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_MMCHOST_SD_ERROR, "SdPrepare Error, Status=%r.\n", Status)); + return Status; + } + + return EFI_SUCCESS; +} + +/** + Notify the state of the SD card. + + @param[in] This Pointer to the EFI_MMC_HOST_PROTOCOL instance. + @param[in] State State of the SD card. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_NOT_READY The card detection has not completed yet. + @retval Other The operation failed. + +**/ +STATIC +EFI_STATUS +SdNotifyState ( + IN EFI_MMC_HOST_PROTOCOL *This, + IN MMC_STATE State + ) +{ + // Stall all operations except init until card detection has occurred. + if (State != MmcHwInitializationState && mCardDetectState != CardDetectCompleted) { + return EFI_NOT_READY; + } + + switch (State) { + case MmcHwInitializationState: + DEBUG ((DEBUG_MMCHOST_SD, "MmcHwInitializationState\n", State)); + + EFI_STATUS Status = SdInit (SD_USE_PIO); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_MMCHOST_SD_ERROR,"SdHost: SdNotifyState(): Fail to initialize!\n")); + return Status; + } + break; + case MmcIdleState: + DEBUG ((DEBUG_MMCHOST_SD, "MmcIdleState\n", State)); + break; + case MmcReadyState: + DEBUG ((DEBUG_MMCHOST_SD, "MmcReadyState\n", State)); + break; + case MmcIdentificationState: + DEBUG ((DEBUG_MMCHOST_SD, "MmcIdentificationState\n", State)); + break; + case MmcStandByState: + DEBUG ((DEBUG_MMCHOST_SD, "MmcStandByState\n", State)); + break; + case MmcTransferState: + DEBUG ((DEBUG_MMCHOST_SD, "MmcTransferState\n", State)); + break; + case MmcSendingDataState: + DEBUG ((DEBUG_MMCHOST_SD, "MmcSendingDataState\n", State)); + break; + case MmcReceiveDataState: + DEBUG ((DEBUG_MMCHOST_SD, "MmcReceiveDataState\n", State)); + break; + case MmcProgrammingState: + DEBUG ((DEBUG_MMCHOST_SD, "MmcProgrammingState\n", State)); + break; + case MmcDisconnectState: + case MmcInvalidState: + default: + DEBUG ((DEBUG_MMCHOST_SD_ERROR, "SdHost: SdNotifyState(): Invalid State: %d\n", State)); + ASSERT (0); + } + + return EFI_SUCCESS; +} + +/** + Check if an SD card is present. + + @param[in] This Pointer to the EFI_MMC_HOST_PROTOCOL instance. + + @retval TRUE An SD card is present. + @retval FALSE No SD card is present. + +**/ +STATIC +BOOLEAN +SdIsCardPresent ( + IN EFI_MMC_HOST_PROTOCOL *This + ) +{ + // + // If we are already in progress (we may get concurrent calls) + // or completed the detection, just return the current value. + // + if (mCardDetectState != CardDetectRequired) { + return mCardIsPresent; + } + + mCardDetectState = CardDetectInProgress; + mCardIsPresent = FALSE; + + if (BmSdCardDetect () == 1) { + mCardIsPresent = TRUE; + goto out; + } + else { + DEBUG ((DEBUG_MMCHOST_SD_ERROR, "SdIsCardPresent: Error SdCardDetect.\n")); + mCardDetectState = CardDetectRequired; + return FALSE; + } + + DEBUG ((DEBUG_MMCHOST_SD_INFO, "SdIsCardPresent: Not detected.\n")); + +out: + mCardDetectState = CardDetectCompleted; + return mCardIsPresent; +} + +/** + Check if the SD card supports multi-block transfers. + + @param[in] This Pointer to the EFI_MMC_HOST_PROTOCOL instance. + + @retval TRUE The SD card supports multi-block transfers. + +**/ +BOOLEAN +SdIsMultiBlock ( + IN EFI_MMC_HOST_PROTOCOL *This + ) +{ + return TRUE; +} + +EFI_MMC_HOST_PROTOCOL gMmcHost = { + MMC_HOST_PROTOCOL_REVISION, + SdIsCardPresent, + SdIsReadOnly, + SdBuildDevicePath, + SdNotifyState, + SdSendCommand, + SdReadBlockData, + SdWriteBlockData, + SdSetIos, + SdPrepare, + SdIsMultiBlock +}; + +/** + Initialize the SD host. + + @param[in] ImageHandle The image handle. + @param[in] SystemTable The system table. + + @retval EFI_SUCCESS The operation completed successfully. + @retval Other The operation failed. +**/ +EFI_STATUS +SdHostInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle; + UINTN Base; + + DEBUG ((DEBUG_MMCHOST_SD, "SdHost: Initialize\n")); + + Handle = NULL; + Base = SDIO_BASE; + + if(!PcdGetBool (PcdForceNoMMU)){ + for (INT32 I = 39; I < 64; I++) { + if (Base & (1ULL << 38)) { + Base |= (1ULL << I); + } else { + Base &= ~(1ULL << I); + } + } + } + + BmParams.RegBase = Base; + BmParams.ClkRate = 50 * 1000 * 1000; + BmParams.BusWidth = MMC_BUS_WIDTH_4; + BmParams.Flags = 0; + BmParams.CardIn = SDCARD_STATUS_UNKNOWN; + + Status = gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gSophgoMmcHostProtocolGuid, + &gMmcHost, + NULL + ); + ASSERT_EFI_ERROR (Status); + return Status; +} -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#108212): https://edk2.groups.io/g/devel/message/108212 Mute This Topic: https://groups.io/mt/101084024/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=- From: caiyuqing379 <202235273@mail.sdu.edu.cn> This driver implements the MMC Host protocol, which is used by SD interface driver that the Sophgo SG2042 EVB supports. Add this driver in Sophgo/SG2042Pkg leveraging the one form Embedded Package. Signed-off-by: caiyuqing379 <202235273@mail.sdu.edu.cn> Co-authored-by: USER0FISH <libing1202@outlook.com> Cc: dahogn <dahogn@hotmail.com> Cc: meng-cz <mengcz1126@gmail.com> Cc: yli147 <yong.li@intel.com> Cc: ChaiEvan <evan.chai@intel.com> Cc: Sunil V L <sunilvl@ventanamicro.com> --- .../SG2042Pkg/Universal/Dxe/MmcDxe/MmcDxe.inf | 46 ++ Platform/Sophgo/SG2042Pkg/Include/MmcHost.h | 225 ++++++ .../SG2042Pkg/Universal/Dxe/MmcDxe/Mmc.h | 513 +++++++++++++ .../Universal/Dxe/MmcDxe/ComponentName.c | 156 ++++ .../Universal/Dxe/MmcDxe/Diagnostics.c | 323 ++++++++ .../SG2042Pkg/Universal/Dxe/MmcDxe/Mmc.c | 527 +++++++++++++ .../Universal/Dxe/MmcDxe/MmcBlockIo.c | 643 ++++++++++++++++ .../SG2042Pkg/Universal/Dxe/MmcDxe/MmcDebug.c | 194 +++++ .../Universal/Dxe/MmcDxe/MmcIdentification.c | 719 ++++++++++++++++++ 9 files changed, 3346 insertions(+) create mode 100644 Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/MmcDxe.inf create mode 100644 Platform/Sophgo/SG2042Pkg/Include/MmcHost.h create mode 100644 Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/Mmc.h create mode 100644 Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/ComponentName.c create mode 100644 Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/Diagnostics.c create mode 100644 Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/Mmc.c create mode 100644 Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/MmcBlockIo.c create mode 100644 Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/MmcDebug.c create mode 100644 Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/MmcIdentification.c diff --git a/Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/MmcDxe.inf b/Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/MmcDxe.inf new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/MmcDxe.inf @@ -XXX,XX +XXX,XX @@ +## @file +# Component description file for the MMC DXE driver module. +# +# Copyright (c) 2011-2015, ARM Limited. All rights reserved. +# Copyright (c) 2023, Academy of Intelligent Innovation, Shandong Universiy, China.P.R. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = MmcDxe + FILE_GUID = B5A53998-42AD-4C66-8D2D-1C5FBD175F25 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = MmcDxeInitialize + +[Sources.common] + ComponentName.c + Mmc.h + Mmc.c + MmcBlockIo.c + MmcIdentification.c + MmcDebug.c + Diagnostics.c + +[Packages] + MdePkg/MdePkg.dec + Platform/Sophgo/SG2042Pkg/SG2042Pkg.dec + +[LibraryClasses] + BaseLib + UefiLib + UefiDriverEntryPoint + BaseMemoryLib + +[Protocols] + gEfiDiskIoProtocolGuid ## CONSUMES + gEfiBlockIoProtocolGuid ## PRODUCES + gEfiDevicePathProtocolGuid ## PRODUCES + gEfiDriverDiagnostics2ProtocolGuid ## SOMETIMES_PRODUCES + gSophgoMmcHostProtocolGuid ## CONSUMES + +[Depex] + TRUE diff --git a/Platform/Sophgo/SG2042Pkg/Include/MmcHost.h b/Platform/Sophgo/SG2042Pkg/Include/MmcHost.h new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/Sophgo/SG2042Pkg/Include/MmcHost.h @@ -XXX,XX +XXX,XX @@ +/** @file + Definition of the MMC Host Protocol + + Copyright (c) 2011-2014, ARM Limited. All rights reserved. + Copyright (c) Academy of Intelligent Innovation. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + + **/ + +#ifndef __MMC_HOST_PROTOCOL_H__ +#define __MMC_HOST_PROTOCOL_H__ + +/* + * Global ID for the MMC Host Protocol + */ +#define MMC_HOST_PROTOCOL_GUID \ + { 0x3e591c00, 0x9e4a, 0x11df, {0x92, 0x44, 0x00, 0x02, 0xA5, 0xF5, 0xF5, 0x1B } } + +#define MMC_BLOCK_SIZE 512U +#define MMC_BLOCK_MASK (MMC_BLOCK_SIZE - 1U) +#define MMC_BOOT_CLK_RATE (400 * 1000) + +/* Values in EXT CSD register */ +#define MMC_BUS_WIDTH_1 0U +#define MMC_BUS_WIDTH_4 1U +#define MMC_BUS_WIDTH_8 2U +#define MMC_BUS_WIDTH_DDR_4 5U +#define MMC_BUS_WIDTH_DDR_8 6U + +#define MMC_RSP_48 BIT0 +#define MMC_RSP_136 BIT1 /* 136 bit response */ +#define MMC_RSP_CRC BIT2 /* expect valid crc */ +#define MMC_RSP_CMD_IDX BIT3 /* response contains cmd idx */ +#define MMC_RSP_BUSY BIT4 /* device may be busy */ + +/* JEDEC 4.51 chapter 6.12 */ +#define MMC_RESPONSE_R1 (MMC_RSP_48 | MMC_RSP_CMD_IDX | MMC_RSP_CRC) +#define MMC_RESPONSE_R1B (MMC_RESPONSE_R1 | MMC_RSP_BUSY) +#define MMC_RESPONSE_R2 (MMC_RSP_48 | MMC_RSP_136 | MMC_RSP_CRC) +#define MMC_RESPONSE_R3 (MMC_RSP_48) +#define MMC_RESPONSE_R4 (MMC_RSP_48) +#define MMC_RESPONSE_R5 (MMC_RSP_48 | MMC_RSP_CRC | MMC_RSP_CMD_IDX) +#define MMC_RESPONSE_R6 (MMC_RSP_48 | MMC_RSP_CRC | MMC_RSP_CMD_IDX) +#define MMC_RESPONSE_R7 (MMC_RSP_48 | MMC_RSP_CRC | MMC_RSP_CMD_IDX) + +typedef UINT32 MMC_RESPONSE_TYPE; + +typedef UINT32 MMC_IDX; + +#define MMC_CMD_WAIT_RESPONSE (1 << 16) +#define MMC_CMD_LONG_RESPONSE (1 << 17) +#define MMC_CMD_NO_CRC_RESPONSE (1 << 18) + +#define MMC_INDX(Index) ((Index) & 0xFFFF) +#define MMC_GET_INDX(MmcCmd) ((MmcCmd) & 0xFFFF) + +#define MMC_CMD0 (MMC_INDX(0)) +#define MMC_CMD1 (MMC_INDX(1)) +#define MMC_CMD2 (MMC_INDX(2)) +#define MMC_CMD3 (MMC_INDX(3)) +#define MMC_CMD5 (MMC_INDX(5)) +#define MMC_CMD6 (MMC_INDX(6)) +#define MMC_CMD7 (MMC_INDX(7)) +#define MMC_CMD8 (MMC_INDX(8)) +#define MMC_CMD9 (MMC_INDX(9)) +#define MMC_CMD11 (MMC_INDX(11)) +#define MMC_CMD12 (MMC_INDX(12)) +#define MMC_CMD13 (MMC_INDX(13)) +#define MMC_CMD16 (MMC_INDX(16)) +#define MMC_CMD17 (MMC_INDX(17)) +#define MMC_CMD18 (MMC_INDX(18)) +#define MMC_CMD20 (MMC_INDX(20)) +#define MMC_CMD23 (MMC_INDX(23)) +#define MMC_CMD24 (MMC_INDX(24)) +#define MMC_CMD25 (MMC_INDX(25)) +#define MMC_CMD55 (MMC_INDX(55)) +#define MMC_ACMD22 (MMC_INDX(22)) +#define MMC_ACMD41 (MMC_INDX(41)) +#define MMC_ACMD51 (MMC_INDX(51)) + +// Valid responses for CMD1 in eMMC +#define EMMC_CMD1_CAPACITY_LESS_THAN_2GB 0x00FF8080 // Capacity <= 2GB, byte addressing used +#define EMMC_CMD1_CAPACITY_GREATER_THAN_2GB 0x40FF8080 // Capacity > 2GB, 512-byte sector addressing used + +#define MMC_STATUS_APP_CMD (1 << 5) + +typedef enum _MMC_STATE { + MmcInvalidState = 0, + MmcHwInitializationState, + MmcIdleState, + MmcReadyState, + MmcIdentificationState, + MmcStandByState, + MmcTransferState, + MmcSendingDataState, + MmcReceiveDataState, + MmcProgrammingState, + MmcDisconnectState, +} MMC_STATE; + +typedef enum _CARD_DETECT_STATE { + CardDetectRequired = 0, + CardDetectInProgress, + CardDetectCompleted +} CARD_DETECT_STATE; + +#define EMMCBACKWARD (0) +#define EMMCHS26 (1 << 0) // High-Speed @26MHz at rated device voltages +#define EMMCHS52 (1 << 1) // High-Speed @52MHz at rated device voltages +#define EMMCHS52DDR1V8 (1 << 2) // High-Speed Dual Data Rate @52MHz 1.8V or 3V I/O +#define EMMCHS52DDR1V2 (1 << 3) // High-Speed Dual Data Rate @52MHz 1.2V I/O +#define EMMCHS200SDR1V8 (1 << 4) // HS200 Single Data Rate @200MHz 1.8V I/O +#define EMMCHS200SDR1V2 (1 << 5) // HS200 Single Data Rate @200MHz 1.2V I/O +#define EMMCHS400DDR1V8 (1 << 6) // HS400 Dual Data Rate @400MHz 1.8V I/O +#define EMMCHS400DDR1V2 (1 << 7) // HS400 Dual Data Rate @400MHz 1.2V I/O + +/// +/// Forward declaration for EFI_MMC_HOST_PROTOCOL +/// +typedef struct _EFI_MMC_HOST_PROTOCOL EFI_MMC_HOST_PROTOCOL; + +typedef +BOOLEAN +(EFIAPI *MMC_ISCARDPRESENT) ( + IN EFI_MMC_HOST_PROTOCOL *This + ); + +typedef +BOOLEAN +(EFIAPI *MMC_ISREADONLY) ( + IN EFI_MMC_HOST_PROTOCOL *This + ); + +typedef +EFI_STATUS +(EFIAPI *MMC_BUILDDEVICEPATH) ( + IN EFI_MMC_HOST_PROTOCOL *This, + OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath + ); + +typedef +EFI_STATUS +(EFIAPI *MMC_NOTIFYSTATE) ( + IN EFI_MMC_HOST_PROTOCOL *This, + IN MMC_STATE State + ); + +typedef +EFI_STATUS +(EFIAPI *MMC_SENDCOMMAND) ( + IN EFI_MMC_HOST_PROTOCOL *This, + IN MMC_IDX Cmd, + IN UINT32 Argument, + IN MMC_RESPONSE_TYPE Type, + IN UINT32 *Buffer + ); + +typedef +EFI_STATUS +(EFIAPI *MMC_READBLOCKDATA) ( + IN EFI_MMC_HOST_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Length, + OUT UINT32 *Buffer + ); + +typedef +EFI_STATUS +(EFIAPI *MMC_WRITEBLOCKDATA) ( + IN EFI_MMC_HOST_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Length, + IN UINT32 *Buffer + ); + +typedef +EFI_STATUS +(EFIAPI *MMC_SETIOS) ( + IN EFI_MMC_HOST_PROTOCOL *This, + IN UINT32 BusClockFreq, + IN UINT32 BusWidth + ); + +typedef +EFI_STATUS +(EFIAPI *MMC_PREPARE) ( + IN EFI_MMC_HOST_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Length, + IN UINTN Buffer + ); + +typedef +BOOLEAN +(EFIAPI *MMC_ISMULTIBLOCK) ( + IN EFI_MMC_HOST_PROTOCOL *This + ); + +struct _EFI_MMC_HOST_PROTOCOL { + UINT32 Revision; + MMC_ISCARDPRESENT IsCardPresent; + MMC_ISREADONLY IsReadOnly; + MMC_BUILDDEVICEPATH BuildDevicePath; + + MMC_NOTIFYSTATE NotifyState; + + MMC_SENDCOMMAND SendCommand; + + MMC_READBLOCKDATA ReadBlockData; + MMC_WRITEBLOCKDATA WriteBlockData; + + MMC_SETIOS SetIos; + MMC_PREPARE Prepare; + MMC_ISMULTIBLOCK IsMultiBlock; +}; + +#define MMC_HOST_PROTOCOL_REVISION 0x00010002 // 1.2 + +#define MMC_HOST_HAS_SETIOS(Host) (Host->Revision >= MMC_HOST_PROTOCOL_REVISION && \ + Host->SetIos != NULL) +#define MMC_HOST_HAS_ISMULTIBLOCK(Host) (Host->Revision >= MMC_HOST_PROTOCOL_REVISION && \ + Host->IsMultiBlock != NULL) + +#endif /* __MMC_HOST_PROTOCOL_H__ */ diff --git a/Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/Mmc.h b/Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/Mmc.h new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/Mmc.h @@ -XXX,XX +XXX,XX @@ +/** @file + Main Header file for the MMC DXE driver + + Copyright (c) 2011-2015, ARM Limited. All rights reserved. + Copyright (c) 2023, Academy of Intelligent Innovation, Shandong Universiy, China.P.R. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __MMC_H +#define __MMC_H + +#include <Uefi.h> +#include <Include/MmcHost.h> +#include <Protocol/DiskIo.h> +#include <Protocol/BlockIo.h> +#include <Protocol/DevicePath.h> +#include <Library/IoLib.h> +#include <Library/UefiLib.h> +#include <Library/DebugLib.h> +#include <Library/UefiBootServicesTableLib.h> + +#define BIT_32(nr) (1U << (nr)) +#define BIT_64(nr) (1ULL << (nr)) +#define UINT64_C(c) (c ## UL) +#define GENMASK_64(h,l) (((~UINT64_C(0)) << (l)) & (~UINT64_C(0) >> (64 - 1 - (h)))) +#define GENMASK(h,l) GENMASK_64(h,l) + +#define MMC_TRACE(txt) DEBUG((DEBUG_BLKIO, "MMC: " txt "\n")) + +#define MMC_IOBLOCKS_READ 0 +#define MMC_IOBLOCKS_WRITE 1 + +/* Value randomly chosen for eMMC RCA, it should be > 1 */ +#define MMC_FIX_RCA 6 +#define RCA_SHIFT_OFFSET 16 + +#define MMC_OCR_POWERUP BIT31 +#define MMC_OCR_ACCESS_MASK 0x3 /* bit[30-29] */ +#define MMC_OCR_ACCESS_BYTE 0x1 /* bit[29] */ +#define MMC_OCR_ACCESS_SECTOR 0x2 /* bit[30] */ +#define OCR_HCS BIT30 +#define OCR_BYTE_MODE (0U << 29) +#define OCR_SECTOR_MODE (2U << 29) +#define OCR_ACCESS_MODE_MASK (3U << 29) +#define OCR_VDD_MIN_2V7 GENMASK(23, 15) +#define OCR_VDD_MIN_2V0 GENMASK(14, 8) +#define OCR_VDD_MIN_1V7 BIT7 + +/* Value randomly chosen for eMMC RCA, it should be > 1 */ +#define MMC_FIX_RCA 6 +#define RCA_SHIFT_OFFSET 16 + +#define CMD_EXTCSD_PARTITION_CONFIG 179 +#define CMD_EXTCSD_BUS_WIDTH 183 +#define CMD_EXTCSD_HS_TIMING 185 +#define CMD_EXTCSD_PART_SWITCH_TIME 199 +#define CMD_EXTCSD_SEC_CNT 212 + +#define EXTCSD_SET_CMD (0U << 24) +#define EXTCSD_SET_BITS (1U << 24) +#define EXTCSD_CLR_BITS (2U << 24) +#define EXTCSD_WRITE_BYTES (3U << 24) +#define EXTCSD_CMD(x) (((x) & 0xff) << 16) +#define EXTCSD_VALUE(x) (((x) & 0xff) << 8) +#define EXTCSD_CMD_SET_NORMAL 1U + +#define CSD_TRAN_SPEED_UNIT_MASK GENMASK(2, 0) +#define CSD_TRAN_SPEED_MULT_MASK GENMASK(6, 3) +#define CSD_TRAN_SPEED_MULT_SHIFT 3 + +#define MMC_CSD_GET_CCC(Response) (Response[2] >> 20) +#define MMC_CSD_GET_TRANSPEED(Response) (Response[3] & 0xFF) +#define MMC_CSD_GET_READBLLEN(Response) ((Response[2] >> 16) & 0xF) +#define MMC_CSD_GET_WRITEBLLEN(Response) ((Response[0] >> 22) & 0xF) +#define MMC_CSD_GET_FILEFORMAT(Response) ((Response[0] >> 10) & 0x3) +#define MMC_CSD_GET_FILEFORMATGRP(Response) ((Response[0] >> 15) & 0x1) +#define MMC_CSD_GET_DEVICESIZE(csd) (((Response[1] >> 30) & 0x3) | ((Response[2] & 0x3FF) << 2)) +#define HC_MMC_CSD_GET_DEVICESIZE(Response) ((Response[1] >> 16) | ((Response[2] & 0x3F) << 16)); +#define MMC_CSD_GET_DEVICESIZEMULT(csd) ((Response[1] >> 15) & 0x7) + +#define MMC_R0_READY_FOR_DATA (1U << 8) +#define MMC_R0_SWITCH_ERROR (1U << 7) +#define MMC_R0_CURRENTSTATE(Response) ((Response[0] >> 9) & 0xF) +#define MMC_R0_STATE_IDLE 0 +#define MMC_R0_STATE_READY 1 +#define MMC_R0_STATE_IDENT 2 +#define MMC_R0_STATE_STDBY 3 +#define MMC_R0_STATE_TRAN 4 +#define MMC_R0_STATE_DATA 5 +#define MMC_R0_STATE_RECV 6 +#define MMC_R0_STATE_PROG 7 +#define MMC_R0_STATE_DIS 8 + +#define EMMC_CMD6_ARG_ACCESS(x) (((x) & 0x3) << 24) +#define EMMC_CMD6_ARG_INDEX(x) (((x) & 0xFF) << 16) +#define EMMC_CMD6_ARG_VALUE(x) (((x) & 0xFF) << 8) +#define EMMC_CMD6_ARG_CMD_SET(x) (((x) & 0x7) << 0) + +#define SWITCH_CMD_DATA_LENGTH 64 +#define SD_HIGH_SPEED_SUPPORTED 0x200 +#define SD_DEFAULT_SPEED 25000000 +#define SD_HIGH_SPEED 50000000 +#define SWITCH_CMD_SUCCESS_MASK 0xf +#define CMD8_CHECK_PATTERN 0xAAU +#define VHS_2_7_3_6_V BIT8 + +#define SD_SCR_BUS_WIDTH_1 BIT8 +#define SD_SCR_BUS_WIDTH_4 BIT10 + +typedef enum { + UNKNOWN_CARD, + MMC_CARD, //MMC card + MMC_CARD_HIGH, //MMC Card with High capacity + EMMC_CARD, //eMMC 4.41 card + SD_CARD, //SD 1.1 card + SD_CARD_2, //SD 2.0 or above standard card + SD_CARD_2_HIGH //SD 2.0 or above high capacity card +} CARD_TYPE; + +typedef struct { + UINT32 Reserved0: 7; // 0 + UINT32 V170_V195: 1; // 1.70V - 1.95V + UINT32 V200_V260: 7; // 2.00V - 2.60V + UINT32 V270_V360: 9; // 2.70V - 3.60V + UINT32 RESERVED_1: 5; // Reserved + UINT32 AccessMode: 2; // 00b (byte mode), 10b (sector mode) + UINT32 PowerUp: 1; // This bit is set to LOW if the card has not finished the power up routine +} OCR; + +typedef struct { + UINT8 SD_SPEC: 4; // SD Memory Card - Spec. Version [59:56] + UINT8 SCR_STRUCTURE: 4; // SCR Structure [63:60] + UINT8 SD_BUS_WIDTHS: 4; // DAT Bus widths supported [51:48] + UINT8 DATA_STAT_AFTER_ERASE: 1; // Data Status after erases [55] + UINT8 SD_SECURITY: 3; // CPRM Security Support [54:52] + UINT8 EX_SECURITY_1: 1; // Extended Security Support [43] + UINT8 SD_SPEC4: 1; // Spec. Version 4.00 or higher [42] + UINT8 RESERVED_1: 2; // Reserved [41:40] + UINT8 SD_SPEC3: 1; // Spec. Version 3.00 or higher [47] + UINT8 EX_SECURITY_2: 3; // Extended Security Support [46:44] + UINT8 CMD_SUPPORT: 4; // Command Support bits [35:32] + UINT8 RESERVED_2: 4; // Reserved [39:36] + UINT32 RESERVED_3; // Manufacturer Usage [31:0] +} SCR; + +typedef struct { + UINT32 NOT_USED; // 1 [0:0] + UINT32 CRC; // CRC7 checksum [7:1] + + UINT32 MDT; // Manufacturing date [19:8] + UINT32 RESERVED_1; // Reserved [23:20] + UINT32 PSN; // Product serial number [55:24] + UINT8 PRV; // Product revision [63:56] + UINT8 PNM[5]; // Product name [64:103] + UINT16 OID; // OEM/Application ID [119:104] + UINT8 MID; // Manufacturer ID [127:120] +} CID; + +/* + * designware can't read out response bit 0-7, it only returns + * bit 8-135, so we shift 8 bits here. + */ +typedef struct { +#ifdef FULL_CSD + UINT8 NOT_USED: 1; // Not used, always 1 [0:0] + UINT8 CRC: 7; // CRC [7:1] +#endif + UINT8 RESERVED_1: 2; // Reserved [9:8] + UINT8 FILE_FORMAT: 2; // File format [11:10] + UINT8 TMP_WRITE_PROTECT: 1; // Temporary write protection [12:12] + UINT8 PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13] + UINT8 COPY: 1; // Copy flag (OTP) [14:14] + UINT8 FILE_FORMAT_GRP: 1; // File format group [15:15] + + UINT16 RESERVED_2: 5; // Reserved [20:16] + UINT16 WRITE_BL_PARTIAL: 1; // Partial blocks for write allowed [21:21] + UINT16 WRITE_BL_LEN: 4; // Max. write data block length [25:22] + UINT16 R2W_FACTOR: 3; // Write speed factor [28:26] + UINT16 RESERVED_3: 2; // Reserved [30:29] + UINT16 WP_GRP_ENABLE: 1; // Write protect group enable [31:31] + + UINT32 WP_GRP_SIZE: 7; // Write protect group size [38:32] + UINT32 SECTOR_SIZE: 7; // Erase sector size [45:39] + UINT32 ERASE_BLK_EN: 1; // Erase single block enable [46:46] + UINT32 C_SIZE_MULT: 3; // Device size multiplier [49:47] + UINT32 VDD_W_CURR_MAX: 3; // Max. write current @ VDD max [52:50] + UINT32 VDD_W_CURR_MIN: 3; // Max. write current @ VDD min [55:53] + UINT32 VDD_R_CURR_MAX: 3; // Max. read current @ VDD max [58:56] + UINT32 VDD_R_CURR_MIN: 3; // Max. read current @ VDD min [61:59] + UINT32 C_SIZELow2: 2; // Device size [63:62] + + UINT32 C_SIZEHigh10: 10;// Device size [73:64] + UINT32 RESERVED_4: 2; // Reserved [75:74] + UINT32 DSR_IMP: 1; // DSR implemented [76:76] + UINT32 READ_BLK_MISALIGN: 1; // Read block misalignment [77:77] + UINT32 WRITE_BLK_MISALIGN: 1; // Write block misalignment [78:78] + UINT32 READ_BL_PARTIAL: 1; // Partial blocks for read allowed [79:79] + UINT32 READ_BL_LEN: 4; // Max. read data block length [83:80] + UINT32 CCC: 12;// Card command classes [95:84] + + UINT8 TRAN_SPEED ; // Max. bus clock frequency [103:96] + UINT8 NSAC ; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104] + UINT8 TAAC ; // Data read access-time 1 [119:112] + + UINT8 RESERVED_5: 2; // Reserved [121:120] + UINT8 SPEC_VERS: 4; // System specification version [125:122] + UINT8 CSD_STRUCTURE: 2; // CSD structure [127:126] +} CSD; + +typedef struct { +#ifdef FULL_CSD + UINT8 NOT_USED: 1; // Not used, always 1 [0:0] + UINT8 CRC: 7; // CRC [7:1] +#endif + UINT8 RESERVED_1: 2; // Reserved [9:8] + UINT8 FILE_FORMAT: 2; // File format [11:10] + UINT8 TMP_WRITE_PROTECT: 1; // Temporary write protection [12:12] + UINT8 PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13] + UINT8 COPY: 1; // Copy flag (OTP) [14:14] + UINT8 FILE_FORMAT_GRP: 1; // File format group [15:15] + + UINT16 RESERVED_2: 5; // Reserved [20:16] + UINT16 WRITE_BL_PARTIAL: 1; // Partial blocks for write allowed [21:21] + UINT16 WRITE_BL_LEN: 4; // Max. write data block length [25:22] + UINT16 R2W_FACTOR: 3; // Write speed factor [28:26] + UINT16 RESERVED_3: 2; // Reserved [30:29] + UINT16 WP_GRP_ENABLE: 1; // Write protect group enable [31:31] + + UINT32 WP_GRP_SIZE: 7; // Write protect group size [38:32] + UINT32 SECTOR_SIZE: 7; // Erase sector size [45:39] + UINT32 ERASE_BLK_EN: 1; // Erase single block enable [46:46] + UINT32 RESERVED_4: 1; // Reserved [47] + UINT32 C_SIZELow16: 16; // Device size [63:48] + + UINT32 C_SIZEHigh6: 6; // Device size [69:64] + UINT32 RESERVED_5: 6; // Reserved [75:70] + UINT32 DSR_IMP: 1; // DSR implemented [76:76] + UINT32 READ_BLK_MISALIGN: 1; // Read block misalignment [77:77] + UINT32 WRITE_BLK_MISALIGN: 1; // Write block misalignment [78:78] + UINT32 READ_BL_PARTIAL: 1; // Partial blocks for read allowed [79:79] + UINT32 READ_BL_LEN: 4; // Max. read data block length [83:80] + UINT32 CCC: 12;// Card command classes [95:84] + + UINT8 TRAN_SPEED: 8; // Max. bus clock frequency [103:96] + UINT8 NSAC: 8; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104] + UINT8 TAAC: 8; // Data read access-time 1 [119:112] + + UINT8 RESERVED_6: 6; // Reserved [121:120] + UINT8 CSD_STRUCTURE: 2; // CSD structure [127:126] +} ECSD; + +typedef struct { + UINT16 RCA; + CARD_TYPE CardType; + OCR OCRData; + CID CIDData; + CSD CSDData; + ECSD *ECSDData; // MMC V2 extended card specific +} CARD_INFO; + +typedef struct _MMC_HOST_INSTANCE { + UINTN Signature; + LIST_ENTRY Link; + EFI_HANDLE MmcHandle; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + + MMC_STATE State; + EFI_BLOCK_IO_PROTOCOL BlockIo; + CARD_INFO CardInfo; + EFI_MMC_HOST_PROTOCOL *MmcHost; + + BOOLEAN Initialized; +} MMC_HOST_INSTANCE; + +#define MMC_HOST_INSTANCE_SIGNATURE SIGNATURE_32('m', 'm', 'c', 'h') +#define MMC_HOST_INSTANCE_FROM_BLOCK_IO_THIS(a) CR (a, MMC_HOST_INSTANCE, BlockIo, MMC_HOST_INSTANCE_SIGNATURE) +#define MMC_HOST_INSTANCE_FROM_LINK(a) CR (a, MMC_HOST_INSTANCE, Link, MMC_HOST_INSTANCE_SIGNATURE) + + +EFI_STATUS +EFIAPI +MmcGetDriverName ( + IN EFI_COMPONENT_NAME_PROTOCOL *This, + IN CHAR8 *Language, + OUT CHAR16 **DriverName + ); + +EFI_STATUS +EFIAPI +MmcGetControllerName ( + IN EFI_COMPONENT_NAME_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_HANDLE ChildHandle OPTIONAL, + IN CHAR8 *Language, + OUT CHAR16 **ControllerName + ); + +extern EFI_COMPONENT_NAME_PROTOCOL gMmcComponentName; +extern EFI_COMPONENT_NAME2_PROTOCOL gMmcComponentName2; + +extern EFI_DRIVER_DIAGNOSTICS2_PROTOCOL gMmcDriverDiagnostics2; + +extern LIST_ENTRY mMmcHostPool; + +/** + Reset the block device. + + This function implements EFI_BLOCK_IO_PROTOCOL.Reset(). + It resets the block device hardware. + ExtendedVerification is ignored in this implementation. + + @param This Indicates a pointer to the calling context. + @param ExtendedVerification Indicates that the driver may perform a more exhaustive + verification operation of the device during reset. + + @retval EFI_SUCCESS The block device was reset. + @retval EFI_DEVICE_ERROR The block device is not functioning correctly and could not be reset. + +**/ +EFI_STATUS +EFIAPI +MmcReset ( + IN EFI_BLOCK_IO_PROTOCOL *This, + IN BOOLEAN ExtendedVerification + ); + +/** + Reads the requested number of blocks from the device. + + This function implements EFI_BLOCK_IO_PROTOCOL.ReadBlocks(). + It reads the requested number of blocks from the device. + All the blocks are read, or an error is returned. + + @param This Indicates a pointer to the calling context. + @param MediaId The media ID that the read request is for. + @param Lba The starting logical block address to read from on the device. + @param BufferSize The size of the Buffer in bytes. + This must be a multiple of the intrinsic block size of the device. + @param Buffer A pointer to the destination buffer for the data. The caller is + responsible for either having implicit or explicit ownership of the buffer. + + @retval EFI_SUCCESS The data was read correctly from the device. + @retval EFI_DEVICE_ERROR The device reported an error while attempting to perform the read operation. + @retval EFI_NO_MEDIA There is no media in the device. + @retval EFI_MEDIA_CHANGED The MediaId is not for the current media. + @retval EFI_BAD_BUFFER_SIZE The BufferSize parameter is not a multiple of the intrinsic block size of the device. + @retval EFI_INVALID_PARAMETER The read request contains LBAs that are not valid, + or the buffer is not on proper alignment. + +**/ +EFI_STATUS +EFIAPI +MmcReadBlocks ( + IN EFI_BLOCK_IO_PROTOCOL *This, + IN UINT32 MediaId, + IN EFI_LBA Lba, + IN UINTN BufferSize, + OUT VOID *Buffer + ); + +/** + Writes a specified number of blocks to the device. + + This function implements EFI_BLOCK_IO_PROTOCOL.WriteBlocks(). + It writes a specified number of blocks to the device. + All blocks are written, or an error is returned. + + @param This Indicates a pointer to the calling context. + @param MediaId The media ID that the write request is for. + @param Lba The starting logical block address to be written. + @param BufferSize The size of the Buffer in bytes. + This must be a multiple of the intrinsic block size of the device. + @param Buffer Pointer to the source buffer for the data. + + @retval EFI_SUCCESS The data were written correctly to the device. + @retval EFI_WRITE_PROTECTED The device cannot be written to. + @retval EFI_NO_MEDIA There is no media in the device. + @retval EFI_MEDIA_CHANGED The MediaId is not for the current media. + @retval EFI_DEVICE_ERROR The device reported an error while attempting to perform the write operation. + @retval EFI_BAD_BUFFER_SIZE The BufferSize parameter is not a multiple of the intrinsic + block size of the device. + @retval EFI_INVALID_PARAMETER The write request contains LBAs that are not valid, + or the buffer is not on proper alignment. + +**/ +EFI_STATUS +EFIAPI +MmcWriteBlocks ( + IN EFI_BLOCK_IO_PROTOCOL *This, + IN UINT32 MediaId, + IN EFI_LBA Lba, + IN UINTN BufferSize, + IN VOID *Buffer + ); + +/** + Flushes all modified data to a physical block device. + + @param This Indicates a pointer to the calling context. + + @retval EFI_SUCCESS All outstanding data were written correctly to the device. + @retval EFI_DEVICE_ERROR The device reported an error while attempting to write data. + @retval EFI_NO_MEDIA There is no media in the device. + +**/ +EFI_STATUS +EFIAPI +MmcFlushBlocks ( + IN EFI_BLOCK_IO_PROTOCOL *This + ); + +/** + Sets the state of the MMC host instance and invokes the + NotifyState function of the MMC host, passing the updated state. + + @param MmcHostInstance Pointer to the MMC host instance. + @param State The new state to be set for the MMC host instance. + + @retval EFI_STATUS + +**/ +EFI_STATUS +MmcNotifyState ( + IN MMC_HOST_INSTANCE *MmcHostInstance, + IN MMC_STATE State + ); + +/** + Initialize the MMC device. + + @param[in] MmcHostInstance MMC host instance + + @retval EFI_SUCCESS MMC device initialized successfully + @retval Other MMC device initialization failed + +**/ +EFI_STATUS +InitializeMmcDevice ( + IN MMC_HOST_INSTANCE *MmcHost + ); + +/** + Callback function to check MMC cards. + + @param[in] Event The event that is being triggered + @param[in] Context The context passed to the event + +**/ +VOID +EFIAPI +CheckCardsCallback ( + IN EFI_EVENT Event, + IN VOID *Context + ); + +/** + Print the Card Specific Data (CSD). + + @param[in] Csd Pointer to the CSD array + +**/ +VOID +PrintCSD ( + IN UINT32* Csd + ); + +/** + Print the Relative Card Address (RCA). + + @param[in] Rca The Relative Card Address (RCA) value + +**/ +VOID +PrintRCA ( + IN UINT32 Rca + ); + +/** + Print the Operation Condition Register (OCR). + + @param[in] Ocr The Operation Condition Register (OCR) value. + +**/ +VOID +PrintOCR ( + IN UINT32 Ocr + ); + +/** + Print the R1 response. + + @param[in] Response The R1 response value. + +**/ +VOID +PrintResponseR1 ( + IN UINT32 Response + ); + +/** + Print the Card Identification (CID) register. + + @param[in] Cid Pointer to the CID array. + +**/ +VOID +PrintCID ( + IN UINT32* Cid + ); + +#endif diff --git a/Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/ComponentName.c b/Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/ComponentName.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/ComponentName.c @@ -XXX,XX +XXX,XX @@ +/** @file + Component Name Protocol implementation for the MMC DXE driver + + Copyright (c) 2011, ARM Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "Mmc.h" + +// +// EFI Component Name Protocol +// +GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gMmcComponentName = { + MmcGetDriverName, + MmcGetControllerName, + "eng" +}; + +// +// EFI Component Name 2 Protocol +// +GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gMmcComponentName2 = { + (EFI_COMPONENT_NAME2_GET_DRIVER_NAME)MmcGetDriverName, + (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME)MmcGetControllerName, + "en" +}; + +GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE +mMmcDriverNameTable[] = { + {"eng;en", L"MMC/SD Card Interface Driver"}, + {NULL, NULL} +}; + +/** + Retrieves a Unicode string that is the user readable name of the driver. + + This function retrieves the user readable name of a driver in the form of a + Unicode string. If the driver specified by This has a user readable name in + the language specified by Language, then a pointer to the driver name is + returned in DriverName, and EFI_SUCCESS is returned. If the driver specified + by This does not support the language specified by Language, + then EFI_UNSUPPORTED is returned. + + @param This A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or + EFI_COMPONENT_NAME_PROTOCOL instance. + @param Language A pointer to a Null-terminated ASCII string + array indicating the language. This is the + language of the driver name that the caller is + requesting, and it must match one of the + languages specified in SupportedLanguages. The + number of languages supported by a driver is up + to the driver writer. Language is specified + in RFC 4646 or ISO 639-2 language code format. + @param DriverName A pointer to the Unicode string to return. + This Unicode string is the name of the + driver specified by This in the language + specified by Language. + + @retval EFI_SUCCESS The Unicode string for the Driver specified by + This and the language specified by Language was + returned in DriverName. + @retval EFI_INVALID_PARAMETER Language is NULL. + @retval EFI_INVALID_PARAMETER DriverName is NULL. + @retval EFI_UNSUPPORTED The driver specified by This does not support + the language specified by Language. + +**/ +EFI_STATUS +EFIAPI +MmcGetDriverName ( + IN EFI_COMPONENT_NAME_PROTOCOL *This, + IN CHAR8 *Language, + OUT CHAR16 **DriverName + ) +{ + return LookupUnicodeString2 ( + Language, + This->SupportedLanguages, + mMmcDriverNameTable, + DriverName, + (BOOLEAN)(This == &gMmcComponentName) + ); +} + +/** + Retrieves a Unicode string that is the user readable name of the controller + that is being managed by a driver. + + This function retrieves the user readable name of the controller specified by + ControllerHandle and ChildHandle in the form of a Unicode string. If the + driver specified by This has a user readable name in the language specified by + Language, then a pointer to the controller name is returned in ControllerName, + and EFI_SUCCESS is returned. If the driver specified by This is not currently + managing the controller specified by ControllerHandle and ChildHandle, + then EFI_UNSUPPORTED is returned. If the driver specified by This does not + support the language specified by Language, then EFI_UNSUPPORTED is returned. + + @param This A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or + EFI_COMPONENT_NAME_PROTOCOL instance. + @param ControllerHandle The handle of a controller that the driver + specified by This is managing. This handle + specifies the controller whose name is to be + returned. + @param ChildHandle The handle of the child controller to retrieve + the name of. This is an optional parameter that + may be NULL. It will be NULL for device + drivers. It will also be NULL for a bus drivers + that wish to retrieve the name of the bus + controller. It will not be NULL for a bus + driver that wishes to retrieve the name of a + child controller. + @param Language A pointer to a Null-terminated ASCII string + array indicating the language. This is the + language of the driver name that the caller is + requesting, and it must match one of the + languages specified in SupportedLanguages. The + number of languages supported by a driver is up + to the driver writer. Language is specified in + RFC 4646 or ISO 639-2 language code format. + @param ControllerName A pointer to the Unicode string to return. + This Unicode string is the name of the + controller specified by ControllerHandle and + ChildHandle in the language specified by + Language from the point of view of the driver + specified by This. + + @retval EFI_SUCCESS The Unicode string for the user readable name in + the language specified by Language for the + driver specified by This was returned in + DriverName. + @retval EFI_INVALID_PARAMETER ControllerHandle is not a valid EFI_HANDLE. + @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid + EFI_HANDLE. + @retval EFI_INVALID_PARAMETER Language is NULL. + @retval EFI_INVALID_PARAMETER ControllerName is NULL. + @retval EFI_UNSUPPORTED The driver specified by This is not currently + managing the controller specified by + ControllerHandle and ChildHandle. + @retval EFI_UNSUPPORTED The driver specified by This does not support + the language specified by Language. + +**/ +EFI_STATUS +EFIAPI +MmcGetControllerName ( + IN EFI_COMPONENT_NAME_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_HANDLE ChildHandle OPTIONAL, + IN CHAR8 *Language, + OUT CHAR16 **ControllerName + ) +{ + return EFI_UNSUPPORTED; +} diff --git a/Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/Diagnostics.c b/Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/Diagnostics.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/Diagnostics.c @@ -XXX,XX +XXX,XX @@ +/** @file + Diagnostics Protocol implementation for the MMC DXE driver + + Copyright (c) 2011-2014, ARM Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <Uefi.h> +#include <Library/DebugLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/BaseLib.h> + +#include "Mmc.h" + +#define DIAGNOSTIC_LOGBUFFER_MAXCHAR 1024 + +CHAR16* mLogBuffer = NULL; +UINTN mLogRemainChar = 0; + +/** + + Initialize the diagnostic log by allocating memory for the log + buffer and setting the maximum buffer size. + + @param MaxBufferChar The maximum number of CHAR16 characters the log buffer can hold. + + @retval A pointer to the allocated log buffer. + +**/ +CHAR16* +DiagnosticInitLog ( + UINTN MaxBufferChar + ) +{ + mLogRemainChar = MaxBufferChar; + mLogBuffer = AllocatePool ((UINTN)MaxBufferChar * sizeof (CHAR16)); + return mLogBuffer; +} + +/** + + Log a diagnostic string by copying it to the log buffer. + + @param Str A pointer to the constant CHAR16 string to be logged. + + @retval The length of the logged string. + +**/ +UINTN +DiagnosticLog ( + CONST CHAR16* Str + ) +{ + UINTN len = StrLen (Str); + if (len < mLogRemainChar) { + StrCpyS (mLogBuffer, mLogRemainChar, Str); + mLogRemainChar -= len; + mLogBuffer += len; + return len; + } else { + return 0; + } +} + +/** + + Generate a random buffer by filling it with pseudo-random data. + + @param Buffer A pointer to the buffer where the generated data will be stored. + @param BufferSize The size of the buffer in bytes. + +**/ +VOID +GenerateRandomBuffer ( + VOID* Buffer, + UINTN BufferSize + ) +{ + UINT64 i; + UINT64* Buffer64 = (UINT64*)Buffer; + + for (i = 0; i < (BufferSize >> 3); i++) { + *Buffer64 = i | (~i << 32); + Buffer64++; + } +} + +/** + + Compares two buffers by iterating through each 64-bit element in the buffers. + + @param BufferA A pointer to the first buffer to compare. + @param BufferB A pointer to the second buffer to compare. + @param BufferSize The size of the buffers in bytes. + + @retval TRUE if the buffers are equal, FALSE if a mismatch is found. + +**/ +BOOLEAN +CompareBuffer ( + VOID *BufferA, + VOID *BufferB, + UINTN BufferSize + ) +{ + UINTN i; + UINT64* BufferA64 = (UINT64*)BufferA; + UINT64* BufferB64 = (UINT64*)BufferB; + + for (i = 0; i < (BufferSize >> 3); i++) { + if (*BufferA64 != *BufferB64) { + DEBUG ((DEBUG_ERROR, "CompareBuffer: Error at %i", i)); + DEBUG ((DEBUG_ERROR, "(0x%lX) != (0x%lX)\n", *BufferA64, *BufferB64)); + return FALSE; + } + BufferA64++; + BufferB64++; + } + return TRUE; +} + +/** + Performs a read/write data test on an MMC device. + + @param MmcHostInstance A pointer to the MMC host instance. + @param Lba The logical block address to perform the test on. + @param BufferSize The size of the buffer in bytes. + + @retval EFI_SUCCESS The test completes successfully. + @retval EFI_NO_MEDIA No media (MMC device) is detected. + @retval EFI_NOT_READY The MMC device is not in the transfer state. + @retval EFI_INVALID_PARAMETER The written data does not match the read data. + +**/ +EFI_STATUS +MmcReadWriteDataTest ( + MMC_HOST_INSTANCE *MmcHostInstance, + EFI_LBA Lba, + UINTN BufferSize + ) +{ + VOID *BackBuffer; + VOID *WriteBuffer; + VOID *ReadBuffer; + EFI_STATUS Status; + + // Check if a Media is Present + if (!MmcHostInstance->BlockIo.Media->MediaPresent) { + DiagnosticLog (L"ERROR: No Media Present\n"); + return EFI_NO_MEDIA; + } + + if (MmcHostInstance->State != MmcTransferState) { + DiagnosticLog (L"ERROR: Not ready for Transfer state\n"); + return EFI_NOT_READY; + } + + BackBuffer = AllocatePool (BufferSize); + WriteBuffer = AllocatePool (BufferSize); + ReadBuffer = AllocatePool (BufferSize); + + // Read (and save) buffer at a specific location + Status = MmcReadBlocks (&(MmcHostInstance->BlockIo), + MmcHostInstance->BlockIo.Media->MediaId, Lba, BufferSize, BackBuffer); + if (Status != EFI_SUCCESS) { + DiagnosticLog (L"ERROR: Fail to Read Block (1)\n"); + return Status; + } + + // Write buffer at the same location + GenerateRandomBuffer (WriteBuffer, BufferSize); + Status = MmcWriteBlocks (&(MmcHostInstance->BlockIo), + MmcHostInstance->BlockIo.Media->MediaId, Lba, BufferSize, WriteBuffer); + if (Status != EFI_SUCCESS) { + DiagnosticLog (L"ERROR: Fail to Write Block (1)\n"); + return Status; + } + + // Read the buffer at the same location + Status = MmcReadBlocks (&(MmcHostInstance->BlockIo), + MmcHostInstance->BlockIo.Media->MediaId, Lba, BufferSize, ReadBuffer); + if (Status != EFI_SUCCESS) { + DiagnosticLog (L"ERROR: Fail to Read Block (2)\n"); + return Status; + } + + // Check that is conform + if (!CompareBuffer (ReadBuffer, WriteBuffer, BufferSize)) { + DiagnosticLog (L"ERROR: Fail to Read/Write Block (1)\n"); + return EFI_INVALID_PARAMETER; + } + + // Restore content at the original location + Status = MmcWriteBlocks (&(MmcHostInstance->BlockIo), + MmcHostInstance->BlockIo.Media->MediaId, Lba, BufferSize, BackBuffer); + if (Status != EFI_SUCCESS) { + DiagnosticLog (L"ERROR: Fail to Write Block (2)\n"); + return Status; + } + + // Read the restored content + Status = MmcReadBlocks (&(MmcHostInstance->BlockIo), + MmcHostInstance->BlockIo.Media->MediaId, Lba, BufferSize, ReadBuffer); + if (Status != EFI_SUCCESS) { + DiagnosticLog (L"ERROR: Fail to Read Block (3)\n"); + return Status; + } + + // Check the content is correct + if (!CompareBuffer (ReadBuffer, BackBuffer, BufferSize)) { + DiagnosticLog (L"ERROR: Fail to Read/Write Block (2)\n"); + return EFI_INVALID_PARAMETER; + } + + return EFI_SUCCESS; +} + +/** + Runs diagnostics tests on the MMC driver for the specified controller handle. + + @param This A pointer to the EFI_DRIVER_DIAGNOSTICS_PROTOCOL instance. + @param ControllerHandle The handle of the controller to run diagnostics on. + @param ChildHandle The handle of the child controller to run diagnostics on (optional). + @param DiagnosticType The type of diagnostics to run. + @param Language The language code (only English is supported). + @param ErrorType The type of error encountered during diagnostics (if any). + @param BufferSize The size of the diagnostic buffer. + @param Buffer The diagnostic buffer. + + @retval EFI_SUCCESS The diagnostics completed successfully. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_UNSUPPORTED The specified language or controller is not supported. +*/ +EFI_STATUS +EFIAPI +MmcDriverDiagnosticsRunDiagnostics ( + IN EFI_DRIVER_DIAGNOSTICS_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_HANDLE ChildHandle OPTIONAL, + IN EFI_DRIVER_DIAGNOSTIC_TYPE DiagnosticType, + IN CHAR8 *Language, + OUT EFI_GUID **ErrorType, + OUT UINTN *BufferSize, + OUT CHAR16 **Buffer + ) +{ + LIST_ENTRY *CurrentLink; + MMC_HOST_INSTANCE *MmcHostInstance; + EFI_STATUS Status; + + if ((Language == NULL) || + (ErrorType == NULL) || + (Buffer == NULL) || + (ControllerHandle == NULL) || + (BufferSize == NULL)) { + return EFI_INVALID_PARAMETER; + } + + // Check Language is supported (i.e. is "en-*" - only English is supported) + if (AsciiStrnCmp (Language, "en", 2) != 0) { + return EFI_UNSUPPORTED; + } + + Status = EFI_SUCCESS; + *ErrorType = NULL; + *BufferSize = DIAGNOSTIC_LOGBUFFER_MAXCHAR; + *Buffer = DiagnosticInitLog (DIAGNOSTIC_LOGBUFFER_MAXCHAR); + + DiagnosticLog (L"MMC Driver Diagnostics\n"); + + // Find the MMC Host instance on which we have been asked to run diagnostics + MmcHostInstance = NULL; + CurrentLink = mMmcHostPool.ForwardLink; + while (CurrentLink != NULL && CurrentLink != &mMmcHostPool && (Status == EFI_SUCCESS)) { + MmcHostInstance = MMC_HOST_INSTANCE_FROM_LINK (CurrentLink); + ASSERT (MmcHostInstance != NULL); + if (MmcHostInstance->MmcHandle == ControllerHandle) { + break; + } + CurrentLink = CurrentLink->ForwardLink; + } + + // If we didn't find the controller, return EFI_UNSUPPORTED + if ((MmcHostInstance == NULL) + || (MmcHostInstance->MmcHandle != ControllerHandle)) { + return EFI_UNSUPPORTED; + } + + // LBA=1 Size=BlockSize + DiagnosticLog (L"MMC Driver Diagnostics - Test: First Block\n"); + Status = MmcReadWriteDataTest (MmcHostInstance, 1, MmcHostInstance->BlockIo.Media->BlockSize); + + // LBA=2 Size=BlockSize + DiagnosticLog (L"MMC Driver Diagnostics - Test: Second Block\n"); + Status = MmcReadWriteDataTest (MmcHostInstance, 2, MmcHostInstance->BlockIo.Media->BlockSize); + + // LBA=10 Size=BlockSize + DiagnosticLog (L"MMC Driver Diagnostics - Test: Any Block\n"); + Status = MmcReadWriteDataTest (MmcHostInstance, MmcHostInstance->BlockIo.Media->LastBlock >> 1, + MmcHostInstance->BlockIo.Media->BlockSize); + + // LBA=LastBlock Size=BlockSize + DiagnosticLog (L"MMC Driver Diagnostics - Test: Last Block\n"); + Status = MmcReadWriteDataTest (MmcHostInstance, MmcHostInstance->BlockIo.Media->LastBlock, + MmcHostInstance->BlockIo.Media->BlockSize); + + // LBA=1 Size=2*BlockSize + DiagnosticLog (L"MMC Driver Diagnostics - Test: First Block / 2 BlockSSize\n"); + Status = MmcReadWriteDataTest (MmcHostInstance, 1, 2 * MmcHostInstance->BlockIo.Media->BlockSize); + + return Status; +} + +// +// EFI Driver Diagnostics 2 Protocol +// +GLOBAL_REMOVE_IF_UNREFERENCED EFI_DRIVER_DIAGNOSTICS2_PROTOCOL gMmcDriverDiagnostics2 = { + (EFI_DRIVER_DIAGNOSTICS2_RUN_DIAGNOSTICS)MmcDriverDiagnosticsRunDiagnostics, + "en" +}; diff --git a/Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/Mmc.c b/Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/Mmc.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/Mmc.c @@ -XXX,XX +XXX,XX @@ +/** @file + Main file of the MMC Dxe driver. The driver entrypoint is defined into this file. + + Copyright (c) 2011-2013, ARM Limited. All rights reserved. + Copyright (c) 2023, Academy of Intelligent Innovation, Shandong Universiy, China.P.R. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <Protocol/DevicePath.h> + +#include <Library/BaseLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/DevicePathLib.h> + +#include "Mmc.h" + +EFI_BLOCK_IO_MEDIA mMmcMediaTemplate = { + SIGNATURE_32 ('m','m','c','o'), // MediaId + TRUE, // RemovableMedia + FALSE, // MediaPresent + FALSE, // LogicalPartition + FALSE, // ReadOnly + FALSE, // WriteCaching + 512, // BlockSize + 4, // IoAlign + 0, // Pad + 0 // LastBlock +}; + +// +// This device structure is serviced as a header. +// Its next field points to the first root bridge device node. +// +LIST_ENTRY mMmcHostPool; + +/** + Event triggered by the timer to check if any cards have been removed + or if new ones have been plugged in +**/ + +EFI_EVENT gCheckCardsEvent; + +/** + Initialize the MMC Host Pool to support multiple MMC devices +**/ +VOID +InitializeMmcHostPool ( + VOID + ) +{ + InitializeListHead (&mMmcHostPool); +} + +/** + Insert a new Mmc Host controller to the pool. + + @param MmcHostInstance The MMC_HOST_INSTANCE to be inserted into the pool. + +**/ +VOID +InsertMmcHost ( + IN MMC_HOST_INSTANCE *MmcHostInstance + ) +{ + InsertTailList (&mMmcHostPool, &(MmcHostInstance->Link)); +} + +/** + Remove a new Mmc Host controller to the pool. + + @param MmcHostInstance The MMC_HOST_INSTANCE to be removed from the pool. + +**/ +VOID +RemoveMmcHost ( + IN MMC_HOST_INSTANCE *MmcHostInstance + ) +{ + RemoveEntryList (&(MmcHostInstance->Link)); +} + +/** + This function creates a new MMC host controller instance and initializes its members. + It allocates memory for the instance, sets the necessary fields, + and installs the BlockIO and DevicePath protocols. + + @param MmcHost The EFI_MMC_HOST_PROTOCOL instance representing the MMC host. + + @return A pointer to the created MMC_HOST_INSTANCE on success, or NULL on failure. +**/ +MMC_HOST_INSTANCE* +CreateMmcHostInstance ( + IN EFI_MMC_HOST_PROTOCOL* MmcHost + ) +{ + EFI_STATUS Status; + MMC_HOST_INSTANCE* MmcHostInstance; + EFI_DEVICE_PATH_PROTOCOL *NewDevicePathNode; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + + MmcHostInstance = AllocateZeroPool (sizeof (MMC_HOST_INSTANCE)); + if (MmcHostInstance == NULL) { + return NULL; + } + + MmcHostInstance->Signature = MMC_HOST_INSTANCE_SIGNATURE; + + MmcHostInstance->State = MmcHwInitializationState; + + MmcHostInstance->BlockIo.Media = AllocateCopyPool (sizeof (EFI_BLOCK_IO_MEDIA), &mMmcMediaTemplate); + if (MmcHostInstance->BlockIo.Media == NULL) { + goto FREE_INSTANCE; + } + + MmcHostInstance->BlockIo.Revision = EFI_BLOCK_IO_INTERFACE_REVISION; + MmcHostInstance->BlockIo.Reset = MmcReset; + MmcHostInstance->BlockIo.ReadBlocks = MmcReadBlocks; + MmcHostInstance->BlockIo.WriteBlocks = MmcWriteBlocks; + MmcHostInstance->BlockIo.FlushBlocks = MmcFlushBlocks; + + MmcHostInstance->MmcHost = MmcHost; + + // Create DevicePath for the new MMC Host + Status = MmcHost->BuildDevicePath (MmcHost, &NewDevicePathNode); + if (EFI_ERROR (Status)) { + goto FREE_MEDIA; + } + + DevicePath = (EFI_DEVICE_PATH_PROTOCOL*)AllocatePool (END_DEVICE_PATH_LENGTH); + if (DevicePath == NULL) { + goto FREE_MEDIA; + } + + SetDevicePathEndNode (DevicePath); + MmcHostInstance->DevicePath = AppendDevicePathNode (DevicePath, NewDevicePathNode); + + // Publish BlockIO protocol interface + Status = gBS->InstallMultipleProtocolInterfaces ( + &MmcHostInstance->MmcHandle, + &gEfiBlockIoProtocolGuid, &MmcHostInstance->BlockIo, + &gEfiDevicePathProtocolGuid, MmcHostInstance->DevicePath, + NULL + ); + if (EFI_ERROR (Status)) { + goto FREE_DEVICE_PATH; + } + + return MmcHostInstance; + +FREE_DEVICE_PATH: + FreePool (DevicePath); + +FREE_MEDIA: + FreePool (MmcHostInstance->BlockIo.Media); + +FREE_INSTANCE: + FreePool (MmcHostInstance); + + return NULL; +} + +/** + This function uninstalls the BlockIO and DevicePath protocols from the MMC host controller instance, + and frees the memory allocated for the instance and its associated resources. + + @param MmcHostInstance The MMC_HOST_INSTANCE to be destroyed. + + @retval EFI_SUCCESS The instance is successfully destroyed. + @retval Other The instance cannot be destroyed. + +**/ +EFI_STATUS +DestroyMmcHostInstance ( + IN MMC_HOST_INSTANCE* MmcHostInstance + ) +{ + EFI_STATUS Status; + + // Uninstall Protocol Interfaces + Status = gBS->UninstallMultipleProtocolInterfaces ( + MmcHostInstance->MmcHandle, + &gEfiBlockIoProtocolGuid, &(MmcHostInstance->BlockIo), + &gEfiDevicePathProtocolGuid, MmcHostInstance->DevicePath, + NULL + ); + ASSERT_EFI_ERROR (Status); + + // Free Memory allocated for the instance + if (MmcHostInstance->BlockIo.Media) { + FreePool (MmcHostInstance->BlockIo.Media); + } + if (MmcHostInstance->CardInfo.ECSDData) { + FreePages (MmcHostInstance->CardInfo.ECSDData, EFI_SIZE_TO_PAGES (sizeof (ECSD))); + } + FreePool (MmcHostInstance); + + return Status; +} + +/** + This function checks if the controller implement the Mmc Host and the Device Path Protocols. + + @param This A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance. + @param Controller The handle of the controller to check for support. + @param RemainingDevicePath A pointer to the remaining portion of the device path. + + @retval EFI_SUCCESS The controller is supported. + @retval EFI_UNSUPPORTED The controller is unsupported. +**/ +EFI_STATUS +EFIAPI +MmcDriverBindingSupported ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath + ) +{ + EFI_STATUS Status; + //EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath; + EFI_MMC_HOST_PROTOCOL *MmcHost; + EFI_DEV_PATH_PTR Node; + + // + // Check RemainingDevicePath validation + // + if (RemainingDevicePath != NULL) { + // + // Check if RemainingDevicePath is the End of Device Path Node, + // if yes, go on checking other conditions + // + if (!IsDevicePathEnd (RemainingDevicePath)) { + // + // If RemainingDevicePath isn't the End of Device Path Node, + // check its validation + // + Node.DevPath = RemainingDevicePath; + if (Node.DevPath->Type != HARDWARE_DEVICE_PATH || + Node.DevPath->SubType != HW_VENDOR_DP || + DevicePathNodeLength (Node.DevPath) != sizeof (VENDOR_DEVICE_PATH)) { + return EFI_UNSUPPORTED; + } + } + } + + // + // Check if Mmc Host protocol is installed by platform + // + Status = gBS->OpenProtocol ( + Controller, + &gSophgoMmcHostProtocolGuid, + (VOID**)&MmcHost, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + if (Status == EFI_ALREADY_STARTED) { + return EFI_SUCCESS; + } + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Close the Mmc Host used to perform the supported test + // + gBS->CloseProtocol ( + Controller, + &gSophgoMmcHostProtocolGuid, + This->DriverBindingHandle, + Controller + ); + + return EFI_SUCCESS; +} + +/** + This function opens the Mmc Host Protocol, creates an MMC_HOST_INSTANCE, and adds it to the MMC host pool. + + @param This A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance. + @param Controller The handle of the controller to start the driver on. + @param RemainingDevicePath A pointer to the remaining portion of the device path. + + @retval EFI_SUCCESS The driver is successfully started. + @retval Other The driver failed to start. + +**/ +EFI_STATUS +EFIAPI +MmcDriverBindingStart ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath + ) +{ + EFI_STATUS Status; + MMC_HOST_INSTANCE *MmcHostInstance; + EFI_MMC_HOST_PROTOCOL *MmcHost; + + // + // Check RemainingDevicePath validation + // + if (RemainingDevicePath != NULL) { + // + // Check if RemainingDevicePath is the End of Device Path Node, + // if yes, return EFI_SUCCESS + // + if (IsDevicePathEnd (RemainingDevicePath)) { + return EFI_SUCCESS; + } + } + + // + // Get the Mmc Host protocol + // + Status = gBS->OpenProtocol ( + Controller, + &gSophgoMmcHostProtocolGuid, + (VOID**)&MmcHost, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + if (EFI_ERROR (Status)) { + if (Status == EFI_ALREADY_STARTED) { + return EFI_SUCCESS; + } + return Status; + } + + MmcHostInstance = CreateMmcHostInstance (MmcHost); + + if (MmcHostInstance != NULL) { + // Add the handle to the pool + InsertMmcHost (MmcHostInstance); + + MmcHostInstance->Initialized = FALSE; + + // Detect card presence now + CheckCardsCallback (NULL, NULL); + } + + return EFI_SUCCESS; +} + +/** + This function closes the Mmc Host Protocol, removes the MMC_HOST_INSTANCE from the pool, and destroys the instance. + + @param This A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance. + @param Controller The handle of the controller to stop the driver on. + @param NumberOfChildren The number of children handles. + @param ChildHandleBuffer An array of child handles. + + @retval EFI_SUCCESS The driver is successfully stopped. + @retval Other The driver failed to stop. + +**/ +EFI_STATUS +EFIAPI +MmcDriverBindingStop ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + IN UINTN NumberOfChildren, + IN EFI_HANDLE *ChildHandleBuffer + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + LIST_ENTRY *CurrentLink; + MMC_HOST_INSTANCE *MmcHostInstance; + + MMC_TRACE ("MmcDriverBindingStop()"); + + // For each MMC instance + CurrentLink = mMmcHostPool.ForwardLink; + while (CurrentLink != NULL && CurrentLink != &mMmcHostPool && (Status == EFI_SUCCESS)) { + MmcHostInstance = MMC_HOST_INSTANCE_FROM_LINK (CurrentLink); + ASSERT (MmcHostInstance != NULL); + + // Close gSophgoMmcHostProtocolGuid + Status = gBS->CloseProtocol ( + Controller, + &gSophgoMmcHostProtocolGuid, + (VOID**)&MmcHostInstance->MmcHost, + This->DriverBindingHandle + ); + + // Remove MMC Host Instance from the pool + RemoveMmcHost (MmcHostInstance); + + // Destroy MmcHostInstance + DestroyMmcHostInstance (MmcHostInstance); + } + + return Status; +} + +/** + Callback function to check MMC cards. + + @param[in] Event The event that is being triggered + @param[in] Context The context passed to the event + +**/ +VOID +EFIAPI +CheckCardsCallback ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + LIST_ENTRY *CurrentLink; + MMC_HOST_INSTANCE *MmcHostInstance; + EFI_STATUS Status; + + CurrentLink = mMmcHostPool.ForwardLink; + while (CurrentLink != NULL && CurrentLink != &mMmcHostPool) { + MmcHostInstance = MMC_HOST_INSTANCE_FROM_LINK (CurrentLink); + ASSERT (MmcHostInstance != NULL); + + if (MmcHostInstance->MmcHost->IsCardPresent (MmcHostInstance->MmcHost) == !MmcHostInstance->Initialized) { + MmcHostInstance->State = MmcHwInitializationState; + MmcHostInstance->BlockIo.Media->MediaPresent = !MmcHostInstance->Initialized; + MmcHostInstance->Initialized = !MmcHostInstance->Initialized; + + if (MmcHostInstance->BlockIo.Media->MediaPresent) { + Status = InitializeMmcDevice (MmcHostInstance); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "CheckCardsCallback: Error InitializeMmcDevice, Status=%r.\n", Status)); + MmcHostInstance->Initialized = !MmcHostInstance->Initialized; + continue; + } + } + + Status = gBS->ReinstallProtocolInterface ( + (MmcHostInstance->MmcHandle), + &gEfiBlockIoProtocolGuid, + &(MmcHostInstance->BlockIo), + &(MmcHostInstance->BlockIo) + ); + + if (EFI_ERROR (Status)) { + Print (L"MMC Card: Error reinstalling BlockIo interface\n"); + } + } + + CurrentLink = CurrentLink->ForwardLink; + } +} + + +EFI_DRIVER_BINDING_PROTOCOL gMmcDriverBinding = { + MmcDriverBindingSupported, + MmcDriverBindingStart, + MmcDriverBindingStop, + 0xa, + NULL, + NULL +}; + +/** + This function is the entry point of the MMC DXE driver. + It initializes the MMC host pool, installs driver model protocols, + driver diagnostics, and sets up a timer for card detection. + + @param ImageHandle The image handle of the driver. + @param SystemTable A pointer to the EFI system table. + + @retval EFI_SUCCESS The driver is successfully initialized. + @retval Other The driver failed to initialize. + +**/ +EFI_STATUS +EFIAPI +MmcDxeInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + // + // Initializes MMC Host pool + // + InitializeMmcHostPool (); + + // + // Install driver model protocol(s). + // + Status = EfiLibInstallDriverBindingComponentName2 ( + ImageHandle, + SystemTable, + &gMmcDriverBinding, + ImageHandle, + &gMmcComponentName, + &gMmcComponentName2 + ); + ASSERT_EFI_ERROR (Status); + + // Install driver diagnostics + Status = gBS->InstallMultipleProtocolInterfaces ( + &ImageHandle, + &gEfiDriverDiagnostics2ProtocolGuid, + &gMmcDriverDiagnostics2, + NULL + ); + ASSERT_EFI_ERROR (Status); + + // Use a timer to detect if a card has been plugged in or removed + Status = gBS->CreateEvent ( + EVT_NOTIFY_SIGNAL | EVT_TIMER, + TPL_CALLBACK, + CheckCardsCallback, + NULL, + &gCheckCardsEvent + ); + ASSERT_EFI_ERROR (Status); + + Status = gBS->SetTimer (gCheckCardsEvent, + TimerPeriodic, + (UINT64)(10 * 1000 * 200)); // 200 ms + ASSERT_EFI_ERROR (Status); + + return Status; +} diff --git a/Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/MmcBlockIo.c b/Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/MmcBlockIo.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/MmcBlockIo.c @@ -XXX,XX +XXX,XX @@ +/** @file + Block I/O Protocol implementation for MMC/SD cards. + + Copyright (c) 2011-2015, ARM Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <Library/BaseMemoryLib.h> + +#include "Mmc.h" + +#define MMCI0_BLOCKLEN 512 +#define MMCI0_TIMEOUT 1000 +#define MAX_BUF_LEN 0x1D00000 +#define MAX_BLK_CNT 0xE800 + +/** + Check if the R1 response indicates that the card is in the "Tran" state and ready for data. + + @param[in] Response Pointer to the R1 response. + + @retval EFI_SUCCESS The card is in the "Tran" state and ready for data. + @retval EFI_NOT_READY The card is not in the expected state. +**/ +STATIC +EFI_STATUS +R1TranAndReady ( + UINT32 *Response + ) +{ + if ((*Response & MMC_R0_READY_FOR_DATA) != 0 && MMC_R0_CURRENTSTATE (Response) == MMC_R0_STATE_TRAN) { + return EFI_SUCCESS; + } + + return EFI_NOT_READY; +} + +/** + Validate the number of blocks written during a write operation. + + @param[in] MmcHostInstance Pointer to the MMC host instance. + @param[in] Count Expected number of blocks written. + @param[out] TransferredBlocks Actual number of blocks written. + + @retval EFI_SUCCESS The number of blocks written is valid. + @retval EFI_NOT_READY The card is not in the expected state. + @retval EFI_DEVICE_ERROR The number of blocks written is incorrect. + @retval Other An error occurred during the validation process. + +**/ +STATIC +EFI_STATUS +ValidateWrittenBlockCount ( + IN MMC_HOST_INSTANCE *MmcHostInstance, + IN UINTN Count, + OUT UINTN *TransferredBlocks + ) +{ + UINT32 R1; + UINT8 Data[4]; + EFI_STATUS Status; + UINT32 BlocksWritten; + EFI_MMC_HOST_PROTOCOL *MmcHost; + + if (MmcHostInstance->CardInfo.CardType == MMC_CARD || + MmcHostInstance->CardInfo.CardType == MMC_CARD_HIGH || + MmcHostInstance->CardInfo.CardType == EMMC_CARD) { + /* + * Not on MMC. + */ + *TransferredBlocks = Count; + return EFI_SUCCESS; + } + + MmcHost = MmcHostInstance->MmcHost; + + Status = MmcHost->SendCommand (MmcHost, MMC_CMD55, + MmcHostInstance->CardInfo.RCA << 16, MMC_RESPONSE_R1, &R1); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a(%u): error: %r\n", __func__, __LINE__, Status)); + return Status; + } + + Status = MmcHost->SendCommand (MmcHost, MMC_ACMD22, 0, MMC_RESPONSE_R1, &R1); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a(%u): error: %r\n", + __func__, __LINE__, Status)); + return Status; + } + + Status = R1TranAndReady (&R1); + if (EFI_ERROR (Status)) { + return Status; + } + + // Read Data + Status = MmcHost->ReadBlockData (MmcHost, 0, sizeof (Data), + (VOID*)Data); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a(%u): error: %r\n", __func__, __LINE__, Status)); + return Status; + } + + /* + * Big Endian. + */ + BlocksWritten = ((UINT32)Data[0] << 24) | + ((UINT32)Data[1] << 16) | + ((UINT32)Data[2] << 8) | + ((UINT32)Data[3] << 0); + if (BlocksWritten != Count) { + DEBUG ((DEBUG_ERROR, "%a(%u): expected %u != gotten %u\n", + __func__, __LINE__, Count, BlocksWritten)); + if (BlocksWritten == 0) { + return EFI_DEVICE_ERROR; + } + } + + *TransferredBlocks = BlocksWritten; + return EFI_SUCCESS; +} + +/** + Wait until the card is in the "Tran" state. + + @param[in] MmcHostInstance Pointer to the MMC host instance. + + @retval EFI_SUCCESS The card is in the "Tran" state. + @retval EFI_NOT_READY The card is not in the expected state or timed out. + @retval Other An error occurred during the waiting process. + +**/ +STATIC +EFI_STATUS +WaitUntilTran ( + IN MMC_HOST_INSTANCE *MmcHostInstance + ) +{ + INTN Timeout; + UINT32 Response[1]; + EFI_STATUS Status; + EFI_MMC_HOST_PROTOCOL *MmcHost; + + Timeout = MMCI0_TIMEOUT; + Status = EFI_SUCCESS; + MmcHost = MmcHostInstance->MmcHost; + + while (Timeout--) { + /* + * We expect CMD13 to timeout while card is programming, + * because the card holds DAT0 low (busy). + */ + Status = MmcHost->SendCommand (MmcHost, MMC_CMD13, + MmcHostInstance->CardInfo.RCA << 16, MMC_RESPONSE_R1, Response); + if (EFI_ERROR (Status) && Status != EFI_TIMEOUT) { + DEBUG ((DEBUG_ERROR, "%a(%u) CMD13 failed: %r\n", __func__, __LINE__, Status)); + return Status; + } + + if (Status == EFI_SUCCESS) { + Status = R1TranAndReady (Response); + if (!EFI_ERROR (Status)) { + break; + } + } + gBS->Stall(1000); + } + + if (0 == Timeout) { + DEBUG ((DEBUG_ERROR, "%a(%u) card is busy\n", __func__, __LINE__)); + return EFI_NOT_READY; + } + + return Status; +} + +/** + Sets the state of the MMC host instance and invokes the + NotifyState function of the MMC host, passing the updated state. + + @param MmcHostInstance Pointer to the MMC host instance. + @param State The new state to be set for the MMC host instance. + + @retval EFI_STATUS + +**/ +EFI_STATUS +MmcNotifyState ( + IN MMC_HOST_INSTANCE *MmcHostInstance, + IN MMC_STATE State + ) +{ + MmcHostInstance->State = State; + return MmcHostInstance->MmcHost->NotifyState (MmcHostInstance->MmcHost, State); +} + +/** + Reset the block device. + + This function implements EFI_BLOCK_IO_PROTOCOL.Reset(). + It resets the block device hardware. + ExtendedVerification is ignored in this implementation. + + @param This Indicates a pointer to the calling context. + @param ExtendedVerification Indicates that the driver may perform a more exhaustive + verification operation of the device during reset. + + @retval EFI_SUCCESS The block device was reset. + @retval EFI_DEVICE_ERROR The block device is not functioning correctly and could not be reset. + +**/ +EFI_STATUS +EFIAPI +MmcReset ( + IN EFI_BLOCK_IO_PROTOCOL *This, + IN BOOLEAN ExtendedVerification + ) +{ + MMC_HOST_INSTANCE *MmcHostInstance; + + MmcHostInstance = MMC_HOST_INSTANCE_FROM_BLOCK_IO_THIS (This); + + if (MmcHostInstance->MmcHost == NULL) { + // Nothing to do + return EFI_SUCCESS; + } + + // If a card is not present then clear all media settings + if (!MmcHostInstance->MmcHost->IsCardPresent (MmcHostInstance->MmcHost)) { + MmcHostInstance->BlockIo.Media->MediaPresent = FALSE; + MmcHostInstance->BlockIo.Media->LastBlock = 0; + MmcHostInstance->BlockIo.Media->BlockSize = 512; // Should be zero but there is a bug in DiskIo + MmcHostInstance->BlockIo.Media->ReadOnly = FALSE; + + // Indicate that the driver requires initialization + MmcHostInstance->State = MmcHwInitializationState; + + return EFI_SUCCESS; + } + + // Implement me. Either send a CMD0 (could not work for some MMC host) + // or just turn off/turn on power and restart Identification mode. + return EFI_SUCCESS; +} + +/** + Detect if an MMC card is present. + + @param[in] MmcHost Pointer to the EFI_MMC_HOST_PROTOCOL instance. + + @retval EFI_NO_MEDIA No MMC card is present. + @retval EFI_SUCCESS An MMC card is present. + +**/ +EFI_STATUS +MmcDetectCard ( + EFI_MMC_HOST_PROTOCOL *MmcHost + ) +{ + if (!MmcHost->IsCardPresent (MmcHost)) { + return EFI_NO_MEDIA; + } else { + return EFI_SUCCESS; + } +} + +/** + Stop the current transmission on the MMC bus. + + @param[in] MmcHost Pointer to the EFI_MMC_HOST_PROTOCOL instance. + + @retval EFI_SUCCESS The transmission was successfully stopped. + @retval Other An error occurred while stopping the transmission. + +**/ +EFI_STATUS +MmcStopTransmission ( + EFI_MMC_HOST_PROTOCOL *MmcHost + ) +{ + EFI_STATUS Status; + UINT32 Response[4]; + // Command 12 - Stop transmission (ends read or write) + // Normally only needed for streaming transfers or after error. + Status = MmcHost->SendCommand (MmcHost, MMC_CMD12, 0, MMC_RESPONSE_R1B, Response); + return Status; +} + +/** + Transfer a block of data to or from the MMC device. + + @param[in] This Pointer to the EFI_BLOCK_IO_PROTOCOL instance. + @param[in] Cmd Command to be sent to the MMC device. + @param[in] Transfer Transfer type (MMC_IOBLOCKS_READ or MMC_IOBLOCKS_WRITE). + @param[in] MediaId Media ID of the MMC device. + @param[in] Lba Logical Block Address. + @param[in] BufferSize Size of the data buffer. + @param[out] Buffer Pointer to the data buffer. + @param[out] TransferredSize Number of bytes transferred. + + @retval EFI_SUCCESS The data transfer was successful. + @retval EFI_NOT_READY The MMC device is not ready for the transfer. + @retval EFI_DEVICE_ERROR An error occurred during the data transfer. + @retval Other An error occurred during the data transfer. + +**/ +STATIC +EFI_STATUS +MmcTransferBlock ( + IN EFI_BLOCK_IO_PROTOCOL *This, + IN UINTN Cmd, + IN UINTN Transfer, + IN UINT32 MediaId, + IN EFI_LBA Lba, + IN UINTN BufferSize, + OUT VOID *Buffer, + OUT UINTN *TransferredSize + ) +{ + EFI_STATUS Status; + MMC_HOST_INSTANCE *MmcHostInstance; + EFI_MMC_HOST_PROTOCOL *MmcHost; + UINTN CmdArg; + + MmcHostInstance = MMC_HOST_INSTANCE_FROM_BLOCK_IO_THIS (This); + MmcHost = MmcHostInstance->MmcHost; + + //Set command argument based on the card access mode (Byte mode or Block mode) + if ((MmcHostInstance->CardInfo.OCRData.AccessMode & MMC_OCR_ACCESS_MASK) == MMC_OCR_ACCESS_SECTOR) { + CmdArg = Lba; + } else { + CmdArg = Lba * This->Media->BlockSize; + } + + Status = MmcHost->SendCommand (MmcHost, Cmd, CmdArg, MMC_RESPONSE_R1, NULL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a(MMC_CMD%d): Error %r\n", __func__, MMC_INDX (Cmd), Status)); + return Status; + } + + if (Transfer == MMC_IOBLOCKS_READ) { + Status = MmcHost->ReadBlockData (MmcHost, Lba, BufferSize, Buffer); + } else { + Status = MmcHost->WriteBlockData (MmcHost, Lba, BufferSize, Buffer); + if (!EFI_ERROR (Status)) { + Status = MmcNotifyState (MmcHostInstance, MmcProgrammingState); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a(): Error MmcProgrammingState\n", __func__)); + return Status; + } + } + } + + if (EFI_ERROR (Status) || + BufferSize > This->Media->BlockSize) { + /* + * CMD12 needs to be set for multiblock (to transition from + * RECV to PROG) or for errors. + */ + EFI_STATUS Status2 = MmcStopTransmission (MmcHost); + if (EFI_ERROR (Status2)) { + DEBUG ((DEBUG_ERROR, "MmcIoBlocks(): CMD12 error on Status %r: %r\n", + Status, Status2)); + return Status2; + } + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_BLKIO, "%a(): Error %a Block Data and Status = %r\n", + __func__, Transfer == MMC_IOBLOCKS_READ ? "Read" : "Write", Status)); + return Status; + } + + ASSERT (Cmd == MMC_CMD25 || Cmd == MMC_CMD18); + } + + // + // For reads, should be already in TRAN. For writes, wait + // until programming finishes. + // + Status = WaitUntilTran (MmcHostInstance); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "WaitUntilTran after write failed\n")); + return Status; + } + + Status = MmcNotifyState (MmcHostInstance, MmcTransferState); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "MmcIoBlocks() : Error MmcTransferState\n")); + return Status; + } + + if (Transfer != MMC_IOBLOCKS_READ) { + UINTN BlocksWritten = 0; + + Status = ValidateWrittenBlockCount (MmcHostInstance, + BufferSize / + This->Media->BlockSize, + &BlocksWritten); + *TransferredSize = BlocksWritten * This->Media->BlockSize; + } else { + *TransferredSize = BufferSize; + } + + return Status; +} + +/** + Perform read or write operations on the MMC device. + + @param[in] This Pointer to the EFI_BLOCK_IO_PROTOCOL instance. + @param[in] Transfer Transfer type (MMC_IOBLOCKS_READ or MMC_IOBLOCKS_WRITE). + @param[in] MediaId Media ID of the MMC device. + @param[in] Lba Logical Block Address. + @param[in] BufferSize Size of the data buffer. + @param[out] Buffer Pointer to the data buffer. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_MEDIA_CHANGED The MediaId is not the current media. + @retval EFI_INVALID_PARAMETER Invalid parameter passed to the function. + @retval EFI_NO_MEDIA There is no media present in the MMC device. + @retval EFI_WRITE_PROTECTED The MMC device is write-protected. + @retval EFI_BAD_BUFFER_SIZE The buffer size is not an exact multiple of the block size. + @retval Other An error occurred during the data transfer. + +**/ +EFI_STATUS +MmcIoBlocks ( + IN EFI_BLOCK_IO_PROTOCOL *This, + IN UINTN Transfer, + IN UINT32 MediaId, + IN EFI_LBA Lba, + IN UINTN BufferSize, + OUT VOID *Buffer + ) +{ + EFI_STATUS Status; + UINTN Cmd; + MMC_HOST_INSTANCE *MmcHostInstance; + EFI_MMC_HOST_PROTOCOL *MmcHost; + UINTN BytesRemainingToBeTransfered; + UINTN BlockCount; + UINTN ConsumeSize; + + BlockCount = 1; + MmcHostInstance = MMC_HOST_INSTANCE_FROM_BLOCK_IO_THIS (This); + ASSERT (MmcHostInstance != NULL); + + MmcHost = MmcHostInstance->MmcHost; + ASSERT (MmcHost); + + if (This->Media->MediaId != MediaId) { + return EFI_MEDIA_CHANGED; + } + + if ((MmcHost == NULL) || (Buffer == NULL)) { + return EFI_INVALID_PARAMETER; + } + + // Check if a Card is Present + if (!MmcHostInstance->BlockIo.Media->MediaPresent) { + return EFI_NO_MEDIA; + } + + if (MMC_HOST_HAS_ISMULTIBLOCK (MmcHost) && + MmcHost->IsMultiBlock (MmcHost)) { + BlockCount = (BufferSize + This->Media->BlockSize - 1) / This->Media->BlockSize; + } + + // All blocks must be within the device + if ((Lba + (BufferSize / This->Media->BlockSize)) > (This->Media->LastBlock + 1)) { + return EFI_INVALID_PARAMETER; + } + + if ((Transfer == MMC_IOBLOCKS_WRITE) && (This->Media->ReadOnly == TRUE)) { + return EFI_WRITE_PROTECTED; + } + + // Reading 0 Byte is valid + if (BufferSize == 0) { + return EFI_SUCCESS; + } + + // The buffer size must be an exact multiple of the block size + if ((BufferSize % This->Media->BlockSize) != 0) { + return EFI_BAD_BUFFER_SIZE; + } + + // Check the alignment + if ((This->Media->IoAlign > 2) && (((UINTN)Buffer & (This->Media->IoAlign - 1)) != 0)) { + return EFI_INVALID_PARAMETER; + } + + BytesRemainingToBeTransfered = BufferSize; + while (BytesRemainingToBeTransfered > 0) { + Status = WaitUntilTran (MmcHostInstance); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "WaitUntilTran before IO failed")); + return Status; + } + + if (Transfer == MMC_IOBLOCKS_READ) { + if (BlockCount == 1) { + // Read a single block + Cmd = MMC_CMD17; + } else { + // Read multiple blocks + Cmd = MMC_CMD18; + } + } else { + if (BlockCount == 1) { + // Write a single block + Cmd = MMC_CMD24; + } else { + // Write multiple blocks + Cmd = MMC_CMD25; + } + } + + ConsumeSize = BlockCount * This->Media->BlockSize; + if (BytesRemainingToBeTransfered < ConsumeSize) { + ConsumeSize = BytesRemainingToBeTransfered; + } + + if (ConsumeSize > MAX_BUF_LEN) { + ConsumeSize = MAX_BUF_LEN; + BlockCount = MAX_BLK_CNT; + } else { + BlockCount = ConsumeSize / This->Media->BlockSize; + } + + MmcHost->Prepare (MmcHost, Lba, ConsumeSize, (UINTN)Buffer); + + Status = MmcTransferBlock (This, Cmd, Transfer, MediaId, Lba, ConsumeSize, Buffer, &ConsumeSize); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a(): Failed to transfer block and Status:%r\n", __func__, Status)); + return Status; + } + + BytesRemainingToBeTransfered -= ConsumeSize; + if (BytesRemainingToBeTransfered > 0) { + Lba += BlockCount; + Buffer = (UINT8*)Buffer + ConsumeSize; + } + } + + return EFI_SUCCESS; +} + +/** + Reads the requested number of blocks from the device. + + This function implements EFI_BLOCK_IO_PROTOCOL.ReadBlocks(). + It reads the requested number of blocks from the device. + All the blocks are read, or an error is returned. + + @param This Indicates a pointer to the calling context. + @param MediaId The media ID that the read request is for. + @param Lba The starting logical block address to read from on the device. + @param BufferSize The size of the Buffer in bytes. + This must be a multiple of the intrinsic block size of the device. + @param Buffer A pointer to the destination buffer for the data. The caller is + responsible for either having implicit or explicit ownership of the buffer. + + @retval EFI_SUCCESS The data was read correctly from the device. + @retval EFI_DEVICE_ERROR The device reported an error while attempting to perform the read operation. + @retval EFI_NO_MEDIA There is no media in the device. + @retval EFI_MEDIA_CHANGED The MediaId is not for the current media. + @retval EFI_BAD_BUFFER_SIZE The BufferSize parameter is not a multiple of the intrinsic block size of the device. + @retval EFI_INVALID_PARAMETER The read request contains LBAs that are not valid, + or the buffer is not on proper alignment. + +**/ +EFI_STATUS +EFIAPI +MmcReadBlocks ( + IN EFI_BLOCK_IO_PROTOCOL *This, + IN UINT32 MediaId, + IN EFI_LBA Lba, + IN UINTN BufferSize, + OUT VOID *Buffer + ) +{ + return MmcIoBlocks (This, MMC_IOBLOCKS_READ, MediaId, Lba, BufferSize, Buffer); +} + +/** + Writes a specified number of blocks to the device. + + This function implements EFI_BLOCK_IO_PROTOCOL.WriteBlocks(). + It writes a specified number of blocks to the device. + All blocks are written, or an error is returned. + + @param This Indicates a pointer to the calling context. + @param MediaId The media ID that the write request is for. + @param Lba The starting logical block address to be written. + @param BufferSize The size of the Buffer in bytes. + This must be a multiple of the intrinsic block size of the device. + @param Buffer Pointer to the source buffer for the data. + + @retval EFI_SUCCESS The data were written correctly to the device. + @retval EFI_WRITE_PROTECTED The device cannot be written to. + @retval EFI_NO_MEDIA There is no media in the device. + @retval EFI_MEDIA_CHANGED The MediaId is not for the current media. + @retval EFI_DEVICE_ERROR The device reported an error while attempting to perform the write operation. + @retval EFI_BAD_BUFFER_SIZE The BufferSize parameter is not a multiple of the intrinsic + block size of the device. + @retval EFI_INVALID_PARAMETER The write request contains LBAs that are not valid, + or the buffer is not on proper alignment. + +**/ +EFI_STATUS +EFIAPI +MmcWriteBlocks ( + IN EFI_BLOCK_IO_PROTOCOL *This, + IN UINT32 MediaId, + IN EFI_LBA Lba, + IN UINTN BufferSize, + IN VOID *Buffer + ) +{ + return MmcIoBlocks (This, MMC_IOBLOCKS_WRITE, MediaId, Lba, BufferSize, Buffer); +} + +/** + Flushes all modified data to a physical block device. + + @param This Indicates a pointer to the calling context. + + @retval EFI_SUCCESS All outstanding data were written correctly to the device. + @retval EFI_DEVICE_ERROR The device reported an error while attempting to write data. + @retval EFI_NO_MEDIA There is no media in the device. + +**/ +EFI_STATUS +EFIAPI +MmcFlushBlocks ( + IN EFI_BLOCK_IO_PROTOCOL *This + ) +{ + return EFI_SUCCESS; +} diff --git a/Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/MmcDebug.c b/Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/MmcDebug.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/MmcDebug.c @@ -XXX,XX +XXX,XX @@ +/** @file + Provides debug functions for MMC/SD card operations. + + Copyright (c) 2011-2013, ARM Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "Mmc.h" + +#if !defined(MDEPKG_NDEBUG) +CONST CHAR8* mStrUnit[] = { "100kbit/s", "1Mbit/s", "10Mbit/s", "100MBit/s", + "Unknown", "Unknown", "Unknown", "Unknown" }; +CONST CHAR8* mStrValue[] = { "1.0", "1.2", "1.3", "1.5", "2.0", "2.5", + "3.0", "3.5", "4.0", "4.5", "5.0", "5.5", + "6.0", "7.0", "8.0" }; +#endif + +/** + Print the Card Identification (CID) register. + + @param[in] Cid Pointer to the CID array. + +**/ +VOID +PrintCID ( + IN UINT32* Cid + ) +{ + DEBUG ((DEBUG_ERROR, "- PrintCID\n")); + DEBUG ((DEBUG_ERROR, "\t- Manufacturing date: %d/%d\n", (Cid[0] >> 8) & 0xF, (Cid[0] >> 12) & 0xFF)); + DEBUG ((DEBUG_ERROR, "\t- Product serial number: 0x%X%X\n", Cid[1] & 0xFFFFFF, (Cid[0] >> 24) & 0xFF)); + DEBUG ((DEBUG_ERROR, "\t- Product revision: %d\n", Cid[1] >> 24)); + //DEBUG ((DEBUG_ERROR, "\t- Product name: %s\n", (char*)(Cid + 2))); + DEBUG ((DEBUG_ERROR, "\t- OEM ID: %c%c\n", (Cid[3] >> 8) & 0xFF, (Cid[3] >> 16) & 0xFF)); +} + +/** + Print the Card Specific Data (CSD). + + @param[in] Csd Pointer to the CSD array + +**/ +VOID +PrintCSD ( + IN UINT32* Csd + ) +{ + UINTN Value; + + if (((Csd[2] >> 30) & 0x3) == 0) { + DEBUG ((DEBUG_ERROR, "- PrintCSD Version 1.01-1.10/Version 2.00/Standard Capacity\n")); + } else if (((Csd[2] >> 30) & 0x3) == 1) { + DEBUG ((DEBUG_ERROR, "- PrintCSD Version 2.00/High Capacity\n")); + } else { + DEBUG ((DEBUG_ERROR, "- PrintCSD Version Higher than v3.3\n")); + } + + DEBUG ((DEBUG_ERROR, "\t- Supported card command class: 0x%X\n", MMC_CSD_GET_CCC (Csd))); + DEBUG ((DEBUG_ERROR, "\t- Max Speed: %a * %a\n", mStrValue[(MMC_CSD_GET_TRANSPEED (Csd) >> 3) & 0xF], + mStrUnit[MMC_CSD_GET_TRANSPEED (Csd) & 7])); + DEBUG ((DEBUG_ERROR, "\t- Maximum Read Data Block: %d\n", 2 << (MMC_CSD_GET_READBLLEN (Csd) - 1))); + DEBUG ((DEBUG_ERROR, "\t- Maximum Write Data Block: %d\n", 2 << (MMC_CSD_GET_WRITEBLLEN (Csd) - 1))); + + if (!MMC_CSD_GET_FILEFORMATGRP (Csd)) { + Value = MMC_CSD_GET_FILEFORMAT (Csd); + if (Value == 0) { + DEBUG ((DEBUG_ERROR, "\t- Format (0): Hard disk-like file system with partition table\n")); + } else if (Value == 1) { + DEBUG ((DEBUG_ERROR, "\t- Format (1): DOS FAT (floppy-like) with boot sector only (no partition table)\n")); + } else if (Value == 2) { + DEBUG ((DEBUG_ERROR, "\t- Format (2): Universal File Format\n")); + } else { + DEBUG ((DEBUG_ERROR, "\t- Format (3): Others/Unknown\n")); + } + } else { + DEBUG ((DEBUG_ERROR, "\t- Format: Reserved\n")); + } +} + +/** + Print the Relative Card Address (RCA). + + @param[in] Rca The Relative Card Address (RCA) value + +**/ +VOID +PrintRCA ( + IN UINT32 Rca + ) +{ + DEBUG ((DEBUG_ERROR, "- PrintRCA: 0x%X\n", Rca)); + DEBUG ((DEBUG_ERROR, "\t- Status: 0x%X\n", Rca & 0xFFFF)); + DEBUG ((DEBUG_ERROR, "\t- RCA: 0x%X\n", (Rca >> 16) & 0xFFFF)); +} + +/** + Print the Operation Condition Register (OCR). + + @param[in] Ocr The Operation Condition Register (OCR) value + +**/ +VOID +PrintOCR ( + IN UINT32 Ocr + ) +{ + UINTN MinV; + UINTN MaxV; + UINTN Volts; + UINTN Loop; + + MinV = 36; // 3.6 + MaxV = 20; // 2.0 + Volts = 20; // 2.0 + + // The MMC register bits [23:8] indicate the working range of the card + for (Loop = 8; Loop < 24; Loop++) { + if (Ocr & (1 << Loop)) { + if (MinV > Volts) { + MinV = Volts; + } + if (MaxV < Volts) { + MaxV = Volts + 1; + } + } + Volts++; + } + + DEBUG ((DEBUG_ERROR, "- PrintOCR Ocr (0x%X)\n", Ocr)); + DEBUG ((DEBUG_ERROR, "\t- Card operating voltage: %d.%d to %d.%d\n", MinV / 10, MinV % 10, MaxV / 10, MaxV % 10)); + if (((Ocr >> 29) & 3) == 0) { + DEBUG ((DEBUG_ERROR, "\t- AccessMode: Byte Mode\n")); + } else { + DEBUG ((DEBUG_ERROR, "\t- AccessMode: Block Mode (0x%X)\n", ((Ocr >> 29) & 3))); + } + + if (Ocr & MMC_OCR_POWERUP) { + DEBUG ((DEBUG_ERROR, "\t- PowerUp\n")); + } else { + DEBUG ((DEBUG_ERROR, "\t- Voltage Not Supported\n")); + } +} + +/** + Print the R1 response. + + @param[in] Response The R1 response value. + +**/ +VOID +PrintResponseR1 ( + IN UINT32 Response + ) +{ + DEBUG ((DEBUG_INFO, "Response: 0x%X\n", Response)); + if (Response & MMC_R0_READY_FOR_DATA) { + DEBUG ((DEBUG_INFO, "\t- READY_FOR_DATA\n")); + } + + switch ((Response >> 9) & 0xF) { + case 0: + DEBUG ((DEBUG_INFO, "\t- State: Idle\n")); + break; + case 1: + DEBUG ((DEBUG_INFO, "\t- State: Ready\n")); + break; + case 2: + DEBUG ((DEBUG_INFO, "\t- State: Ident\n")); + break; + case 3: + DEBUG ((DEBUG_INFO, "\t- State: StandBy\n")); + break; + case 4: + DEBUG ((DEBUG_INFO, "\t- State: Tran\n")); + break; + case 5: + DEBUG ((DEBUG_INFO, "\t- State: Data\n")); + break; + case 6: + DEBUG ((DEBUG_INFO, "\t- State: Rcv\n")); + break; + case 7: + DEBUG ((DEBUG_INFO, "\t- State: Prg\n")); + break; + case 8: + DEBUG ((DEBUG_INFO, "\t- State: Dis\n")); + break; + default: + DEBUG ((DEBUG_INFO, "\t- State: Reserved\n")); + break; + } +} diff --git a/Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/MmcIdentification.c b/Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/MmcIdentification.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/MmcIdentification.c @@ -XXX,XX +XXX,XX @@ +/** @file + Define a simple and generic interface to access SD-card devices. + + Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved. + Copyright (c) 2023, Academy of Intelligent Innovation, Shandong Universiy, China.P.R. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-3-Clause + +**/ + +#include <Uefi.h> +#include <Include/MmcHost.h> +#include <Library/UefiLib.h> +#include <Library/DebugLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/IoLib.h> +#include <Library/BaseMemoryLib.h> + +#include "Mmc.h" + +#define MMC_DEFAULT_MAX_RETRIES 5 +#define SEND_OP_COND_MAX_RETRIES 100 + +#define MULT_BY_512K_SHIFT 19 + +STATIC UINT32 MmcOCR; +STATIC CSD MmcCsd; +STATIC UINT8 MmcExtCsd[512] __attribute__ ((aligned(16))); +STATIC UINT32 MmcRCA; +STATIC UINT32 MmcSCR[2] __attribute__ ((aligned(16))) = { 0 }; + +typedef enum _MMC_DEVICE_TYPE { + MMC_IS_EMMC, + MMC_IS_SD, + MMC_IS_SD_HC, +} MMC_DEVICE_TYPE; + +typedef struct { + UINT64 DeviceSize; /* Size of device in bytes */ + UINT32 BlockSize; /* Block size in bytes */ + UINT32 MaxBusFreq; /* Max bus freq in Hz */ + UINT32 OCRVoltage; /* OCR voltage */ + MMC_DEVICE_TYPE MmcDevType; /* Type of MMC */ +} MMC_DEVICE_INFO; + +STATIC MMC_DEVICE_INFO MmcDevInfo = { + .MmcDevType = MMC_IS_SD_HC, + .OCRVoltage = 0x00300000, // OCR 3.2~3.3 3.3~3.4 +}; + +STATIC CONST UINT8 TranSpeedBase[16] = { + 0, 10, 12, 13, 15, 20, 26, 30, 35, 40, 45, 52, 55, 60, 70, 80 +}; + +STATIC CONST UINT8 SdTranSpeedBase[16] = { + 0, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80 +}; + +/** + Get the current state of the MMC device. + + @param[in] MmcHostInstance Pointer to the MMC_HOST_INSTANCE structure. + @param[out] State Pointer to the variable to store the device state. + + @retval EFI_SUCCESS The device state was retrieved successfully. + @retval EFI_DEVICE_ERROR Failed to retrieve the device state. + +**/ +STATIC +EFI_STATUS +MmcDeviceState ( + IN MMC_HOST_INSTANCE *MmcHostInstance, + IN UINT32 *State + ) +{ + EFI_STATUS Status; + INT32 RetryCount; + UINT32 Response[4]; + + RetryCount = MMC_DEFAULT_MAX_RETRIES; + + do { + if (RetryCount == 0) { + DEBUG ((DEBUG_ERROR, "%a: CMD13 failed after %d retries\n", __func__, MMC_DEFAULT_MAX_RETRIES)); + return EFI_DEVICE_ERROR; + } + + Status = MmcHostInstance->MmcHost->SendCommand (MmcHostInstance->MmcHost, MMC_CMD13, MmcRCA << RCA_SHIFT_OFFSET, + MMC_RESPONSE_R1, Response); + if (EFI_ERROR (Status)) { + RetryCount--; + continue; + } + + if ((Response[0] & MMC_R0_SWITCH_ERROR) != 0U) { + return EFI_DEVICE_ERROR; + } + + RetryCount--; + } while ((Response[0] & MMC_R0_READY_FOR_DATA) == 0U); + + // DEBUG ((DEBUG_INFO, "%a: sd state %x\n", __func__, MMC_R0_CURRENTSTATE(Response))); + *State = MMC_R0_CURRENTSTATE (Response); + + return EFI_SUCCESS; +} + +/** + Set the value of the specified MMC extended CSD register. + + @param[in] MmcHostInstance Pointer to the MMC_HOST_INSTANCE structure. + @param[in] ExtCmd The extended CSD command. + @param[in] Value The value to set. + + @retval EFI_SUCCESS The value was successfully set. + @retval Other An error occurred while setting the value. + +**/ +STATIC +EFI_STATUS +MmcSetExtCsd ( + IN MMC_HOST_INSTANCE *MmcHostInstance, + IN UINT32 ExtCmd, + IN UINT32 Value + ) +{ + EFI_STATUS Status; + UINT32 State; + + Status = MmcHostInstance->MmcHost->SendCommand (MmcHostInstance->MmcHost, MMC_CMD6, + EXTCSD_WRITE_BYTES | EXTCSD_CMD(ExtCmd) | + EXTCSD_VALUE(Value) | EXTCSD_CMD_SET_NORMAL, + MMC_RESPONSE_R1B, NULL); + if (EFI_ERROR (Status)) { + return Status; + } + + do { + Status = MmcDeviceState (MmcHostInstance, &State); + if (EFI_ERROR (Status)) { + return Status; + } + } while (State == MMC_R0_STATE_PROG); + + return EFI_SUCCESS; +} + +/** + Perform an SD switch to set the bus width for the MMC/SD device. + + @param[in] MmcHostInstance Pointer to the MMC_HOST_INSTANCE structure. + @param[in] BusWidth The desired bus width. + + @retval EFI_SUCCESS The bus width was successfully set. + @retval Other An error occurred while setting the bus width. + +**/ +STATIC +EFI_STATUS +MmcSdSwitch ( + IN MMC_HOST_INSTANCE *MmcHostInstance, + IN UINT32 BusWidth + ) +{ + EFI_STATUS Status; + UINT32 State; + INT32 RetryCount; + UINT32 BusWidthArg; + + RetryCount = MMC_DEFAULT_MAX_RETRIES; + BusWidthArg = 0; + + Status = MmcHostInstance->MmcHost->Prepare (MmcHostInstance->MmcHost, 0, sizeof(MmcSCR), (UINTN)&MmcSCR); + if (EFI_ERROR (Status)) { + return Status; + } + + // CMD55: Application Specific Command + Status = MmcHostInstance->MmcHost->SendCommand (MmcHostInstance->MmcHost, MMC_CMD55, MmcRCA << RCA_SHIFT_OFFSET, + MMC_RESPONSE_R5, NULL); + if (EFI_ERROR (Status)) { + return Status; + } + + // ACMD51: SEND_SCR + do { + Status = MmcHostInstance->MmcHost->SendCommand (MmcHostInstance->MmcHost, MMC_ACMD51, 0, MMC_RESPONSE_R1, NULL); + if ((EFI_ERROR (Status)) && (RetryCount == 0)) { + DEBUG ((DEBUG_ERROR, "%a: ACMD51 failed after %d retries (Status=%r)\n", __func__, MMC_DEFAULT_MAX_RETRIES, Status)); + return Status; + } + + RetryCount--; + } while (EFI_ERROR (Status)); + + Status = MmcHostInstance->MmcHost->ReadBlockData (MmcHostInstance->MmcHost, 0, sizeof(MmcSCR), MmcSCR); + if (EFI_ERROR (Status)) { + return Status; + } + + if (((MmcSCR[0] & SD_SCR_BUS_WIDTH_4) != 0U) && (BusWidth == MMC_BUS_WIDTH_4)) { + BusWidthArg = 2; + } + + // CMD55: Application Specific Command + Status = MmcHostInstance->MmcHost->SendCommand (MmcHostInstance->MmcHost, MMC_CMD55, MmcRCA << RCA_SHIFT_OFFSET, + MMC_RESPONSE_R5, NULL); + if (EFI_ERROR (Status)) { + return Status; + } + + // ACMD6: SET_BUS_WIDTH + Status = MmcHostInstance->MmcHost->SendCommand (MmcHostInstance->MmcHost, MMC_CMD6, BusWidthArg, MMC_RESPONSE_R1, NULL); + if (EFI_ERROR (Status)) { + return Status; + } + + do { + Status = MmcDeviceState (MmcHostInstance, &State); + if (EFI_ERROR (Status)) { + return Status; + } + } while (State == MMC_R0_STATE_PROG); + + return EFI_SUCCESS; +} + +/** + Set the I/O settings for the MMC/SD device. + + @param[in] MmcHostInstance Pointer to the MMC_HOST_INSTANCE structure. + @param[in] Clk The desired clock frequency. + @param[in] BusWidth The desired bus width. + + @retval EFI_SUCCESS The I/O settings were successfully set. + @retval Other An error occurred while setting the I/O settings. + +**/ +STATIC +EFI_STATUS +MmcSetIos ( + IN MMC_HOST_INSTANCE *MmcHostInstance, + IN UINT32 Clk, + IN UINT32 BusWidth + ) +{ + EFI_STATUS Status; + UINT32 Width; + + Width = BusWidth; + + if (MmcDevInfo.MmcDevType != MMC_IS_EMMC) { + if (Width == MMC_BUS_WIDTH_8) { + DEBUG ((DEBUG_INFO, "%a: Wrong bus config for SD-card, force to 4\n", __func__)); + Width = MMC_BUS_WIDTH_4; + } + + Status = MmcSdSwitch (MmcHostInstance, Width); + if (EFI_ERROR (Status)) { + return Status; + } + } else if (MmcCsd.SPEC_VERS == 4U) { + Status = MmcSetExtCsd (MmcHostInstance, CMD_EXTCSD_BUS_WIDTH, (UINT32)Width); + if (EFI_ERROR (Status)) { + return Status; + } + } else { + DEBUG ((DEBUG_INFO, "%a: Wrong MMC type or spec version\n", __func__)); + } + + return MmcHostInstance->MmcHost->SetIos (MmcHostInstance->MmcHost, Clk, Width); +} + +/** + Fill the MMC device information. + + @param[in] MmcHostInstance Pointer to the MMC_HOST_INSTANCE structure. + + @retval EFI_SUCCESS The MMC device information was successfully filled. + @retval EFI_DEVICE_ERROR Failed to fill the MMC device information. + @retval Other An error occurred while filling the MMC device information. + +**/ +STATIC +EFI_STATUS +MmcFillDeviceInfo ( + IN MMC_HOST_INSTANCE *MmcHostInstance + ) +{ + EFI_STATUS Status; + UINTN CardSize; + UINT32 SpeedIdx; + UINT32 NumBlocks; + UINT32 FreqUnit; + UINT32 State; + ECSD *CsdSdV2; + + Status = EFI_SUCCESS; + + switch (MmcDevInfo.MmcDevType) { + case MMC_IS_EMMC: + MmcDevInfo.BlockSize = MMC_BLOCK_SIZE; + + Status = MmcHostInstance->MmcHost->Prepare (MmcHostInstance->MmcHost, 0, sizeof(MmcExtCsd), (UINTN)&MmcExtCsd); + + if (EFI_ERROR (Status)) { + return Status; + } + + /* MMC CMD8: SEND_EXT_CSD */ + Status = MmcHostInstance->MmcHost->SendCommand (MmcHostInstance->MmcHost, MMC_CMD8, 0, MMC_RESPONSE_R1, NULL); + if (EFI_ERROR (Status)) { + return Status; + } + + Status = MmcHostInstance->MmcHost->ReadBlockData (MmcHostInstance->MmcHost, 0, sizeof(MmcExtCsd), (UINT32*)MmcExtCsd); + if (EFI_ERROR (Status)) { + return Status; + } + + do { + Status = MmcDeviceState (MmcHostInstance, &State); + if (EFI_ERROR (Status)) { + return Status; + } + } while (State != MMC_R0_STATE_TRAN); + + NumBlocks = (MmcExtCsd[CMD_EXTCSD_SEC_CNT] << 0) | + (MmcExtCsd[CMD_EXTCSD_SEC_CNT + 1] << 8) | + (MmcExtCsd[CMD_EXTCSD_SEC_CNT + 2] << 16) | + (MmcExtCsd[CMD_EXTCSD_SEC_CNT + 3] << 24); + + MmcDevInfo.DeviceSize = (UINT64)NumBlocks * MmcDevInfo.BlockSize; + + break; + + case MMC_IS_SD: + /* + * Use the same MmcCsd struct, as required fields here + * (READ_BL_LEN, C_SIZE, CSIZE_MULT) are common with eMMC. + */ + MmcDevInfo.BlockSize = BIT_32(MmcCsd.READ_BL_LEN); + + CardSize = ((UINT64)MmcCsd.C_SIZEHigh10 << 2U) | + (UINT64)MmcCsd.C_SIZELow2; + ASSERT(CardSize != 0xFFFU); + + MmcDevInfo.DeviceSize = (CardSize + 1U) * + BIT_64(MmcCsd.C_SIZE_MULT + 2U) * + MmcDevInfo.BlockSize; + + break; + + case MMC_IS_SD_HC: + MmcHostInstance->CardInfo.CardType = SD_CARD_2_HIGH; + + ASSERT (MmcCsd.CSD_STRUCTURE == 1U); + + MmcDevInfo.BlockSize = MMC_BLOCK_SIZE; + + /* Need to use ECSD struct */ + CsdSdV2 = (ECSD *)&MmcCsd; + CardSize = ((UINT64)CsdSdV2->C_SIZEHigh6 << 16) | + (UINT64)CsdSdV2->C_SIZELow16; + + MmcDevInfo.DeviceSize = (CardSize + 1U) << MULT_BY_512K_SHIFT; + break; + + default: + Status = EFI_DEVICE_ERROR; + break; + } + + if (EFI_ERROR (Status)) { + return Status; + } + + SpeedIdx = (MmcCsd.TRAN_SPEED & CSD_TRAN_SPEED_MULT_MASK) >> + CSD_TRAN_SPEED_MULT_SHIFT; + + ASSERT (SpeedIdx > 0U); + + if (MmcDevInfo.MmcDevType == MMC_IS_EMMC) { + MmcDevInfo.MaxBusFreq = TranSpeedBase[SpeedIdx]; + } else { + MmcDevInfo.MaxBusFreq = SdTranSpeedBase[SpeedIdx]; + } + + FreqUnit = MmcCsd.TRAN_SPEED & CSD_TRAN_SPEED_UNIT_MASK; + while (FreqUnit != 0U) { + MmcDevInfo.MaxBusFreq *= 10U; + --FreqUnit; + } + + MmcDevInfo.MaxBusFreq *= 10000U; + + return EFI_SUCCESS; +} + +/** + Send the SD_SEND_OP_COND command to initialize the SD card. + + @param[in] MmcHostInstance Pointer to the MMC_HOST_INSTANCE structure. + + @retval EFI_SUCCESS The SD_SEND_OP_COND command was successfully sent. + @retval EFI_DEVICE_ERROR Failed to send the SD_SEND_OP_COND command. + @retval Other An error occurred while sending the SD_SEND_OP_COND command. + +**/ +STATIC +EFI_STATUS +SdSendOpCond ( + IN MMC_HOST_INSTANCE *MmcHostInstance + ) +{ + EFI_STATUS Status; + INT32 I; + UINT32 Response[4]; + + for (I = 0; I < SEND_OP_COND_MAX_RETRIES; I++) { + // CMD55: Application Specific Command + Status = MmcHostInstance->MmcHost->SendCommand (MmcHostInstance->MmcHost, MMC_CMD55, 0, MMC_RESPONSE_R1, NULL); + if (EFI_ERROR (Status)) { + return Status; + } + + // ACMD41: SD_SEND_OP_COND + Status = MmcHostInstance->MmcHost->SendCommand (MmcHostInstance->MmcHost, MMC_ACMD41, OCR_HCS | + MmcDevInfo.OCRVoltage, MMC_RESPONSE_R3, Response); + if (EFI_ERROR (Status)) { + return Status; + } + + if ((Response[0] & MMC_OCR_POWERUP) != 0U) { + MmcOCR = Response[0]; + + if ((MmcOCR & OCR_HCS) != 0U) { + MmcDevInfo.MmcDevType = MMC_IS_SD_HC; + MmcHostInstance->CardInfo.OCRData.AccessMode = 0x2; + } else { + MmcDevInfo.MmcDevType = MMC_IS_SD; + MmcHostInstance->CardInfo.OCRData.AccessMode = 0x0; + } + + return EFI_SUCCESS; + } + + gBS->Stall (10000); + } + + DEBUG ((DEBUG_ERROR, "%a: ACMD41 failed after %d retries\n", __func__, SEND_OP_COND_MAX_RETRIES)); + + return EFI_DEVICE_ERROR; +} + +/** + Reset the MMC/SD card to the idle state. + + @param[in] MmcHostInstance Pointer to the MMC_HOST_INSTANCE structure. + + @retval EFI_SUCCESS The MMC/SD card was successfully reset to the idle state. + @retval Other An error occurred while resetting the MMC/SD card to the idle state. + +**/ +STATIC +EFI_STATUS +MmcResetToIdle( + IN MMC_HOST_INSTANCE *MmcHostInstance + ) +{ + EFI_STATUS Status; + + /* CMD0: reset to IDLE */ + Status = MmcHostInstance->MmcHost->SendCommand (MmcHostInstance->MmcHost, MMC_CMD0, 0, 0, NULL); + if (EFI_ERROR (Status)) { + return Status; + } + + gBS->Stall (2000); + + return EFI_SUCCESS; +} + +/** + Send the Operation Condition (CMD1) to the MMC/SD card. + + @param[in] MmcHostInstance Pointer to the MMC_HOST_INSTANCE structure. + + @retval EFI_SUCCESS The Operation Condition was successfully sent to the MMC/SD card. + @retval EFI_DEVICE_ERROR Failed to send the Operation Condition to the MMC/SD card. + @retval Other An error occurred while sending the Operation Condition to the MMC/SD card. + +**/ +STATIC +EFI_STATUS +MmcSendOpCond ( + IN MMC_HOST_INSTANCE *MmcHostInstance + ) +{ + INT32 I; + EFI_STATUS Status; + UINT32 Response[4]; + + Status = MmcResetToIdle (MmcHostInstance); + if (EFI_ERROR (Status)) { + return Status; + } + + for (I = 0; I < SEND_OP_COND_MAX_RETRIES; I++) { + Status = MmcHostInstance->MmcHost->SendCommand (MmcHostInstance->MmcHost, MMC_CMD1, OCR_SECTOR_MODE | + OCR_VDD_MIN_2V7 | OCR_VDD_MIN_1V7, + MMC_RESPONSE_R3, Response); + if (EFI_ERROR (Status)) { + return Status; + } + + if ((Response[0] & MMC_OCR_POWERUP) != 0U) { + MmcOCR = Response[0]; + return EFI_SUCCESS; + } + + gBS->Stall (10000); + } + + DEBUG ((DEBUG_ERROR, "%a: CMD1 failed after %d retries\n", __func__, SEND_OP_COND_MAX_RETRIES)); + + return EFI_DEVICE_ERROR; +} + +/** + Enumerate and initialize the MMC/SD card. + + @param[in] MmcHostInstance Pointer to the MMC_HOST_INSTANCE structure. + @param[in] Clk Clock frequency for the MMC/SD card. + @param[in] BusWidth Bus width for the MMC/SD card. + + @retval EFI_SUCCESS The MMC/SD card was successfully enumerated and initialized. + @retval Other An error occurred while enumerating and initializing the MMC/SD card. + +**/ +STATIC +EFI_STATUS +MmcEnumerte ( + IN MMC_HOST_INSTANCE *MmcHostInstance, + IN UINT32 Clk, + IN UINT32 BusWidth + ) +{ + EFI_STATUS Status; + UINT32 State; + UINT32 Response[4]; + + Status = MmcResetToIdle (MmcHostInstance); + if (EFI_ERROR (Status)) { + return Status; + } + + if (MmcDevInfo.MmcDevType == MMC_IS_EMMC) { + Status = MmcSendOpCond (MmcHostInstance); + } else { + // CMD8: Send Interface Condition Command + Status = MmcHostInstance->MmcHost->SendCommand (MmcHostInstance->MmcHost, MMC_CMD8, VHS_2_7_3_6_V | CMD8_CHECK_PATTERN, + MMC_RESPONSE_R5, Response); + + if ((Status == EFI_SUCCESS) && ((Response[0] & 0xffU) == CMD8_CHECK_PATTERN)) { + Status = SdSendOpCond (MmcHostInstance); + } + } + if (EFI_ERROR (Status)) { + return Status; + } + + // CMD2: Card Identification + Status = MmcHostInstance->MmcHost->SendCommand (MmcHostInstance->MmcHost, MMC_CMD2, 0, MMC_RESPONSE_R2, NULL); + if (EFI_ERROR (Status)) { + return Status; + } + + // CMD3: Set Relative Address + if (MmcDevInfo.MmcDevType == MMC_IS_EMMC) { + MmcRCA = MMC_FIX_RCA; + Status = MmcHostInstance->MmcHost->SendCommand (MmcHostInstance->MmcHost, MMC_CMD3, MmcRCA << RCA_SHIFT_OFFSET, + MMC_RESPONSE_R1, NULL); + if (EFI_ERROR (Status)) { + return Status; + } + } else { + Status = MmcHostInstance->MmcHost->SendCommand (MmcHostInstance->MmcHost, MMC_CMD3, 0, + MMC_RESPONSE_R6, Response); + if (EFI_ERROR (Status)) { + return Status; + } + + MmcRCA = (Response[0] & 0xFFFF0000U) >> 16; + } + + // CMD9: CSD Register + Status = MmcHostInstance->MmcHost->SendCommand (MmcHostInstance->MmcHost, MMC_CMD9, MmcRCA << RCA_SHIFT_OFFSET, + MMC_RESPONSE_R2, Response); + if (EFI_ERROR (Status)) { + return Status; + } + + CopyMem(&MmcCsd, &Response, sizeof(Response)); + + // CMD7: Select Card + Status = MmcHostInstance->MmcHost->SendCommand (MmcHostInstance->MmcHost, MMC_CMD7, MmcRCA << RCA_SHIFT_OFFSET, + MMC_RESPONSE_R1, NULL); + if (EFI_ERROR (Status)) { + return Status; + } + + do { + Status = MmcDeviceState (MmcHostInstance, &State); + if (EFI_ERROR (Status)) { + return Status; + } + } while (State != MMC_R0_STATE_TRAN); + + Status = MmcSetIos (MmcHostInstance, Clk, BusWidth); + if (EFI_ERROR (Status)) { + return Status; + } + + return MmcFillDeviceInfo (MmcHostInstance); +} + +/** + Perform the MMC Identification Mode. + + @param[in] MmcHostInstance Pointer to the MMC_HOST_INSTANCE structure. + + @retval EFI_SUCCESS The MMC Identification Mode was performed successfully. + @retval EFI_INVALID_PARAMETER MmcHost is NULL. + @retval Other An error occurred while performing the MMC Identification Mode. + +**/ +STATIC +EFI_STATUS +EFIAPI +MmcIdentificationMode ( + IN MMC_HOST_INSTANCE *MmcHostInstance + ) +{ + EFI_STATUS Status; + UINTN CmdArg; + BOOLEAN IsHCS; + EFI_MMC_HOST_PROTOCOL *MmcHost; + + MmcHost = MmcHostInstance->MmcHost; + CmdArg = 0; + IsHCS = FALSE; + + if (MmcHost == NULL) { + return EFI_INVALID_PARAMETER; + } + + // We can get into this function if we restart the identification mode + if (MmcHostInstance->State == MmcHwInitializationState) { + // Initialize the MMC Host HW + Status = MmcNotifyState (MmcHostInstance, MmcHwInitializationState); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "MmcIdentificationMode() : Error MmcHwInitializationState, Status=%r.\n", Status)); + return Status; + } + } + + Status = MmcEnumerte (MmcHostInstance, 50 * 1000 * 1000, MMC_BUS_WIDTH_4); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "MmcIdentificationMode() : Error MmcEnumerte, Status=%r.\n", Status)); + return Status; + } + + MmcHostInstance->CardInfo.RCA = MmcRCA; + MmcHostInstance->BlockIo.Media->LastBlock = ((MmcDevInfo.DeviceSize >> 9) - 1); + MmcHostInstance->BlockIo.Media->BlockSize = MmcDevInfo.BlockSize; + MmcHostInstance->BlockIo.Media->ReadOnly = MmcHost->IsReadOnly (MmcHost); + MmcHostInstance->BlockIo.Media->MediaPresent = TRUE; + MmcHostInstance->BlockIo.Media->MediaId++; + + return EFI_SUCCESS; +} + +/** + Initialize the MMC device. + + @param[in] MmcHostInstance MMC host instance + + @retval EFI_SUCCESS MMC device initialized successfully + @retval Other MMC device initialization failed + +**/ +EFI_STATUS +InitializeMmcDevice ( + IN MMC_HOST_INSTANCE *MmcHostInstance + ) +{ + EFI_STATUS Status; + EFI_MMC_HOST_PROTOCOL *MmcHost; + UINTN BlockCount; + + BlockCount = 1; + MmcHost = MmcHostInstance->MmcHost; + + Status = MmcIdentificationMode (MmcHostInstance); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "InitializeMmcDevice(): Error in Identification Mode, Status=%r\n", Status)); + return Status; + } + + Status = MmcNotifyState (MmcHostInstance, MmcTransferState); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "InitializeMmcDevice(): Error MmcTransferState, Status=%r\n", Status)); + return Status; + } + + return EFI_SUCCESS; +} -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#108214): https://edk2.groups.io/g/devel/message/108214 Mute This Topic: https://groups.io/mt/101084026/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=- From: caiyuqing379 <202235273@mail.sdu.edu.cn> This module supports Sophgo SG2042 EVB platform. It uses the PEI less design. Add this module in SG2042Pkg leveraging the one from OvmfPkg/RiscVVirt. Signed-off-by: caiyuqing379 <202235273@mail.sdu.edu.cn> Co-authored-by: USER0FISH <libing1202@outlook.com> Cc: dahogn <dahogn@hotmail.com> Cc: meng-cz <mengcz1126@gmail.com> Cc: yli147 <yong.li@intel.com> Cc: ChaiEvan <evan.chai@intel.com> Cc: Sunil V L <sunilvl@ventanamicro.com> --- Platform/Sophgo/SG2042Pkg/Sec/SecMain.inf | 68 ++++ Platform/Sophgo/SG2042Pkg/Sec/SecMain.h | 103 ++++++ Platform/Sophgo/SG2042Pkg/Sec/Cpu.c | 29 ++ Platform/Sophgo/SG2042Pkg/Sec/Memory.c | 363 ++++++++++++++++++++++ Platform/Sophgo/SG2042Pkg/Sec/Platform.c | 141 +++++++++ Platform/Sophgo/SG2042Pkg/Sec/SecMain.c | 116 +++++++ Platform/Sophgo/SG2042Pkg/Sec/SecEntry.S | 18 ++ 7 files changed, 838 insertions(+) create mode 100644 Platform/Sophgo/SG2042Pkg/Sec/SecMain.inf create mode 100644 Platform/Sophgo/SG2042Pkg/Sec/SecMain.h create mode 100644 Platform/Sophgo/SG2042Pkg/Sec/Cpu.c create mode 100644 Platform/Sophgo/SG2042Pkg/Sec/Memory.c create mode 100644 Platform/Sophgo/SG2042Pkg/Sec/Platform.c create mode 100644 Platform/Sophgo/SG2042Pkg/Sec/SecMain.c create mode 100644 Platform/Sophgo/SG2042Pkg/Sec/SecEntry.S diff --git a/Platform/Sophgo/SG2042Pkg/Sec/SecMain.inf b/Platform/Sophgo/SG2042Pkg/Sec/SecMain.inf new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/Sophgo/SG2042Pkg/Sec/SecMain.inf @@ -XXX,XX +XXX,XX @@ +## @file +# SEC Driver for RISC-V +# +# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR> +# Copyright (c) 2023, Academy of Intelligent Innovation, Shandong Universiy, China.P.R. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001B + BASE_NAME = SecMainRiscV64 + FILE_GUID = 125E1236-9D4F-457B-BF7E-6311C88A1621 + MODULE_TYPE = SEC + VERSION_STRING = 1.0 + ENTRY_POINT = SecMain + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = RISCV64 +# + +[Sources] + SecEntry.S + SecMain.c + SecMain.h + Cpu.c + Memory.c + Platform.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + Platform/Sophgo/SG2042Pkg/SG2042Pkg.dec + Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + PcdLib + IoLib + PeCoffLib + LzmaDecompressLib + RiscVSbiLib + PrePiLib + FdtLib + MemoryAllocationLib + HobLib + SerialPortLib + +[FixedPcd] + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase ## CONSUMES + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize ## CONSUMES + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress ## CONSUMES + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize ## CONSUMES + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES + +[Guids] + gFdtHobGuid ## PRODUCES + +[BuildOptions] + GCC:*_*_*_PP_FLAGS = -D__ASSEMBLY__ + diff --git a/Platform/Sophgo/SG2042Pkg/Sec/SecMain.h b/Platform/Sophgo/SG2042Pkg/Sec/SecMain.h new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/Sophgo/SG2042Pkg/Sec/SecMain.h @@ -XXX,XX +XXX,XX @@ +/** @file + Master header file for SecCore. + + Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR> + Copyright (c) 2023, Academy of Intelligent Innovation, Shandong Universiy, China.P.R. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SEC_MAIN_H_ +#define SEC_MAIN_H_ + +#include <PiPei.h> +#include <Library/BaseLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/DebugAgentLib.h> +#include <Library/DebugLib.h> +#include <Library/ExtractGuidedSectionLib.h> +#include <Library/IoLib.h> +#include <Library/HobLib.h> +#include <Library/PcdLib.h> +#include <Library/PeCoffExtraActionLib.h> +#include <Library/PeCoffGetEntryPointLib.h> +#include <Library/PeCoffLib.h> +#include <Library/PeiServicesLib.h> +#include <Library/PeiServicesTablePointerLib.h> +#include <Library/DebugPrintErrorLevelLib.h> +#include <Library/PrintLib.h> +#include <Library/BaseRiscVSbiLib.h> +#include <Library/PrePiLib.h> +#include <Library/PrePiHobListPointerLib.h> +#include <Library/SerialPortLib.h> +#include <Register/RiscV64/RiscVImpl.h> + +/** + Entry point to the C language phase of SEC. After the SEC assembly + code has initialized some temporary memory and set up the stack, + the control is transferred to this function. + + @param SizeOfRam Size of the temporary memory available for use. + @param TempRamBase Base address of temporary ram + @param BootFirmwareVolume Base address of the Boot Firmware Volume. +**/ +VOID +NORETURN +EFIAPI +SecStartup ( + IN UINTN BootHartId, + IN VOID *DeviceTreeAddress + ); + +/** + Auto-generated function that calls the library constructors for all of the module's + dependent libraries. This function must be called by the SEC Core once a stack has + been established. + +**/ +VOID +EFIAPI +ProcessLibraryConstructorList ( + VOID + ); + +/** + Perform Platform PEIM initialization. + + @return EFI_SUCCESS The platform initialized successfully. + @retval Others - As the error code indicates + +**/ +EFI_STATUS +EFIAPI +PlatformPeimInitialization ( + VOID + ); + +/** + Perform Memory PEIM initialization. + + @return EFI_SUCCESS The platform initialized successfully. + @retval Others - As the error code indicates + +**/ +EFI_STATUS +EFIAPI +MemoryPeimInitialization ( + VOID + ); + +/** + Perform CPU PEIM initialization. + + @return EFI_SUCCESS The platform initialized successfully. + @retval Others - As the error code indicates + +**/ +EFI_STATUS +EFIAPI +CpuPeimInitialization ( + VOID + ); + +#endif diff --git a/Platform/Sophgo/SG2042Pkg/Sec/Cpu.c b/Platform/Sophgo/SG2042Pkg/Sec/Cpu.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/Sophgo/SG2042Pkg/Sec/Cpu.c @@ -XXX,XX +XXX,XX @@ +/** @file +The library call to pass the device tree to DXE via HOB. + +Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR> + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <PiPei.h> +#include <Library/DebugLib.h> +#include <Library/HobLib.h> + +/** + Cpu Peim initialization. + +**/ +EFI_STATUS +CpuPeimInitialization ( + VOID + ) +{ + // + // for MMU type >= sv39 + // + BuildCpuHob (40, 39); + + return EFI_SUCCESS; +} diff --git a/Platform/Sophgo/SG2042Pkg/Sec/Memory.c b/Platform/Sophgo/SG2042Pkg/Sec/Memory.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/Sophgo/SG2042Pkg/Sec/Memory.c @@ -XXX,XX +XXX,XX @@ +/** @file + Memory Detection for SG2042 EVB. + + Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR> + Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR> + Copyright (c) 2023, Academy of Intelligent Innovation, Shandong Universiy, China.P.R. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +Module Name: + + MemDetect.c + +**/ + +#include <PiPei.h> +#include <Library/BaseMemoryLib.h> +#include <Library/DebugLib.h> +#include <Library/HobLib.h> +#include <Library/IoLib.h> +#include <Library/PcdLib.h> +#include <Library/PeimEntryPoint.h> +#include <Library/ResourcePublicationLib.h> +#include <Library/BaseRiscVSbiLib.h> +#include <Register/RiscV64/RiscVEncoding.h> +#include <Library/PrePiLib.h> +#include <libfdt.h> +#include <Guid/FdtHob.h> + +VOID +BuildMemoryTypeInformationHob ( + VOID + ); + +/** + Create memory range resource HOB using the memory base + address and size. + + @param MemoryBase Memory range base address. + @param MemorySize Memory range size. + +**/ +STATIC +VOID +AddMemoryBaseSizeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN UINT64 MemorySize + ) +{ + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED, + MemoryBase, + MemorySize + ); +} + +/** + Create memory range resource HOB using memory base + address and top address of the memory range. + + @param MemoryBase Memory range base address. + @param MemoryLimit Memory range size. + +**/ +STATIC +VOID +AddMemoryRangeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN EFI_PHYSICAL_ADDRESS MemoryLimit + ) +{ + AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase)); +} + +/** + Publish system RAM and reserve memory regions. + +**/ +STATIC +VOID +InitializeRamRegions ( + IN EFI_PHYSICAL_ADDRESS SystemMemoryBase, + IN UINT64 SystemMemorySize + ) +{ + AddMemoryRangeHob ( + SystemMemoryBase, + SystemMemoryBase + SystemMemorySize + ); +} + +/** Get the number of cells for a given property + + @param[in] Fdt Pointer to Device Tree (DTB) + @param[in] Node Node + @param[in] Name Name of the property + + @return Number of cells. +**/ +STATIC +INT32 +GetNumCells ( + IN VOID *Fdt, + IN INT32 Node, + IN CONST CHAR8 *Name + ) +{ + CONST INT32 *Prop; + INT32 Len; + UINT32 Val; + + Prop = fdt_getprop (Fdt, Node, Name, &Len); + if (Prop == NULL) { + return Len; + } + + if (Len != sizeof (*Prop)) { + return -FDT_ERR_BADNCELLS; + } + + Val = fdt32_to_cpu (*Prop); + if (Val > FDT_MAX_NCELLS) { + return -FDT_ERR_BADNCELLS; + } + + return (INT32)Val; +} + +/** Mark reserved memory ranges in the EFI memory map + + * As per DT spec v0.4 Section 3.5.4, + * "Reserved regions with the no-map property must be listed in the + * memory map with type EfiReservedMemoryType. All other reserved + * regions must be listed with type EfiBootServicesData." + + @param FdtPointer Pointer to FDT + +**/ +STATIC +VOID +AddReservedMemoryMap ( + IN VOID *FdtPointer + ) +{ + CONST INT32 *RegProp; + INT32 Node; + INT32 SubNode; + INT32 Len; + EFI_PHYSICAL_ADDRESS Addr; + UINT64 Size; + INTN NumRsv, i; + INT32 NumAddrCells, NumSizeCells; + + NumRsv = fdt_num_mem_rsv (FdtPointer); + + /* Look for an existing entry and add it to the efi mem map. */ + for (i = 0; i < NumRsv; i++) { + if (fdt_get_mem_rsv (FdtPointer, i, &Addr, &Size) != 0) { + continue; + } + + BuildMemoryAllocationHob ( + Addr, + Size, + EfiReservedMemoryType + ); + } + + /* process reserved-memory */ + Node = fdt_subnode_offset (FdtPointer, 0, "reserved-memory"); + if (Node >= 0) { + NumAddrCells = GetNumCells (FdtPointer, Node, "#address-cells"); + if (NumAddrCells <= 0) { + return; + } + + NumSizeCells = GetNumCells (FdtPointer, Node, "#size-cells"); + if (NumSizeCells <= 0) { + return; + } + + fdt_for_each_subnode (SubNode, FdtPointer, Node) { + RegProp = fdt_getprop (FdtPointer, SubNode, "reg", &Len); + + if ((RegProp != 0) && (Len == ((NumAddrCells + NumSizeCells) * sizeof (INT32)))) { + Addr = fdt32_to_cpu (RegProp[0]); + + if (NumAddrCells > 1) { + Addr = (Addr << 32) | fdt32_to_cpu (RegProp[1]); + } + + RegProp += NumAddrCells; + Size = fdt32_to_cpu (RegProp[0]); + + if (NumSizeCells > 1) { + Size = (Size << 32) | fdt32_to_cpu (RegProp[1]); + } + + DEBUG (( + DEBUG_INFO, + "%a: Adding Reserved Memory Addr = 0x%llx, Size = 0x%llx\n", + __func__, + Addr, + Size + )); + + if (fdt_getprop (FdtPointer, SubNode, "no-map", &Len)) { + BuildMemoryAllocationHob ( + Addr, + Size, + EfiReservedMemoryType + ); + } else { + BuildMemoryAllocationHob ( + Addr, + Size, + EfiBootServicesData + ); + } + } + } + } +} + +/** + Initialize memory hob based on the DTB information. + + NOTE: The memory space size of SG2042 EVB is determined by the number + and size of DDRs inserted on the board. There is an error with initializing + the system ram space of each memory node separately using InitializeRamRegions, + so InitializeRamRegions is only called once for total system ram initialization. + + @return EFI_SUCCESS The memory hob added successfully. + +**/ +EFI_STATUS +MemoryPeimInitialization ( + VOID + ) +{ + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext; + CONST UINT64 *RegProp; + CONST CHAR8 *Type; + UINT64 UefiMemoryBase; + UINT64 CurBase; + UINT64 CurSize; + UINT64 LongestStart; + UINT64 LongestLength; + UINT64 PrevEnd; + UINT64 CurStart; + UINT64 CurLength; + UINT64 MaxLength; + INT32 Node; + INT32 Prev; + INT32 Len; + VOID *FdtPointer; + + FirmwareContext = NULL; + GetFirmwareContextPointer (&FirmwareContext); + + if (FirmwareContext == NULL) { + DEBUG ((DEBUG_ERROR, "%a: Firmware Context is NULL\n", __func__)); + return EFI_UNSUPPORTED; + } + + FdtPointer = (VOID *)FirmwareContext->FlattenedDeviceTree; + if (FdtPointer == NULL) { + DEBUG ((DEBUG_ERROR, "%a: Invalid FDT pointer\n", __func__)); + return EFI_UNSUPPORTED; + } + + UefiMemoryBase = (UINT64)FixedPcdGet32 (PcdTemporaryRamBase) + FixedPcdGet32 (PcdTemporaryRamSize) - SIZE_32MB; + LongestStart = 0; + LongestLength = 0; + PrevEnd = 0; + CurStart = 0; + CurLength = 0; + MaxLength = 0; + + // Look for the lowest memory node + for (Prev = 0; ; Prev = Node) { + Node = fdt_next_node (FdtPointer, Prev, NULL); + if (Node < 0) { + break; + } + + // Check for memory node + Type = fdt_getprop (FdtPointer, Node, "device_type", &Len); + if (Type && (AsciiStrnCmp (Type, "memory", Len) == 0)) { + // Get the 'reg' property of this node. For now, we will assume + // two 8 byte quantities for base and size, respectively. + RegProp = fdt_getprop (FdtPointer, Node, "reg", &Len); + if ((RegProp != 0) && (Len == (2 * sizeof (UINT64)))) { + CurBase = fdt64_to_cpu (ReadUnaligned64 (RegProp)); + CurSize = fdt64_to_cpu (ReadUnaligned64 (RegProp + 1)); + + DEBUG (( + DEBUG_INFO, + "%a: System RAM @ 0x%lx - 0x%lx\n", + __func__, + CurBase, + CurBase + CurSize - 1 + )); + + if (PrevEnd == 0 || CurBase == PrevEnd) { + if (CurLength == 0) { + CurStart = CurBase; + } + CurLength += CurSize; + + if (CurLength > MaxLength) { + MaxLength = CurLength; + LongestStart = CurStart; + LongestLength = MaxLength; + } + } else { + CurStart = CurBase; + CurLength = CurSize; + } + + PrevEnd = CurBase + CurSize; + + } else { + DEBUG (( + DEBUG_ERROR, + "%a: Failed to parse FDT memory node\n", + __func__ + )); + } + } + } + + if (UefiMemoryBase > LongestStart) { + LongestStart = UefiMemoryBase; + LongestLength -= UefiMemoryBase; + } + + DEBUG (( + DEBUG_INFO, + "%a: Total System RAM @ 0x%lx - 0x%lx\n", + __func__, + LongestStart, + LongestStart + LongestLength - 1 + )); + + InitializeRamRegions (LongestStart, LongestLength); + + AddReservedMemoryMap (FdtPointer); + + /* Make sure SEC is booting with bare mode */ + ASSERT ((RiscVGetSupervisorAddressTranslationRegister () & SATP64_MODE) == (SATP_MODE_OFF << SATP64_MODE_SHIFT)); + + BuildMemoryTypeInformationHob (); + + return EFI_SUCCESS; +} diff --git a/Platform/Sophgo/SG2042Pkg/Sec/Platform.c b/Platform/Sophgo/SG2042Pkg/Sec/Platform.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/Sophgo/SG2042Pkg/Sec/Platform.c @@ -XXX,XX +XXX,XX @@ +/** @file +The library call to pass the device tree to DXE via HOB. + +Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR> + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <PiPei.h> +#include <Library/DebugLib.h> +#include <Library/HobLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/BaseRiscVSbiLib.h> +#include <Library/PcdLib.h> +#include <Include/Library/PrePiLib.h> +#include <libfdt.h> +#include <Guid/FdtHob.h> + +/** + Build memory map I/O range resource HOB using the + base address and size. + + @param MemoryBase Memory map I/O base. + @param MemorySize Memory map I/O size. + +**/ +STATIC +VOID +AddIoMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ) +{ + /* Align to EFI_PAGE_SIZE */ + MemorySize = ALIGN_VALUE (MemorySize, EFI_PAGE_SIZE); + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_MAPPED_IO, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED, + MemoryBase, + MemorySize + ); +} + +/** + Populate IO resources from FDT that not added to GCD by its + driver in the DXE phase. + + @param FdtBase Fdt base address + @param Compatible Compatible string + +**/ +STATIC +VOID +PopulateIoResources ( + VOID *FdtBase, + CONST CHAR8 *Compatible + ) +{ + UINT64 *Reg; + INT32 Node, LenP; + + Node = fdt_node_offset_by_compatible (FdtBase, -1, Compatible); + while (Node != -FDT_ERR_NOTFOUND) { + Reg = (UINT64 *)fdt_getprop (FdtBase, Node, "reg", &LenP); + if (Reg) { + ASSERT (LenP == (2 * sizeof (UINT64))); + AddIoMemoryBaseSizeHob (SwapBytes64 (Reg[0]), SwapBytes64 (Reg[1])); + } + + Node = fdt_node_offset_by_compatible (FdtBase, Node, Compatible); + } +} + +/** + @retval EFI_SUCCESS The address of FDT is passed in HOB. + EFI_UNSUPPORTED Can't locate FDT. +**/ +EFI_STATUS +EFIAPI +PlatformPeimInitialization ( + VOID + ) +{ + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext; + VOID *FdtPointer; + VOID *Base; + VOID *NewBase; + UINTN FdtSize; + UINTN FdtPages; + UINT64 *FdtHobData; + + FirmwareContext = NULL; + GetFirmwareContextPointer (&FirmwareContext); + + if (FirmwareContext == NULL) { + DEBUG ((DEBUG_ERROR, "%a: Firmware Context is NULL\n", __func__)); + return EFI_UNSUPPORTED; + } + + FdtPointer = (VOID *)FirmwareContext->FlattenedDeviceTree; + if (FdtPointer == NULL) { + DEBUG ((DEBUG_ERROR, "%a: Invalid FDT pointer\n", __func__)); + return EFI_UNSUPPORTED; + } + + DEBUG ((DEBUG_INFO, "%a: Build FDT HOB - FDT at address: 0x%x \n", __func__, FdtPointer)); + Base = FdtPointer; + if (fdt_check_header (Base) != 0) { + DEBUG ((DEBUG_ERROR, "%a: Corrupted DTB\n", __func__)); + return EFI_UNSUPPORTED; + } + + FdtSize = fdt_totalsize (Base); + FdtPages = EFI_SIZE_TO_PAGES (FdtSize); + NewBase = AllocatePages (FdtPages); + if (NewBase == NULL) { + DEBUG ((DEBUG_ERROR, "%a: Could not allocate memory for DTB\n", __func__)); + return EFI_UNSUPPORTED; + } + + fdt_open_into (Base, NewBase, EFI_PAGES_TO_SIZE (FdtPages)); + + FdtHobData = BuildGuidHob (&gFdtHobGuid, sizeof *FdtHobData); + if (FdtHobData == NULL) { + DEBUG ((DEBUG_ERROR, "%a: Could not build FDT Hob\n", __func__)); + return EFI_UNSUPPORTED; + } + + *FdtHobData = (UINTN)NewBase; + + BuildFvHob (PcdGet32 (PcdRiscVDxeFvBase), PcdGet32 (PcdRiscVDxeFvSize)); + + PopulateIoResources (Base, "bitmain,bm-sd"); + PopulateIoResources (Base, "snps,dw-apb-uart"); + + return EFI_SUCCESS; +} diff --git a/Platform/Sophgo/SG2042Pkg/Sec/SecMain.c b/Platform/Sophgo/SG2042Pkg/Sec/SecMain.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/Sophgo/SG2042Pkg/Sec/SecMain.c @@ -XXX,XX +XXX,XX @@ +/** @file + RISC-V SEC phase module for SG2042 EVB. + + Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR> + Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR> + Copyright (c) 2023, Academy of Intelligent Innovation, Shandong Universiy, China.P.R. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SecMain.h" + +/** + Initialize the memory and CPU, setting the boot mode, and platform + initialization. It also builds the core information HOB. + + @return EFI_SUCCESS Status. +**/ +STATIC +EFI_STATUS +EFIAPI +SecInitializePlatform ( + VOID + ) +{ + EFI_STATUS Status; + + MemoryPeimInitialization (); + + CpuPeimInitialization (); + + // Set the Boot Mode + SetBootMode (BOOT_WITH_FULL_CONFIGURATION); + + Status = PlatformPeimInitialization (); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} + +/** + + Entry point to the C language phase of SEC. After the SEC assembly + code has initialized some temporary memory and set up the stack, + the control is transferred to this function. + + + @param[in] BootHartId Hardware thread ID of boot hart. + @param[in] DeviceTreeAddress Pointer to Device Tree (DTB) +**/ +VOID +NORETURN +EFIAPI +SecStartup ( + IN UINTN BootHartId, + IN VOID *DeviceTreeAddress + ) +{ + EFI_HOB_HANDOFF_INFO_TABLE *HobList; + EFI_RISCV_FIRMWARE_CONTEXT FirmwareContext; + EFI_STATUS Status; + UINT64 UefiMemoryBase; + UINT64 StackBase; + UINT32 StackSize; + + SerialPortInitialize (); + + // + // Report Status Code to indicate entering SEC core + // + DEBUG (( + DEBUG_INFO, + "%a() BootHartId: 0x%x, DeviceTreeAddress=0x%x\n", + __func__, + BootHartId, + DeviceTreeAddress + )); + + FirmwareContext.BootHartId = BootHartId; + FirmwareContext.FlattenedDeviceTree = (UINT64)DeviceTreeAddress; + SetFirmwareContextPointer (&FirmwareContext); + + StackBase = (UINT64)FixedPcdGet32 (PcdTemporaryRamBase); + StackSize = FixedPcdGet32 (PcdTemporaryRamSize); + UefiMemoryBase = StackBase + StackSize - SIZE_32MB; + + // Declare the PI/UEFI memory region + HobList = HobConstructor ( + (VOID *)UefiMemoryBase, + SIZE_32MB, + (VOID *)UefiMemoryBase, + (VOID *)StackBase // The top of the UEFI Memory is reserved for the stacks + ); + PrePeiSetHobList (HobList); + + SecInitializePlatform (); + + BuildStackHob (StackBase, StackSize); + + // + // Process all libraries constructor function linked to SecMain. + // + ProcessLibraryConstructorList (); + + // Assume the FV that contains the SEC (our code) also contains a compressed FV. + Status = DecompressFirstFv (); + ASSERT_EFI_ERROR (Status); + + // Load the DXE Core and transfer control to it + Status = LoadDxeCoreFromFv (NULL, 0); + ASSERT_EFI_ERROR (Status); + // + // Should not come here. + // + UNREACHABLE (); +} diff --git a/Platform/Sophgo/SG2042Pkg/Sec/SecEntry.S b/Platform/Sophgo/SG2042Pkg/Sec/SecEntry.S new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/Sophgo/SG2042Pkg/Sec/SecEntry.S @@ -XXX,XX +XXX,XX @@ +/* + Copyright (c) 2022 Ventana Micro Systems Inc. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + */ + +#include "SecMain.h" + +ASM_FUNC (_ModuleEntryPoint) + /* Use Temp memory as the stack for calling to C code */ + li a4, FixedPcdGet32 (PcdTemporaryRamBase) + li a5, FixedPcdGet32 (PcdTemporaryRamSize) + + /* Use Temp memory as the stack for calling to C code */ + add sp, a4, a5 + + call SecStartup -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#108211): https://edk2.groups.io/g/devel/message/108211 Mute This Topic: https://groups.io/mt/101084023/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=- From: caiyuqing379 <202235273@mail.sdu.edu.cn> Add infrastructure files to build edk2-platforms for Sophgo SG2042 platform. It follows PEI less design. Signed-off-by: caiyuqing379 <202235273@mail.sdu.edu.cn> Co-authored-by: USER0FISH <libing1202@outlook.com> Cc: dahogn <dahogn@hotmail.com> Cc: meng-cz <mengcz1126@gmail.com> Cc: yli147 <yong.li@intel.com> Cc: ChaiEvan <evan.chai@intel.com> Cc: Sunil V L <sunilvl@ventanamicro.com> --- .../SG2042Pkg/SG2042_EVB_Board/SG2042.dec | 19 + .../SG2042Pkg/SG2042_EVB_Board/SG2042.dsc | 548 ++++++++++++++++++ .../SG2042Pkg/SG2042_EVB_Board/SG2042.fdf | 247 ++++++++ .../SG2042Pkg/SG2042_EVB_Board/SG2042.fdf.inc | 62 ++ .../SG2042_EVB_Board/VarStore.fdf.inc | 77 +++ 5 files changed, 953 insertions(+) create mode 100644 Platform/Sophgo/SG2042Pkg/SG2042_EVB_Board/SG2042.dec create mode 100644 Platform/Sophgo/SG2042Pkg/SG2042_EVB_Board/SG2042.dsc create mode 100644 Platform/Sophgo/SG2042Pkg/SG2042_EVB_Board/SG2042.fdf create mode 100644 Platform/Sophgo/SG2042Pkg/SG2042_EVB_Board/SG2042.fdf.inc create mode 100644 Platform/Sophgo/SG2042Pkg/SG2042_EVB_Board/VarStore.fdf.inc diff --git a/Platform/Sophgo/SG2042Pkg/SG2042_EVB_Board/SG2042.dec b/Platform/Sophgo/SG2042Pkg/SG2042_EVB_Board/SG2042.dec new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/Sophgo/SG2042Pkg/SG2042_EVB_Board/SG2042.dec @@ -XXX,XX +XXX,XX @@ +## @file SG2042.dec +# This Package provides Sophgo SG2042 modules and libraries. +# +# Copyright (c) 2023, Academy of Intelligent Innovation, Shandong Universiy, China.P.R. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + DEC_SPECIFICATION = 0x0001001b + PACKAGE_NAME = SG2042 + PACKAGE_GUID = BBF86176-C58B-4EC5-8D76-B8D458A2548E + PACKAGE_VERSION = 1.0 + +[LibraryClasses] + +[Guids] + gUefiRiscVPlatformSG2042PkgTokenSpaceGuid = {0xD0D80952, 0x8371, 0x4D8D, { 0x8E, 0x65, 0x27, 0x52, 0x63, 0xF3, 0xD9, 0x27 }} diff --git a/Platform/Sophgo/SG2042Pkg/SG2042_EVB_Board/SG2042.dsc b/Platform/Sophgo/SG2042Pkg/SG2042_EVB_Board/SG2042.dsc new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/Sophgo/SG2042Pkg/SG2042_EVB_Board/SG2042.dsc @@ -XXX,XX +XXX,XX @@ +## @file +# RISC-V EFI on Sophgo SG2042 EVB RISC-V platform +# +# Copyright (c) 2023, Academy of Intelligent Innovation, Shandong Universiy, China.P.R. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = SG2042_EVB + PLATFORM_GUID = 8014637B-6999-4110-9762-464BE11E935F + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x0001001c + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = RISCV64 + BUILD_TARGETS = DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/Sophgo/SG2042Pkg/SG2042_EVB_Board/SG2042.fdf + + # + # Enable below options may cause build error or may not work on + # the initial version of RISC-V package + # Defines for default states. These can be changed on the command line. + # -D FLAG=VALUE + # + DEFINE SECURE_BOOT_ENABLE = FALSE + DEFINE DEBUG_ON_SERIAL_PORT = TRUE + + # + # Network definition + # + DEFINE NETWORK_SNP_ENABLE = FALSE + DEFINE NETWORK_IP6_ENABLE = FALSE + DEFINE NETWORK_TLS_ENABLE = FALSE + DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE + DEFINE NETWORK_ISCSI_ENABLE = FALSE + +[BuildOptions] + GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG +!ifdef $(SOURCE_DEBUG_ENABLE) + GCC:*_*_RISCV64_GENFW_FLAGS = --keepexceptiontable +!endif + +################################################################################ +# +# SKU Identification section - list of all SKU IDs supported by this Platform. +# +################################################################################ +[SkuIds] + 0|DEFAULT + +################################################################################ +# +# Library Class section - list of all Library Classes needed by this Platform. +# +################################################################################ + +!include MdePkg/MdeLibs.dsc.inc + +[LibraryClasses] + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf + SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf + PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf + PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf + SerialPortLib|MdePkg/Library/BaseSerialPortLibRiscVSbiLib/BaseSerialPortLibRiscVSbiLibRam.inf + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDevicePathLibDevicePathProtocol.inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf + SortLib|MdeModulePkg/Library/BaseSortLib/BaseSortLib.inf + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf + VariableFlashInfoLib|MdeModulePkg/Library/BaseVariableFlashInfoLib/BaseVariableFlashInfoLib.inf + VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/VariablePolicyHelperLib.inf + +!ifdef $(SOURCE_DEBUG_ENABLE) + PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraActionLibDebug.inf + DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicationLibSerialPort/DebugCommunicationLibSerialPort.inf +!else + PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf +!endif + + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf + +!if $(SECURE_BOOT_ENABLE) == TRUE + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf + TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasurementLib.inf + AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf + SecureBootVariableLib|SecurityPkg/Library/SecureBootVariableLib/SecureBootVariableLib.inf + SecureBootVariableProvisionLib|SecurityPkg/Library/SecureBootVariableProvisionLib/SecureBootVariableProvisionLib.inf + PlatformPKProtectionLib|SecurityPkg/Library/PlatformPKProtectionLibVarPolicy/PlatformPKProtectionLibVarPolicy.inf +!else + TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf + AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf +!endif + VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf + +!if $(HTTP_BOOT_ENABLE) == TRUE + HttpLib|MdeModulePkg/Library/DxeHttpLib/DxeHttpLib.inf +!endif + + # ACPI not supported yet. + # S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf + SmbusLib|MdePkg/Library/BaseSmbusLibNull/BaseSmbusLibNull.inf + OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf + +[LibraryClasses.common] +!if $(SECURE_BOOT_ENABLE) == TRUE + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf +!endif + + # RISC-V Architectural Libraries + RiscVSbiLib|MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf + RiscVMmuLib|UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf + CpuExceptionHandlerLib|UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.inf + + TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf + TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf + RealTimeClockLib|EmbeddedPkg//Library/VirtualRealTimeClockLib/VirtualRealTimeClockLib.inf + + # Flattened Device Tree (FDT) access library + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf + +[LibraryClasses.common.SEC] +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif + + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf + ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.inf + PlatformSecLib|UefiCpuPkg/Library/PlatformSecLibNull/PlatformSecLibNull.inf + HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf + PrePiHobListPointerLib|OvmfPkg/RiscVVirt/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf + MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf + +!ifdef $(SOURCE_DEBUG_ENABLE) + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib.inf +!endif + +[LibraryClasses.common.DXE_CORE] + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf +!ifdef $(SOURCE_DEBUG_ENABLE) + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf +!endif + +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf + ResetSystemLib|OvmfPkg/RiscVVirt/Library/ResetSystemLib/BaseResetSystemLib.inf + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif +!if $(SECURE_BOOT_ENABLE) == TRUE + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf +!endif + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf + VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyLibRuntimeDxe.inf + +[LibraryClasses.common.UEFI_DRIVER] + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf + VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyLib.inf + +[LibraryClasses.common.DXE_DRIVER] + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif +!ifdef $(SOURCE_DEBUG_ENABLE) + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf +!endif + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf + PlatformBootManagerLib|Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf + PlatformMemoryTestLib|Platform/RISC-V/PlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.inf + PlatformUpdateProgressLib|Platform/RISC-V/PlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateProgressLibNull.inf + +[LibraryClasses.common.UEFI_APPLICATION] + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform. +# +################################################################################ +[PcdsFeatureFlag] + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSupportUefiDecompress|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE + +[PcdsFixedAtBuild] + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeMemorySize|1 + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE + gEfiMdePkgTokenSpaceGuid.PcdMaximumGuidedExtractHandler|0x10 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x8000 + gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize|0xe000 + + gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0 + + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000004F +!ifdef $(SOURCE_DEBUG_ENABLE) + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x17 +!else + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F +!endif + +!ifdef $(SOURCE_DEBUG_ENABLE) + gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 +!endif + +!if $(SECURE_BOOT_ENABLE) == TRUE + # override the default values from SecurityPkg to ensure images from all sources are verified in secure boot + gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x04 + gEfiSecurityPkgTokenSpaceGuid.PcdFixedMediaImageVerificationPolicy|0x04 + gEfiSecurityPkgTokenSpaceGuid.PcdRemovableMediaImageVerificationPolicy|0x04 +!endif + + # + # F2 for UI APP + # + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 } + + # + # Optional feature to help prevent EFI memory map fragments + # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob + # Values are in EFI Pages (4K). DXE Core will make sure that + # at least this much of each type of memory can be allocated + # from a single memory range. This way you only end up with + # maximum of two fragments for each type in the memory map + # (the memory used, and the free memory that was prereserved + # but not used). + # + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0 +!if $(SECURE_BOOT_ENABLE) == TRUE + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|600 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|400 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|1500 +!else + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|300 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|150 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|1000 +!endif + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|6000 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0 + + # + # Enable strict image permissions for all images. (This applies + # only to images that were built with >= 4 KB section alignment.) + # + gEfiMdeModulePkgTokenSpaceGuid.PcdImageProtectionPolicy|0x3 + + # + # Enable NX memory protection for all non-code regions, including OEM and OS + # reserved ones, with the exception of LoaderData regions, of which OS loaders + # (i.e., GRUB) may assume that its contents are executable. + # + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeNxMemoryProtectionPolicy|0xC000000000007FD5 + +################################################################################ +# +# Pcd Dynamic Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################ + +[PcdsDynamicDefault] + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800 + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600 + + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|0x000A + + # Set video resolution for text setup. + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480 + + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0208 + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosDocRev|0x0 + +[PcdsDynamicHii] + gUefiOvmfPkgTokenSpaceGuid.PcdForceNoAcpi|L"ForceNoAcpi"|gOvmfVariableGuid|0x0|TRUE|NV,BS + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform. +# +################################################################################ +[Components] + + # + # SEC Phase modules + # + Platform/Sophgo/SG2042Pkg/Sec/SecMain.inf { + <LibraryClasses> + ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf + LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf + PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf + HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf + PrePiHobListPointerLib|OvmfPkg/RiscVVirt/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf + MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf + } + + # + # DXE Phase modules + # + MdeModulePkg/Core/Dxe/DxeMain.inf { + <LibraryClasses> + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + } + + MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf + MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf { + <LibraryClasses> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + + ArmVirtPkg/CloudHvPlatformHasAcpiDtDxe/CloudHvHasAcpiDtDxe.inf + EmbeddedPkg/Drivers/FdtClientDxe/FdtClientDxe.inf { + <LibraryClasses> + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + } + + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + +!if $(SECURE_BOOT_ENABLE) == TRUE + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf { + <LibraryClasses> + NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificationLib.inf + } +!else + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf +!endif + + UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf { + <LibraryClasses> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + } + MdeModulePkg/Universal/Metronome/Metronome.inf + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf { + <LibraryClasses> + ResetSystemLib|MdeModulePkg/Library/BaseResetSystemLibNull/BaseResetSystemLibNull.inf + } + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + + # + # RISC-V Platform module + # + Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf { + <LibraryClasses> + SerialPortLib|Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf + } + Platform/Sophgo/SG2042Pkg/Universal/Dxe/PlatformUpdateMmuDxe/PlatformUpdateMmuDxe.inf + Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/MmcDxe.inf + Platform/Sophgo/SG2042Pkg/Universal/Dxe/SdHostDxe/SdHostDxe.inf + + # + # RISC-V Core module + # + UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf + UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf + MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { + <LibraryClasses> + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/VariablePolicyHelperLib.inf + } + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + + # No graphic console supported yet. + # MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf { + # <LibraryClasses> + # PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + # } + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf { + <LibraryClasses> + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + MdeModulePkg/Universal/PrintDxe/PrintDxe.inf + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf + MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + # + # SMBIOS Support + # + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + Platform/Sophgo/SG2042Pkg/Universal/Dxe/SmbiosPlatformDxe/SmbiosPlatformDxe.inf + + # + # Network Support + # + !include NetworkPkg/Network.dsc.inc + + # + # Usb Support + # + MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + # + # FAT filesystem + GPT/MBR partitioning + UDF filesystem + # + FatPkg/EnhancedFatDxe/Fat.inf + MdeModulePkg/Universal/Disk/UdfDxe/UdfDxe.inf + + OvmfPkg/LinuxInitrdDynamicShellCommand/LinuxInitrdDynamicShellCommand.inf { + <PcdsFixedAtBuild> + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + <LibraryClasses> + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + } + + ShellPkg/Application/Shell/Shell.inf { + <LibraryClasses> + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf + + <PcdsFixedAtBuild> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000 + } + +!if $(SECURE_BOOT_ENABLE) == TRUE + SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf +!endif + + MdeModulePkg/Application/UiApp/UiApp.inf { + <LibraryClasses> + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf + } diff --git a/Platform/Sophgo/SG2042Pkg/SG2042_EVB_Board/SG2042.fdf b/Platform/Sophgo/SG2042Pkg/SG2042_EVB_Board/SG2042.fdf new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/Sophgo/SG2042Pkg/SG2042_EVB_Board/SG2042.fdf @@ -XXX,XX +XXX,XX @@ +# @file +# Flash definition file on Sophgo SG2042 EVB RISC-V platform +# +# Copyright (c) 2023, Academy of Intelligent Innovation, Shandong Universiy, China.P.R. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# Platform definitions +# +!include SG2042.fdf.inc + +# +# Build the variable store and the firmware code as one unified flash device +# image. +# +[FD.SG2042] +BaseAddress = $(FW_BASE_ADDRESS) +Size = $(FW_SIZE) +ErasePolarity = 1 +BlockSize = $(BLOCK_SIZE) +NumBlocks = $(FW_BLOCKS) + + +$(FVMAIN_OFFSET)|$(FVMAIN_SIZE) +gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase|gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize +FV = FVMAIN_COMPACT + +!include VarStore.fdf.inc +################################################################################ + +[FV.DXEFV] +BlockSize = 0x10000 +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + +APRIORI DXE { + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + INF Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf + INF UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf + INF Platform/Sophgo/SG2042Pkg/Universal/Dxe/PlatformUpdateMmuDxe/PlatformUpdateMmuDxe.inf +} + +# +# DXE Phase modules +# +INF MdeModulePkg/Core/Dxe/DxeMain.inf +INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf +INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf +INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf +INF ArmVirtPkg/CloudHvPlatformHasAcpiDtDxe/CloudHvHasAcpiDtDxe.inf +INF EmbeddedPkg/Drivers/FdtClientDxe/FdtClientDxe.inf + +INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf +INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf +INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf +INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf +INF MdeModulePkg/Universal/Metronome/Metronome.inf +INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + +# RISC-V Platform Drivers +INF Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf +INF Platform/Sophgo/SG2042Pkg/Universal/Dxe/PlatformUpdateMmuDxe/PlatformUpdateMmuDxe.inf +INF Platform/Sophgo/SG2042Pkg/Universal/Dxe/MmcDxe/MmcDxe.inf +INF Platform/Sophgo/SG2042Pkg/Universal/Dxe/SdHostDxe/SdHostDxe.inf + +# RISC-V Core Drivers +INF UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf +INF UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf + +INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf +INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf +!if $(SECURE_BOOT_ENABLE) == TRUE + INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf +!endif + +INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf +INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf +INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf +INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf +INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf +INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf +INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf +INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf +INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf +INF MdeModulePkg/Universal/PrintDxe/PrintDxe.inf +INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf +INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf +INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf +INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf +INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf +INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf +INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf +INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf +INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf +INF FatPkg/EnhancedFatDxe/Fat.inf +INF MdeModulePkg/Universal/Disk/UdfDxe/UdfDxe.inf + +!ifndef $(SOURCE_DEBUG_ENABLE) +INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf +!endif + +# +# SMBIOS Support +# +INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf +INF Platform/Sophgo/SG2042Pkg/Universal/Dxe/SmbiosPlatformDxe/SmbiosPlatformDxe.inf + +INF OvmfPkg/LinuxInitrdDynamicShellCommand/LinuxInitrdDynamicShellCommand.inf +INF ShellPkg/Application/Shell/Shell.inf + +# +# Network modules +# +!if $(E1000_ENABLE) + FILE DRIVER = 5D695E11-9B3F-4b83-B25F-4A8D5D69BE07 { + SECTION PE32 = Intel3.5/EFIX64/E3507X2.EFI + } +!endif + +!include NetworkPkg/Network.fdf.inc + +# +# Usb Support +# +INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf +INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf +INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf +INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf +INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf +INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + +INF MdeModulePkg/Application/UiApp/UiApp.inf + +################################################################################ + +[FV.FVMAIN_COMPACT] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 27A72E80-3118-4c0c-8673-AA5B4EFA9613 + +INF Platform/Sophgo/SG2042Pkg/Sec/SecMain.inf + +FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + # + # These firmware volumes will have files placed in them uncompressed, + # and then both firmware volumes will be compressed in a single + # compression operation in order to achieve better overall compression. + # + SECTION FV_IMAGE = DXEFV + } + } + +[Rule.Common.SEC] + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED { + PE32 PE32 Align=4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING ="$(MODULE_NAME)" Optional + VERSION STRING ="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE = $(NAMED_GUID) { + PE32 PE32 Align=4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 Align=4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 Align=4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_DRIVER.BINARY] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 Align=4K |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION = $(NAMED_GUID) { + PE32 PE32 Align=4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_APPLICATION.BINARY] + FILE APPLICATION = $(NAMED_GUID) { + PE32 PE32 Align=4K |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.USER_DEFINED.ACPITABLE] + FILE FREEFORM = $(NAMED_GUID) { + RAW ACPI |.acpi + RAW ASL |.aml + } diff --git a/Platform/Sophgo/SG2042Pkg/SG2042_EVB_Board/SG2042.fdf.inc b/Platform/Sophgo/SG2042Pkg/SG2042_EVB_Board/SG2042.fdf.inc new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/Sophgo/SG2042Pkg/SG2042_EVB_Board/SG2042.fdf.inc @@ -XXX,XX +XXX,XX @@ +## @file +# Definitions of Flash definition file on Sophgo SG2042 EVB RISC-V platform +# +# Copyright (c) 2023, Academy of Intelligent Innovation, Shandong Universiy, China.P.R. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## +[Defines] +DEFINE BLOCK_SIZE = 0x1000 + +DEFINE FW_BASE_ADDRESS = 0x02000000 +DEFINE FW_SIZE = 0x00800000 +DEFINE FW_BLOCKS = 0x800 + +# +# 0x000000-0x7DFFFF code +# 0x7E0000-0x800000 variables +# +DEFINE CODE_BASE_ADDRESS = $(FW_BASE_ADDRESS) +DEFINE CODE_SIZE = 0x00780000 +DEFINE CODE_BLOCKS = 0x780 +DEFINE VARS_BLOCKS = 0x20 + +# +# Other FV regions are in the second FW domain. +# The size of memory region must be power of 2. +# The base address must be aligned with the size. +# +# FW memory region +# +DEFINE FVMAIN_OFFSET = 0x00000000 +DEFINE FVMAIN_SIZE = 0x00780000 + +# +# EFI Variable memory region. +# The total size of EFI Variable FD must include +# all of sub regions of EFI Variable +# +DEFINE VARS_OFFSET = 0x00780000 +DEFINE VARS_SIZE = 0x00007000 +DEFINE VARS_FTW_WORKING_OFFSET = $(VARS_OFFSET) + $(VARS_SIZE) +DEFINE VARS_FTW_WORKING_SIZE = 0x00001000 +DEFINE VARS_FTW_SPARE_OFFSET = $(VARS_FTW_WORKING_OFFSET) + $(VARS_FTW_WORKING_SIZE) +DEFINE VARS_FTW_SPARE_SIZE = 0x00018000 + +DEFINE VARIABLE_FW_SIZE = $(VARS_FTW_SPARE_OFFSET) + $(VARS_FTW_SPARE_SIZE) - $(VARS_OFFSET) + +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress = $(FW_BASE_ADDRESS) + $(VARS_OFFSET) +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize = $(VARS_SIZE) + $(VARS_FTW_WORKING_SIZE) + $(VARS_FTW_SPARE_SIZE) +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBlockSize = $(BLOCK_SIZE) +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress = $(CODE_BASE_ADDRESS) + $(VARS_OFFSET) +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize = $(VARIABLE_FW_SIZE) +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamBase = $(CODE_BASE_ADDRESS) + $(FW_SIZE) + 0x1FF0000 +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSize = 0x10000 + +SET gSophgoSG2042PlatformPkgTokenSpaceGuid.PcdSG2042SDIOBase = 0x704002B000 +SET gSophgoSG2042PlatformPkgTokenSpaceGuid.PcdForceNoMMU = TRUE +SET gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase = 0x7040000000 +SET gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate = 115200 +SET gHisiTokenSpaceGuid.PcdSerialPortSendDelay = 10000000 +SET gHisiTokenSpaceGuid.PcdUartClkInHz = 500000000 diff --git a/Platform/Sophgo/SG2042Pkg/SG2042_EVB_Board/VarStore.fdf.inc b/Platform/Sophgo/SG2042Pkg/SG2042_EVB_Board/VarStore.fdf.inc new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/Sophgo/SG2042Pkg/SG2042_EVB_Board/VarStore.fdf.inc @@ -XXX,XX +XXX,XX @@ +## @file +# FDF include file with Layout Regions that define an empty variable store. +# +# Copyright (C) 2014, Red Hat, Inc. +# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +$(VARS_OFFSET)|$(VARS_SIZE) +gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +# +# NV_VARIABLE_STORE +# +DATA = { + ## This is the EFI_FIRMWARE_VOLUME_HEADER + # ZeroVector [] + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + # FileSystemGuid: gEfiSystemNvDataFvGuid = + # { 0xFFF12B8D, 0x7696, 0x4C8B, + # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }} + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, + # FvLength: 0x20000 + 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + # Signature "_FVH" # Attributes + 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00, + # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision + 0x48, 0x00, 0x39, 0xF1, 0x00, 0x00, 0x00, 0x02, + # Blockmap[0]: 0x20 Blocks * 0x1000 Bytes / Block + 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, + # Blockmap[1]: End + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ## This is the VARIABLE_STORE_HEADER +!if $(SECURE_BOOT_ENABLE) == TRUE + # Signature: gEfiAuthenticatedVariableGuid = + # { 0xaaf32c78, 0x947b, 0x439a, + # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }} + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, +!else + # Signature: gEfiVariableGuid = + # { 0xddcf3616, 0x3275, 0x4164, + # { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }} + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, +!endif + # Size: 0x7000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - + # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x6fb8 + # This can speed up the Variable Dispatch a bit. + 0xB8, 0x6F, 0x00, 0x00, + # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +$(VARS_FTW_WORKING_OFFSET)|$(VARS_FTW_WORKING_SIZE) +gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +# +#NV_FTW_WROK +# +DATA = { + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid = + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }} + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49, + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95, + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved + 0x2c, 0xaf, 0x2c, 0x64, 0xFE, 0xFF, 0xFF, 0xFF, + # WriteQueueSize: UINT64 + 0xE0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +$(VARS_FTW_SPARE_OFFSET)|$(VARS_FTW_SPARE_SIZE) +gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize +# +#NV_FTW_SPARE -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#108215): https://edk2.groups.io/g/devel/message/108215 Mute This Topic: https://groups.io/mt/101084027/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=- From: caiyuqing379 <202235273@mail.sdu.edu.cn> Add SG2042Pkg for Sophgo SG2042 platform. Provides PCD tokens. Signed-off-by: caiyuqing379 <202235273@mail.sdu.edu.cn> Co-authored-by: USER0FISH <libing1202@outlook.com> Cc: dahogn <dahogn@hotmail.com> Cc: meng-cz <mengcz1126@gmail.com> Cc: yli147 <yong.li@intel.com> Cc: ChaiEvan <evan.chai@intel.com> Cc: Sunil V L <sunilvl@ventanamicro.com> --- Platform/Sophgo/SG2042Pkg/SG2042Pkg.dec | 35 ++++++++++++++++++++ Platform/Sophgo/SG2042Pkg/SG2042Pkg.uni | 13 ++++++++ Platform/Sophgo/SG2042Pkg/SG2042PkgExtra.uni | 12 +++++++ 3 files changed, 60 insertions(+) create mode 100644 Platform/Sophgo/SG2042Pkg/SG2042Pkg.dec create mode 100644 Platform/Sophgo/SG2042Pkg/SG2042Pkg.uni create mode 100644 Platform/Sophgo/SG2042Pkg/SG2042PkgExtra.uni diff --git a/Platform/Sophgo/SG2042Pkg/SG2042Pkg.dec b/Platform/Sophgo/SG2042Pkg/SG2042Pkg.dec new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/Sophgo/SG2042Pkg/SG2042Pkg.dec @@ -XXX,XX +XXX,XX @@ +## @file SG2042Pkg.dec +# This Package provides modules and libraries.for Sophgo SG2042 platform. +# +# Copyright (c) 2023, Academy of Intelligent Innovation, Shandong Universiy, China.P.R. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + DEC_SPECIFICATION = 0x0001001b + PACKAGE_NAME = SG2042Pkg + PACKAGE_UNI_FILE = SG2042Pkg.uni + PACKAGE_GUID = A10E7DF0-B8AB-4DD0-B383-46358139D313 + PACKAGE_VERSION = 1.0 + +[Includes] + Include + +[Protocols] + gSophgoMmcHostProtocolGuid = { 0x3E591C00, 0x9E4A, 0x11DF, {0x92, 0x44, 0x00, 0x02, 0xA5, 0xF5, 0xF5, 0x1B } } + +[Guids] + gSophgoSG2042PlatformPkgTokenSpaceGuid = {0x779E9346, 0x3C24, 0x478C, { 0xB1, 0x60, 0xB6, 0x09, 0xFC, 0xED, 0xA0, 0x72 }} + +[PcdsFixedAtBuild] + gSophgoSG2042PlatformPkgTokenSpaceGuid.PcdSG2042SDIOBase|0x0|UINT64|0x00001001 + gSophgoSG2042PlatformPkgTokenSpaceGuid.PcdForceNoMMU|0x0|BOOLEAN|0x1002 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x0|UINT64|0x00001004 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|0x0|UINT64|0x00001005 + gHisiTokenSpaceGuid.PcdSerialPortSendDelay|0x0|UINT32|0x00001006 + gHisiTokenSpaceGuid.PcdUartClkInHz|0x0|UINT32|0x00001007 + +[UserExtensions.TianoCore."ExtraFiles"] + SG2042PkgExtra.uni diff --git a/Platform/Sophgo/SG2042Pkg/SG2042Pkg.uni b/Platform/Sophgo/SG2042Pkg/SG2042Pkg.uni new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/Sophgo/SG2042Pkg/SG2042Pkg.uni @@ -XXX,XX +XXX,XX @@ +// /** @file +// Sophgo SG2042 Package Localized Strings and Content. +// +// Copyright (c) 2023, Academy of Intelligent Innovation, Shandong Universiy, China.P.R. All rights reserved.<BR> +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + + +#string STR_PACKAGE_ABSTRACT #language en-US "Provides Sophgo RISC-V SG2042 platform modules and libraries" + +#string STR_PACKAGE_DESCRIPTION #language en-US "This Package Sophgo RISC-V SG2042 platform modules and libraries." diff --git a/Platform/Sophgo/SG2042Pkg/SG2042PkgExtra.uni b/Platform/Sophgo/SG2042Pkg/SG2042PkgExtra.uni new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/Sophgo/SG2042Pkg/SG2042PkgExtra.uni @@ -XXX,XX +XXX,XX @@ +// /** @file +// SiFive U5 Series Package Localized Strings and Content. +// +// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR> +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_PROPERTIES_PACKAGE_NAME +#language en-US +"SG2042 platform package" -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#108217): https://edk2.groups.io/g/devel/message/108217 Mute This Topic: https://groups.io/mt/101084029/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=- From: caiyuqing379 <202235273@mail.sdu.edu.cn> Add a readme file which provides information regarding how to build and test EDK2 on Sophgo SG2042 platform. And add a about file which provides the details of Sophgo SG2042 EVB Board and SG2042 EDK2 design and the boot process. Signed-off-by: caiyuqing379 <202235273@mail.sdu.edu.cn> Co-authored-by: USER0FISH <libing1202@outlook.com> Cc: dahogn <dahogn@hotmail.com> Cc: meng-cz <mengcz1126@gmail.com> Cc: yli147 <yong.li@intel.com> Cc: ChaiEvan <evan.chai@intel.com> Cc: Sunil V L <sunilvl@ventanamicro.com> --- .../Sophgo/SG2042Pkg/About_Sophgo_platform.md | 39 +++++++ .../Documents/Media/EDK2_SDU_Programme.png | Bin 0 -> 59830 bytes .../SG2042Pkg/Documents/Media/SG2042_CPU.png | Bin 0 -> 806062 bytes .../Documents/Media/Sophgo_SG2042_EVB.png | Bin 0 -> 1445528 bytes Platform/Sophgo/SG2042Pkg/Maintainers.md | 107 ++++++++++++++++++ Platform/Sophgo/SG2042Pkg/Readme.md | 79 +++++++++++++ 6 files changed, 225 insertions(+) create mode 100644 Platform/Sophgo/SG2042Pkg/About_Sophgo_platform.md create mode 100644 Platform/Sophgo/SG2042Pkg/Documents/Media/EDK2_SDU_Programme.png create mode 100644 Platform/Sophgo/SG2042Pkg/Documents/Media/SG2042_CPU.png create mode 100644 Platform/Sophgo/SG2042Pkg/Documents/Media/Sophgo_SG2042_EVB.png create mode 100644 Platform/Sophgo/SG2042Pkg/Maintainers.md create mode 100644 Platform/Sophgo/SG2042Pkg/Readme.md diff --git a/Platform/Sophgo/SG2042Pkg/About_Sophgo_platform.md b/Platform/Sophgo/SG2042Pkg/About_Sophgo_platform.md new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/Platform/Sophgo/SG2042Pkg/About_Sophgo_platform.md @@ -XXX,XX +XXX,XX @@ +# Sophogo SG2042 EDK2 RISC-V Platform Project +## Sophgo SG2042 Platform +The development work for this project was carried out around the Sophgo SG2042 EVB development board. +The deployment of EDK2 was completed on the EVB test version. Below is the external appearance display of the EVB version. + + +SG2042 is a server processor based on the RISC-V architecture.It has 64 RISC-V cores and supports up to 2-way SG2042 interconnectivity. +Each SG2042 CPU can be configured with a maximum of 4 DIMM memory slots (RDIMM & UDIMM), supporting a maximum memory capacity of 256GB. It also supports a maximum of 32 PCIe 4.0 channels. + + +## SG2042 EDK2 RISC-V Design and the Boot Processes +The SG2042 RISC-V EDK2 project is developed based on the original Sophgo SG2042 project.SG2042 RISC-V edk2 is designed and optimized based on the edk2 startup phase. The startup process can be roughly divided into the following stages:**ZSBL+FSBL+OpenSBI+EDK2+GRUB2+OS**.The design diagram and start-up process are shown in the figure below. + +**SG2042 RISC-V EDK2 startup flowchart** + + +**ZSBL Phase** +ZSBL is the first stage of chip initialization, Code provided by Sophgo.the main work is to initialize DDR. +**FSBL Phase** +**Note:** The FSBL here corresponds to the ZSBL stage code provided by Sophgo. +The ZSBL stage works for the following: +1. Initialize the serial port of the ZSBL stage for DEBUG. +2. Establish a memory mapping table for initializing and configuring the memory management of the operating system or firmware. +3. Initialization of some CPU functions. + +**OpenSBI Phase** +OpenSBI provides the conditions for platform initialization of SG2042, which runs as an independent firmware and an environment of an initialization link before edk2, which exists in the form of FW_PAYLOAD, which initializes the system in M-mode and initializes some functions of SG2042 , and put the subsequent edk2 operating environment in S-mode. +**PrePI Phase** +The PrePI phase builds some HOBs on Memory, CPU, FV, Stack and processor smbios information, eventually loading the DXE Core and transferring control. +**DXE Phase** +edk2 DXE OpenSBI protocol provides the unified interface for all DXE drivers to invoke SBI services，the DXE stage mainly adds the SG2042 SD card reading driver to read the contents of the SD card. +**BDS Phase** +The BDS stage runs under S-mode,The implementation of the RISC-V edk2 port in the BDS stage is executed with the PcdDxeCorePrivilegeMode PCD configuration permission, because OpenSBI converts the mode to S-mode, when BDS hands over the power to the operating system, it must be S-mode, avoiding another mode switch. +**TSL Phase** +The work at this stage is mainly to use edk2 Shell to boot and start the GRUB2 program code in the SD card, and use GRUB to load different OS operating systems in the partition. +**RT Phase** +No work done. +**AL Phase** +No work done. diff --git a/Platform/Sophgo/SG2042Pkg/Documents/Media/EDK2_SDU_Programme.png b/Platform/Sophgo/SG2042Pkg/Documents/Media/EDK2_SDU_Programme.png new file mode 100644 index XXXXXXX..XXXXXXX GIT binary patch literal 59830 zcmeFZby!qu+cv%s6%|lH6r?32lrG7^pd=L#rIiK&ksM;c2BeXel5Rn|1|_9?qz0vH zKys*o-@VZNKF{-h@A3QR`|CT7cO83g7-rVJ?zrMS&+D4)r=g}meunl81VQ9Vig)fq z(5XfUBBnic68t5=!=xAdIQ>lVks}11t%v_5YPQcbg&<}~>CR0pw~tF>9_6OaNRC}s zT#ZK`kLZ~(X4g==dz8F}bCW5@!Wxp!(gw<yP@V{@pm$gM{oI%`JjTM@1wSQ@4D$_% z^Rs+HmZJ9Ltx&~d^M(r|0!^tD6#Vi}kJH-AzG}(i+bim1a@ow+_0S&3UeqmFSVtzH z+%c84B~@6gN8aw>N>r*9EtufZrNJR&M*YtVsQxMy@!uD+ICx2aE)B_B0{{HpAEZI{ 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