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Mon, 22 May 2023 09:29:03 +0000 X-Received: from SATLEXMB08.amd.com (10.181.40.132) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 22 May 2023 04:29:02 -0500 X-Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB08.amd.com (10.181.40.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 22 May 2023 02:29:02 -0700 X-Received: from BLR-LAB-SFW01.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Mon, 22 May 2023 04:29:01 -0500 From: "Abdul Lateef Attar via groups.io" To: CC: Abdul Lateef Attar , Abner Chang Subject: [edk2-devel] [PATCH v2 1/2] AMD/AmdMinBoardPkg: Implements PCI hotplug init protocol Date: Mon, 22 May 2023 14:58:50 +0530 Message-ID: In-Reply-To: References: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT088:EE_|BL0PR12MB5009:EE_ X-MS-Office365-Filtering-Correlation-Id: f5f14596-4377-449a-5f5e-08db5aa6fbbd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Message-Info: NPTenKe5xBcL7oTNArAdhRnZDZzQGiYi2Hr2QPRuehT0IVAFtlDYec0TA0hyyYz5XUSgBFwD3IxO//6Xdy8Cri8M1Arql7cywbsi+7d7szGP90VitaRFD0oX2eilHIgMS67QgrsW5oXjrgcuS/pvSperV13BNeY/16d6S028JWq/ffgGATeao+afCyz7U+UsrExg3BulgGEfWb6/8wqeAg+vGlVV3iXKS5FC79I6OsfogG3tFadtKiLbdN9u0s5YYD/FE+AZks8uz/cqWPnAVeeWX3meNzq2doGGUqM0OxoSCuSUjYFkC1VtT0Cygx/fGqOIPogKPHl2fsK1psgoiQfUE6tCWblv4JcWyLVxUzLomQaMp3XjVts9aKuP0KXF3rkdHtWOFrSCi+KDxIZYEAUvHuT0bS7Fv+iZQ3NXymT8ByDlaihjVqjoV4dNnn8ylFbiJxUUAiE115fLZT3dd6kqsN68hOxGl1djkgYiYNaefOI5yK/HMiKJ6NeKU/G69e1ZGwRgGyTIg6AwZq6LacceXSgmY6pTvuVhGS4uNWdp/Kh5KqISlmzkQfTJj5P1O75OS+fzSeH4Cii0MbzyrO4MEcvn/nKU6iCBEM6X89Fzw/LnsDnEEiAqFQfAIdylvi6yQrgMr2SR0mOiuab30gjUa4ulrdli1N0u+Aqs76WeeAIr45fhdwaxghz6dwpxEjwDA2PbSfuvHXZAbyxEkY6+EtaJpJ+NLCPMt/ysk2IXYXZyaxgwtoKapRalQ9msy7b2hD+LW1Q6l7aRoHP3apzH1CtpSq2O1wFrwTF/guo= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 May 2023 09:29:03.6213 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f5f14596-4377-449a-5f5e-08db5aa6fbbd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT088.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB5009 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abdattar@amd.com X-Gm-Message-State: gEgyI3Z3zgPXXHj1PvELtFBqx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1684747749; bh=LZDNZA5mhGT+nM7RDFSX4OOghKci8Jno2Db/BSZ710I=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=CFYuv1VHLlm1Uxgbbos+0vNrHXc2JikA9UgZE9QlyQrIlM+WaNKzZEFWGmLzFKDDMwi +IE+9chN1ECaT+wShWk92bGPkceYFC/x1HuI07QUVTmoOAOb7OxegPsC2DtfP7NNQeKBy FyDkuEKt5FDoxmlsT4fYmWJivvCXOwCPO4A= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1684747751519100007 Content-Type: text/plain; charset="utf-8" From: Abdul Lateef Attar Implements PCI hotplug init protocol. Adds resources padding based on PCD values. Cc: Abner Chang Signed-off-by: Abdul Lateef Attar Reviewed-by: Abner Chang --- .../AMD/AmdMinBoardPkg/AmdMinBoardPkg.dec | 16 + .../AMD/AmdMinBoardPkg/AmdMinBoardPkg.dsc | 14 +- .../PciHotPlug/PciHotPlugInit.inf | 39 +++ .../PciHotPlug/PciHotPlugInit.c | 331 ++++++++++++++++++ 4 files changed, 399 insertions(+), 1 deletion(-) create mode 100755 Platform/AMD/AmdMinBoardPkg/PciHotPlug/PciHotPlugInit.i= nf create mode 100755 Platform/AMD/AmdMinBoardPkg/PciHotPlug/PciHotPlugInit.c diff --git a/Platform/AMD/AmdMinBoardPkg/AmdMinBoardPkg.dec b/Platform/AMD/= AmdMinBoardPkg/AmdMinBoardPkg.dec index e37b02c4cf5a..65ba08545021 100644 --- a/Platform/AMD/AmdMinBoardPkg/AmdMinBoardPkg.dec +++ b/Platform/AMD/AmdMinBoardPkg/AmdMinBoardPkg.dec @@ -17,3 +17,19 @@ [Defines] PACKAGE_GUID =3D 44F9D761-9ECB-43DD-A5AC-177E5048701B PACKAGE_VERSION =3D 0.1 =20 +[Guids] + gAmdMinBoardPkgTokenSpaceGuid =3D {0xd4d23d79, 0x73bf, 0x460a, {0xa1, 0= xc7, 0x85, 0xa3, 0xca, 0x71, 0xb9, 0x4c}} + +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] + # + # PCI HotPlug Resource Padding + # + # PCI bus padding, number of bus to reserve, default 2 bus + gAmdMinBoardPkgTokenSpaceGuid.PcdPciHotPlugResourcePadBus|2|UINT8|0x1000= 0003 + # IO Resource padding in bytes, default 4KB + gAmdMinBoardPkgTokenSpaceGuid.PcdPciHotPlugResourcePadIo|0x00001000|UINT= 32|0x10000000 + # Non-PreFetch Memory padding in bytes, default 1MB + gAmdMinBoardPkgTokenSpaceGuid.PcdPciHotPlugResourcePadMem|0x00100000|UIN= T32|0x10000002 + # PreFetch Memory padding in bytes, default 2MB + gAmdMinBoardPkgTokenSpaceGuid.PcdPciHotPlugResourcePadPMem|0x00200000|UI= NT32|0x10000001 + diff --git a/Platform/AMD/AmdMinBoardPkg/AmdMinBoardPkg.dsc b/Platform/AMD/= AmdMinBoardPkg/AmdMinBoardPkg.dsc index 273cd74f7842..1a8407250c56 100644 --- a/Platform/AMD/AmdMinBoardPkg/AmdMinBoardPkg.dsc +++ b/Platform/AMD/AmdMinBoardPkg/AmdMinBoardPkg.dsc @@ -9,7 +9,7 @@ =20 [Defines] DSC_SPECIFICATION =3D 1.30 - PLATFORM_GUID =3D 88F8A9AE-2FA0-4D58-A6F9-05F635C05F4E + PLATFORM_GUID =3D 939B559B-269B-4B8F-9637-44DF6575C1E2 PLATFORM_NAME =3D AmdMinBoardPkg PLATFORM_VERSION =3D 0.1 OUTPUT_DIRECTORY =3D Build/$(PLATFORM_NAME) @@ -25,6 +25,16 @@ [Packages] [LibraryClasses] SpcrDeviceLib|AmdMinBoardPkg/Library/SpcrDeviceLib/SpcrDeviceLib.inf =20 +[LibraryClasses.common] + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + RegisterFilterLib|MdePkg/Library/RegisterFilterLibNull/RegisterFilterLib= Null.inf + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo= tServicesTableLib.inf + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntry= Point.inf + [LibraryClasses.common.PEIM] SetCacheMtrrLib|AmdMinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.i= nf =20 @@ -34,3 +44,5 @@ [Components] [Components.IA32] AmdMinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf =20 +[Components.X64] + AmdMinBoardPkg/PciHotPlug/PciHotPlugInit.inf diff --git a/Platform/AMD/AmdMinBoardPkg/PciHotPlug/PciHotPlugInit.inf b/Pl= atform/AMD/AmdMinBoardPkg/PciHotPlug/PciHotPlugInit.inf new file mode 100755 index 000000000000..44564df38718 --- /dev/null +++ b/Platform/AMD/AmdMinBoardPkg/PciHotPlug/PciHotPlugInit.inf @@ -0,0 +1,39 @@ +## @file +# This driver implements EFI_PCI_HOT_PLUG_INIT_PROTOCOL. +# Adds resource padding information, for PCIe hotplug purposes. +# +# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved +# SPDX-License-Identifier: BSD-2-Clause-Patent ## + +[Defines] + INF_VERSION =3D 1.29 + BASE_NAME =3D PciHotPlugInit + FILE_GUID =3D 85F78A6D-6438-4BCC-B796-759A48D00C72 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 0.1 + ENTRY_POINT =3D PciHotPlugInitialize + +[Sources] + PciHotPlugInit.c + +[Packages] + AmdMinBoardPkg/AmdMinBoardPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + MemoryAllocationLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[Protocols] + gEfiPciHotPlugInitProtocolGuid + +[Pcd] + gAmdMinBoardPkgTokenSpaceGuid.PcdPciHotPlugResourcePadBus + gAmdMinBoardPkgTokenSpaceGuid.PcdPciHotPlugResourcePadIo + gAmdMinBoardPkgTokenSpaceGuid.PcdPciHotPlugResourcePadMem + gAmdMinBoardPkgTokenSpaceGuid.PcdPciHotPlugResourcePadPMem + +[Depex] + TRUE diff --git a/Platform/AMD/AmdMinBoardPkg/PciHotPlug/PciHotPlugInit.c b/Plat= form/AMD/AmdMinBoardPkg/PciHotPlug/PciHotPlugInit.c new file mode 100755 index 000000000000..a26ca16741b8 --- /dev/null +++ b/Platform/AMD/AmdMinBoardPkg/PciHotPlug/PciHotPlugInit.c @@ -0,0 +1,331 @@ +/** @file + This file declares EFI PCI Hot Plug Init Protocol. + + This protocol provides the necessary functionality to initialize the Hot= Plug + Controllers (HPCs) and the buses that they control. This protocol also p= rovides + information regarding resource padding. + + @par Note: + This source has the reference of OVMF PciHotPluginit.c and Intel platf= orm PciHotPlug.c. + + This protocol is required only on platforms that support one or more P= CI Hot + Plug* slots or CardBus sockets. + + The EFI_PCI_HOT_PLUG_INIT_PROTOCOL provides a mechanism for the PCI bus = enumerator + to properly initialize the HPCs and CardBus sockets that require initial= ization. + The HPC initialization takes place before the PCI enumeration process is= complete. + There cannot be more than one instance of this protocol in a system. Thi= s protocol + is installed on its own separate handle. + + Because the system may include multiple HPCs, one instance of this proto= col + should represent all of them. The protocol functions use the device path= of + the HPC to identify the HPC. When the PCI bus enumerator finds a root HP= C, it + will call EFI_PCI_HOT_PLUG_INIT_PROTOCOL.InitializeRootHpc(). If Initial= izeRootHpc() + is unable to initialize a root HPC, the PCI enumerator will ignore that = root HPC + and continue the enumeration process. If the HPC is not initialized, the= devices + that it controls may not be initialized, and no resource padding will be= provided. + + From the standpoint of the PCI bus enumerator, HPCs are divided into the= following + two classes: + + - Root HPC: + These HPCs must be initialized by calling InitializeRootHpc() duri= ng the + enumeration process. These HPCs will also require resource padding= . The + platform code must have a priori knowledge of these devices and mu= st know + how to initialize them. There may not be any way to access their P= CI + configuration space before the PCI enumerator programs all the ups= tream + bridges and thus enables the path to these devices. The PCI bus en= umerator + is responsible for determining the PCI bus address of the HPC befo= re it + calls InitializeRootHpc(). + - Nonroot HPC: + These HPCs will not need explicit initialization during enumeratio= n process. + These HPCs will require resource padding. The platform code does n= ot have + to have a priori knowledge of these devices. + + Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+ Copyright (C) 2016, Red Hat, Inc.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is defined in UEFI Platform Initialization Specification 1= .2 + Volume 5: Standards + +**/ + +#include +#include +#include +#include +#include + +// +// The protocol interface this driver produces. +// +STATIC EFI_PCI_HOT_PLUG_INIT_PROTOCOL mPciHotPlugInit; + +/** + Returns a list of root Hot Plug Controllers (HPCs) that require initiali= zation + during the boot process. + + This procedure returns a list of root HPCs. The PCI bus driver must init= ialize + these controllers during the boot process. The PCI bus driver may or may= not be + able to detect these HPCs. If the platform includes a PCI-to-CardBus bri= dge, it + can be included in this list if it requires initialization. The HpcList= must be + self consistent. An HPC cannot control any of its parent buses. Only one= HPC can + control a PCI bus. Because this list includes only root HPCs, no HPC in = the list + can be a child of another HPC. This policy must be enforced by the + EFI_PCI_HOT_PLUG_INIT_PROTOCOL. The PCI bus driver may not check for s= uch + invalid conditions. The callee allocates the buffer HpcList + + @param[in] This Pointer to the EFI_PCI_HOT_PLUG_INIT_PROTOCOL ins= tance. + @param[out] HpcCount The number of root HPCs that were returned. + @param[out] HpcList The list of root HPCs. HpcCount defines the numbe= r of + elements in this list. + + @retval EFI_SUCCESS HpcList was returned. + @retval EFI_INVALID_PARAMETER HpcCount is NULL or HpcList is NULL. + +**/ +EFI_STATUS +EFIAPI +GetRootHpcList ( + IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This, + OUT UINTN *HpcCount, + OUT EFI_HPC_LOCATION **HpcList + ) +{ + if ((HpcCount =3D=3D NULL) || (HpcList =3D=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + // + // Platform BIOS not doing any extra/special HPC initialization + // Hence returning the HpcCount as zero and HpcList as NULL + // + *HpcCount =3D 0; + *HpcList =3D NULL; + + return EFI_SUCCESS; +} + +/** + Initializes one root Hot Plug Controller (HPC). This process may causes + initialization of its subordinate buses. + + This function initializes the specified HPC. At the end of initializatio= n, + the hot-plug slots or sockets (controlled by this HPC) are powered and a= re + connected to the bus. All the necessary registers in the HPC are set up.= For + a Standard (PCI) Hot Plug Controller (SHPC), the registers that must be = set + up are defined in the PCI Standard Hot Plug Controller and Subsystem + Specification. + + @param[in] This Pointer to the EFI_PCI_HOT_PLUG_INIT_PROTOCO= L instance. + @param[in] HpcDevicePath The device path to the HPC that is being ini= tialized. + @param[in] HpcPciAddress The address of the HPC function on the PCI b= us. + @param[in] Event The event that should be signaled when the H= PC + initialization is complete. Set to NULL if = the + caller wants to wait until the entire initia= lization + process is complete. + @param[out] HpcState The state of the HPC hardware. The state is + EFI_HPC_STATE_INITIALIZED or EFI_HPC_STATE_E= NABLED. + + @retval EFI_UNSUPPORTED This instance of EFI_PCI_HOT_PLUG_INIT_P= ROTOCOL + does not support the specified HPC. + @retval EFI_INVALID_PARAMETER HpcState is NULL. + +**/ +EFI_STATUS +EFIAPI +InitializeRootHpc ( + IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This, + IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath, + IN UINT64 HpcPciAddress, + IN EFI_EVENT Event, OPTIONAL + OUT EFI_HPC_STATE *HpcState + ) +{ + if (HpcState =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + // + // HPC is initialized by respective platform PI modules. + // Hence no extra initialization required. + // + return EFI_UNSUPPORTED; +} + +/** + Returns the resource padding that is required by the PCI bus that is con= trolled + by the specified Hot Plug Controller (HPC). + + This function returns the resource padding that is required by the PCI b= us that + is controlled by the specified HPC. This member function is called for a= ll the + root HPCs and nonroot HPCs that are detected by the PCI bus enumerator. = This + function will be called before PCI resource allocation is completed. Thi= s function + must be called after all the root HPCs, with the possible exception of a + PCI-to-CardBus bridge, have completed initialization. + + @param[in] This Pointer to the EFI_PCI_HOT_PLUG_INIT_PROTOCO= L instance. + @param[in] HpcDevicePath The device path to the HPC. + @param[in] HpcPciAddress The address of the HPC function on the PCI b= us. + @param[in] HpcState The state of the HPC hardware. + @param[out] Padding The amount of resource padding that is requi= red by the + PCI bus under the control of the specified H= PC. + @param[out] Attributes Describes how padding is accounted for. The = padding + is returned in the form of ACPI 2.0 resource= descriptors. + + @retval EFI_SUCCESS The resource padding was successfully re= turned. + @retval EFI_INVALID_PARAMETER HpcState or Padding or Attributes is NUL= L. + @retval EFI_OUT_OF_RESOURCES ACPI 2.0 resource descriptors for Padding + cannot be allocated due to insufficient = resources. + +**/ +EFI_STATUS +EFIAPI +GetResourcePadding ( + IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This, + IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath, + IN UINT64 HpcPciAddress, + OUT EFI_HPC_STATE *HpcState, + OUT VOID **Padding, + OUT EFI_HPC_PADDING_ATTRIBUTES *Attributes + ) +{ + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *PaddingResource; + + if ((HpcState =3D=3D NULL) || (Padding =3D=3D NULL) || (Attributes =3D= =3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + // + // Need total 5 resources + // 1 - IO resource + // 2 - Mem resource + // 3 - PMem resource + // 4 - Bus resource + // 5 - end tag resource + PaddingResource =3D AllocateZeroPool (4 * sizeof (EFI_ACPI_ADDRESS_SPACE= _DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)); + if (PaddingResource =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + *Padding =3D (VOID *)PaddingResource; + + // + // Padding for bus + // + *Attributes =3D EfiPaddingPciBus; + + PaddingResource->Desc =3D ACPI_ADDRESS_SPACE_DESCRIPTOR; + PaddingResource->Len =3D (UINT16)( + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPT= OR) - + OFFSET_OF ( + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR, + ResType + ) + ); + PaddingResource->ResType =3D ACPI_ADDRESS_SPACE_TYPE_BUS; + PaddingResource->GenFlag =3D 0x0; + PaddingResource->SpecificFlag =3D 0; + PaddingResource->AddrRangeMin =3D 0; + PaddingResource->AddrRangeMax =3D 0; + PaddingResource->AddrLen =3D PcdGet8 (PcdPciHotPlugResourcePadBus); + + // + // Padding for non-prefetchable memory + // + PaddingResource++; + PaddingResource->Desc =3D ACPI_ADDRESS_SPACE_DESCRIPTOR; + PaddingResource->Len =3D (UINT16)( + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPT= OR) - + OFFSET_OF ( + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR, + ResType + ) + ); + PaddingResource->ResType =3D ACPI_ADDRESS_SPACE_TYPE_MEM; + PaddingResource->GenFlag =3D 0x0; + PaddingResource->AddrSpaceGranularity =3D 32; + PaddingResource->SpecificFlag =3D EFI_ACPI_MEMORY_RESOURCE_SPECI= FIC_FLAG_NON_CACHEABLE; + PaddingResource->AddrRangeMin =3D 0; + PaddingResource->AddrLen =3D (UINT64)PcdGet32 (PcdPciHotPlu= gResourcePadMem); + PaddingResource->AddrRangeMax =3D PaddingResource->AddrLen - 1; + + // + // Padding for prefetchable memory + // + PaddingResource++; + PaddingResource->Desc =3D ACPI_ADDRESS_SPACE_DESCRIPTOR; + PaddingResource->Len =3D (UINT16)( + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPT= OR) - + OFFSET_OF ( + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR, + ResType + ) + ); + PaddingResource->ResType =3D ACPI_ADDRESS_SPACE_TYPE_MEM; + PaddingResource->GenFlag =3D 0x0; + PaddingResource->AddrSpaceGranularity =3D 32; + PaddingResource->SpecificFlag =3D EFI_ACPI_MEMORY_RESOURCE_SPECI= FIC_FLAG_CACHEABLE_PREFETCHABLE; + PaddingResource->AddrLen =3D (UINT64)PcdGet32 (PcdPciHotPlu= gResourcePadPMem); + PaddingResource->AddrRangeMax =3D PaddingResource->AddrLen - 1; + + // + // Padding for I/O + // + PaddingResource++; + PaddingResource->Desc =3D ACPI_ADDRESS_SPACE_DESCRIPTOR; + PaddingResource->Len =3D (UINT16)( + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPT= OR) - + OFFSET_OF ( + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR, + ResType + ) + ); + PaddingResource->ResType =3D ACPI_ADDRESS_SPACE_TYPE_IO; + PaddingResource->GenFlag =3D 0x0; + PaddingResource->SpecificFlag =3D 0; + PaddingResource->AddrRangeMin =3D 0; + PaddingResource->AddrLen =3D (UINT64)PcdGet32 (PcdPciHotPlugResourc= ePadIo); + PaddingResource->AddrRangeMax =3D PaddingResource->AddrLen - 1; + + // + // Terminate the entries. + // + PaddingResource++; + ((EFI_ACPI_END_TAG_DESCRIPTOR *)PaddingResource)->Desc =3D ACPI_END_= TAG_DESCRIPTOR; + ((EFI_ACPI_END_TAG_DESCRIPTOR *)PaddingResource)->Checksum =3D 0x0; + + *HpcState =3D EFI_HPC_STATE_INITIALIZED | EFI_HPC_STATE_ENABLED; + + return EFI_SUCCESS; +} + +/** + Entry point for this driver. + + @param[in] ImageHandle Image handle of this driver. + @param[in] SystemTable Pointer to SystemTable. + + @retval EFI_SUCCESS Driver has loaded successfully. + @return Error codes from lower level functions. + +**/ +EFI_STATUS +EFIAPI +PciHotPlugInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + mPciHotPlugInit.GetRootHpcList =3D GetRootHpcList; + mPciHotPlugInit.InitializeRootHpc =3D InitializeRootHpc; + mPciHotPlugInit.GetResourcePadding =3D GetResourcePadding; + return gBS->InstallMultipleProtocolInterfaces ( + &ImageHandle, + &gEfiPciHotPlugInitProtocolGuid, + &mPciHotPlugInit, + NULL + ); +} --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Mon, 22 May 2023 04:29:03 -0500 From: "Abdul Lateef Attar via groups.io" To: CC: Abdul Lateef Attar , Abner Chang Subject: [edk2-devel] [PATCH v2 2/2] AMD/AmdMinBoardkPkg: Implements PeiReportFvLib Library Date: Mon, 22 May 2023 14:58:51 +0530 Message-ID: <19efba7e1a2883cbc9607c81d018d08c2ea734a8.1684747555.git.abdattar@amd.com> In-Reply-To: References: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT088:EE_|CH2PR12MB4905:EE_ X-MS-Office365-Filtering-Correlation-Id: e4f28d77-3f42-480a-524d-08db5aa6fdc0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Message-Info: T1nd6ZFDeeR37i3nTFh4pO7bytg1zFWD/X/iS+N83QVzbWUxqd5Ngn1fpJpK3gXLALZlWl2rBeg45N/mMdpKzlok0pMQXCNS7DshI1FuqXc1oqGZHgSiNFrymZteOEFf0RMZXHOniy6KW5wWKUSC/lSXe/SNNd9yCGdN67H8dvj+JgdSTq9mi1ipzWNm1ScZvtz1q4GDIaZKWHyY8r9VMGzCWKaeFNrQMvt/XwSnt31sZP9tjkz/tmRwzzzTGTTnNiLsVSbSMyjDhz7HxlaqdbbVeyJ5Y4OoxtuxMJ/UUrOmtKJJhbSnWVo2yoL8cqXjALpvptM5VemNrHk64Zf8b93fv+XxFbkcSgielEe49+V4WFbTf+WkkGvwlcuhY//YLPDmzisCgwbroLXhVjt/5+HEq//1RLv4Fe0Ex81ByFhW8Vo/+yGHBpK3nN77MDPJQnglkdrH4oBJxVvwk6CY2TNtv0/Nak0pck8NPOYsDssFhiOtUaU9XZECIpiktWfIW0Xf/yhDRcvpoUOyf3+3SYtRNjTweOTOnnTYtZqmScHJW1ipiBt1JWFdIm5ee9Fp8rekukpn/kHJzqxcoXKdcB8Z6Jk7dBOINlj8IEjcr7cv1wNcqrISrT18pc5ng7gkEdNXfXkk1AY9eLmuk5yXgka/tNgJmLTy8DZ2btbd369iHSmhq57U/40a4o9ewKjVhaweCVyclauQ0H55ZYkBCPBkeFFQ27qQrZfGQZyM1pk1IIPurRwjffaIbVGpyRo6yfh73tdkgi0Cm4ZotUlPgA== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 May 2023 09:29:06.9961 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e4f28d77-3f42-480a-524d-08db5aa6fdc0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT088.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4905 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abdattar@amd.com X-Gm-Message-State: WPpIKatk5CFR1H7i5AYHKqWUx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1684747751; bh=vRxHAglEJASFowNewqSbGzaybdso9KD4FbjkofMB3eg=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=nr7WnpaiIAbzn0sMvESpm8UzouP6yx0Zn+ncCvoSVjd85zjZZYK7eqZ3LJKxPm8Ko55 aRfMWnmhHDoSzlgIpOmWVwwETkLzBEDulU9Q1qjbDt20PfzezFMiQ70SF4coC1wZ+14e3 TtT70surtjL+G4y2DCKhk4ADhLfUv61xFJQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1684747753754100011 Content-Type: text/plain; charset="utf-8" Customize PeiReportFvLib library for AMD platforms by adding below changes. Installs Advanced Security FV. Adds facility to install FV above 4GB address space. Cc: Abner Chang Signed-off-by: Abdul Lateef Attar Reviewed-by: Abner Chang --- .../AMD/AmdMinBoardPkg/AmdMinBoardPkg.dec | 8 + .../AMD/AmdMinBoardPkg/AmdMinBoardPkg.dsc | 2 + .../Library/PeiReportFvLib/PeiReportFvLib.inf | 57 +++++ .../Library/PeiReportFvLib/PeiReportFvLib.c | 239 ++++++++++++++++++ 4 files changed, 306 insertions(+) create mode 100644 Platform/AMD/AmdMinBoardPkg/Library/PeiReportFvLib/PeiR= eportFvLib.inf create mode 100644 Platform/AMD/AmdMinBoardPkg/Library/PeiReportFvLib/PeiR= eportFvLib.c diff --git a/Platform/AMD/AmdMinBoardPkg/AmdMinBoardPkg.dec b/Platform/AMD/= AmdMinBoardPkg/AmdMinBoardPkg.dec index 65ba08545021..03d1d77c34eb 100644 --- a/Platform/AMD/AmdMinBoardPkg/AmdMinBoardPkg.dec +++ b/Platform/AMD/AmdMinBoardPkg/AmdMinBoardPkg.dec @@ -33,3 +33,11 @@ [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, P= cdsDynamicEx] # PreFetch Memory padding in bytes, default 2MB gAmdMinBoardPkgTokenSpaceGuid.PcdPciHotPlugResourcePadPMem|0x00200000|UI= NT32|0x10000001 =20 + # PCDs to support loading of FV above 4GB address space + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedBase |0x00= 00000000000000|UINT64|0x10000004 + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvOsBootBase |0x00= 00000000000000|UINT64|0x10000005 + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvUefiBootBase |0x00= 00000000000000|UINT64|0x10000006 + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityBase |0x00= 00000000000000|UINT64|0x10000007 + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize |0x00= 000000|UINT32|0x10000008 + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityOffset |0x00= 000000|UINT32|0x10000009 + diff --git a/Platform/AMD/AmdMinBoardPkg/AmdMinBoardPkg.dsc b/Platform/AMD/= AmdMinBoardPkg/AmdMinBoardPkg.dsc index 1a8407250c56..be33089a45ef 100644 --- a/Platform/AMD/AmdMinBoardPkg/AmdMinBoardPkg.dsc +++ b/Platform/AMD/AmdMinBoardPkg/AmdMinBoardPkg.dsc @@ -24,6 +24,7 @@ [Packages] =20 [LibraryClasses] SpcrDeviceLib|AmdMinBoardPkg/Library/SpcrDeviceLib/SpcrDeviceLib.inf + ReportFvLib|AmdMinBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.inf =20 [LibraryClasses.common] BaseLib|MdePkg/Library/BaseLib/BaseLib.inf @@ -43,6 +44,7 @@ [Components] =20 [Components.IA32] AmdMinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf + AmdMinBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.inf =20 [Components.X64] AmdMinBoardPkg/PciHotPlug/PciHotPlugInit.inf diff --git a/Platform/AMD/AmdMinBoardPkg/Library/PeiReportFvLib/PeiReportFv= Lib.inf b/Platform/AMD/AmdMinBoardPkg/Library/PeiReportFvLib/PeiReportFvLib= .inf new file mode 100644 index 000000000000..23ee503c42be --- /dev/null +++ b/Platform/AMD/AmdMinBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.inf @@ -0,0 +1,57 @@ +### @file +# Component information file for the Report Firmware Volume (FV) library. +# +# Copyright (c) 2018 - 2020, Intel Corporation. All rights reserved.
+# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +### + +[Defines] + INF_VERSION =3D 1.29 + BASE_NAME =3D PeiReportFvLib + FILE_GUID =3D 3C207C28-DC43-4A3A-B572-6794C77AB519 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D PEIM + LIBRARY_CLASS =3D ReportFvLib + +[LibraryClasses] + BaseMemoryLib + DebugLib + HobLib + PeiServicesLib + +[Packages] + AmdMinBoardPkg/AmdMinBoardPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + +[Sources] + PeiReportFvLib.c + +[Pcd] + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedBase ## CONSU= MES + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityBase ## CONSU= MES + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize ## CONSU= MES + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvOsBootBase ## CONSU= MES + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvUefiBootBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdBootStage ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode ## CONSU= MES diff --git a/Platform/AMD/AmdMinBoardPkg/Library/PeiReportFvLib/PeiReportFv= Lib.c b/Platform/AMD/AmdMinBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.c new file mode 100644 index 000000000000..f0b2abef611b --- /dev/null +++ b/Platform/AMD/AmdMinBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.c @@ -0,0 +1,239 @@ +/** @file + Source code file for Report Firmware Volume (FV) library for AMD platfor= ms. + + @par Note: + This source has the reference of MinPlatformPkgs's PeriReportFvLib.c m= odule. + + Copyright (c) 2018 - 2020, Intel Corporation. All rights reserved.
+ Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +VOID +ReportPreMemFv ( + VOID + ) +{ + /// + /// Note : FSP FVs except FSP-T FV are installed in IntelFsp2WrapperPkg = in Dispatch mode. + /// + if (PcdGetBool (PcdFspWrapperBootMode)) { + DEBUG ((DEBUG_INFO, "Install FlashFvFspT - 0x%x, 0x%x\n", PcdGet32 (Pc= dFlashFvFspTBase), PcdGet32 (PcdFlashFvFspTSize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)PcdGet32 (PcdFlashFvFspTBase= ))->FileSystemGuid), + (VOID *)(UINTN)PcdGet32 (PcdFlashFvFspTBase), + PcdGet32 (PcdFlashFvFspTSize), + NULL, + NULL, + 0 + ); + } + + DEBUG ((DEBUG_INFO, "Install FlashFvSecurity - 0x%x, 0x%x\n", PcdGet32 (= PcdFlashFvSecurityBase), PcdGet32 (PcdFlashFvSecuritySize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)PcdGet32 (PcdFlashFvSecurityBa= se))->FileSystemGuid), + (VOID *)(UINTN)PcdGet32 (PcdFlashFvSecurityBase), + PcdGet32 (PcdFlashFvSecuritySize), + NULL, + NULL, + 0 + ); + if (PcdGet8 (PcdBootStage) >=3D 6) { + DEBUG (( + DEBUG_INFO, + "Install FlashFvAdvancedPreMemory - 0x%x, 0x%x\n", + PcdGet32 (PcdFlashFvAdvancedPreMemoryBase), + PcdGet32 (PcdFlashFvAdvancedPreMemorySize) + )); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)PcdGet32 (PcdFlashFvAdvanced= PreMemoryBase))->FileSystemGuid), + (VOID *)(UINTN)PcdGet32 (PcdFlashFvAdvancedPreMemoryBase), + PcdGet32 (PcdFlashFvAdvancedPreMemorySize), + NULL, + NULL, + 0 + ); + } +} + +VOID +ReportPostMemFv ( + VOID + ) +{ + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; + EFI_HOB_FIRMWARE_VOLUME3 *Hob3; + EFI_HOB_FIRMWARE_VOLUME *Hob; + + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + + /// + /// Note : FSP FVs except FSP-T FV are installed in IntelFsp2WrapperPkg = in Dispatch mode. + /// + + /// + /// Build HOB for DXE + /// + if (BootMode =3D=3D BOOT_IN_RECOVERY_MODE) { + /// + /// Prepare the recovery service + /// + } else { + DEBUG ((DEBUG_INFO, "Install FlashFvPostMemory - 0x%x, 0x%x\n", PcdGet= 32 (PcdFlashFvPostMemoryBase), PcdGet32 (PcdFlashFvPostMemorySize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)PcdGet32 (PcdFlashFvPostMemo= ryBase))->FileSystemGuid), + (VOID *)(UINTN)PcdGet32 (PcdFlashFvPostMemoryBase), + PcdGet32 (PcdFlashFvPostMemorySize), + NULL, + NULL, + 0 + ); + + if (PcdGet64 (PcdAmdFlashFvUefiBootBase) >=3D BASE_4GB) { + Hob =3D NULL; + Hob3 =3D NULL; + DEBUG ((DEBUG_INFO, "Found FvUefiBoot FV above 4GB, creating FV HOBs= .\n")); + Status =3D PeiServicesCreateHob (EFI_HOB_TYPE_FV, sizeof (EFI_HOB_FI= RMWARE_VOLUME), (VOID **)&Hob); + if (!EFI_ERROR (Status)) { + Hob->BaseAddress =3D PcdGet64 (PcdAmdFlashFvUefiBootBase); + Hob->Length =3D PcdGet32 (PcdFlashFvUefiBootSize); + } + + Status =3D PeiServicesCreateHob (EFI_HOB_TYPE_FV3, sizeof (EFI_HOB_F= IRMWARE_VOLUME3), (VOID **)&Hob3); + if (!EFI_ERROR (Status)) { + Hob3->BaseAddress =3D PcdGet64 (PcdAmdFlashFvUefiBootBase= ); + Hob3->Length =3D PcdGet32 (PcdFlashFvUefiBootSize); + Hob3->AuthenticationStatus =3D 0; + Hob3->ExtractedFv =3D FALSE; + } + } else { + DEBUG ((DEBUG_INFO, "Install FlashFvUefiBoot - 0x%lx, 0x%x\n", PcdGe= t64 (PcdAmdFlashFvUefiBootBase), PcdGet32 (PcdFlashFvUefiBootSize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)PcdGet64 (PcdAmdFlashFvUef= iBootBase))->FileSystemGuid), + (VOID *)(UINTN)PcdGet64 (PcdAmdFlashFvUefiBootBase), + PcdGet32 (PcdFlashFvUefiBootSize), + NULL, + NULL, + 0 + ); + } + + if (PcdGet64 (PcdAmdFlashFvOsBootBase) >=3D BASE_4GB) { + Hob =3D NULL; + Hob3 =3D NULL; + DEBUG ((DEBUG_INFO, "Found FvOsBoot FV above 4GB, creating FV HOBs.\= n")); + Status =3D PeiServicesCreateHob (EFI_HOB_TYPE_FV, sizeof (EFI_HOB_FI= RMWARE_VOLUME), (VOID **)&Hob); + if (!EFI_ERROR (Status)) { + Hob->BaseAddress =3D PcdGet64 (PcdAmdFlashFvOsBootBase); + Hob->Length =3D PcdGet32 (PcdFlashFvOsBootSize); + } + + Status =3D PeiServicesCreateHob (EFI_HOB_TYPE_FV3, sizeof (EFI_HOB_F= IRMWARE_VOLUME3), (VOID **)&Hob3); + if (!EFI_ERROR (Status)) { + Hob3->BaseAddress =3D PcdGet64 (PcdAmdFlashFvOsBootBase); + Hob3->Length =3D PcdGet32 (PcdFlashFvOsBootSize); + Hob3->AuthenticationStatus =3D 0; + Hob3->ExtractedFv =3D FALSE; + } + } else { + DEBUG ((DEBUG_INFO, "Install FlashFvOsBoot - 0x%lx, 0x%x\n", PcdGet6= 4 (PcdAmdFlashFvOsBootBase), PcdGet32 (PcdFlashFvOsBootSize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)PcdGet64 (PcdAmdFlashFvOsB= ootBase))->FileSystemGuid), + (VOID *)(UINTN)PcdGet64 (PcdAmdFlashFvOsBootBase), + PcdGet32 (PcdFlashFvOsBootSize), + NULL, + NULL, + 0 + ); + } + + if (PcdGet8 (PcdBootStage) >=3D 6) { + if (PcdGet64 (PcdAmdFlashFvAdvancedBase) >=3D BASE_4GB) { + Hob =3D NULL; + Hob3 =3D NULL; + DEBUG ((DEBUG_INFO, "Found FvAdvanced FV above 4GB, creating FV HO= Bs.\n")); + Status =3D PeiServicesCreateHob (EFI_HOB_TYPE_FV, sizeof (EFI_HOB_= FIRMWARE_VOLUME), (VOID **)&Hob); + if (!EFI_ERROR (Status)) { + Hob->BaseAddress =3D PcdGet64 (PcdAmdFlashFvAdvancedBase); + Hob->Length =3D PcdGet32 (PcdFlashFvAdvancedSize); + } + + Status =3D PeiServicesCreateHob (EFI_HOB_TYPE_FV3, sizeof (EFI_HOB= _FIRMWARE_VOLUME3), (VOID **)&Hob3); + if (!EFI_ERROR (Status)) { + Hob3->BaseAddress =3D PcdGet64 (PcdAmdFlashFvAdvancedBa= se); + Hob3->Length =3D PcdGet32 (PcdFlashFvAdvancedSize); + Hob3->AuthenticationStatus =3D 0; + Hob3->ExtractedFv =3D FALSE; + } + } else { + DEBUG ((DEBUG_INFO, "Install FlashFvAdvanced - 0x%lx, 0x%x\n", Pcd= Get64 (PcdAmdFlashFvAdvancedBase), PcdGet32 (PcdFlashFvAdvancedSize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)PcdGet64 (PcdAmdFlashFvA= dvancedBase))->FileSystemGuid), + (VOID *)(UINTN)PcdGet64 (PcdAmdFlashFvAdvancedBase), + PcdGet32 (PcdFlashFvAdvancedSize), + NULL, + NULL, + 0 + ); + } + } + } + + if (PcdGet64 (PcdAmdFlashFvAdvancedSecurityBase) >=3D BASE_4GB) { + Hob =3D NULL; + Hob3 =3D NULL; + DEBUG ((DEBUG_INFO, "Found FvAdvancedSecurity FV above 4GB, creating F= V HOBs.\n")); + Status =3D PeiServicesCreateHob (EFI_HOB_TYPE_FV, sizeof (EFI_HOB_FIRM= WARE_VOLUME), (VOID **)&Hob); + if (!EFI_ERROR (Status)) { + Hob->BaseAddress =3D PcdGet64 (PcdAmdFlashFvAdvancedSecurityBase); + Hob->Length =3D PcdGet32 (PcdAmdFlashFvAdvancedSecuritySize); + } + + Status =3D PeiServicesCreateHob (EFI_HOB_TYPE_FV3, sizeof (EFI_HOB_FIR= MWARE_VOLUME3), (VOID **)&Hob3); + if (!EFI_ERROR (Status)) { + Hob3->BaseAddress =3D PcdGet64 (PcdAmdFlashFvAdvancedSecuri= tyBase); + Hob3->Length =3D PcdGet32 (PcdAmdFlashFvAdvancedSecuri= tySize); + Hob3->AuthenticationStatus =3D 0; + Hob3->ExtractedFv =3D FALSE; + } + } else { + DEBUG ((DEBUG_INFO, "Install FvAdvancedSecurity - 0x%lx, 0x%x\n", PcdG= et64 (PcdAmdFlashFvAdvancedSecurityBase), PcdGet32 (PcdAmdFlashFvAdvancedSe= curitySize))); + PeiServicesInstallFvInfo2Ppi ( + &(((EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)PcdGet64 (PcdAmdFlashFvAdvan= cedSecurityBase))->FileSystemGuid), + (VOID *)(UINTN)PcdGet64 (PcdAmdFlashFvAdvancedSecurityBase), + PcdGet32 (PcdAmdFlashFvAdvancedSecuritySize), + NULL, + NULL, + 0 + ); + } + + // + // Report resource HOB for flash FV + // + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_MAPPED_IO, + (EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), + (UINTN)PcdGet32 (PcdFlashAreaBaseAddress), + (UINTN)PcdGet32 (PcdFlashAreaSize) + ); + BuildMemoryAllocationHob ( + (UINTN)PcdGet32 (PcdFlashAreaBaseAddress), + (UINTN)PcdGet32 (PcdFlashAreaSize), + EfiMemoryMappedIO + ); +} --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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