From nobody Mon Apr 29 10:32:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+85971+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85971+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1642901846; cv=none; d=zohomail.com; s=zohoarc; b=QEhKlf3CJTrSUATN2sGK+RbZVDisMV5HM603MzfOeU8QNaFeEJUkWZUMVaTNtwT2MLWkuZdraw61GMYL4Dms+dHlQFcM/8+qQJtCi6Gzmvh+Q/ky9aPWEkEcDsiWYOeKyIZ6bwlVWmwAF/OOK1HT2+CtqCtaBcZzDR0JaWyLROw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1642901846; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=BKtuiqO0bdM42HkN/GBscwwLQWQHBUahXJpnmhKHjLM=; b=TDlNagSKr787MLDsvTdVr2hrmAEfWhHM9xCN8eEFJmlWxLLmpMR96ujqFLNOOpUVRn2gw8ekgUbEJX3nFwiOTBWk14qohiSvMqzE4KbkDEqqoIj8wobu1HBTKLeLaomA7XSjLPQ3xXWHwIzqm+yamWv0zSXpIJSFE3ujCsrNOtU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85971+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1642901846726916.6796213687686; Sat, 22 Jan 2022 17:37:26 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 3XsSYY1788612xeGKRuwCETs; Sat, 22 Jan 2022 17:37:26 -0800 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web10.4433.1642901844629889719 for ; Sat, 22 Jan 2022 17:37:25 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10235"; a="243454662" X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="243454662" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:37:24 -0800 X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="695032762" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.255.30.84]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:37:22 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Michael D Kinney , Liming Gao , Zhiguang Liu , Gerd Hoffmann , Jiewen Yao Subject: [edk2-devel] [PATCH V5 01/33] MdePkg: Add Tdx.h Date: Sun, 23 Jan 2022 09:36:32 +0800 Message-Id: <1182a9bbbc40ca3bb048d1329fa270b74a27bf92.1642899774.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: 7ElkT1VhjIRYUdy750a6G2RAx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1642901846; bh=uNoiQmNZlyMf7ZYja7cGMfPhwzeQ047linC5xUH7ESo=; h=Cc:Date:From:Reply-To:Subject:To; b=fJdmTGoZluxzve7kKXiCJbtesIIKEab9j/7r51yLWoCywZn0yw97T+NGv/7b17xliT4 DAYSSEuKZvGEpGz68FtGxAs7q3VMu+i6E3SzaPripPzVuX4gTQRXnPAgUfJOG3A5DEIGQ Pb1gYOYF0M8Pwi1fovsEpxQf3eOYKTQ/NvQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1642901848771100005 Content-Type: text/plain; charset="utf-8" RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 Tdx.h includes the Intel Trust Domain Extension definitions. Detailed information can be found in below document: https://software.intel.com/content/dam/develop/external/us/en/ documents/tdx-module-1eas-v0.85.039.pdf Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Gerd Hoffmann Cc: Jiewen Yao Acked-by: Gerd Hoffmann Signed-off-by: Min Xu --- MdePkg/Include/IndustryStandard/Tdx.h | 203 ++++++++++++++++++++++++++ 1 file changed, 203 insertions(+) create mode 100644 MdePkg/Include/IndustryStandard/Tdx.h diff --git a/MdePkg/Include/IndustryStandard/Tdx.h b/MdePkg/Include/Industr= yStandard/Tdx.h new file mode 100644 index 000000000000..81df1361842b --- /dev/null +++ b/MdePkg/Include/IndustryStandard/Tdx.h @@ -0,0 +1,203 @@ +/** @file + Intel Trust Domain Extension definitions + Detailed information is in below document: + https://software.intel.com/content/dam/develop/external/us/en/documents + /tdx-module-1eas-v0.85.039.pdf + + Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef MDE_PKG_TDX_H_ +#define MDE_PKG_TDX_H_ + +#define EXIT_REASON_EXTERNAL_INTERRUPT 1 +#define EXIT_REASON_TRIPLE_FAULT 2 + +#define EXIT_REASON_PENDING_INTERRUPT 7 +#define EXIT_REASON_NMI_WINDOW 8 +#define EXIT_REASON_TASK_SWITCH 9 +#define EXIT_REASON_CPUID 10 +#define EXIT_REASON_HLT 12 +#define EXIT_REASON_INVD 13 +#define EXIT_REASON_INVLPG 14 +#define EXIT_REASON_RDPMC 15 +#define EXIT_REASON_RDTSC 16 +#define EXIT_REASON_VMCALL 18 +#define EXIT_REASON_VMCLEAR 19 +#define EXIT_REASON_VMLAUNCH 20 +#define EXIT_REASON_VMPTRLD 21 +#define EXIT_REASON_VMPTRST 22 +#define EXIT_REASON_VMREAD 23 +#define EXIT_REASON_VMRESUME 24 +#define EXIT_REASON_VMWRITE 25 +#define EXIT_REASON_VMOFF 26 +#define EXIT_REASON_VMON 27 +#define EXIT_REASON_CR_ACCESS 28 +#define EXIT_REASON_DR_ACCESS 29 +#define EXIT_REASON_IO_INSTRUCTION 30 +#define EXIT_REASON_MSR_READ 31 +#define EXIT_REASON_MSR_WRITE 32 +#define EXIT_REASON_INVALID_STATE 33 +#define EXIT_REASON_MSR_LOAD_FAIL 34 +#define EXIT_REASON_MWAIT_INSTRUCTION 36 +#define EXIT_REASON_MONITOR_TRAP_FLAG 37 +#define EXIT_REASON_MONITOR_INSTRUCTION 39 +#define EXIT_REASON_PAUSE_INSTRUCTION 40 +#define EXIT_REASON_MCE_DURING_VMENTRY 41 +#define EXIT_REASON_TPR_BELOW_THRESHOLD 43 +#define EXIT_REASON_APIC_ACCESS 44 +#define EXIT_REASON_EOI_INDUCED 45 +#define EXIT_REASON_GDTR_IDTR 46 +#define EXIT_REASON_LDTR_TR 47 +#define EXIT_REASON_EPT_VIOLATION 48 +#define EXIT_REASON_EPT_MISCONFIG 49 +#define EXIT_REASON_INVEPT 50 +#define EXIT_REASON_RDTSCP 51 +#define EXIT_REASON_PREEMPTION_TIMER 52 +#define EXIT_REASON_INVVPID 53 +#define EXIT_REASON_WBINVD 54 +#define EXIT_REASON_XSETBV 55 +#define EXIT_REASON_APIC_WRITE 56 +#define EXIT_REASON_RDRAND 57 +#define EXIT_REASON_INVPCID 58 +#define EXIT_REASON_VMFUNC 59 +#define EXIT_REASON_ENCLS 60 +#define EXIT_REASON_RDSEED 61 +#define EXIT_REASON_PML_FULL 62 +#define EXIT_REASON_XSAVES 63 +#define EXIT_REASON_XRSTORS 64 + +// TDCALL API Function Completion Status Codes +#define TDX_EXIT_REASON_SUCCESS 0x0000000000000000 +#define TDX_EXIT_REASON_PAGE_ALREADY_ACCEPTED 0x00000B0A00000000 +#define TDX_EXIT_REASON_PAGE_SIZE_MISMATCH 0xC0000B0B00000000 +#define TDX_EXIT_REASON_OPERAND_INVALID 0xC000010000000000 +#define TDX_EXIT_REASON_OPERAND_BUSY 0x8000020000000000 + +// TDCALL [TDG.MEM.PAGE.ACCEPT] page size +#define TDCALL_ACCEPT_PAGE_SIZE_4K 0 +#define TDCALL_ACCEPT_PAGE_SIZE_2M 1 +#define TDCALL_ACCEPT_PAGE_SIZE_1G 2 + +#define TDCALL_TDVMCALL 0 +#define TDCALL_TDINFO 1 +#define TDCALL_TDEXTENDRTMR 2 +#define TDCALL_TDGETVEINFO 3 +#define TDCALL_TDREPORT 4 +#define TDCALL_TDSETCPUIDVE 5 +#define TDCALL_TDACCEPTPAGE 6 + +#define TDVMCALL_CPUID 0x0000a +#define TDVMCALL_HALT 0x0000c +#define TDVMCALL_IO 0x0001e +#define TDVMCALL_RDMSR 0x0001f +#define TDVMCALL_WRMSR 0x00020 +#define TDVMCALL_MMIO 0x00030 +#define TDVMCALL_PCONFIG 0x00041 + +#define TDVMCALL_GET_TDVMCALL_INFO 0x10000 +#define TDVMCALL_MAPGPA 0x10001 +#define TDVMCALL_GET_QUOTE 0x10002 +#define TDVMCALL_REPORT_FATAL_ERR 0x10003 +#define TDVMCALL_SETUP_EVENT_NOTIFY 0x10004 + +#pragma pack(1) +typedef struct { + UINT64 Data[6]; +} TDCALL_GENERIC_RETURN_DATA; + +typedef struct { + UINT64 Gpaw; + UINT64 Attributes; + UINT32 MaxVcpus; + UINT32 NumVcpus; + UINT64 Resv[3]; +} TDCALL_INFO_RETURN_DATA; + +typedef union { + UINT64 Val; + struct { + UINT32 Size : 3; + UINT32 Direction : 1; + UINT32 String : 1; + UINT32 Rep : 1; + UINT32 Encoding : 1; + UINT32 Resv : 9; + UINT32 Port : 16; + UINT32 Resv2; + } Io; +} VMX_EXIT_QUALIFICATION; + +typedef struct { + UINT32 ExitReason; + UINT32 Resv; + VMX_EXIT_QUALIFICATION ExitQualification; + UINT64 GuestLA; + UINT64 GuestPA; + UINT32 ExitInstructionLength; + UINT32 ExitInstructionInfo; + UINT32 Resv1; +} TDCALL_VEINFO_RETURN_DATA; + +typedef union { + TDCALL_GENERIC_RETURN_DATA Generic; + TDCALL_INFO_RETURN_DATA TdInfo; + TDCALL_VEINFO_RETURN_DATA VeInfo; +} TD_RETURN_DATA; + +/* data structure used in TDREPORT_STRUCT */ +typedef struct { + UINT8 Type; + UINT8 Subtype; + UINT8 Version; + UINT8 Rsvd; +} TD_REPORT_TYPE; + +typedef struct { + TD_REPORT_TYPE ReportType; + UINT8 Rsvd1[12]; + UINT8 CpuSvn[16]; + UINT8 TeeTcbInfoHash[48]; + UINT8 TeeInfoHash[48]; + UINT8 ReportData[64]; + UINT8 Rsvd2[32]; + UINT8 Mac[32]; +} REPORTMACSTRUCT; + +typedef struct { + UINT8 Seam[2]; + UINT8 Rsvd[14]; +} TEE_TCB_SVN; + +typedef struct { + UINT8 Valid[8]; + TEE_TCB_SVN TeeTcbSvn; + UINT8 Mrseam[48]; + UINT8 Mrsignerseam[48]; + UINT8 Attributes[8]; + UINT8 Rsvd[111]; +} TEE_TCB_INFO; + +typedef struct { + UINT8 Attributes[8]; + UINT8 Xfam[8]; + UINT8 Mrtd[48]; + UINT8 Mrconfigid[48]; + UINT8 Mrowner[48]; + UINT8 Mrownerconfig[48]; + UINT8 Rtmrs[4][48]; + UINT8 Rsvd[112]; +} TDINFO; + +typedef struct { + REPORTMACSTRUCT ReportMacStruct; + TEE_TCB_INFO TeeTcbInfo; + UINT8 Rsvd[17]; + TDINFO Tdinfo; +} TDREPORT_STRUCT; + +#pragma pack() + +#endif --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85971): https://edk2.groups.io/g/devel/message/85971 Mute This Topic: https://groups.io/mt/88617487/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Apr 29 10:32:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+85972+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85972+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1642901849; cv=none; d=zohomail.com; s=zohoarc; b=itZW3fT4/J+NzOjRWMWgRYtpsEzApCu49YSAEjGAUslzuOW3PqUwna7dCWAOp9sVVitzUiKVxvfJk50WFjZjzuLHUQj6cZxCvoJz5Xr1hM4up1s+r35XB8YglheZ4Jy5Wn7tMGLkhvun9JbJsKOc4m6MmPALXtf7wOPUi7LrpzI= ARC-Message-Signature: i=1; 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Sat, 22 Jan 2022 17:37:28 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10235"; a="243454686" X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="243454686" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:37:27 -0800 X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="695032783" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.255.30.84]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:37:24 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Michael D Kinney , Liming Gao , Zhiguang Liu , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann Subject: [edk2-devel] [PATCH V5 02/33] MdePkg: Introduce basic Tdx functions in BaseLib Date: Sun, 23 Jan 2022 09:36:33 +0800 Message-Id: <3ef61f1d5e4d02671a9ed1b5f54da54a4125744b.1642899774.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: vywLzM4XHOihY9ThZ81tTVTix1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1642901849; bh=YiCW0Qf2Y7u68Fb5tB7DUl30Bl1PCX9erIjsGj32YkI=; h=Cc:Date:From:Reply-To:Subject:To; b=U/PFPWFMRikoD/UA4AEuQ3lO5uxOKRyldQ3IK2oxKUaawDdUzOIgeBLXbQjNyLQ5KeU hMPq3/846OnUqQCWlD+FNyEX74yp5SfhMavzf592lX8ZX2bg42xUwBdE5mDDBmL/fWqS5 WgwiC0kFt5rxp41X61iamQNyjrhRp8QBcjQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1642901851011100001 Content-Type: text/plain; charset="utf-8" RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 Introduce basic Tdx functions in BaseLib: - TdCall () - TdVmCall () - TdIsEnabled () Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Signed-off-by: Min Xu --- MdePkg/Include/Library/BaseLib.h | 62 ++++++++++ MdePkg/Library/BaseLib/BaseLib.inf | 11 ++ MdePkg/Library/BaseLib/IntelTdxNull.c | 83 +++++++++++++ MdePkg/Library/BaseLib/X64/TdCall.nasm | 85 +++++++++++++ MdePkg/Library/BaseLib/X64/TdProbe.c | 62 ++++++++++ MdePkg/Library/BaseLib/X64/TdVmcall.nasm | 145 +++++++++++++++++++++++ 6 files changed, 448 insertions(+) create mode 100644 MdePkg/Library/BaseLib/IntelTdxNull.c create mode 100644 MdePkg/Library/BaseLib/X64/TdCall.nasm create mode 100644 MdePkg/Library/BaseLib/X64/TdProbe.c create mode 100644 MdePkg/Library/BaseLib/X64/TdVmcall.nasm diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/Base= Lib.h index 6aa0d972186e..bd762843198f 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -4759,6 +4759,68 @@ SpeculationBarrier ( VOID ); =20 +/** + The TDCALL instruction causes a VM exit to the Intel TDX module. It is + used to call guest-side Intel TDX functions, either local or a TD exit + to the host VMM, as selected by Leaf. + + @param[in] Leaf Leaf number of TDCALL instruction + @param[in] Arg1 Arg1 + @param[in] Arg2 Arg2 + @param[in] Arg3 Arg3 + @param[in,out] Results Returned result of the Leaf function + + @return EFI_SUCCESS + @return Other See individual leaf functions +**/ +UINTN +EFIAPI +TdCall ( + IN UINT64 Leaf, + IN UINT64 Arg1, + IN UINT64 Arg2, + IN UINT64 Arg3, + IN OUT VOID *Results + ); + +/** + TDVMALL is a leaf function 0 for TDCALL. It helps invoke services from t= he + host VMM to pass/receive information. + + @param[in] Leaf Number of sub-functions + @param[in] Arg1 Arg1 + @param[in] Arg2 Arg2 + @param[in] Arg3 Arg3 + @param[in] Arg4 Arg4 + @param[in,out] Results Returned result of the sub-function + + @return EFI_SUCCESS + @return Other See individual sub-functions + +**/ +UINTN +EFIAPI +TdVmCall ( + IN UINT64 Leaf, + IN UINT64 Arg1, + IN UINT64 Arg2, + IN UINT64 Arg3, + IN UINT64 Arg4, + IN OUT VOID *Results + ); + +/** + Probe if TD is enabled. + + @return TRUE TD is enabled. + @return FALSE TD is not enabled. +**/ +BOOLEAN +EFIAPI +TdIsEnabled ( + VOID + ); + #if defined (MDE_CPU_X64) // // The page size for the PVALIDATE instruction diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/Ba= seLib.inf index cebda3b210c1..1185f13204df 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -210,6 +210,7 @@ X86RdRand.c X86PatchInstruction.c X86SpeculationBarrier.c + IntelTdxNull.c =20 [Sources.X64] X64/Thunk16.nasm @@ -293,6 +294,9 @@ X64/ReadCr0.nasm| MSFT X64/ReadEflags.nasm| MSFT =20 + X64/TdCall.nasm + X64/TdVmcall.nasm + X64/TdProbe.c =20 X64/Non-existing.c Math64.c @@ -333,6 +337,7 @@ Ebc/SpeculationBarrier.c Unaligned.c Math64.c + IntelTdxNull.c =20 [Sources.ARM] Arm/InternalSwitchStack.c @@ -370,6 +375,8 @@ Arm/MemoryFence.S | GCC Arm/SpeculationBarrier.S | GCC =20 + IntelTdxNull.c + [Sources.AARCH64] Arm/InternalSwitchStack.c Arm/Unaligned.c @@ -393,6 +400,8 @@ AArch64/CpuBreakpoint.asm | MSFT AArch64/SpeculationBarrier.asm | MSFT =20 + IntelTdxNull.c + [Sources.RISCV64] Math64.c Unaligned.c @@ -409,6 +418,8 @@ RiscV64/RiscVInterrupt.S | GCC RiscV64/FlushCache.S | GCC =20 + IntelTdxNull.c + [Packages] MdePkg/MdePkg.dec =20 diff --git a/MdePkg/Library/BaseLib/IntelTdxNull.c b/MdePkg/Library/BaseLib= /IntelTdxNull.c new file mode 100644 index 000000000000..ec95470bd43e --- /dev/null +++ b/MdePkg/Library/BaseLib/IntelTdxNull.c @@ -0,0 +1,83 @@ +/** @file + + Null stub of TdxLib + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include + +/** + The TDCALL instruction causes a VM exit to the Intel TDX module. It is + used to call guest-side Intel TDX functions, either local or a TD exit + to the host VMM, as selected by Leaf. + Leaf functions are described at + + @param[in] Leaf Leaf number of TDCALL instruction + @param[in] Arg1 Arg1 + @param[in] Arg2 Arg2 + @param[in] Arg3 Arg3 + @param[in,out] Results Returned result of the Leaf function + + @return EFI_SUCCESS + @return Other See individual leaf functions +**/ +UINTN +EFIAPI +TdCall ( + IN UINT64 Leaf, + IN UINT64 Arg1, + IN UINT64 Arg2, + IN UINT64 Arg3, + IN OUT VOID *Results + ) +{ + return EFI_UNSUPPORTED; +} + +/** + TDVMALL is a leaf function 0 for TDCALL. It helps invoke services from t= he + host VMM to pass/receive information. + + @param[in] Leaf Number of sub-functions + @param[in] Arg1 Arg1 + @param[in] Arg2 Arg2 + @param[in] Arg3 Arg3 + @param[in] Arg4 Arg4 + @param[in,out] Results Returned result of the sub-function + + @return EFI_SUCCESS + @return Other See individual sub-functions + +**/ +UINTN +EFIAPI +TdVmCall ( + IN UINT64 Leaf, + IN UINT64 Arg1, + IN UINT64 Arg2, + IN UINT64 Arg3, + IN UINT64 Arg4, + IN OUT VOID *Results + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Probe if TD is enabled. + + @return TRUE TD is enabled. + @return FALSE TD is not enabled. +**/ +BOOLEAN +EFIAPI +TdIsEnabled ( + ) +{ + return FALSE; +} diff --git a/MdePkg/Library/BaseLib/X64/TdCall.nasm b/MdePkg/Library/BaseLi= b/X64/TdCall.nasm new file mode 100644 index 000000000000..e8a094b0eb3f --- /dev/null +++ b/MdePkg/Library/BaseLib/X64/TdCall.nasm @@ -0,0 +1,85 @@ +;-------------------------------------------------------------------------= ----- +;* +;* Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
+;* SPDX-License-Identifier: BSD-2-Clause-Patent +;* +;* +;-------------------------------------------------------------------------= ----- + +DEFAULT REL +SECTION .text + +%macro tdcall 0 + db 0x66,0x0f,0x01,0xcc +%endmacro + +%macro tdcall_push_regs 0 + push rbp + mov rbp, rsp + push r15 + push r14 + push r13 + push r12 + push rbx + push rsi + push rdi +%endmacro + +%macro tdcall_pop_regs 0 + pop rdi + pop rsi + pop rbx + pop r12 + pop r13 + pop r14 + pop r15 + pop rbp +%endmacro + +%define number_of_regs_pushed 8 +%define number_of_parameters 4 + +; +; Keep these in sync for push_regs/pop_regs, code below +; uses them to find 5th or greater parameters +; +%define first_variable_on_stack_offset \ + ((number_of_regs_pushed * 8) + (number_of_parameters * 8) + 8) +%define second_variable_on_stack_offset \ + ((first_variable_on_stack_offset) + 8) + +; TdCall ( +; UINT64 Leaf, // Rcx +; UINT64 P1, // Rdx +; UINT64 P2, // R8 +; UINT64 P3, // R9 +; UINT64 Results, // rsp + 0x28 +; ) +global ASM_PFX(TdCall) +ASM_PFX(TdCall): + tdcall_push_regs + + mov rax, rcx + mov rcx, rdx + mov rdx, r8 + mov r8, r9 + + tdcall + + ; exit if tdcall reports failure. + test rax, rax + jnz .exit + + ; test if caller wanted results + mov r12, [rsp + first_variable_on_stack_offset ] + test r12, r12 + jz .exit + mov [r12 + 0 ], rcx + mov [r12 + 8 ], rdx + mov [r12 + 16], r8 + mov [r12 + 24], r9 + mov [r12 + 32], r10 + mov [r12 + 40], r11 +.exit: + tdcall_pop_regs + ret diff --git a/MdePkg/Library/BaseLib/X64/TdProbe.c b/MdePkg/Library/BaseLib/= X64/TdProbe.c new file mode 100644 index 000000000000..a1cf02717bf2 --- /dev/null +++ b/MdePkg/Library/BaseLib/X64/TdProbe.c @@ -0,0 +1,62 @@ +/** @file + + Copyright (c) 2020-2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include + +/** + Probe if TD is enabled. + + @return TRUE TD is enabled. + @return FALSE TD is not enabled. +**/ +BOOLEAN +EFIAPI +TdIsEnabled ( + ) +{ + UINT32 Eax; + UINT32 Ebx; + UINT32 Ecx; + UINT32 Edx; + UINT32 LargestEax; + BOOLEAN TdEnabled; + + TdEnabled =3D FALSE; + + do { + AsmCpuid (CPUID_SIGNATURE, &LargestEax, &Ebx, &Ecx, &Edx); + + if ( (Ebx !=3D CPUID_SIGNATURE_GENUINE_INTEL_EBX) + || (Edx !=3D CPUID_SIGNATURE_GENUINE_INTEL_EDX) + || (Ecx !=3D CPUID_SIGNATURE_GENUINE_INTEL_ECX)) + { + break; + } + + AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, &Ecx, NULL); + if ((Ecx & BIT31) =3D=3D 0) { + break; + } + + if (LargestEax < 0x21) { + break; + } + + AsmCpuidEx (0x21, 0, &Eax, &Ebx, &Ecx, &Edx); + if ( (Ebx !=3D SIGNATURE_32 ('I', 'n', 't', 'e')) + || (Edx !=3D SIGNATURE_32 ('l', 'T', 'D', 'X')) + || (Ecx !=3D SIGNATURE_32 (' ', ' ', ' ', ' '))) + { + break; + } + + TdEnabled =3D TRUE; + } while (FALSE); + + return TdEnabled; +} diff --git a/MdePkg/Library/BaseLib/X64/TdVmcall.nasm b/MdePkg/Library/Base= Lib/X64/TdVmcall.nasm new file mode 100644 index 000000000000..5ecc10b17193 --- /dev/null +++ b/MdePkg/Library/BaseLib/X64/TdVmcall.nasm @@ -0,0 +1,145 @@ +;-------------------------------------------------------------------------= ----- +;* +;* Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
+;* SPDX-License-Identifier: BSD-2-Clause-Patent +;* +;* +;-------------------------------------------------------------------------= ----- + +DEFAULT REL +SECTION .text + +%define TDVMCALL_EXPOSE_REGS_MASK 0xffec +%define TDVMCALL 0x0 + +%macro tdcall 0 + db 0x66,0x0f,0x01,0xcc +%endmacro + +%macro tdcall_push_regs 0 + push rbp + mov rbp, rsp + push r15 + push r14 + push r13 + push r12 + push rbx + push rsi + push rdi +%endmacro + +%macro tdcall_pop_regs 0 + pop rdi + pop rsi + pop rbx + pop r12 + pop r13 + pop r14 + pop r15 + pop rbp +%endmacro + +%define number_of_regs_pushed 8 +%define number_of_parameters 4 + +; +; Keep these in sync for push_regs/pop_regs, code below +; uses them to find 5th or greater parameters +; +%define first_variable_on_stack_offset \ + ((number_of_regs_pushed * 8) + (number_of_parameters * 8) + 8) +%define second_variable_on_stack_offset \ + ((first_variable_on_stack_offset) + 8) + +%macro tdcall_regs_preamble 2 + mov rax, %1 + + xor rcx, rcx + mov ecx, %2 + + ; R10 =3D 0 (standard TDVMCALL) + + xor r10d, r10d + + ; Zero out unused (for standard TDVMCALL) registers to avoid leaking + ; secrets to the VMM. + + xor ebx, ebx + xor esi, esi + xor edi, edi + + xor edx, edx + xor ebp, ebp + xor r8d, r8d + xor r9d, r9d +%endmacro + +%macro tdcall_regs_postamble 0 + xor ebx, ebx + xor esi, esi + xor edi, edi + + xor ecx, ecx + xor edx, edx + xor r8d, r8d + xor r9d, r9d + xor r10d, r10d + xor r11d, r11d +%endmacro + +;-------------------------------------------------------------------------= ----- +; 0 =3D> RAX =3D TDCALL leaf +; M =3D> RCX =3D TDVMCALL register behavior +; 1 =3D> R10 =3D standard vs. vendor +; RDI =3D> R11 =3D TDVMCALL function / nr +; RSI =3D R12 =3D p1 +; RDX =3D> R13 =3D p2 +; RCX =3D> R14 =3D p3 +; R8 =3D> R15 =3D p4 + +; UINT64 +; EFIAPI +; TdVmCall ( +; UINT64 Leaf, // Rcx +; UINT64 P1, // Rdx +; UINT64 P2, // R8 +; UINT64 P3, // R9 +; UINT64 P4, // rsp + 0x28 +; UINT64 *Val // rsp + 0x30 +; ) +global ASM_PFX(TdVmCall) +ASM_PFX(TdVmCall): + tdcall_push_regs + + mov r11, rcx + mov r12, rdx + mov r13, r8 + mov r14, r9 + mov r15, [rsp + first_variable_on_stack_offset ] + + tdcall_regs_preamble TDVMCALL, TDVMCALL_EXPOSE_REGS_MASK + + tdcall + + ; ignore return dataif TDCALL reports failure. + test rax, rax + jnz .no_return_data + + ; Propagate TDVMCALL success/failure to return value. + mov rax, r10 + + ; Retrieve the Val pointer. + mov r9, [rsp + second_variable_on_stack_offset ] + test r9, r9 + jz .no_return_data + + ; On success, propagate TDVMCALL output value to output param + test rax, rax + jnz .no_return_data + mov [r9], r11 +.no_return_data: + tdcall_regs_postamble + + tdcall_pop_regs + + ret --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85972): https://edk2.groups.io/g/devel/message/85972 Mute This Topic: https://groups.io/mt/88617488/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Apr 29 10:32:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+85973+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85973+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1642901852; cv=none; d=zohomail.com; s=zohoarc; b=CKYUP00Jmv8LNGKXjRTPos96mvkZNYgOfKElw2BMiOE7sZN6V026vaJhj3jLCtBCPqK4Wv2o0AZlUZMb1Pnj+pM37DajUaZ2cq6WrOvL0hUSY1EHBa4+W1Y11/M3SQsvJ12B/U2H3+HuNBGgNJoxPQ4+weYXk3N3pOi49fXr4hA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1642901852; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=xObfuejf9vjKho6/cM9o3lraZ9i4tPfVSrUcIxEcsO8=; b=N3eJ+aJnHt4sq8Gy++Nydw9Cl/kBRjsZ5erEcLVzZpylO2jpG7f48/xXXlG6ZqQ4jE6Snml7ITIPmua9YW0t6EH/XrDQwriAamRCetmge0uD84etWcdmKK2NUSmvfkO7uwrds3lEYLs5EZhIRqXHtIiaaGOg0rrMdhZJ1JIszRA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85973+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 164290185259141.89059692261026; Sat, 22 Jan 2022 17:37:32 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 5ZUfYY1788612xgOxFB0M4aE; Sat, 22 Jan 2022 17:37:32 -0800 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web12.4557.1642901847770499599 for ; Sat, 22 Jan 2022 17:37:31 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10235"; a="243454704" X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="243454704" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:37:30 -0800 X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="695032833" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.255.30.84]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:37:27 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Michael D Kinney , Liming Gao , Zhiguang Liu , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann Subject: [edk2-devel] [PATCH V5 03/33] MdePkg: Add TdxLib to wrap Tdx operations Date: Sun, 23 Jan 2022 09:36:34 +0800 Message-Id: In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: C5iDoPJFN50L7X1K0eiPACuBx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1642901852; bh=Wv4rr3QxN6Uhv9egGVzHgr41vhwSGinYl/Nv6AllhC4=; h=Cc:Date:From:Reply-To:Subject:To; b=fjplsBUAg6TkzPddQ3XSykIWtmhDkvhMvoBRyMQtGMtNbpoglt4QRugxsn7mZC9Jsih SO1JggMq5kmH1hfSuQw49BlsDxNuz3jMewLANCqlfCA939IzTY258SMhHFmLs64pELimu gKkfZoIW+nZCrdXzBmXsFTnjTdFiUN9QEcs= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1642901853509100002 Content-Type: text/plain; charset="utf-8" RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 TdxLib is created with functions to perform the related Tdx operation. This includes functions for: - TdAcceptPages : Accept pending private pages and initialize the pages to all-0 using the TD ephemeral private key. - TdExtendRtmr : Extend measurement to one of the RTMR registers. - TdSharedPageMask: Get the Td guest shared page mask which indicates it is a Shared or Private page. - TdMaxVCpuNum : Get the maximum number of virtual CPUs. - TdVCpuNum : Get the number of virtual CPUs. Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Signed-off-by: Min Xu --- MdePkg/Include/Library/TdxLib.h | 97 +++++++++++++++ MdePkg/Library/TdxLib/AcceptPages.c | 180 ++++++++++++++++++++++++++++ MdePkg/Library/TdxLib/Rtmr.c | 83 +++++++++++++ MdePkg/Library/TdxLib/TdInfo.c | 114 ++++++++++++++++++ MdePkg/Library/TdxLib/TdxLib.inf | 37 ++++++ MdePkg/Library/TdxLib/TdxLibNull.c | 107 +++++++++++++++++ MdePkg/MdePkg.dec | 3 + MdePkg/MdePkg.dsc | 1 + 8 files changed, 622 insertions(+) create mode 100644 MdePkg/Include/Library/TdxLib.h create mode 100644 MdePkg/Library/TdxLib/AcceptPages.c create mode 100644 MdePkg/Library/TdxLib/Rtmr.c create mode 100644 MdePkg/Library/TdxLib/TdInfo.c create mode 100644 MdePkg/Library/TdxLib/TdxLib.inf create mode 100644 MdePkg/Library/TdxLib/TdxLibNull.c diff --git a/MdePkg/Include/Library/TdxLib.h b/MdePkg/Include/Library/TdxLi= b.h new file mode 100644 index 000000000000..86539460c9f9 --- /dev/null +++ b/MdePkg/Include/Library/TdxLib.h @@ -0,0 +1,97 @@ +/** @file + TdxLib definitions + + Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef TDX_LIB_H_ +#define TDX_LIB_H_ + +#include +#include +#include +#include + +/** + This function accepts a pending private page, and initialize the page to + all-0 using the TD ephemeral private key. + + @param[in] StartAddress Guest physical address of the private page + to accept. [63:52] and [11:0] must be 0. + @param[in] NumberOfPages Number of the pages to be accepted. + @param[in] PageSize GPA page size. Accept 2M/4K page size. + + @return EFI_SUCCESS +**/ +EFI_STATUS +EFIAPI +TdAcceptPages ( + IN UINT64 StartAddress, + IN UINT64 NumberOfPages, + IN UINT32 PageSize + ); + +/** + This function extends one of the RTMR measurement register + in TDCS with the provided extension data in memory. + RTMR extending supports SHA384 which length is 48 bytes. + + @param[in] Data Point to the data to be extended + @param[in] DataLen Length of the data. Must be 48 + @param[in] Index RTMR index + + @return EFI_SUCCESS + @return EFI_INVALID_PARAMETER + @return EFI_DEVICE_ERROR + +**/ +EFI_STATUS +EFIAPI +TdExtendRtmr ( + IN UINT32 *Data, + IN UINT32 DataLen, + IN UINT8 Index + ); + +/** + This function gets the Td guest shared page mask. + + The guest indicates if a page is shared using the Guest Physical Address + (GPA) Shared (S) bit. If the GPA Width(GPAW) is 48, the S-bit is bit-47. + If the GPAW is 52, the S-bit is bit-51. + + @return Shared page bit mask +**/ +UINT64 +EFIAPI +TdSharedPageMask ( + VOID + ); + +/** + This function gets the maximum number of Virtual CPUs that are usable for + Td Guest. + + @return maximum Virtual CPUs number +**/ +UINT32 +EFIAPI +TdMaxVCpuNum ( + VOID + ); + +/** + This function gets the number of Virtual CPUs that are usable for Td + Guest. + + @return Virtual CPUs number +**/ +UINT32 +EFIAPI +TdVCpuNum ( + VOID + ); + +#endif diff --git a/MdePkg/Library/TdxLib/AcceptPages.c b/MdePkg/Library/TdxLib/Ac= ceptPages.c new file mode 100644 index 000000000000..651d47a8d8a1 --- /dev/null +++ b/MdePkg/Library/TdxLib/AcceptPages.c @@ -0,0 +1,180 @@ +/** @file + + Unaccepted memory is a special type of private memory. In Td guest + TDCALL [TDG.MEM.PAGE.ACCEPT] is invoked to accept the unaccepted + memory before use it. + + Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include + +UINT64 mNumberOfDuplicatedAcceptedPages; + +#define TDX_ACCEPTPAGE_MAX_RETRIED 3 + +// PageSize is mapped to PageLevel like below: +// 4KB - 0, 2MB - 1 +UINT32 mTdxAcceptPageLevelMap[2] =3D { + SIZE_4KB, + SIZE_2MB +}; + +#define INVALID_ACCEPT_PAGELEVEL ARRAY_SIZE(mTdxAcceptPageLevelMap) + +/** + This function gets the PageLevel according to the input page size. + + @param[in] PageSize Page size + + @return UINT32 The mapped page level +**/ +UINT32 +GetGpaPageLevel ( + UINT32 PageSize + ) +{ + UINT32 Index; + + for (Index =3D 0; Index < ARRAY_SIZE (mTdxAcceptPageLevelMap); Index++) { + if (mTdxAcceptPageLevelMap[Index] =3D=3D PageSize) { + break; + } + } + + return Index; +} + +/** + This function accept a pending private page, and initialize the page to + all-0 using the TD ephemeral private key. + + Sometimes TDCALL [TDG.MEM.PAGE.ACCEPT] may return + TDX_EXIT_REASON_PAGE_SIZE_MISMATCH. It indicates the input PageLevel is + not workable. In this case we need to try to fallback to a smaller + PageLevel if possible. + + @param[in] StartAddress Guest physical address of the private + page to accept. [63:52] and [11:0] must be= 0. + @param[in] NumberOfPages Number of the pages to be accepted. + @param[in] PageSize GPA page size. Only accept 2M/4K size. + + @return EFI_SUCCESS Accept successfully + @return others Indicate other errors +**/ +EFI_STATUS +EFIAPI +TdAcceptPages ( + IN UINT64 StartAddress, + IN UINT64 NumberOfPages, + IN UINT32 PageSize + ) +{ + EFI_STATUS Status; + UINT64 Address; + UINT64 TdxStatus; + UINT64 Index; + UINT32 GpaPageLevel; + UINT32 PageSize2; + UINTN Retried; + + Retried =3D 0; + + if ((StartAddress & ~0xFFFFFFFFFF000ULL) !=3D 0) { + ASSERT (FALSE); + DEBUG ((DEBUG_ERROR, "Accept page address(0x%llx) is not valid. [63:52= ] and [11:0] must be 0\n", StartAddress)); + return EFI_INVALID_PARAMETER; + } + + Address =3D StartAddress; + + GpaPageLevel =3D GetGpaPageLevel (PageSize); + if (GpaPageLevel =3D=3D INVALID_ACCEPT_PAGELEVEL) { + ASSERT (FALSE); + DEBUG ((DEBUG_ERROR, "Accept page size must be 4K/2M. Invalid page siz= e - 0x%llx\n", PageSize)); + return EFI_INVALID_PARAMETER; + } + + Status =3D EFI_SUCCESS; + for (Index =3D 0; Index < NumberOfPages; Index++) { + Retried =3D 0; + +DoAcceptPage: + TdxStatus =3D TdCall (TDCALL_TDACCEPTPAGE, Address | GpaPageLevel, 0, = 0, 0); + if (TdxStatus !=3D TDX_EXIT_REASON_SUCCESS) { + if ((TdxStatus & ~0xFFFFULL) =3D=3D TDX_EXIT_REASON_PAGE_ALREADY_ACC= EPTED) { + // + // Already accepted + // + mNumberOfDuplicatedAcceptedPages++; + DEBUG ((DEBUG_WARN, "Page at Address (0x%llx) has already been acc= epted. - %d\n", Address, mNumberOfDuplicatedAcceptedPages)); + } else if ((TdxStatus & ~0xFFFFULL) =3D=3D TDX_EXIT_REASON_PAGE_SIZE= _MISMATCH) { + // + // GpaPageLevel is mismatch, fall back to a smaller GpaPageLevel i= f possible + // + DEBUG ((DEBUG_VERBOSE, "Address %llx cannot be accepted in PageLev= el of %d\n", Address, GpaPageLevel)); + + if (GpaPageLevel =3D=3D 0) { + // + // Cannot fall back to smaller page level + // + DEBUG ((DEBUG_ERROR, "AcceptPage cannot fallback from PageLevel = %d\n", GpaPageLevel)); + Status =3D EFI_INVALID_PARAMETER; + break; + } else { + // + // Fall back to a smaller page size + // + PageSize2 =3D mTdxAcceptPageLevelMap[GpaPageLevel - 1]; + Status =3D TdAcceptPages (Address, 512, PageSize2); + if (EFI_ERROR (Status)) { + break; + } + } + } else if ((TdxStatus & ~0xFFFFULL) =3D=3D TDX_EXIT_REASON_OPERAND_B= USY) { + // + // Concurrent TDG.MEM.PAGE.ACCEPT is using the same Secure EPT ent= ry + // So try it again. There is a max retried count. If Retried excee= ds the max count, + // report the error and quit. + // + Retried +=3D 1; + if (Retried > TDX_ACCEPTPAGE_MAX_RETRIED) { + DEBUG (( + DEBUG_ERROR, + "Address %llx (%d) failed to be accepted because of OPERAND_BU= SY. Retried %d time.\n", + Address, + Index, + Retried + )); + Status =3D EFI_INVALID_PARAMETER; + break; + } else { + goto DoAcceptPage; + } + } else { + // + // Other errors + // + DEBUG (( + DEBUG_ERROR, + "Address %llx (%d) failed to be accepted. Error =3D 0x%llx\n", + Address, + Index, + TdxStatus + )); + Status =3D EFI_INVALID_PARAMETER; + break; + } + } + + Address +=3D PageSize; + } + + return Status; +} diff --git a/MdePkg/Library/TdxLib/Rtmr.c b/MdePkg/Library/TdxLib/Rtmr.c new file mode 100644 index 000000000000..bdc91b3ebe6a --- /dev/null +++ b/MdePkg/Library/TdxLib/Rtmr.c @@ -0,0 +1,83 @@ +/** @file + + Extends one of the RTMR measurement registers in TDCS with the provided + extension data in memory. + + Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include + +#define RTMR_COUNT 4 +#define TD_EXTEND_BUFFER_LEN (64 + 48) + +UINT8 mExtendBuffer[TD_EXTEND_BUFFER_LEN]; + +/** + This function extends one of the RTMR measurement register + in TDCS with the provided extension data in memory. + RTMR extending supports SHA384 which length is 48 bytes. + + @param[in] Data Point to the data to be extended + @param[in] DataLen Length of the data. Must be 48 + @param[in] Index RTMR index + + @return EFI_SUCCESS + @return EFI_INVALID_PARAMETER + @return EFI_DEVICE_ERROR + +**/ +EFI_STATUS +EFIAPI +TdExtendRtmr ( + IN UINT32 *Data, + IN UINT32 DataLen, + IN UINT8 Index + ) +{ + EFI_STATUS Status; + UINT64 TdCallStatus; + UINT8 *ExtendBuffer; + + Status =3D EFI_SUCCESS; + + ASSERT (Data !=3D NULL); + ASSERT (DataLen =3D=3D SHA384_DIGEST_SIZE); + ASSERT (Index >=3D 0 && Index < RTMR_COUNT); + + if ((Data =3D=3D NULL) || (DataLen !=3D SHA384_DIGEST_SIZE) || (Index >= =3D RTMR_COUNT)) { + return EFI_INVALID_PARAMETER; + } + + // TD.RTMR.EXTEND requires 64B-aligned guest physical address of + // 48B-extension data. We use ALIGN_POINTER(Pointer, 64) to get + // the 64B-aligned guest physical address. + ExtendBuffer =3D ALIGN_POINTER (mExtendBuffer, 64); + ASSERT (((UINTN)ExtendBuffer & 0x3f) =3D=3D 0); + + ZeroMem (ExtendBuffer, SHA384_DIGEST_SIZE); + CopyMem (ExtendBuffer, Data, SHA384_DIGEST_SIZE); + + TdCallStatus =3D TdCall (TDCALL_TDEXTENDRTMR, (UINT64)(UINTN)ExtendBuffe= r, Index, 0, 0); + + if (TdCallStatus =3D=3D TDX_EXIT_REASON_SUCCESS) { + Status =3D EFI_SUCCESS; + } else if (TdCallStatus =3D=3D TDX_EXIT_REASON_OPERAND_INVALID) { + Status =3D EFI_INVALID_PARAMETER; + } else { + Status =3D EFI_DEVICE_ERROR; + } + + if (Status !=3D EFI_SUCCESS) { + DEBUG ((DEBUG_ERROR, "Error returned from TdExtendRtmr call - 0x%lx\n"= , TdCallStatus)); + } + + return Status; +} diff --git a/MdePkg/Library/TdxLib/TdInfo.c b/MdePkg/Library/TdxLib/TdInfo.c new file mode 100644 index 000000000000..a40a15116f30 --- /dev/null +++ b/MdePkg/Library/TdxLib/TdInfo.c @@ -0,0 +1,114 @@ +/** @file + + Fetch the Tdx info. + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include + +UINT64 mTdSharedPageMask =3D 0; +UINT32 mTdMaxVCpuNum =3D 0; +UINT32 mTdVCpuNum =3D 0; +BOOLEAN mTdDataReturned =3D FALSE; + +/** + This function call TDCALL_TDINFO to get the TD_RETURN_DATA. + If the TDCALL is successful, populate below variables: + - mTdSharedPageMask + - mTdMaxVCpunum + - mTdVCpuNum + - mTdDataReturned + + @return TRUE The TDCALL is successful and above variables are populated. + @return FALSE The TDCALL is failed. Above variables are not set. +**/ +BOOLEAN +GetTdInfo ( + VOID + ) +{ + UINT64 Status; + TD_RETURN_DATA TdReturnData; + UINT8 Gpaw; + + Status =3D TdCall (TDCALL_TDINFO, 0, 0, 0, &TdReturnData); + if (Status =3D=3D TDX_EXIT_REASON_SUCCESS) { + Gpaw =3D (UINT8)(TdReturnData.TdInfo.Gpaw & 0x3f); + mTdSharedPageMask =3D 1ULL << (Gpaw - 1); + mTdMaxVCpuNum =3D TdReturnData.TdInfo.MaxVcpus; + mTdVCpuNum =3D TdReturnData.TdInfo.NumVcpus; + mTdDataReturned =3D TRUE; + } else { + DEBUG ((DEBUG_ERROR, "Failed call TDCALL_TDINFO. %llx\n", Status)); + mTdDataReturned =3D FALSE; + } + + return mTdDataReturned; +} + +/** + This function gets the Td guest shared page mask. + + The guest indicates if a page is shared using the Guest Physical Address + (GPA) Shared (S) bit. If the GPA Width(GPAW) is 48, the S-bit is bit-47. + If the GPAW is 52, the S-bit is bit-51. + + @return Shared page bit mask +**/ +UINT64 +EFIAPI +TdSharedPageMask ( + VOID + ) +{ + if (mTdDataReturned) { + return mTdSharedPageMask; + } + + return GetTdInfo () ? mTdSharedPageMask : 0; +} + +/** + This function gets the maximum number of Virtual CPUs that are usable for + Td Guest. + + @return maximum Virtual CPUs number +**/ +UINT32 +EFIAPI +TdMaxVCpuNum ( + VOID + ) +{ + if (mTdDataReturned) { + return mTdMaxVCpuNum; + } + + return GetTdInfo () ? mTdMaxVCpuNum : 0; +} + +/** + This function gets the number of Virtual CPUs that are usable for Td + Guest. + + @return Virtual CPUs number +**/ +UINT32 +EFIAPI +TdVCpuNum ( + VOID + ) +{ + if (mTdDataReturned) { + return mTdVCpuNum; + } + + return GetTdInfo () ? mTdVCpuNum : 0; +} diff --git a/MdePkg/Library/TdxLib/TdxLib.inf b/MdePkg/Library/TdxLib/TdxLi= b.inf new file mode 100644 index 000000000000..442e63d079da --- /dev/null +++ b/MdePkg/Library/TdxLib/TdxLib.inf @@ -0,0 +1,37 @@ +## @file +# Tdx library +# +# Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D TdxLib + FILE_GUID =3D 032A8E0D-0C27-40C0-9CAA-23B731C1B223 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D TdxLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +[Sources.IA32] + TdxLibNull.c + +[Sources.X64] + AcceptPages.c + Rtmr.c + TdInfo.c + +[Packages] + MdePkg/MdePkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib diff --git a/MdePkg/Library/TdxLib/TdxLibNull.c b/MdePkg/Library/TdxLib/Tdx= LibNull.c new file mode 100644 index 000000000000..83ab929b4a3b --- /dev/null +++ b/MdePkg/Library/TdxLib/TdxLibNull.c @@ -0,0 +1,107 @@ +/** @file + + Null stub of TdxLib + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include + +/** + This function accepts a pending private page, and initialize the page to + all-0 using the TD ephemeral private key. + + @param[in] StartAddress Guest physical address of the private page + to accept. + @param[in] NumberOfPages Number of the pages to be accepted. + @param[in] PageSize GPA page size. Accept 1G/2M/4K page size. + + @return EFI_SUCCESS +**/ +EFI_STATUS +EFIAPI +TdAcceptPages ( + IN UINT64 StartAddress, + IN UINT64 NumberOfPages, + IN UINT32 PageSize + ) +{ + return EFI_UNSUPPORTED; +} + +/** + This function extends one of the RTMR measurement register + in TDCS with the provided extension data in memory. + RTMR extending supports SHA384 which length is 48 bytes. + + @param[in] Data Point to the data to be extended + @param[in] DataLen Length of the data. Must be 48 + @param[in] Index RTMR index + + @return EFI_SUCCESS + @return EFI_INVALID_PARAMETER + @return EFI_DEVICE_ERROR + +**/ +EFI_STATUS +EFIAPI +TdExtendRtmr ( + IN UINT32 *Data, + IN UINT32 DataLen, + IN UINT8 Index + ) +{ + return EFI_UNSUPPORTED; +} + +/** + This function gets the Td guest shared page mask. + + The guest indicates if a page is shared using the Guest Physical Address + (GPA) Shared (S) bit. If the GPA Width(GPAW) is 48, the S-bit is bit-47. + If the GPAW is 52, the S-bit is bit-51. + + @return Shared page bit mask +**/ +UINT64 +EFIAPI +TdSharedPageMask ( + VOID + ) +{ + return 0; +} + +/** + This function gets the maximum number of Virtual CPUs that are usable for + Td Guest. + + @return maximum Virtual CPUs number +**/ +UINT32 +EFIAPI +TdMaxVCpuNum ( + VOID + ) +{ + return 0; +} + +/** + This function gets the number of Virtual CPUs that are usable for Td + Guest. + + @return Virtual CPUs number +**/ +UINT32 +EFIAPI +TdVCpuNum ( + VOID + ) +{ + return 0; +} diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index 59b405928bf8..1934c9840423 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -296,6 +296,9 @@ ## @libraryclass Provides services to log the SMI handler registration. SmiHandlerProfileLib|Include/Library/SmiHandlerProfileLib.h =20 + ## @libraryclass Provides function to support TDX processing. + TdxLib|Include/Library/TdxLib.h + [Guids] # # GUID defined in UEFI2.1/UEFI2.0/EFI1.1 diff --git a/MdePkg/MdePkg.dsc b/MdePkg/MdePkg.dsc index a94959169b2f..d6a7af412be7 100644 --- a/MdePkg/MdePkg.dsc +++ b/MdePkg/MdePkg.dsc @@ -175,6 +175,7 @@ MdePkg/Library/SmiHandlerProfileLibNull/SmiHandlerProfileLibNull.inf MdePkg/Library/MmServicesTableLib/MmServicesTableLib.inf MdePkg/Library/MmUnblockMemoryLib/MmUnblockMemoryLibNull.inf + MdePkg/Library/TdxLib/TdxLib.inf =20 [Components.EBC] MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85973): https://edk2.groups.io/g/devel/message/85973 Mute This Topic: https://groups.io/mt/88617493/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Apr 29 10:32:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+85974+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85974+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1642901854; cv=none; d=zohomail.com; s=zohoarc; b=n1T4RwKLGqOR0ZApaa9DegZNuuA9F4vvpwZydBSQmlz1WhEFTpo4b8TyNaAdEqLk7LapBmRV7tLbwOLWBd46GjNcGvFc/RnSTCqIwqAwUAu4DU+2jTO/0zKwpjbCL1pKR7OkMickn5aOR+2flYZmMcSvrVhnDBGhbzPHNiPByYY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1642901854; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=TNbI76/YU+Vu6gVuY5jJqkPpeC57AsmOfF+xuBSb+Ts=; b=bXk+CLc7/xXlkCQafcK92GMp8xJmanJ2yu4vOecC9tZbZXMy7sL75uN/ShuKu2VJUMmBJyPqr/XB1BPvgFjG2TGPysbebx+BaBd6vBvk97XwSR4wkXDGTYdpkcRXpdrUdC2Kn+xA6A8UHzsXVoiJ86+Fg+aN0DOZKhzmHZZvaig= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85974+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1642901854482768.5079244803421; Sat, 22 Jan 2022 17:37:34 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id CJiTYY1788612xJ55qPZmRXM; Sat, 22 Jan 2022 17:37:34 -0800 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web12.4557.1642901847770499599 for ; Sat, 22 Jan 2022 17:37:33 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10235"; a="243454717" X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="243454717" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:37:33 -0800 X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="695032858" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.255.30.84]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:37:30 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [PATCH V5 04/33] UefiCpuPkg: Extend VmgExitLibNull to handle #VE exception Date: Sun, 23 Jan 2022 09:36:35 +0800 Message-Id: In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: rPwov0kAS4H28TLTcojDt0ppx1787277AA= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1642901854; bh=Qj+x1pqSh67lrYR+N9hzqsOesqFbMLA+Oi2PBufxnBE=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=L86QPi2gPowf5IxuADMvM2+Fe02sEiZuSGOHBH5aEzHmdQe4JCSD4/lA6rMuwrwsmuq VVDaG3jKvhN3Yqp/C+WewIdmLcafGpgrOKzqmpgnXitiWFhfWfsAvkNgJQXYcBxcyx31q gEFTKiXcYXK8lJQBK0BvpgCmDem+j5FiUhI= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1642901855406100006 RFC=EF=BC=9A https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 VmgExitLib performs the necessary processing to handle a #VC exception. VmgExitLibNull is a NULL instance of VmgExitLib which provides a default limited interface. In this commit VmgExitLibNull is extended to handle a #VE exception with a default limited interface. A full feature version of #VE handler will be created later. Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Signed-off-by: Min Xu --- UefiCpuPkg/Include/Library/VmgExitLib.h | 28 ++++++++++++++ .../Library/VmgExitLibNull/VmTdExitNull.c | 38 +++++++++++++++++++ .../Library/VmgExitLibNull/VmgExitLibNull.inf | 1 + 3 files changed, 67 insertions(+) create mode 100644 UefiCpuPkg/Library/VmgExitLibNull/VmTdExitNull.c diff --git a/UefiCpuPkg/Include/Library/VmgExitLib.h b/UefiCpuPkg/Include/L= ibrary/VmgExitLib.h index ebda1c3d907c..f9f911099a7b 100644 --- a/UefiCpuPkg/Include/Library/VmgExitLib.h +++ b/UefiCpuPkg/Include/Library/VmgExitLib.h @@ -15,6 +15,8 @@ #include #include =20 +#define VE_EXCEPTION 20 + /** Perform VMGEXIT. =20 @@ -142,4 +144,30 @@ VmgExitHandleVc ( IN OUT EFI_SYSTEM_CONTEXT SystemContext ); =20 +/** + Handle a #VE exception. + + Performs the necessary processing to handle a #VE exception. + + The base library function returns an error equal to VE_EXCEPTION, + to be propagated to the standard exception handling stack. + + @param[in, out] ExceptionType Pointer to an EFI_EXCEPTION_TYPE to be s= et + as value to use on error. + @param[in, out] SystemContext Pointer to EFI_SYSTEM_CONTEXT + + @retval EFI_SUCCESS Exception handled + @retval EFI_UNSUPPORTED #VE not supported, (new) exception value= to + propagate provided + @retval EFI_PROTOCOL_ERROR #VE handling failed, (new) exception val= ue to + propagate provided + +**/ +EFI_STATUS +EFIAPI +VmTdExitHandleVe ( + IN OUT EFI_EXCEPTION_TYPE *ExceptionType, + IN OUT EFI_SYSTEM_CONTEXT SystemContext + ); + #endif diff --git a/UefiCpuPkg/Library/VmgExitLibNull/VmTdExitNull.c b/UefiCpuPkg/= Library/VmgExitLibNull/VmTdExitNull.c new file mode 100644 index 000000000000..6a4e8087cb89 --- /dev/null +++ b/UefiCpuPkg/Library/VmgExitLibNull/VmTdExitNull.c @@ -0,0 +1,38 @@ +/** @file + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include +#include +#include + +/** + Handle a #VE exception. + + Performs the necessary processing to handle a #VE exception. + + @param[in, out] ExceptionType Pointer to an EFI_EXCEPTION_TYPE to be s= et + as value to use on error. + @param[in, out] SystemContext Pointer to EFI_SYSTEM_CONTEXT + + @retval EFI_SUCCESS Exception handled + @retval EFI_UNSUPPORTED #VE not supported, (new) exception value= to + propagate provided + @retval EFI_PROTOCOL_ERROR #VE handling failed, (new) exception val= ue to + propagate provided + +**/ +EFI_STATUS +EFIAPI +VmTdExitHandleVe ( + IN OUT EFI_EXCEPTION_TYPE *ExceptionType, + IN OUT EFI_SYSTEM_CONTEXT SystemContext + ) +{ + *ExceptionType =3D VE_EXCEPTION; + + return EFI_UNSUPPORTED; +} diff --git a/UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf b/UefiCpu= Pkg/Library/VmgExitLibNull/VmgExitLibNull.inf index d8770a21c355..4aab601939ff 100644 --- a/UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf +++ b/UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf @@ -17,6 +17,7 @@ =20 [Sources.common] VmgExitLibNull.c + VmTdExitNull.c =20 [Packages] MdePkg/MdePkg.dec --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85974): https://edk2.groups.io/g/devel/message/85974 Mute This Topic: https://groups.io/mt/88617494/1787277 Mute #ve:https://edk2.groups.io/g/devel/mutehashtag/ve Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Apr 29 10:32:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+85975+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85975+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1642901857; cv=none; d=zohomail.com; s=zohoarc; b=N817+YyMGFNroXGd8Io/JEEeKKKJkgvDgckdLi+NJXQ4BaKgVM+K7DPFv4T/KOwMAev7uGvaOPdhwVI/TLbdST/OCSdZlK5mIGDaD6Yz9k6x0eC9q8tEnK8eS41WR6MC83zFRW6zi/V9LV7TVajwLvhrP0wxKCNIEwUTuZnNh6s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1642901857; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=cXxKRGNPsw/OdUbXwmyNGN2M3IBmNn2h37tJtYci9HE=; b=USibNR5gY1ptZb8gC8aSvfbWdd+kuSp0ZLCiQ5TIdH4+OMSJqmimRo1YByhERbK5Ciw2LXJmKHnkvB3MZau29Uej0HnXNLAE8zBzDmksk3UjswlFMl6/hZVbKNCDwfyereHjkPRncAeIxGAmCSox8B/yRkYo2ywRb7XAv6uZKcw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85975+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 164290185713173.40912807379209; Sat, 22 Jan 2022 17:37:37 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 9NkjYY1788612xV3Rnx4uUb9; Sat, 22 Jan 2022 17:37:36 -0800 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web12.4557.1642901847770499599 for ; Sat, 22 Jan 2022 17:37:36 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10235"; a="243454736" X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="243454736" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:37:35 -0800 X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="695032913" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.255.30.84]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:37:33 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jiewen Yao , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Tom Lendacky , Gerd Hoffmann Subject: [edk2-devel] [PATCH V5 05/33] OvmfPkg: Extend VmgExitLib to handle #VE exception Date: Sun, 23 Jan 2022 09:36:36 +0800 Message-Id: In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: WtydPjn9SlOQ7rmkavbPgduFx1787277AA= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1642901856; bh=TkffKsdSIAZcpbibxucxz6mywWkCym6MiHbAAFHd8xY=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=jaq7QxhMc7sefGWuJnSIbHQKYhoorQ1avEtiwtr3fPK/CKCUdsKpgmZGSVJOzM+tK6n O0RNcYJuyuS8Z/Jibb1L5HbncwnO/sVTltqOyf7/Yhqc3AHf64iT1MSYlduLrrYfCYiJh XasBL03kqd924ynGSLE6rFYa7GmW/xuJKGQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1642901857695100001 RFC=EF=BC=9A https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 The base VmgExitLib library provides a default limited interface to handle #VE exception. To provide full support, the OVMF version of VmgExitLib is extended to provide full support of #VE handler. Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Signed-off-by: Min Xu Acked-by: Gerd Hoffmann --- OvmfPkg/Library/VmgExitLib/SecVmgExitLib.inf | 3 +- OvmfPkg/Library/VmgExitLib/VmTdExitHandler.h | 32 + .../Library/VmgExitLib/VmTdExitVeHandler.c | 559 ++++++++++++++++++ OvmfPkg/Library/VmgExitLib/VmgExitLib.inf | 2 + .../Library/VmgExitLib/X64/TdVmcallCpuid.nasm | 146 +++++ 5 files changed, 741 insertions(+), 1 deletion(-) create mode 100644 OvmfPkg/Library/VmgExitLib/VmTdExitHandler.h create mode 100644 OvmfPkg/Library/VmgExitLib/VmTdExitVeHandler.c create mode 100644 OvmfPkg/Library/VmgExitLib/X64/TdVmcallCpuid.nasm diff --git a/OvmfPkg/Library/VmgExitLib/SecVmgExitLib.inf b/OvmfPkg/Library= /VmgExitLib/SecVmgExitLib.inf index 78207fa0f9c9..f9bd4974f6dc 100644 --- a/OvmfPkg/Library/VmgExitLib/SecVmgExitLib.inf +++ b/OvmfPkg/Library/VmgExitLib/SecVmgExitLib.inf @@ -25,6 +25,8 @@ VmgExitVcHandler.c VmgExitVcHandler.h SecVmgExitVcHandler.c + VmTdExitVeHandler.c + X64/TdVmcallCpuid.nasm =20 [Packages] MdePkg/MdePkg.dec @@ -44,4 +46,3 @@ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBackupSize gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidSize - diff --git a/OvmfPkg/Library/VmgExitLib/VmTdExitHandler.h b/OvmfPkg/Library= /VmgExitLib/VmTdExitHandler.h new file mode 100644 index 000000000000..7eacd0872f46 --- /dev/null +++ b/OvmfPkg/Library/VmgExitLib/VmTdExitHandler.h @@ -0,0 +1,32 @@ +/** @file + + Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef VMTD_EXIT_HANDLER_H_ +#define VMTD_EXIT_HANDLER_H_ + +#include +#include + +/** + This function enable the TD guest to request the VMM to emulate CPUID + operation, especially for non-architectural, CPUID leaves. + + @param[in] Eax Main leaf of the CPUID + @param[in] Ecx Sub-leaf of the CPUID + @param[out] Results Returned result of CPUID operation + + @return EFI_SUCCESS +**/ +EFI_STATUS +EFIAPI +TdVmCallCpuid ( + IN UINT64 Eax, + IN UINT64 Ecx, + OUT VOID *Results + ); + +#endif diff --git a/OvmfPkg/Library/VmgExitLib/VmTdExitVeHandler.c b/OvmfPkg/Libra= ry/VmgExitLib/VmTdExitVeHandler.c new file mode 100644 index 000000000000..b73e877c093b --- /dev/null +++ b/OvmfPkg/Library/VmgExitLib/VmTdExitVeHandler.c @@ -0,0 +1,559 @@ +/** @file + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include "VmTdExitHandler.h" +#include +#include +#include +#include + +typedef union { + struct { + UINT32 Eax; + UINT32 Edx; + } Regs; + UINT64 Val; +} MSR_DATA; + +typedef union { + UINT8 Val; + struct { + UINT8 B : 1; + UINT8 X : 1; + UINT8 R : 1; + UINT8 W : 1; + } Bits; +} REX; + +typedef union { + UINT8 Val; + struct { + UINT8 Rm : 3; + UINT8 Reg : 3; + UINT8 Mod : 2; + } Bits; +} MODRM; + +typedef struct { + UINT64 Regs[4]; +} CPUID_DATA; + +/** + Handle an CPUID event. + + Use the TDVMCALL instruction to handle cpuid #ve + + @param[in, out] Regs x64 processor context + @param[in] Veinfo VE Info + + @retval 0 Event handled successfully + @return New exception value to propagate +**/ +STATIC +UINT64 +EFIAPI +CpuIdExit ( + IN EFI_SYSTEM_CONTEXT_X64 *Regs, + IN TDCALL_VEINFO_RETURN_DATA *Veinfo + ) +{ + CPUID_DATA CpuIdData; + UINT64 Status; + + Status =3D TdVmCallCpuid (Regs->Rax, Regs->Rcx, &CpuIdData); + + if (Status =3D=3D 0) { + Regs->Rax =3D CpuIdData.Regs[0]; + Regs->Rbx =3D CpuIdData.Regs[1]; + Regs->Rcx =3D CpuIdData.Regs[2]; + Regs->Rdx =3D CpuIdData.Regs[3]; + } + + return Status; +} + +/** + Handle an IO event. + + Use the TDVMCALL instruction to handle either an IO read or an IO write. + + @param[in, out] Regs x64 processor context + @param[in] Veinfo VE Info + + @retval 0 Event handled successfully + @return New exception value to propagate +**/ +STATIC +UINT64 +EFIAPI +IoExit ( + IN OUT EFI_SYSTEM_CONTEXT_X64 *Regs, + IN TDCALL_VEINFO_RETURN_DATA *Veinfo + ) +{ + BOOLEAN Write; + UINTN Size; + UINTN Port; + UINT64 Val; + UINT64 RepCnt; + UINT64 Status; + + Val =3D 0; + Write =3D Veinfo->ExitQualification.Io.Direction ? FALSE : TRUE; + Size =3D Veinfo->ExitQualification.Io.Size + 1; + Port =3D Veinfo->ExitQualification.Io.Port; + + if (Veinfo->ExitQualification.Io.String) { + // + // If REP is set, get rep-cnt from Rcx + // + RepCnt =3D Veinfo->ExitQualification.Io.Rep ? Regs->Rcx : 1; + + while (RepCnt) { + Val =3D 0; + if (Write =3D=3D TRUE) { + CopyMem (&Val, (VOID *)Regs->Rsi, Size); + Regs->Rsi +=3D Size; + } + + Status =3D TdVmCall (EXIT_REASON_IO_INSTRUCTION, Size, Write, Port, = Val, (Write ? NULL : &Val)); + if (Status !=3D 0) { + break; + } + + if (Write =3D=3D FALSE) { + CopyMem ((VOID *)Regs->Rdi, &Val, Size); + Regs->Rdi +=3D Size; + } + + if (Veinfo->ExitQualification.Io.Rep) { + Regs->Rcx -=3D 1; + } + + RepCnt -=3D 1; + } + } else { + if (Write =3D=3D TRUE) { + CopyMem (&Val, (VOID *)&Regs->Rax, Size); + } + + Status =3D TdVmCall (EXIT_REASON_IO_INSTRUCTION, Size, Write, Port, Va= l, (Write ? NULL : &Val)); + if ((Status =3D=3D 0) && (Write =3D=3D FALSE)) { + CopyMem ((VOID *)&Regs->Rax, &Val, Size); + } + } + + return Status; +} + +/** + Handle an READ MSR event. + + Use the TDVMCALL instruction to handle msr read + + @param[in, out] Regs x64 processor context + @param[in] Veinfo VE Info + + @retval 0 Event handled successfully + @return New exception value to propagate +**/ +STATIC +UINT64 +ReadMsrExit ( + IN OUT EFI_SYSTEM_CONTEXT_X64 *Regs, + IN TDCALL_VEINFO_RETURN_DATA *Veinfo + ) +{ + MSR_DATA Data; + UINT64 Status; + + Status =3D TdVmCall (EXIT_REASON_MSR_READ, Regs->Rcx, 0, 0, 0, &Data); + if (Status =3D=3D 0) { + Regs->Rax =3D Data.Regs.Eax; + Regs->Rdx =3D Data.Regs.Edx; + } + + return Status; +} + +/** + Handle an WRITE MSR event. + + Use the TDVMCALL instruction to handle msr write + + @param[in, out] Regs x64 processor context + @param[in] Veinfo VE Info + + @retval 0 Event handled successfully + @return New exception value to propagate +**/ +STATIC +UINT64 +WriteMsrExit ( + IN OUT EFI_SYSTEM_CONTEXT_X64 *Regs, + IN TDCALL_VEINFO_RETURN_DATA *Veinfo + ) +{ + UINT64 Status; + MSR_DATA Data; + + Data.Regs.Eax =3D (UINT32)Regs->Rax; + Data.Regs.Edx =3D (UINT32)Regs->Rdx; + + Status =3D TdVmCall (EXIT_REASON_MSR_WRITE, Regs->Rcx, Data.Val, 0, 0, = NULL); + + return Status; +} + +STATIC +VOID +EFIAPI +TdxDecodeInstruction ( + IN UINT8 *Rip + ) +{ + UINTN i; + + DEBUG ((DEBUG_INFO, "TDX: #TD[EPT] instruction (%p):", Rip)); + for (i =3D 0; i < 15; i++) { + DEBUG ((DEBUG_INFO, "%02x:", Rip[i])); + } + + DEBUG ((DEBUG_INFO, "\n")); +} + +#define TDX_DECODER_BUG_ON(x) \ + if ((x)) { \ + TdxDecodeInstruction(Rip); \ + TdVmCall(TDVMCALL_HALT, 0, 0, 0, 0, 0); \ + } + +STATIC +UINT64 * +EFIAPI +GetRegFromContext ( + IN EFI_SYSTEM_CONTEXT_X64 *Regs, + IN UINTN RegIndex + ) +{ + switch (RegIndex) { + case 0: return &Regs->Rax; + break; + case 1: return &Regs->Rcx; + break; + case 2: return &Regs->Rdx; + break; + case 3: return &Regs->Rbx; + break; + case 4: return &Regs->Rsp; + break; + case 5: return &Regs->Rbp; + break; + case 6: return &Regs->Rsi; + break; + case 7: return &Regs->Rdi; + break; + case 8: return &Regs->R8; + break; + case 9: return &Regs->R9; + break; + case 10: return &Regs->R10; + break; + case 11: return &Regs->R11; + break; + case 12: return &Regs->R12; + break; + case 13: return &Regs->R13; + break; + case 14: return &Regs->R14; + break; + case 15: return &Regs->R15; + break; + } + + return NULL; +} + +/** + Handle an MMIO event. + + Use the TDVMCALL instruction to handle either an mmio read or an mmio wr= ite. + + @param[in, out] Regs x64 processor context + @param[in] Veinfo VE Info + + @retval 0 Event handled successfully + @return New exception value to propagate +**/ +STATIC +INTN +EFIAPI +MmioExit ( + IN OUT EFI_SYSTEM_CONTEXT_X64 *Regs, + IN TDCALL_VEINFO_RETURN_DATA *Veinfo + ) +{ + UINT64 Status; + UINT32 MmioSize; + UINT32 RegSize; + UINT8 OpCode; + BOOLEAN SeenRex; + UINT64 *Reg; + UINT8 *Rip; + UINT64 Val; + UINT32 OpSize; + MODRM ModRm; + REX Rex; + + Rip =3D (UINT8 *)Regs->Rip; + Val =3D 0; + Rex.Val =3D 0; + SeenRex =3D FALSE; + + // + // Default to 32bit transfer + // + OpSize =3D 4; + + do { + OpCode =3D *Rip++; + if (OpCode =3D=3D 0x66) { + OpSize =3D 2; + } else if ((OpCode =3D=3D 0x64) || (OpCode =3D=3D 0x65) || (OpCode =3D= =3D 0x67)) { + continue; + } else if ((OpCode >=3D 0x40) && (OpCode <=3D 0x4f)) { + SeenRex =3D TRUE; + Rex.Val =3D OpCode; + } else { + break; + } + } while (TRUE); + + // + // We need to have at least 2 more bytes for this instruction + // + TDX_DECODER_BUG_ON (((UINT64)Rip - Regs->Rip) > 13); + + OpCode =3D *Rip++; + // + // Two-byte opecode, get next byte + // + if (OpCode =3D=3D 0x0F) { + OpCode =3D *Rip++; + } + + switch (OpCode) { + case 0x88: + case 0x8A: + case 0xB6: + MmioSize =3D 1; + break; + case 0xB7: + MmioSize =3D 2; + break; + default: + MmioSize =3D Rex.Bits.W ? 8 : OpSize; + break; + } + + /* Punt on AH/BH/CH/DH unless it shows up. */ + ModRm.Val =3D *Rip++; + TDX_DECODER_BUG_ON (MmioSize =3D=3D 1 && ModRm.Bits.Reg > 4 && !SeenRex = && OpCode !=3D 0xB6); + Reg =3D GetRegFromContext (Regs, ModRm.Bits.Reg | ((int)Rex.Bits.R << 3)= ); + TDX_DECODER_BUG_ON (!Reg); + + if (ModRm.Bits.Rm =3D=3D 4) { + ++Rip; /* SIB byte */ + } + + if ((ModRm.Bits.Mod =3D=3D 2) || ((ModRm.Bits.Mod =3D=3D 0) && (ModRm.Bi= ts.Rm =3D=3D 5))) { + Rip +=3D 4; /* DISP32 */ + } else if (ModRm.Bits.Mod =3D=3D 1) { + ++Rip; /* DISP8 */ + } + + switch (OpCode) { + case 0x88: + case 0x89: + CopyMem ((void *)&Val, Reg, MmioSize); + Status =3D TdVmCall (TDVMCALL_MMIO, MmioSize, 1, Veinfo->GuestPA, Va= l, 0); + break; + case 0xC7: + CopyMem ((void *)&Val, Rip, OpSize); + Status =3D TdVmCall (TDVMCALL_MMIO, MmioSize, 1, Veinfo->GuestPA, Va= l, 0); + Rip +=3D OpSize; + default: + // + // 32-bit write registers are zero extended to the full register + // Hence 'MOVZX r[32/64], r/m16' is + // hardcoded to reg size 8, and the straight MOV case has a reg + // size of 8 in the 32-bit read case. + // + switch (OpCode) { + case 0xB6: + RegSize =3D Rex.Bits.W ? 8 : OpSize; + break; + case 0xB7: + RegSize =3D 8; + break; + default: + RegSize =3D MmioSize =3D=3D 4 ? 8 : MmioSize; + break; + } + + Status =3D TdVmCall (TDVMCALL_MMIO, MmioSize, 0, Veinfo->GuestPA, 0,= &Val); + if (Status =3D=3D 0) { + ZeroMem (Reg, RegSize); + CopyMem (Reg, (void *)&Val, MmioSize); + } + } + + if (Status =3D=3D 0) { + TDX_DECODER_BUG_ON (((UINT64)Rip - Regs->Rip) > 15); + + // + // We change instruction length to reflect true size so handler can + // bump rip + // + Veinfo->ExitInstructionLength =3D (UINT32)((UINT64)Rip - Regs->Rip); + } + + return Status; +} + +/** + Handle a #VE exception. + + Performs the necessary processing to handle a #VE exception. + + @param[in, out] ExceptionType Pointer to an EFI_EXCEPTION_TYPE to be s= et + as value to use on error. + @param[in, out] SystemContext Pointer to EFI_SYSTEM_CONTEXT + + @retval EFI_SUCCESS Exception handled + @retval EFI_UNSUPPORTED #VE not supported, (new) exception value= to + propagate provided + @retval EFI_PROTOCOL_ERROR #VE handling failed, (new) exception val= ue to + propagate provided + +**/ +EFI_STATUS +EFIAPI +VmTdExitHandleVe ( + IN OUT EFI_EXCEPTION_TYPE *ExceptionType, + IN OUT EFI_SYSTEM_CONTEXT SystemContext + ) +{ + UINT64 Status; + TD_RETURN_DATA ReturnData; + EFI_SYSTEM_CONTEXT_X64 *Regs; + + Regs =3D SystemContext.SystemContextX64; + Status =3D TdCall (TDCALL_TDGETVEINFO, 0, 0, 0, &ReturnData); + ASSERT (Status =3D=3D 0); + if (Status !=3D 0) { + DEBUG ((DEBUG_ERROR, "#VE happened. TDGETVEINFO failed with Status =3D= 0x%llx\n", Status)); + TdVmCall (TDVMCALL_HALT, 0, 0, 0, 0, 0); + } + + switch (ReturnData.VeInfo.ExitReason) { + case EXIT_REASON_CPUID: + Status =3D CpuIdExit (Regs, &ReturnData.VeInfo); + DEBUG (( + DEBUG_VERBOSE, + "CPUID #VE happened, ExitReasion is %d, ExitQualification =3D 0x%x= .\n", + ReturnData.VeInfo.ExitReason, + ReturnData.VeInfo.ExitQualification.Val + )); + break; + + case EXIT_REASON_HLT: + Status =3D TdVmCall (EXIT_REASON_HLT, 0, 0, 0, 0, 0); + break; + + case EXIT_REASON_IO_INSTRUCTION: + Status =3D IoExit (Regs, &ReturnData.VeInfo); + DEBUG (( + DEBUG_VERBOSE, + "IO_Instruction #VE happened, ExitReasion is %d, ExitQualification= =3D 0x%x.\n", + ReturnData.VeInfo.ExitReason, + ReturnData.VeInfo.ExitQualification.Val + )); + break; + + case EXIT_REASON_MSR_READ: + Status =3D ReadMsrExit (Regs, &ReturnData.VeInfo); + DEBUG (( + DEBUG_VERBOSE, + "RDMSR #VE happened, ExitReasion is %d, ExitQualification =3D 0x%x= . Regs->Rcx=3D0x%llx, Status =3D 0x%llx\n", + ReturnData.VeInfo.ExitReason, + ReturnData.VeInfo.ExitQualification.Val, + Regs->Rcx, + Status + )); + break; + + case EXIT_REASON_MSR_WRITE: + Status =3D WriteMsrExit (Regs, &ReturnData.VeInfo); + DEBUG (( + DEBUG_VERBOSE, + "WRMSR #VE happened, ExitReasion is %d, ExitQualification =3D 0x%x= . Regs->Rcx=3D0x%llx, Status =3D 0x%llx\n", + ReturnData.VeInfo.ExitReason, + ReturnData.VeInfo.ExitQualification.Val, + Regs->Rcx, + Status + )); + break; + + case EXIT_REASON_EPT_VIOLATION: + Status =3D MmioExit (Regs, &ReturnData.VeInfo); + DEBUG (( + DEBUG_VERBOSE, + "MMIO #VE happened, ExitReasion is %d, ExitQualification =3D 0x%x.= \n", + ReturnData.VeInfo.ExitReason, + ReturnData.VeInfo.ExitQualification.Val + )); + break; + + case EXIT_REASON_VMCALL: + case EXIT_REASON_MWAIT_INSTRUCTION: + case EXIT_REASON_MONITOR_INSTRUCTION: + case EXIT_REASON_WBINVD: + case EXIT_REASON_RDPMC: + /* Handle as nops. */ + break; + + default: + DEBUG (( + DEBUG_ERROR, + "Unsupported #VE happened, ExitReason is %d, ExitQualification =3D= 0x%x.\n", + ReturnData.VeInfo.ExitReason, + ReturnData.VeInfo.ExitQualification.Val + )); + + ASSERT (FALSE); + CpuDeadLoop (); + } + + if (Status) { + DEBUG (( + DEBUG_ERROR, + "#VE Error (0x%llx) returned from host, ExitReason is %d, ExitQualif= ication =3D 0x%x.\n", + Status, + ReturnData.VeInfo.ExitReason, + ReturnData.VeInfo.ExitQualification.Val + )); + + TdVmCall (TDVMCALL_HALT, 0, 0, 0, 0, 0); + } + + SystemContext.SystemContextX64->Rip +=3D ReturnData.VeInfo.ExitInstructi= onLength; + return EFI_SUCCESS; +} diff --git a/OvmfPkg/Library/VmgExitLib/VmgExitLib.inf b/OvmfPkg/Library/Vm= gExitLib/VmgExitLib.inf index 7963670e7d30..255b0c1a2f7f 100644 --- a/OvmfPkg/Library/VmgExitLib/VmgExitLib.inf +++ b/OvmfPkg/Library/VmgExitLib/VmgExitLib.inf @@ -25,6 +25,8 @@ VmgExitVcHandler.c VmgExitVcHandler.h PeiDxeVmgExitVcHandler.c + VmTdExitVeHandler.c + X64/TdVmcallCpuid.nasm =20 [Packages] MdePkg/MdePkg.dec diff --git a/OvmfPkg/Library/VmgExitLib/X64/TdVmcallCpuid.nasm b/OvmfPkg/Li= brary/VmgExitLib/X64/TdVmcallCpuid.nasm new file mode 100644 index 000000000000..fa86440904fe --- /dev/null +++ b/OvmfPkg/Library/VmgExitLib/X64/TdVmcallCpuid.nasm @@ -0,0 +1,146 @@ +;-------------------------------------------------------------------------= ----- +;* +;* Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
+;* SPDX-License-Identifier: BSD-2-Clause-Patent +;* +;* +;-------------------------------------------------------------------------= ----- + +DEFAULT REL +SECTION .text + +%define TDVMCALL_EXPOSE_REGS_MASK 0xffec +%define TDVMCALL 0x0 +%define EXIT_REASON_CPUID 0xa + +%macro tdcall 0 + db 0x66,0x0f,0x01,0xcc +%endmacro + +%macro tdcall_push_regs 0 + push rbp + mov rbp, rsp + push r15 + push r14 + push r13 + push r12 + push rbx + push rsi + push rdi +%endmacro + +%macro tdcall_pop_regs 0 + pop rdi + pop rsi + pop rbx + pop r12 + pop r13 + pop r14 + pop r15 + pop rbp +%endmacro + +%define number_of_regs_pushed 8 +%define number_of_parameters 4 + +; +; Keep these in sync for push_regs/pop_regs, code below +; uses them to find 5th or greater parameters +; +%define first_variable_on_stack_offset \ + ((number_of_regs_pushed * 8) + (number_of_parameters * 8) + 8) +%define second_variable_on_stack_offset \ + ((first_variable_on_stack_offset) + 8) + +%macro tdcall_regs_preamble 2 + mov rax, %1 + + xor rcx, rcx + mov ecx, %2 + + ; R10 =3D 0 (standard TDVMCALL) + + xor r10d, r10d + + ; Zero out unused (for standard TDVMCALL) registers to avoid leaking + ; secrets to the VMM. + + xor ebx, ebx + xor esi, esi + xor edi, edi + + xor edx, edx + xor ebp, ebp + xor r8d, r8d + xor r9d, r9d + xor r14, r14 + xor r15, r15 +%endmacro + +%macro tdcall_regs_postamble 0 + xor ebx, ebx + xor esi, esi + xor edi, edi + + xor ecx, ecx + xor edx, edx + xor r8d, r8d + xor r9d, r9d + xor r10d, r10d + xor r11d, r11d +%endmacro + +;-------------------------------------------------------------------------= ----- +; 0 =3D> RAX =3D TDCALL leaf / TDVMCALL +; M =3D> RCX =3D TDVMCALL register behavior +; 0xa =3D> R11 =3D TDVMCALL function / CPUID +; RCX =3D> R12 =3D p1 +; RDX =3D> R13 =3D p2 +; +; UINT64 +; EFIAPI +; TdVmCallCpuid ( +; UINT64 EaxIn, // Rcx +; UINT64 EcxIn, // Rdx +; UINT64 *Results // R8 +; ) +global ASM_PFX(TdVmCallCpuid) +ASM_PFX(TdVmCallCpuid): + tdcall_push_regs + + mov r11, EXIT_REASON_CPUID + mov r12, rcx + mov r13, rdx + + ; Save *results pointers + push r8 + + tdcall_regs_preamble TDVMCALL, TDVMCALL_EXPOSE_REGS_MASK + + tdcall + + ; ignore return data if TDCALL reports failure. + test rax, rax + jnz .no_return_data + + ; Propagate TDVMCALL success/failure to return value. + mov rax, r10 + test rax, rax + jnz .no_return_data + + ; Retrieve *Results + pop r8 + test r8, r8 + jz .no_return_data + ; Caller pass in buffer so store results r12-r15 contains eax-edx + mov [r8 + 0], r12 + mov [r8 + 8], r13 + mov [r8 + 16], r14 + mov [r8 + 24], r15 + +.no_return_data: + tdcall_regs_postamble + + tdcall_pop_regs + + ret --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85975): https://edk2.groups.io/g/devel/message/85975 Mute This Topic: https://groups.io/mt/88617496/1787277 Mute #ve:https://edk2.groups.io/g/devel/mutehashtag/ve Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Apr 29 10:32:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+85976+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85976+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1642901859; cv=none; d=zohomail.com; s=zohoarc; b=Ju7auX7QFySseip+cPx6CWEJEkAyEQyN/5ZYNNHJjMUU7SO4MCY60ZsrKoSZ72sE3DVDdxoP5CDKZahhle96wd+stbDc7TiRk8q5j7Aa0L5UYkNfn0AwJyb05jX4Dg17UueQkmgrduEUMpHhW7iVE+OrOXmJmvK75rOQdZ3nSs8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1642901859; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=k7i0n0yExpgvluGwI+YPLr4O7uZTNo0f7mBC3llWHxY=; b=ZJCUQCRkaw8eCjm5H1fHI2OfhM9fcxodv1cLNkeMrDs9OC1n/RGB5X9gBZcflmFfjcoZ5NOOkMk3rdVZX04NmV26U/FCX04zpK2XYD9jZrNb60Eg/84cdGtyWb1Xi3U2x06lAZLIktFGPLkXYFnMFh6Eu/xElbo+17Ny09ieWTw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85976+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1642901859994691.8303367242995; Sat, 22 Jan 2022 17:37:39 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id z2s9YY1788612xFFqkG5WXK5; Sat, 22 Jan 2022 17:37:39 -0800 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web12.4557.1642901847770499599 for ; Sat, 22 Jan 2022 17:37:38 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10235"; a="243454749" X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="243454749" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:37:38 -0800 X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="695032952" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.255.30.84]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:37:35 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [PATCH V5 06/33] UefiCpuPkg/CpuExceptionHandler: Add base support for the #VE exception Date: Sun, 23 Jan 2022 09:36:37 +0800 Message-Id: <18d041d59fe9de9332df30d346a7fb946d7e0ebe.1642899774.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: wFO1oUHeNSqdprWvQ3pEAzR2x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1642901859; bh=EVDukdwHjE1wwlVxCQYxFdkmdOLssOxG3wyIGGLaDdY=; h=Cc:Date:From:Reply-To:Subject:To; b=LlaaA10TiYGWT6t+eJ8kcRDiGrOMr1WzYa2Q72x0bm+OV4IwDi6a3cM1Ker1Sd8yCVv 8AJ6FH8dghmJPd5nXcPTf333jPMUsQS3EPCIYm3nf8FEFviyzV/qbtt5tdeQIBtc87Vs6 6QjG4fvGqXea7fWAcN+IkZBIEo6NDwDPVxA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1642901861731100002 Content-Type: text/plain; charset="utf-8" RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 Add base support to handle #VE exceptions. Update the common exception handlers to invoke the VmTdExitHandleVe () function of the VmgExitLib library when a #VE is encountered. A non-zero return code will propagate to the targeted exception handler. Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Signed-off-by: Min Xu --- .../PeiDxeSmmCpuException.c | 17 +++++++++++++++++ .../SecPeiCpuException.c | 18 ++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuExceptio= n.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c index 762ea2460f91..4fa3f8202a33 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c @@ -45,6 +45,23 @@ CommonExceptionHandlerWorker ( } } =20 + if (ExceptionType =3D=3D VE_EXCEPTION) { + EFI_STATUS Status; + // + // #VE needs to be handled immediately upon enabling exception handling + // and therefore can't use the RegisterCpuInterruptHandler() interface. + // + // Handle the #VE: + // On EFI_SUCCESS - Exception has been handled, return + // On other - ExceptionType contains (possibly new) exception + // value + // + Status =3D VmTdExitHandleVe (&ExceptionType, SystemContext); + if (!EFI_ERROR (Status)) { + return; + } + } + ExceptionHandlerContext =3D (EXCEPTION_HANDLER_CONTEXT *)(UINTN)(System= Context.SystemContextIa32); ReservedVectors =3D ExceptionHandlerData->ReservedVectors; ExternalInterruptHandler =3D ExceptionHandlerData->ExternalInterruptHand= ler; diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c= b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c index c614d5b0b6f1..148d89011721 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c @@ -43,6 +43,24 @@ CommonExceptionHandler ( } } =20 + if (ExceptionType =3D=3D VE_EXCEPTION) { + EFI_STATUS Status; + // + // #VE needs to be handled immediately upon enabling exception handling + // and therefore can't use the RegisterCpuInterruptHandler() interface + // (which isn't supported under Sec and Pei anyway). + // + // Handle the #VE: + // On EFI_SUCCESS - Exception has been handled, return + // On other - ExceptionType contains (possibly new) exception + // value + // + Status =3D VmTdExitHandleVe (&ExceptionType, SystemContext); + if (!EFI_ERROR (Status)) { + return; + } + } + // // Initialize the serial port before dumping. // --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85976): https://edk2.groups.io/g/devel/message/85976 Mute This Topic: https://groups.io/mt/88617497/1787277 Mute #ve:https://edk2.groups.io/g/devel/mutehashtag/ve Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Apr 29 10:32:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+85977+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85977+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1642901863; cv=none; d=zohomail.com; s=zohoarc; b=dqpPJIZpBTy/utC6a4azq+rSDlOxDWPKR7E3Ipfg/VPAqF5PixEh1oZG6D3/FOTKOTl3eVx8BHH8WDaaI/F0UGb63Dx/1uycBaCe66IcT/Req5hdYAUdNpb2U/mjeCaRRbuxSCJlwpH85J/aubliU/SvoNEVph4IzonWDSGXCTI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1642901863; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=OlXJtXkHFD2Deo3lFWuMoR203BcEhU3moODC5Vanq+Q=; b=NTjdvMjo1dayjy6OVIO14vtubXj3HUlcYnnCrk0LNRtynuywW6kvPrDnHgEPpL1cajqXubRqZPDYp+nO9/ipkCUQgvoSqZD5J7NRv3tM2KY0NPLOYYi8MWnWVjPqc6Pc9RDkh13lfutMWc3Qd1wPnsv8qazUgSZIpZwJRtOpe/c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85977+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1642901863033824.7484396380988; Sat, 22 Jan 2022 17:37:43 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id JEV7YY1788612xCCCEaHllkP; Sat, 22 Jan 2022 17:37:42 -0800 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web12.4557.1642901847770499599 for ; Sat, 22 Jan 2022 17:37:42 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10235"; a="243454760" X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="243454760" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:37:41 -0800 X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="695032962" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.255.30.84]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:37:38 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Michael D Kinney , Liming Gao , Zhiguang Liu , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky Subject: [edk2-devel] [PATCH V5 07/33] MdePkg: Add helper functions for Tdx guest in BaseIoLibIntrinsic Date: Sun, 23 Jan 2022 09:36:38 +0800 Message-Id: In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: Dkgm5p2Tl4uEN0eteryTkeyzx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1642901862; bh=6LkxuQA2bdTi5fIWMZvh80aFR5zm09P1xHF9N2ywFiU=; h=Cc:Date:From:Reply-To:Subject:To; b=wFJkBTZLm04cU5hAEoC552AmynIcIzRk5C55zV6NawztB3kYq4HEvhW7bY1wylkbfAx GPA270UElkm6AgPrLW7VdU6f0Ugzv3z/WhKqkDw/nN+2bDgtF+p0cUoAUILeKX4awsDah YIWrLW/78kolmcTKUCNuQ/CtR+BWzFcxk7o= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1642901864000100001 Content-Type: text/plain; charset="utf-8" RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 Intel TDX architecture does not prescribe a specific software convention to perform I/O from the guest TD. Guest TD providers have many choices to provide I/O to the guest. The common I/O models are emulated devices, para-virtualized devices, SRIOV devices and Direct Device assignments. TDVF chooses para-virtualized I/O (Choice-A) which use the TDG.VP.VMCALL function to invoke the funtions provided by the host VMM to perform I/O. Another choice (Choice-B) is the emulation performed by the #VE handler. There are 2 benefits of para-virtualized I/O: 1. Performance. VMEXIT/VMENTRY is skipped so that the performance is better than #VE handler. 2. De-couple with #VE handler. Choice-B depends on the #VE handler which means I/O is not available until #VE handler is installed. For example, in PEI phase #VE handler is installed in CpuMpPei, while communication with Qemu (via I/O port) happen earlier than it. IoLibInternalTdx.c provides the helper functions for Tdx guest. IoLibInternalTdxNull.c provides the null version of the helper functions. It is included in the Non-X64 IoLib so that the build will not be broken. Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Signed-off-by: Min Xu --- .../BaseIoLibIntrinsicSev.inf | 2 + .../BaseIoLibIntrinsic/IoLibInternalTdx.c | 675 ++++++++++++++++++ .../BaseIoLibIntrinsic/IoLibInternalTdxNull.c | 497 +++++++++++++ MdePkg/Library/BaseIoLibIntrinsic/IoLibTdx.h | 410 +++++++++++ 4 files changed, 1584 insertions(+) create mode 100644 MdePkg/Library/BaseIoLibIntrinsic/IoLibInternalTdx.c create mode 100644 MdePkg/Library/BaseIoLibIntrinsic/IoLibInternalTdxNull.c create mode 100644 MdePkg/Library/BaseIoLibIntrinsic/IoLibTdx.h diff --git a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf b/= MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf index 34f9d1d1062f..336d79736d9a 100644 --- a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf +++ b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf @@ -51,3 +51,5 @@ BaseLib RegisterFilterLib =20 +[LibraryClasses.X64] + TdxLib diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibInternalTdx.c b/MdePkg/= Library/BaseIoLibIntrinsic/IoLibInternalTdx.c new file mode 100644 index 000000000000..368eea49116a --- /dev/null +++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibInternalTdx.c @@ -0,0 +1,675 @@ +/** @file + TDX I/O Library routines. + + Copyright (c) 2020-2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include "BaseIoLibIntrinsicInternal.h" +#include +#include +#include +#include +#include +#include "IoLibTdx.h" + +// Size of TDVMCALL Access, including IO and MMIO +#define TDVMCALL_ACCESS_SIZE_1 1 +#define TDVMCALL_ACCESS_SIZE_2 2 +#define TDVMCALL_ACCESS_SIZE_4 4 +#define TDVMCALL_ACCESS_SIZE_8 8 + +// Direction of TDVMCALL Access, including IO and MMIO +#define TDVMCALL_ACCESS_READ 0 +#define TDVMCALL_ACCESS_WRITE 1 + +BOOLEAN mTdxEnabled =3D FALSE; +BOOLEAN mTdxProbed =3D FALSE; + +/** + Check if it is Tdx guest. + + @return TRUE It is Tdx guest + @return FALSE It is not Tdx guest + +**/ +BOOLEAN +EFIAPI +IsTdxGuest ( + VOID + ) +{ + if (mTdxProbed) { + return mTdxEnabled; + } + + mTdxEnabled =3D TdIsEnabled (); + mTdxProbed =3D TRUE; + + return mTdxEnabled; +} + +/** + Reads an 8-bit I/O port. + + TDVMCALL_IO is invoked to read I/O port. + + @param Port The I/O port to read. + + @return The value read. + +**/ +UINT8 +EFIAPI +TdIoRead8 ( + IN UINTN Port + ) +{ + UINT64 Status; + UINT64 Val; + + Status =3D TdVmCall (TDVMCALL_IO, TDVMCALL_ACCESS_SIZE_1, TDVMCALL_ACCES= S_READ, Port, 0, &Val); + if (Status !=3D 0) { + TdVmCall (TDVMCALL_HALT, 0, 0, 0, 0, 0); + } + + return (UINT8)Val; +} + +/** + Reads a 16-bit I/O port. + + TDVMCALL_IO is invoked to write I/O port. + + @param Port The I/O port to read. + + @return The value read. + +**/ +UINT16 +EFIAPI +TdIoRead16 ( + IN UINTN Port + ) +{ + UINT64 Status; + UINT64 Val; + + ASSERT ((Port & 1) =3D=3D 0); + + Status =3D TdVmCall (TDVMCALL_IO, TDVMCALL_ACCESS_SIZE_2, TDVMCALL_ACCES= S_READ, Port, 0, &Val); + if (Status !=3D 0) { + TdVmCall (TDVMCALL_HALT, 0, 0, 0, 0, 0); + } + + return (UINT16)Val; +} + +/** + Reads a 32-bit I/O port. + + TDVMCALL_IO is invoked to read I/O port. + + @param Port The I/O port to read. + + @return The value read. + +**/ +UINT32 +EFIAPI +TdIoRead32 ( + IN UINTN Port + ) +{ + UINT64 Status; + UINT64 Val; + + ASSERT ((Port & 3) =3D=3D 0); + + Status =3D TdVmCall (TDVMCALL_IO, TDVMCALL_ACCESS_SIZE_4, TDVMCALL_ACCES= S_READ, Port, 0, &Val); + if (Status !=3D 0) { + TdVmCall (TDVMCALL_HALT, 0, 0, 0, 0, 0); + } + + return (UINT32)Val; +} + +/** + Writes an 8-bit I/O port. + + TDVMCALL_IO is invoked to write I/O port. + + @param Port The I/O port to write. + @param Value The value to write to the I/O port. + + @return The value written the I/O port. + +**/ +UINT8 +EFIAPI +TdIoWrite8 ( + IN UINTN Port, + IN UINT8 Value + ) +{ + UINT64 Status; + UINT64 Val; + + Val =3D Value; + Status =3D TdVmCall (TDVMCALL_IO, TDVMCALL_ACCESS_SIZE_1, TDVMCALL_ACCES= S_WRITE, Port, Val, 0); + if (Status !=3D 0) { + TdVmCall (TDVMCALL_HALT, 0, 0, 0, 0, 0); + } + + return Value; +} + +/** + Writes a 16-bit I/O port. + + TDVMCALL_IO is invoked to write I/O port. + + @param Port The I/O port to write. + @param Value The value to write to the I/O port. + + @return The value written the I/O port. + +**/ +UINT16 +EFIAPI +TdIoWrite16 ( + IN UINTN Port, + IN UINT16 Value + ) +{ + UINT64 Status; + UINT64 Val; + + ASSERT ((Port & 1) =3D=3D 0); + Val =3D Value; + Status =3D TdVmCall (TDVMCALL_IO, TDVMCALL_ACCESS_SIZE_2, TDVMCALL_ACCES= S_WRITE, Port, Val, 0); + if (Status !=3D 0) { + TdVmCall (TDVMCALL_HALT, 0, 0, 0, 0, 0); + } + + return Value; +} + +/** + Writes a 32-bit I/O port. + + TDVMCALL_IO is invoked to write I/O port. + + @param Port The I/O port to write. + @param Value The value to write to the I/O port. + + @return The value written the I/O port. + +**/ +UINT32 +EFIAPI +TdIoWrite32 ( + IN UINTN Port, + IN UINT32 Value + ) +{ + UINT64 Status; + UINT64 Val; + + ASSERT ((Port & 3) =3D=3D 0); + Val =3D Value; + Status =3D TdVmCall (TDVMCALL_IO, TDVMCALL_ACCESS_SIZE_4, TDVMCALL_ACCES= S_WRITE, Port, Val, 0); + if (Status !=3D 0) { + TdVmCall (TDVMCALL_HALT, 0, 0, 0, 0, 0); + } + + return Value; +} + +/** + Reads an 8-bit MMIO register. + + TDVMCALL_MMIO is invoked to read MMIO registers. + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT8 +EFIAPI +TdMmioRead8 ( + IN UINTN Address + ) +{ + UINT64 Value; + UINT64 Status; + + Status =3D TdVmCall (TDVMCALL_MMIO, TDVMCALL_ACCESS_SIZE_1, TDVMCALL_ACC= ESS_READ, Address | TdSharedPageMask (), 0, &Value); + if (Status !=3D 0) { + Value =3D *(volatile UINT64 *)Address; + } + + return (UINT8)Value; +} + +/** + Writes an 8-bit MMIO register. + + TDVMCALL_MMIO is invoked to read write registers. + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + + @return Value. + +**/ +UINT8 +EFIAPI +TdMmioWrite8 ( + IN UINTN Address, + IN UINT8 Value + ) +{ + UINT64 Val; + UINT64 Status; + + Val =3D Value; + Status =3D TdVmCall (TDVMCALL_MMIO, TDVMCALL_ACCESS_SIZE_1, TDVMCALL_ACC= ESS_WRITE, Address | TdSharedPageMask (), Val, 0); + if (Status !=3D 0) { + *(volatile UINT8 *)Address =3D Value; + } + + return Value; +} + +/** + Reads a 16-bit MMIO register. + + TDVMCALL_MMIO is invoked to read MMIO registers. + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT16 +EFIAPI +TdMmioRead16 ( + IN UINTN Address + ) +{ + UINT64 Value; + UINT64 Status; + + Status =3D TdVmCall (TDVMCALL_MMIO, TDVMCALL_ACCESS_SIZE_2, TDVMCALL_ACC= ESS_READ, Address | TdSharedPageMask (), 0, &Value); + if (Status !=3D 0) { + Value =3D *(volatile UINT64 *)Address; + } + + return (UINT16)Value; +} + +/** + Writes a 16-bit MMIO register. + + TDVMCALL_MMIO is invoked to write MMIO registers. + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + + @return Value. + +**/ +UINT16 +EFIAPI +TdMmioWrite16 ( + IN UINTN Address, + IN UINT16 Value + ) +{ + UINT64 Val; + UINT64 Status; + + ASSERT ((Address & 1) =3D=3D 0); + + Val =3D Value; + Status =3D TdVmCall (TDVMCALL_MMIO, TDVMCALL_ACCESS_SIZE_2, TDVMCALL_ACC= ESS_WRITE, Address | TdSharedPageMask (), Val, 0); + if (Status !=3D 0) { + *(volatile UINT16 *)Address =3D Value; + } + + return Value; +} + +/** + Reads a 32-bit MMIO register. + + TDVMCALL_MMIO is invoked to read MMIO registers. + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT32 +EFIAPI +TdMmioRead32 ( + IN UINTN Address + ) +{ + UINT64 Value; + UINT64 Status; + + Status =3D TdVmCall (TDVMCALL_MMIO, TDVMCALL_ACCESS_SIZE_4, TDVMCALL_ACC= ESS_READ, Address | TdSharedPageMask (), 0, &Value); + if (Status !=3D 0) { + Value =3D *(volatile UINT64 *)Address; + } + + return (UINT32)Value; +} + +/** + Writes a 32-bit MMIO register. + + TDVMCALL_MMIO is invoked to write MMIO registers. + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + + @return Value. + +**/ +UINT32 +EFIAPI +TdMmioWrite32 ( + IN UINTN Address, + IN UINT32 Value + ) +{ + UINT64 Val; + UINT64 Status; + + ASSERT ((Address & 3) =3D=3D 0); + + Val =3D Value; + Status =3D TdVmCall (TDVMCALL_MMIO, TDVMCALL_ACCESS_SIZE_4, TDVMCALL_ACC= ESS_WRITE, Address | TdSharedPageMask (), Val, 0); + if (Status !=3D 0) { + *(volatile UINT32 *)Address =3D Value; + } + + return Value; +} + +/** + Reads a 64-bit MMIO register. + + TDVMCALL_MMIO is invoked to read MMIO registers. + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT64 +EFIAPI +TdMmioRead64 ( + IN UINTN Address + ) +{ + UINT64 Value; + UINT64 Status; + + Status =3D TdVmCall (TDVMCALL_MMIO, TDVMCALL_ACCESS_SIZE_8, TDVMCALL_ACC= ESS_READ, Address | TdSharedPageMask (), 0, &Value); + if (Status !=3D 0) { + Value =3D *(volatile UINT64 *)Address; + } + + return Value; +} + +/** + Writes a 64-bit MMIO register. + + TDVMCALL_MMIO is invoked to write MMIO registers. + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + +**/ +UINT64 +EFIAPI +TdMmioWrite64 ( + IN UINTN Address, + IN UINT64 Value + ) +{ + UINT64 Status; + UINT64 Val; + + ASSERT ((Address & 7) =3D=3D 0); + + Val =3D Value; + Status =3D TdVmCall (TDVMCALL_MMIO, TDVMCALL_ACCESS_SIZE_8, TDVMCALL_ACC= ESS_WRITE, Address | TdSharedPageMask (), Val, 0); + if (Status !=3D 0) { + *(volatile UINT64 *)Address =3D Value; + } + + return Value; +} + +/** + Reads an 8-bit I/O port fifo into a block of memory. + + Reads the 8-bit I/O fifo port specified by Port. + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + In TDX a serial of TdIoRead8 is invoked to read the I/O port fifo. + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +TdIoReadFifo8 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + UINT8 *Buf8; + UINTN Index; + + Buf8 =3D (UINT8 *)Buffer; + for (Index =3D 0; Index < Count; Index++) { + Buf8[Index] =3D TdIoRead8 (Port); + } +} + +/** + Writes a block of memory into an 8-bit I/O port fifo. + + Writes the 8-bit I/O fifo port specified by Port. + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + In TDX a serial of TdIoWrite8 is invoked to write data to the I/O port. + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to retrieve the write data from. + +**/ +VOID +EFIAPI +TdIoWriteFifo8 ( + IN UINTN Port, + IN UINTN Count, + IN VOID *Buffer + ) +{ + UINT8 *Buf8; + UINTN Index; + + Buf8 =3D (UINT8 *)Buffer; + for (Index =3D 0; Index < Count; Index++) { + TdIoWrite8 (Port, Buf8[Index]); + } +} + +/** + Reads a 16-bit I/O port fifo into a block of memory. + + Reads the 16-bit I/O fifo port specified by Port. + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + + In TDX a serial of TdIoRead16 is invoked to read data from the I/O port. + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +TdIoReadFifo16 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + UINT16 *Buf16; + UINTN Index; + + Buf16 =3D (UINT16 *)Buffer; + for (Index =3D 0; Index < Count; Index++) { + Buf16[Index] =3D TdIoRead16 (Port); + } +} + +/** + Writes a block of memory into a 16-bit I/O port fifo. + + Writes the 16-bit I/O fifo port specified by Port. + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + + In TDX a serial of TdIoWrite16 is invoked to write data to the I/O port. + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to retrieve the write data from. + +**/ +VOID +EFIAPI +TdIoWriteFifo16 ( + IN UINTN Port, + IN UINTN Count, + IN VOID *Buffer + ) +{ + UINT16 *Buf16; + UINTN Index; + + Buf16 =3D (UINT16 *)Buffer; + for (Index =3D 0; Index < Count; Index++) { + TdIoWrite16 (Port, Buf16[Index]); + } +} + +/** + Reads a 32-bit I/O port fifo into a block of memory. + + Reads the 32-bit I/O fifo port specified by Port. + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + + In TDX a serial of TdIoRead32 is invoked to read data from the I/O port. + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +TdIoReadFifo32 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + UINT32 *Buf32; + UINTN Index; + + Buf32 =3D (UINT32 *)Buffer; + for (Index =3D 0; Index < Count; Index++) { + Buf32[Index] =3D TdIoRead32 (Port); + } +} + +/** + Writes a block of memory into a 32-bit I/O port fifo. + + Writes the 32-bit I/O fifo port specified by Port. + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + + In TDX a serial of TdIoWrite32 is invoked to write data to the I/O port. + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to retrieve the write data from. + +**/ +VOID +EFIAPI +TdIoWriteFifo32 ( + IN UINTN Port, + IN UINTN Count, + IN VOID *Buffer + ) +{ + UINT32 *Buf32; + UINTN Index; + + Buf32 =3D (UINT32 *)Buffer; + for (Index =3D 0; Index < Count; Index++) { + TdIoWrite32 (Port, Buf32[Index]); + } +} diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibInternalTdxNull.c b/Mde= Pkg/Library/BaseIoLibIntrinsic/IoLibInternalTdxNull.c new file mode 100644 index 000000000000..7262704d6b14 --- /dev/null +++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibInternalTdxNull.c @@ -0,0 +1,497 @@ +/** @file + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include "BaseIoLibIntrinsicInternal.h" +#include "IoLibTdx.h" + +/** + Check if it is Tdx guest. + + @return TRUE It is Tdx guest + @return FALSE It is not Tdx guest + +**/ +BOOLEAN +EFIAPI +IsTdxGuest ( + VOID + ) +{ + return FALSE; +} + +/** + Reads an 8-bit I/O port. + + TDVMCALL_IO is invoked to read I/O port. + + @param Port The I/O port to read. + + @return The value read. + +**/ +UINT8 +EFIAPI +TdIoRead8 ( + IN UINTN Port + ) +{ + ASSERT (FALSE); + return 0; +} + +/** + Reads a 16-bit I/O port. + + TDVMCALL_IO is invoked to write I/O port. + + @param Port The I/O port to read. + + @return The value read. + +**/ +UINT16 +EFIAPI +TdIoRead16 ( + IN UINTN Port + ) +{ + ASSERT (FALSE); + return 0; +} + +/** + Reads a 32-bit I/O port. + + TDVMCALL_IO is invoked to read I/O port. + + @param Port The I/O port to read. + + @return The value read. + +**/ +UINT32 +EFIAPI +TdIoRead32 ( + IN UINTN Port + ) +{ + ASSERT (FALSE); + return 0; +} + +/** + Writes an 8-bit I/O port. + + TDVMCALL_IO is invoked to write I/O port. + + @param Port The I/O port to write. + @param Value The value to write to the I/O port. + + @return The value written the I/O port. + +**/ +UINT8 +EFIAPI +TdIoWrite8 ( + IN UINTN Port, + IN UINT8 Value + ) +{ + ASSERT (FALSE); + return 0; +} + +/** + Writes a 16-bit I/O port. + + TDVMCALL_IO is invoked to write I/O port. + + @param Port The I/O port to write. + @param Value The value to write to the I/O port. + + @return The value written the I/O port. + +**/ +UINT16 +EFIAPI +TdIoWrite16 ( + IN UINTN Port, + IN UINT16 Value + ) +{ + ASSERT (FALSE); + return 0; +} + +/** + Writes a 32-bit I/O port. + + TDVMCALL_IO is invoked to write I/O port. + + @param Port The I/O port to write. + @param Value The value to write to the I/O port. + + @return The value written the I/O port. + +**/ +UINT32 +EFIAPI +TdIoWrite32 ( + IN UINTN Port, + IN UINT32 Value + ) +{ + ASSERT (FALSE); + return 0; +} + +/** + Reads an 8-bit MMIO register. + + TDVMCALL_MMIO is invoked to read MMIO registers. + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT8 +EFIAPI +TdMmioRead8 ( + IN UINTN Address + ) +{ + ASSERT (FALSE); + return 0; +} + +/** + Writes an 8-bit MMIO register. + + TDVMCALL_MMIO is invoked to read write registers. + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + + @return Value. + +**/ +UINT8 +EFIAPI +TdMmioWrite8 ( + IN UINTN Address, + IN UINT8 Val + ) +{ + ASSERT (FALSE); + return 0; +} + +/** + Reads a 16-bit MMIO register. + + TDVMCALL_MMIO is invoked to read MMIO registers. + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT16 +EFIAPI +TdMmioRead16 ( + IN UINTN Address + ) +{ + ASSERT (FALSE); + return 0; +} + +/** + Writes a 16-bit MMIO register. + + TDVMCALL_MMIO is invoked to write MMIO registers. + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + + @return Value. + +**/ +UINT16 +EFIAPI +TdMmioWrite16 ( + IN UINTN Address, + IN UINT16 Val + ) +{ + ASSERT (FALSE); + return 0; +} + +/** + Reads a 32-bit MMIO register. + + TDVMCALL_MMIO is invoked to read MMIO registers. + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT32 +EFIAPI +TdMmioRead32 ( + IN UINTN Address + ) +{ + ASSERT (FALSE); + return 0; +} + +/** + Writes a 32-bit MMIO register. + + TDVMCALL_MMIO is invoked to write MMIO registers. + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + + @return Value. + +**/ +UINT32 +EFIAPI +TdMmioWrite32 ( + IN UINTN Address, + IN UINT32 Val + ) +{ + ASSERT (FALSE); + return 0; +} + +/** + Reads a 64-bit MMIO register. + + TDVMCALL_MMIO is invoked to read MMIO registers. + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT64 +EFIAPI +TdMmioRead64 ( + IN UINTN Address + ) +{ + ASSERT (FALSE); + return 0; +} + +/** + Writes a 64-bit MMIO register. + + TDVMCALL_MMIO is invoked to write MMIO registers. + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + +**/ +UINT64 +EFIAPI +TdMmioWrite64 ( + IN UINTN Address, + IN UINT64 Value + ) +{ + ASSERT (FALSE); + return 0; +} + +/** + Reads an 8-bit I/O port fifo into a block of memory. + + Reads the 8-bit I/O fifo port specified by Port. + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + In TDX a serial of TdIoRead8 is invoked to read the I/O port fifo. + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +TdIoReadFifo8 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + ASSERT (FALSE); +} + +/** + Writes a block of memory into an 8-bit I/O port fifo. + + Writes the 8-bit I/O fifo port specified by Port. + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + In TDX a serial of TdIoWrite8 is invoked to write data to the I/O port. + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to retrieve the write data from. + +**/ +VOID +EFIAPI +TdIoWriteFifo8 ( + IN UINTN Port, + IN UINTN Count, + IN VOID *Buffer + ) +{ + ASSERT (FALSE); +} + +/** + Reads a 16-bit I/O port fifo into a block of memory. + + Reads the 16-bit I/O fifo port specified by Port. + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + + In TDX a serial of TdIoRead16 is invoked to read data from the I/O port. + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +TdIoReadFifo16 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + ASSERT (FALSE); +} + +/** + Writes a block of memory into a 16-bit I/O port fifo. + + Writes the 16-bit I/O fifo port specified by Port. + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + + In TDX a serial of TdIoWrite16 is invoked to write data to the I/O port. + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to retrieve the write data from. + +**/ +VOID +EFIAPI +TdIoWriteFifo16 ( + IN UINTN Port, + IN UINTN Count, + IN VOID *Buffer + ) +{ + ASSERT (FALSE); +} + +/** + Reads a 32-bit I/O port fifo into a block of memory. + + Reads the 32-bit I/O fifo port specified by Port. + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + + In TDX a serial of TdIoRead32 is invoked to read data from the I/O port. + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +TdIoReadFifo32 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + ASSERT (FALSE); +} + +/** + Writes a block of memory into a 32-bit I/O port fifo. + + Writes the 32-bit I/O fifo port specified by Port. + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + + In TDX a serial of TdIoWrite32 is invoked to write data to the I/O port. + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to retrieve the write data from. + +**/ +VOID +EFIAPI +TdIoWriteFifo32 ( + IN UINTN Port, + IN UINTN Count, + IN VOID *Buffer + ) +{ + ASSERT (FALSE); +} diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibTdx.h b/MdePkg/Library/= BaseIoLibIntrinsic/IoLibTdx.h new file mode 100644 index 000000000000..ab2fa771f6c8 --- /dev/null +++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibTdx.h @@ -0,0 +1,410 @@ +/** @file + Header file for Tdx IO library. + + Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef IOLIB_TDX_H_ +#define IOLIB_TDX_H_ + +/** + Check if it is Tdx guest. + + @return TRUE It is Tdx guest + @return FALSE It is not Tdx guest + +**/ +BOOLEAN +EFIAPI +IsTdxGuest ( + VOID + ); + +/** + Reads an 8-bit I/O port. + + TDVMCALL_IO is invoked to read I/O port. + + @param Port The I/O port to read. + + @return The value read. + +**/ +UINT8 +EFIAPI +TdIoRead8 ( + IN UINTN Port + ); + +/** + Reads a 16-bit I/O port. + + TDVMCALL_IO is invoked to write I/O port. + + @param Port The I/O port to read. + + @return The value read. + +**/ +UINT16 +EFIAPI +TdIoRead16 ( + IN UINTN Port + ); + +/** + Reads a 32-bit I/O port. + + TDVMCALL_IO is invoked to read I/O port. + + @param Port The I/O port to read. + + @return The value read. + +**/ +UINT32 +EFIAPI +TdIoRead32 ( + IN UINTN Port + ); + +/** + Writes an 8-bit I/O port. + + TDVMCALL_IO is invoked to write I/O port. + + @param Port The I/O port to write. + @param Value The value to write to the I/O port. + + @return The value written the I/O port. + +**/ +UINT8 +EFIAPI +TdIoWrite8 ( + IN UINTN Port, + IN UINT8 Value + ); + +/** + Writes a 16-bit I/O port. + + TDVMCALL_IO is invoked to write I/O port. + + @param Port The I/O port to write. + @param Value The value to write to the I/O port. + + @return The value written the I/O port. + +**/ +UINT16 +EFIAPI +TdIoWrite16 ( + IN UINTN Port, + IN UINT16 Value + ); + +/** + Writes a 32-bit I/O port. + + TDVMCALL_IO is invoked to write I/O port. + + @param Port The I/O port to write. + @param Value The value to write to the I/O port. + + @return The value written the I/O port. + +**/ +UINT32 +EFIAPI +TdIoWrite32 ( + IN UINTN Port, + IN UINT32 Value + ); + +/** + Reads an 8-bit MMIO register. + + TDVMCALL_MMIO is invoked to read MMIO registers. + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT8 +EFIAPI +TdMmioRead8 ( + IN UINTN Address + ); + +/** + Writes an 8-bit MMIO register. + + TDVMCALL_MMIO is invoked to read write registers. + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + + @return Value. + +**/ +UINT8 +EFIAPI +TdMmioWrite8 ( + IN UINTN Address, + IN UINT8 Val + ); + +/** + Reads a 16-bit MMIO register. + + TDVMCALL_MMIO is invoked to read MMIO registers. + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT16 +EFIAPI +TdMmioRead16 ( + IN UINTN Address + ); + +/** + Writes a 16-bit MMIO register. + + TDVMCALL_MMIO is invoked to write MMIO registers. + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + + @return Value. + +**/ +UINT16 +EFIAPI +TdMmioWrite16 ( + IN UINTN Address, + IN UINT16 Val + ); + +/** + Reads a 32-bit MMIO register. + + TDVMCALL_MMIO is invoked to read MMIO registers. + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT32 +EFIAPI +TdMmioRead32 ( + IN UINTN Address + ); + +/** + Writes a 32-bit MMIO register. + + TDVMCALL_MMIO is invoked to write MMIO registers. + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + + @return Value. + +**/ +UINT32 +EFIAPI +TdMmioWrite32 ( + IN UINTN Address, + IN UINT32 Val + ); + +/** + Reads a 64-bit MMIO register. + + TDVMCALL_MMIO is invoked to read MMIO registers. + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT64 +EFIAPI +TdMmioRead64 ( + IN UINTN Address + ); + +/** + Writes a 64-bit MMIO register. + + TDVMCALL_MMIO is invoked to write MMIO registers. + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + +**/ +UINT64 +EFIAPI +TdMmioWrite64 ( + IN UINTN Address, + IN UINT64 Value + ); + +/** + Reads an 8-bit I/O port fifo into a block of memory in Tdx. + + Reads the 8-bit I/O fifo port specified by Port. + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +TdIoReadFifo8 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ); + +/** + Writes a block of memory into an 8-bit I/O port fifo in Tdx. + + Writes the 8-bit I/O fifo port specified by Port. + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to retrieve the write data from. + +**/ +VOID +EFIAPI +TdIoWriteFifo8 ( + IN UINTN Port, + IN UINTN Count, + IN VOID *Buffer + ); + +/** + Reads a 16-bit I/O port fifo into a block of memory in Tdx. + + Reads the 16-bit I/O fifo port specified by Port. + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +TdIoReadFifo16 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ); + +/** + Writes a block of memory into a 16-bit I/O port fifo in Tdx. + + Writes the 16-bit I/O fifo port specified by Port. + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to retrieve the write data from. + +**/ +VOID +EFIAPI +TdIoWriteFifo16 ( + IN UINTN Port, + IN UINTN Count, + IN VOID *Buffer + ); + +/** + Reads a 32-bit I/O port fifo into a block of memory in Tdx. + + Reads the 32-bit I/O fifo port specified by Port. + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +TdIoReadFifo32 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ); + +/** + Writes a block of memory into a 32-bit I/O port fifo in Tdx. + + Writes the 32-bit I/O fifo port specified by Port. + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to retrieve the write data from. + +**/ +VOID +EFIAPI +TdIoWriteFifo32 ( + IN UINTN Port, + IN UINTN Count, + IN VOID *Buffer + ); + +#endif --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85977): https://edk2.groups.io/g/devel/message/85977 Mute This Topic: https://groups.io/mt/88617498/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Apr 29 10:32:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+85978+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85978+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1642901865; cv=none; d=zohomail.com; s=zohoarc; b=ntyC0W/nMUYsqbQbalLswmkHparp3/4gB0zVDW8OqKx9IIvkJrjC+XMVSHbFFNE8CriVQaAGfxeYMbPMwMjdTbPjC1iLTHBybVh4fLpNquurF+KfsdsZDomBGEAGPphPVXIvNrLSF5F5w5arcW1xafs1f/5lR7sL8ZnwFni45eo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1642901865; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=kv1pBqm2LJAJfzrtiUegOq8AfBmZUZEm1eVx7fH2fWY=; b=O55SGKElxRa/xjxNt5Z3NMNMN30lxDPikj6eFJuu6wvhHY7z0Pil+nRW1Neg3/pBZcepB1BlvKzSQDQ80Ey8c/ZYuXRLFB4bb+F/sS40Y0trGmdi8jPWYONu6m8Esf8g4phnnQ0FWhDRCpQ2FtYW0J9n17xNEdBPTVG9Q288Ank= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85978+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1642901865599585.2286891211443; Sat, 22 Jan 2022 17:37:45 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id ULpTYY1788612xAge8wbkFCm; Sat, 22 Jan 2022 17:37:45 -0800 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web12.4557.1642901847770499599 for ; Sat, 22 Jan 2022 17:37:44 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10235"; a="243454771" X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="243454771" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:37:44 -0800 X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="695032972" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.255.30.84]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:37:41 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Michael D Kinney , Liming Gao , Zhiguang Liu , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann Subject: [edk2-devel] [PATCH V5 08/33] MdePkg: Support mmio for Tdx guest in BaseIoLibIntrinsic Date: Sun, 23 Jan 2022 09:36:39 +0800 Message-Id: <17f545da2f2c9ee6b2f8f3619d8abf2e2252e8cd.1642899774.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: gOleixa7Vp9p8qncjkVEfSN1x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1642901865; bh=AhoUjlVmIPwB0IP1iso7eLAArqnA23v1+p+L9U8vqUA=; h=Cc:Date:From:Reply-To:Subject:To; b=WrYlVwagA8cCvx6kReB3pj17f1eN/j9W3KkHx6vtdfKnjlpSWyYLlZWEyY0iaqnyHvU eeUcfiZCgT2TpRhVaQFndzW7dHMrd8Mlokb/hbSj6py10rfb1uz/LMtppkHjiEnUQlxVG 0jygSOv2W6npi8pJW/YvZSOGdpDhlyv5qGQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1642901866216100005 Content-Type: text/plain; charset="utf-8" RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 TDVF access MMIO with TDG.VP.VMCALL to invoke VMM provided emulation functions. If the access to MMIO fails, it fall backs to the direct access. BaseIoLibIntrinsic.inf is the IoLib used by other packages. It will not support I/O in Td guest. But some files are shared between BaseIoLibIntrinsic and BaseIoLibIntrinsicSev (IoLib.c is the example). So IoLibInternalTdxNull.c (which holds the null stub of the Td I/O routines) is included in BaseIoLibIntrinsic.inf. BaseIoLibIntrinsic.inf doesn't import TdxLib so that the Pkgs which include BaseIoLibIntrinsic.inf need not include TdxLib. Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Signed-off-by: Min Xu --- .../BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf | 2 + .../BaseIoLibIntrinsicSev.inf | 3 + MdePkg/Library/BaseIoLibIntrinsic/IoLib.c | 81 +++++++++++++++++-- 3 files changed, 78 insertions(+), 8 deletions(-) diff --git a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf b/Mde= Pkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf index 97eeada0656e..27b15d9ae256 100644 --- a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +++ b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf @@ -34,6 +34,8 @@ IoLibMmioBuffer.c BaseIoLibIntrinsicInternal.h IoHighLevel.c + IoLibInternalTdxNull.c + IoLibTdx.h =20 [Sources.IA32] IoLibGcc.c | GCC diff --git a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf b/= MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf index 336d79736d9a..a74e54bee8b5 100644 --- a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf +++ b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf @@ -30,17 +30,20 @@ IoLibMmioBuffer.c BaseIoLibIntrinsicInternal.h IoHighLevel.c + IoLibTdx.h =20 [Sources.IA32] IoLibGcc.c | GCC IoLibMsc.c | MSFT IoLib.c + IoLibInternalTdxNull.c Ia32/IoFifoSev.nasm =20 [Sources.X64] IoLibGcc.c | GCC IoLibMsc.c | MSFT IoLib.c + IoLibInternalTdx.c X64/IoFifoSev.nasm =20 [Packages] diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLib.c b/MdePkg/Library/Bas= eIoLibIntrinsic/IoLib.c index 9d42e21a691c..5bd02b56a1fa 100644 --- a/MdePkg/Library/BaseIoLibIntrinsic/IoLib.c +++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLib.c @@ -7,6 +7,7 @@ **/ =20 #include "BaseIoLibIntrinsicInternal.h" +#include "IoLibTdx.h" =20 /** Reads a 64-bit I/O port. @@ -69,6 +70,8 @@ IoWrite64 ( =20 If 8-bit MMIO register operations are not supported, then ASSERT(). =20 + For Td guest TDVMCALL_MMIO is invoked to read MMIO registers. + @param Address The MMIO register to read. =20 @return The value read. @@ -86,7 +89,13 @@ MmioRead8 ( Flag =3D FilterBeforeMmIoRead (FilterWidth8, Address, &Value); if (Flag) { MemoryFence (); - Value =3D *(volatile UINT8 *)Address; + + if (IsTdxGuest ()) { + Value =3D TdMmioRead8 (Address); + } else { + Value =3D *(volatile UINT8 *)Address; + } + MemoryFence (); } =20 @@ -104,6 +113,8 @@ MmioRead8 ( =20 If 8-bit MMIO register operations are not supported, then ASSERT(). =20 + For Td guest TDVMCALL_MMIO is invoked to write MMIO registers. + @param Address The MMIO register to write. @param Value The value to write to the MMIO register. =20 @@ -122,7 +133,13 @@ MmioWrite8 ( Flag =3D FilterBeforeMmIoWrite (FilterWidth8, Address, &Value); if (Flag) { MemoryFence (); - *(volatile UINT8 *)Address =3D Value; + + if (IsTdxGuest ()) { + TdMmioWrite8 (Address, Value); + } else { + *(volatile UINT8 *)Address =3D Value; + } + MemoryFence (); } =20 @@ -141,6 +158,8 @@ MmioWrite8 ( If 16-bit MMIO register operations are not supported, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). =20 + For Td guest TDVMCALL_MMIO is invoked to read MMIO registers. + @param Address The MMIO register to read. =20 @return The value read. @@ -159,7 +178,13 @@ MmioRead16 ( Flag =3D FilterBeforeMmIoRead (FilterWidth16, Address, &Value); if (Flag) { MemoryFence (); - Value =3D *(volatile UINT16 *)Address; + + if (IsTdxGuest ()) { + Value =3D TdMmioRead16 (Address); + } else { + Value =3D *(volatile UINT16 *)Address; + } + MemoryFence (); } =20 @@ -178,6 +203,8 @@ MmioRead16 ( If 16-bit MMIO register operations are not supported, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). =20 + For Td guest TDVMCALL_MMIO is invoked to write MMIO registers. + @param Address The MMIO register to write. @param Value The value to write to the MMIO register. =20 @@ -198,7 +225,13 @@ MmioWrite16 ( Flag =3D FilterBeforeMmIoWrite (FilterWidth16, Address, &Value); if (Flag) { MemoryFence (); - *(volatile UINT16 *)Address =3D Value; + + if (IsTdxGuest ()) { + TdMmioWrite16 (Address, Value); + } else { + *(volatile UINT16 *)Address =3D Value; + } + MemoryFence (); } =20 @@ -217,6 +250,8 @@ MmioWrite16 ( If 32-bit MMIO register operations are not supported, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). =20 + For Td guest TDVMCALL_MMIO is invoked to read MMIO registers. + @param Address The MMIO register to read. =20 @return The value read. @@ -236,7 +271,13 @@ MmioRead32 ( Flag =3D FilterBeforeMmIoRead (FilterWidth32, Address, &Value); if (Flag) { MemoryFence (); - Value =3D *(volatile UINT32 *)Address; + + if (IsTdxGuest ()) { + Value =3D TdMmioRead32 (Address); + } else { + Value =3D *(volatile UINT32 *)Address; + } + MemoryFence (); } =20 @@ -255,6 +296,8 @@ MmioRead32 ( If 32-bit MMIO register operations are not supported, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). =20 + For Td guest TDVMCALL_MMIO is invoked to write MMIO registers. + @param Address The MMIO register to write. @param Value The value to write to the MMIO register. =20 @@ -275,7 +318,13 @@ MmioWrite32 ( Flag =3D FilterBeforeMmIoWrite (FilterWidth32, Address, &Value); if (Flag) { MemoryFence (); - *(volatile UINT32 *)Address =3D Value; + + if (IsTdxGuest ()) { + TdMmioWrite32 (Address, Value); + } else { + *(volatile UINT32 *)Address =3D Value; + } + MemoryFence (); } =20 @@ -294,6 +343,8 @@ MmioWrite32 ( If 64-bit MMIO register operations are not supported, then ASSERT(). If Address is not aligned on a 64-bit boundary, then ASSERT(). =20 + For Td guest TDVMCALL_MMIO is invoked to read MMIO registers. + @param Address The MMIO register to read. =20 @return The value read. @@ -313,7 +364,13 @@ MmioRead64 ( Flag =3D FilterBeforeMmIoRead (FilterWidth64, Address, &Value); if (Flag) { MemoryFence (); - Value =3D *(volatile UINT64 *)Address; + + if (IsTdxGuest ()) { + Value =3D TdMmioRead64 (Address); + } else { + Value =3D *(volatile UINT64 *)Address; + } + MemoryFence (); } =20 @@ -332,6 +389,8 @@ MmioRead64 ( If 64-bit MMIO register operations are not supported, then ASSERT(). If Address is not aligned on a 64-bit boundary, then ASSERT(). =20 + For Td guest TDVMCALL_MMIO is invoked to write MMIO registers. + @param Address The MMIO register to write. @param Value The value to write to the MMIO register. =20 @@ -350,7 +409,13 @@ MmioWrite64 ( Flag =3D FilterBeforeMmIoWrite (FilterWidth64, Address, &Value); if (Flag) { MemoryFence (); - *(volatile UINT64 *)Address =3D Value; + + if (IsTdxGuest ()) { + TdMmioWrite64 (Address, Value); + } else { + *(volatile UINT64 *)Address =3D Value; + } + MemoryFence (); } =20 --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85978): https://edk2.groups.io/g/devel/message/85978 Mute This Topic: https://groups.io/mt/88617499/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Apr 29 10:32:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+85979+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85979+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1642901868; cv=none; d=zohomail.com; s=zohoarc; b=cQmnODl/k/TJ6SuwFhUjZV9KWCiauF24IpogMhXjbJvERNU9nZ8lZBv+mBGBr6cGG3EHJXT4XuqqJP6P2fUrgWxAPPNHl1QyjV4DwTLR+4wojOzjOPKPSZ8kj8r4US5+RKcLK808gDk/dSSw4ZJ9q0ZDAH1KDPNo/JzBnMtJ2tc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1642901868; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=HajYzu4PXHKtyy9bWj1DYu/4hmKc79Q3bNbVmg+zrN4=; b=EkhJ43issvICdOnuzHqTrnGO+Sp0nDwDvTTgfNqbU04kUUE2LcZqMcOc7uAUaaY1gWaI1jeW96L5A0YaUEDf6LdfN8SXfwHF5xp6PJ2dFPIWtz/gKY++Mxa3OQW9ughHLaiH6S53xiw8NSOgSOdfY81xTA0ozQcp+KbA9ByMjkI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85979+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1642901868849465.223522320279; Sat, 22 Jan 2022 17:37:48 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 0Lt3YY1788612xV7LhZiXc5n; Sat, 22 Jan 2022 17:37:48 -0800 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web12.4557.1642901847770499599 for ; Sat, 22 Jan 2022 17:37:48 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10235"; a="243454790" X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="243454790" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:37:47 -0800 X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="695032999" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.255.30.84]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:37:44 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Michael D Kinney , Liming Gao , Zhiguang Liu , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann Subject: [edk2-devel] [PATCH V5 09/33] MdePkg: Support IoFifo for Tdx guest in BaseIoLibIntrinsic Date: Sun, 23 Jan 2022 09:36:40 +0800 Message-Id: <90ec09409d82af158c4b081f9c0b27fb9edcf6ba.1642899774.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: UDq0lvutdm7SQJxRP7SgQ87Ex1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1642901868; bh=xVTHxDGkexomfo53CLYuqehGWCyG3r6uc6rJlSz5UI4=; h=Cc:Date:From:Reply-To:Subject:To; b=Q9GMdpiISlxJx4F+yjZWJqKF1plhRIkesJ4HpFVoKpE24hAhlx7ZYyqulvLVIevyAsi +SdUPz22+xCW48ooG3UBvAB8fQJgmpGdrJ4aN5tSHRP+IVDS8JX1G3iERofP89QvzidBz eJy0JpgmGjVxxgU5e2ur+cX+eL1wJtOMg6o= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1642901870344100001 Content-Type: text/plain; charset="utf-8" RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 Previously IoFifo functions are in X64/IoFifoSev.nasm which supports both SEV guest and Legacy guest. IoLibFifo.c is introduced to support SEV/TDX/Legacy guest in one binary. It checks the guest type in runtime and call corresponding functions then. Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Signed-off-by: Min Xu --- .../BaseIoLibIntrinsicSev.inf | 2 + MdePkg/Library/BaseIoLibIntrinsic/IoLibFifo.c | 216 ++++++++++++++++++ MdePkg/Library/BaseIoLibIntrinsic/IoLibSev.h | 166 ++++++++++++++ .../BaseIoLibIntrinsic/X64/IoFifoSev.nasm | 34 +-- 4 files changed, 401 insertions(+), 17 deletions(-) create mode 100644 MdePkg/Library/BaseIoLibIntrinsic/IoLibFifo.c create mode 100644 MdePkg/Library/BaseIoLibIntrinsic/IoLibSev.h diff --git a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf b/= MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf index a74e54bee8b5..7fe1c60f046e 100644 --- a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf +++ b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf @@ -31,6 +31,7 @@ BaseIoLibIntrinsicInternal.h IoHighLevel.c IoLibTdx.h + IoLibSev.h =20 [Sources.IA32] IoLibGcc.c | GCC @@ -44,6 +45,7 @@ IoLibMsc.c | MSFT IoLib.c IoLibInternalTdx.c + IoLibFifo.c X64/IoFifoSev.nasm =20 [Packages] diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibFifo.c b/MdePkg/Library= /BaseIoLibIntrinsic/IoLibFifo.c new file mode 100644 index 000000000000..08761a15a86c --- /dev/null +++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibFifo.c @@ -0,0 +1,216 @@ +/** @file + IoFifo read/write routines. + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "BaseIoLibIntrinsicInternal.h" +#include "IoLibSev.h" +#include "IoLibTdx.h" +#include + +/** + Reads an 8-bit I/O port fifo into a block of memory. + + Reads the 8-bit I/O fifo port specified by Port. + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + In TDX a serial of TdIoRead8 is invoked to read the I/O port fifo. + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +IoReadFifo8 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + if (IsTdxGuest ()) { + TdIoReadFifo8 (Port, Count, Buffer); + } else { + SevIoReadFifo8 (Port, Count, Buffer); + } +} + +/** + Writes a block of memory into an 8-bit I/O port fifo. + + Writes the 8-bit I/O fifo port specified by Port. + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + In TDX a serial of TdIoWrite8 is invoked to write data to the I/O port. + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to retrieve the write data from. + +**/ +VOID +EFIAPI +IoWriteFifo8 ( + IN UINTN Port, + IN UINTN Count, + IN VOID *Buffer + ) +{ + if (IsTdxGuest ()) { + TdIoWriteFifo8 (Port, Count, Buffer); + } else { + SevIoWriteFifo8 (Port, Count, Buffer); + } +} + +/** + Reads a 16-bit I/O port fifo into a block of memory. + + Reads the 16-bit I/O fifo port specified by Port. + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + + In TDX a serial of TdIoRead16 is invoked to read data from the I/O port. + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +IoReadFifo16 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + if (IsTdxGuest ()) { + TdIoReadFifo16 (Port, Count, Buffer); + } else { + SevIoReadFifo16 (Port, Count, Buffer); + } +} + +/** + Writes a block of memory into a 16-bit I/O port fifo. + + Writes the 16-bit I/O fifo port specified by Port. + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + + In TDX a serial of TdIoWrite16 is invoked to write data to the I/O port. + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to retrieve the write data from. + +**/ +VOID +EFIAPI +IoWriteFifo16 ( + IN UINTN Port, + IN UINTN Count, + IN VOID *Buffer + ) +{ + if (IsTdxGuest ()) { + TdIoWriteFifo16 (Port, Count, Buffer); + } else { + SevIoWriteFifo16 (Port, Count, Buffer); + } +} + +/** + Reads a 32-bit I/O port fifo into a block of memory. + + Reads the 32-bit I/O fifo port specified by Port. + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + + In TDX a serial of TdIoRead32 is invoked to read data from the I/O port. + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +IoReadFifo32 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + if (IsTdxGuest ()) { + TdIoReadFifo32 (Port, Count, Buffer); + } else { + SevIoReadFifo32 (Port, Count, Buffer); + } +} + +/** + Writes a block of memory into a 32-bit I/O port fifo. + + Writes the 32-bit I/O fifo port specified by Port. + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + + In TDX a serial of TdIoWrite32 is invoked to write data to the I/O port. + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to retrieve the write data from. + +**/ +VOID +EFIAPI +IoWriteFifo32 ( + IN UINTN Port, + IN UINTN Count, + IN VOID *Buffer + ) +{ + if (IsTdxGuest ()) { + TdIoWriteFifo32 (Port, Count, Buffer); + } else { + SevIoWriteFifo32 (Port, Count, Buffer); + } +} diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibSev.h b/MdePkg/Library/= BaseIoLibIntrinsic/IoLibSev.h new file mode 100644 index 000000000000..6d7cafcff27a --- /dev/null +++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibSev.h @@ -0,0 +1,166 @@ +/** @file + Header file for SEV IO library. + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef IOLIB_SEV_H_ +#define IOLIB_SEV_H_ + +#include + +#include +#include + +/** + Reads an 8-bit I/O port fifo into a block of memory. + + Reads the 8-bit I/O fifo port specified by Port. + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +SevIoReadFifo8 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ); + +/** + Writes a block of memory into an 8-bit I/O port fifo. + + Writes the 8-bit I/O fifo port specified by Port. + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to retrieve the write data from. + +**/ +VOID +EFIAPI +SevIoWriteFifo8 ( + IN UINTN Port, + IN UINTN Count, + IN VOID *Buffer + ); + +/** + Reads an 8-bit I/O port fifo into a block of memory. + + Reads the 8-bit I/O fifo port specified by Port. + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +SevIoReadFifo16 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ); + +/** + Writes a block of memory into an 8-bit I/O port fifo. + + Writes the 8-bit I/O fifo port specified by Port. + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to retrieve the write data from. + +**/ +VOID +EFIAPI +SevIoWriteFifo16 ( + IN UINTN Port, + IN UINTN Count, + IN VOID *Buffer + ); + +/** + Reads an 8-bit I/O port fifo into a block of memory. + + Reads the 8-bit I/O fifo port specified by Port. + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +SevIoReadFifo32 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ); + +/** + Writes a block of memory into an 8-bit I/O port fifo. + + Writes the 8-bit I/O fifo port specified by Port. + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to retrieve the write data from. + +**/ +VOID +EFIAPI +SevIoWriteFifo32 ( + IN UINTN Port, + IN UINTN Count, + IN VOID *Buffer + ); + +#endif diff --git a/MdePkg/Library/BaseIoLibIntrinsic/X64/IoFifoSev.nasm b/MdePkg/= Library/BaseIoLibIntrinsic/X64/IoFifoSev.nasm index 106f8881c55c..d02286b4d518 100644 --- a/MdePkg/Library/BaseIoLibIntrinsic/X64/IoFifoSev.nasm +++ b/MdePkg/Library/BaseIoLibIntrinsic/X64/IoFifoSev.nasm @@ -67,14 +67,14 @@ ASM_PFX(SevNoRepIo): ;-------------------------------------------------------------------------= ----- ; VOID ; EFIAPI -; IoReadFifo8 ( +; SevIoReadFifo8 ( ; IN UINTN Port, // rcx ; IN UINTN Size, // rdx ; OUT VOID *Buffer // r8 ; ); ;-------------------------------------------------------------------------= ----- -global ASM_PFX(IoReadFifo8) -ASM_PFX(IoReadFifo8): +global ASM_PFX(SevIoReadFifo8) +ASM_PFX(SevIoReadFifo8): xchg rcx, rdx xchg rdi, r8 ; rdi: buffer address; r8: save rdi =20 @@ -103,14 +103,14 @@ ASM_PFX(IoReadFifo8): ;-------------------------------------------------------------------------= ----- ; VOID ; EFIAPI -; IoReadFifo16 ( +; SevIoReadFifo16 ( ; IN UINTN Port, // rcx ; IN UINTN Size, // rdx ; OUT VOID *Buffer // r8 ; ); ;-------------------------------------------------------------------------= ----- -global ASM_PFX(IoReadFifo16) -ASM_PFX(IoReadFifo16): +global ASM_PFX(SevIoReadFifo16) +ASM_PFX(SevIoReadFifo16): xchg rcx, rdx xchg rdi, r8 ; rdi: buffer address; r8: save rdi =20 @@ -139,14 +139,14 @@ ASM_PFX(IoReadFifo16): ;-------------------------------------------------------------------------= ----- ; VOID ; EFIAPI -; IoReadFifo32 ( +; SevIoReadFifo32 ( ; IN UINTN Port, // rcx ; IN UINTN Size, // rdx ; OUT VOID *Buffer // r8 ; ); ;-------------------------------------------------------------------------= ----- -global ASM_PFX(IoReadFifo32) -ASM_PFX(IoReadFifo32): +global ASM_PFX(SevIoReadFifo32) +ASM_PFX(SevIoReadFifo32): xchg rcx, rdx xchg rdi, r8 ; rdi: buffer address; r8: save rdi =20 @@ -181,8 +181,8 @@ ASM_PFX(IoReadFifo32): ; IN VOID *Buffer // r8 ; ); ;-------------------------------------------------------------------------= ----- -global ASM_PFX(IoWriteFifo8) -ASM_PFX(IoWriteFifo8): +global ASM_PFX(SevIoWriteFifo8) +ASM_PFX(SevIoWriteFifo8): xchg rcx, rdx xchg rsi, r8 ; rsi: buffer address; r8: save rsi =20 @@ -211,14 +211,14 @@ ASM_PFX(IoWriteFifo8): ;-------------------------------------------------------------------------= ----- ; VOID ; EFIAPI -; IoWriteFifo16 ( +; SevIoWriteFifo16 ( ; IN UINTN Port, // rcx ; IN UINTN Size, // rdx ; IN VOID *Buffer // r8 ; ); ;-------------------------------------------------------------------------= ----- -global ASM_PFX(IoWriteFifo16) -ASM_PFX(IoWriteFifo16): +global ASM_PFX(SevIoWriteFifo16) +ASM_PFX(SevIoWriteFifo16): xchg rcx, rdx xchg rsi, r8 ; rsi: buffer address; r8: save rsi =20 @@ -247,14 +247,14 @@ ASM_PFX(IoWriteFifo16): ;-------------------------------------------------------------------------= ----- ; VOID ; EFIAPI -; IoWriteFifo32 ( +; SevIoWriteFifo32 ( ; IN UINTN Port, // rcx ; IN UINTN Size, // rdx ; IN VOID *Buffer // r8 ; ); ;-------------------------------------------------------------------------= ----- -global ASM_PFX(IoWriteFifo32) -ASM_PFX(IoWriteFifo32): +global ASM_PFX(SevIoWriteFifo32) +ASM_PFX(SevIoWriteFifo32): xchg rcx, rdx xchg rsi, r8 ; rsi: buffer address; r8: save rsi =20 --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85979): https://edk2.groups.io/g/devel/message/85979 Mute This Topic: https://groups.io/mt/88617502/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Apr 29 10:32:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+85980+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85980+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1642901871; cv=none; d=zohomail.com; s=zohoarc; b=BlZiiP9jFGkmGNREutrosRCp4awIb9DsRrCVaYJ2h/Stn83kvSSWc+f7DBKllXsHhOQ0JSJYRBbq0Q4I2DmWKPM6Z5carQ12/EJTjAXZF49tsVzFT+0zo7BrTrBAv0zBKoJxT4x1KKVEesV7xGdCMimEuha3efVMFI9sA/lwmwc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1642901871; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Ly9kgKEA34vNyyQxaZ8jVw1J0BJ7RlrT8/00MPdUwUk=; b=SKnNa3RP9ba80ETwYKtFzFAwsYttcmCRC75Q2x2bpJMhqokHeGiCObu2V/RxxRzT/9f6ADPAVy2cV783ynidtCQD0J2bK+8ZV+/hDw4I1vCKrR8dbOukPruJWRZq2Xa4KvQ2YUH5i3NpuTkPPuE0agE2biJR5AekfBDvNiXqGBE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85980+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1642901871857504.6395216142963; Sat, 22 Jan 2022 17:37:51 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id Vue3YY1788612xrePOprVo6s; Sat, 22 Jan 2022 17:37:51 -0800 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web12.4557.1642901847770499599 for ; Sat, 22 Jan 2022 17:37:50 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10235"; a="243454802" X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="243454802" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:37:50 -0800 X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="695033016" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.255.30.84]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:37:47 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Michael D Kinney , Liming Gao , Zhiguang Liu , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann Subject: [edk2-devel] [PATCH V5 10/33] MdePkg: Support IoRead/IoWrite for Tdx guest in BaseIoLibIntrinsic Date: Sun, 23 Jan 2022 09:36:41 +0800 Message-Id: In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: KvqdsirGaF2VhNGHxjAXgvcIx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1642901871; bh=DQDeHKOXZ7SIqT7ao7uUYyqtOQ6LgDpBLAG0O0Aratw=; h=Cc:Date:From:Reply-To:Subject:To; b=cfwVk77o1E6cVi8umRVS2ENmBCiDyLEBAsNCUYEB+v8jkdt0kv9aS9ANoifzIodbasj r9V7r00JFeg4T3aBuX3Yd7bv+OAsat0Ca/rFBw4Q19Cy2ILmq+yZjf1tJDZrOZCK+BfbW TBbZxKke/b1OaO25Bi/8Kr9vLa0kcVSHeME= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1642901872471100001 Content-Type: text/plain; charset="utf-8" RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 This commit supports IoRead/IoWrite for SEV/TDX/Legacy guest in one binary. It checks the guest type in runtime and then call corresponding functions. Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Signed-off-by: Min Xu --- MdePkg/Library/BaseIoLibIntrinsic/IoLibGcc.c | 51 ++++++++++++-- MdePkg/Library/BaseIoLibIntrinsic/IoLibMsc.c | 73 +++++++++++++++----- 2 files changed, 99 insertions(+), 25 deletions(-) diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibGcc.c b/MdePkg/Library/= BaseIoLibIntrinsic/IoLibGcc.c index 5c791289c469..05a739085967 100644 --- a/MdePkg/Library/BaseIoLibIntrinsic/IoLibGcc.c +++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibGcc.c @@ -16,6 +16,7 @@ **/ =20 #include "BaseIoLibIntrinsicInternal.h" +#include "IoLibTdx.h" =20 /** Reads an 8-bit I/O port. @@ -24,7 +25,9 @@ This function must guarantee that all I/O read and write operations are serialized. =20 - If 8-bit I/O port operations are not supported, then ASSERT(). + If 8-bit I/O port operations are not supported, then ASSERT() + + For Td guest TDVMCALL_IO is invoked to read I/O port. =20 @param Port The I/O port to read. =20 @@ -42,7 +45,11 @@ IoRead8 ( =20 Flag =3D FilterBeforeIoRead (FilterWidth8, Port, &Data); if (Flag) { - __asm__ __volatile__ ("inb %w1,%b0" : "=3Da" (Data) : "d" ((UINT16)Por= t)); + if (IsTdxGuest ()) { + Data =3D TdIoRead8 (Port); + } else { + __asm__ __volatile__ ("inb %w1,%b0" : "=3Da" (Data) : "d" ((UINT16)P= ort)); + } } =20 FilterAfterIoRead (FilterWidth8, Port, &Data); @@ -59,6 +66,8 @@ IoRead8 ( =20 If 8-bit I/O port operations are not supported, then ASSERT(). =20 + For Td guest TDVMCALL_IO is invoked to write I/O port. + @param Port The I/O port to write. @param Value The value to write to the I/O port. =20 @@ -76,7 +85,11 @@ IoWrite8 ( =20 Flag =3D FilterBeforeIoWrite (FilterWidth8, Port, &Value); if (Flag) { - __asm__ __volatile__ ("outb %b0,%w1" : : "a" (Value), "d" ((UINT16)Por= t)); + if (IsTdxGuest ()) { + TdIoWrite8 (Port, Value); + } else { + __asm__ __volatile__ ("outb %b0,%w1" : : "a" (Value), "d" ((UINT16)P= ort)); + } } =20 FilterAfterIoWrite (FilterWidth8, Port, &Value); @@ -94,6 +107,8 @@ IoWrite8 ( If 16-bit I/O port operations are not supported, then ASSERT(). If Port is not aligned on a 16-bit boundary, then ASSERT(). =20 + For Td guest TDVMCALL_IO is invoked to read I/O port. + @param Port The I/O port to read. =20 @return The value read. @@ -112,7 +127,11 @@ IoRead16 ( =20 Flag =3D FilterBeforeIoRead (FilterWidth16, Port, &Data); if (Flag) { - __asm__ __volatile__ ("inw %w1,%w0" : "=3Da" (Data) : "d" ((UINT16)Por= t)); + if (IsTdxGuest ()) { + Data =3D TdIoRead16 (Port); + } else { + __asm__ __volatile__ ("inw %w1,%w0" : "=3Da" (Data) : "d" ((UINT16)P= ort)); + } } =20 FilterAfterIoRead (FilterWidth16, Port, &Data); @@ -130,6 +149,8 @@ IoRead16 ( If 16-bit I/O port operations are not supported, then ASSERT(). If Port is not aligned on a 16-bit boundary, then ASSERT(). =20 + For Td guest TDVMCALL_IO is invoked to write I/O port. + @param Port The I/O port to write. @param Value The value to write to the I/O port. =20 @@ -149,7 +170,11 @@ IoWrite16 ( =20 Flag =3D FilterBeforeIoWrite (FilterWidth16, Port, &Value); if (Flag) { - __asm__ __volatile__ ("outw %w0,%w1" : : "a" (Value), "d" ((UINT16)Por= t)); + if (IsTdxGuest ()) { + TdIoWrite16 (Port, Value); + } else { + __asm__ __volatile__ ("outw %w0,%w1" : : "a" (Value), "d" ((UINT16)P= ort)); + } } =20 FilterAfterIoWrite (FilterWidth16, Port, &Value); @@ -167,6 +192,8 @@ IoWrite16 ( If 32-bit I/O port operations are not supported, then ASSERT(). If Port is not aligned on a 32-bit boundary, then ASSERT(). =20 + For Td guest TDVMCALL_IO is invoked to read I/O port. + @param Port The I/O port to read. =20 @return The value read. @@ -185,7 +212,11 @@ IoRead32 ( =20 Flag =3D FilterBeforeIoRead (FilterWidth32, Port, &Data); if (Flag) { - __asm__ __volatile__ ("inl %w1,%0" : "=3Da" (Data) : "d" ((UINT16)Port= )); + if (IsTdxGuest ()) { + Data =3D TdIoRead32 (Port); + } else { + __asm__ __volatile__ ("inl %w1,%0" : "=3Da" (Data) : "d" ((UINT16)Po= rt)); + } } =20 FilterAfterIoRead (FilterWidth32, Port, &Data); @@ -203,6 +234,8 @@ IoRead32 ( If 32-bit I/O port operations are not supported, then ASSERT(). If Port is not aligned on a 32-bit boundary, then ASSERT(). =20 + For Td guest TDVMCALL_IO is invoked to write I/O port. + @param Port The I/O port to write. @param Value The value to write to the I/O port. =20 @@ -222,7 +255,11 @@ IoWrite32 ( =20 Flag =3D FilterBeforeIoWrite (FilterWidth32, Port, &Value); if (Flag) { - __asm__ __volatile__ ("outl %0,%w1" : : "a" (Value), "d" ((UINT16)Port= )); + if (IsTdxGuest ()) { + TdIoWrite32 (Port, Value); + } else { + __asm__ __volatile__ ("outl %0,%w1" : : "a" (Value), "d" ((UINT16)Po= rt)); + } } =20 FilterAfterIoWrite (FilterWidth32, Port, &Value); diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibMsc.c b/MdePkg/Library/= BaseIoLibIntrinsic/IoLibMsc.c index 9f225a6b5d39..f1b7d51a7245 100644 --- a/MdePkg/Library/BaseIoLibIntrinsic/IoLibMsc.c +++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibMsc.c @@ -14,6 +14,7 @@ **/ =20 #include "BaseIoLibIntrinsicInternal.h" +#include "IoLibTdx.h" =20 // // Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics. @@ -82,6 +83,8 @@ _ReadWriteBarrier ( =20 If 8-bit I/O port operations are not supported, then ASSERT(). =20 + For Td guest TDVMCALL_IO is invoked to read I/O port. + @param Port The I/O port to read. =20 @return The value read. @@ -98,9 +101,13 @@ IoRead8 ( =20 Flag =3D FilterBeforeIoRead (FilterWidth8, Port, &Value); if (Flag) { - _ReadWriteBarrier (); - Value =3D (UINT8)_inp ((UINT16)Port); - _ReadWriteBarrier (); + if (IsTdxGuest ()) { + Value =3D TdIoRead8 (Port); + } else { + _ReadWriteBarrier (); + Value =3D (UINT8)_inp ((UINT16)Port); + _ReadWriteBarrier (); + } } =20 FilterAfterIoRead (FilterWidth8, Port, &Value); @@ -117,6 +124,8 @@ IoRead8 ( =20 If 8-bit I/O port operations are not supported, then ASSERT(). =20 + For Td guest TDVMCALL_IO is invoked to write I/O port. + @param Port The I/O port to write. @param Value The value to write to the I/O port. =20 @@ -134,9 +143,13 @@ IoWrite8 ( =20 Flag =3D FilterBeforeIoWrite (FilterWidth8, Port, &Value); if (Flag) { - _ReadWriteBarrier (); - (UINT8)_outp ((UINT16)Port, Value); - _ReadWriteBarrier (); + if (IsTdxGuest ()) { + TdIoWrite8 (Port, Value); + } else { + _ReadWriteBarrier (); + (UINT8)_outp ((UINT16)Port, Value); + _ReadWriteBarrier (); + } } =20 FilterAfterIoWrite (FilterWidth8, Port, &Value); @@ -154,6 +167,8 @@ IoWrite8 ( If 16-bit I/O port operations are not supported, then ASSERT(). If Port is not aligned on a 16-bit boundary, then ASSERT(). =20 + For Td guest TDVMCALL_IO is invoked to read I/O port. + @param Port The I/O port to read. =20 @return The value read. @@ -172,9 +187,13 @@ IoRead16 ( =20 Flag =3D FilterBeforeIoRead (FilterWidth16, Port, &Value); if (Flag) { - _ReadWriteBarrier (); - Value =3D _inpw ((UINT16)Port); - _ReadWriteBarrier (); + if (IsTdxGuest ()) { + Value =3D TdIoRead16 (Port); + } else { + _ReadWriteBarrier (); + Value =3D _inpw ((UINT16)Port); + _ReadWriteBarrier (); + } } =20 FilterBeforeIoRead (FilterWidth16, Port, &Value); @@ -192,6 +211,8 @@ IoRead16 ( If 16-bit I/O port operations are not supported, then ASSERT(). If Port is not aligned on a 16-bit boundary, then ASSERT(). =20 + For Td guest TDVMCALL_IO is invoked to write I/O port. + @param Port The I/O port to write. @param Value The value to write to the I/O port. =20 @@ -211,9 +232,13 @@ IoWrite16 ( =20 Flag =3D FilterBeforeIoWrite (FilterWidth16, Port, &Value); if (Flag) { - _ReadWriteBarrier (); - _outpw ((UINT16)Port, Value); - _ReadWriteBarrier (); + if (IsTdxGuest ()) { + TdIoWrite16 (Port, Value); + } else { + _ReadWriteBarrier (); + _outpw ((UINT16)Port, Value); + _ReadWriteBarrier (); + } } =20 FilterAfterIoWrite (FilterWidth16, Port, &Value); @@ -231,6 +256,8 @@ IoWrite16 ( If 32-bit I/O port operations are not supported, then ASSERT(). If Port is not aligned on a 32-bit boundary, then ASSERT(). =20 + For Td guest TDVMCALL_IO is invoked to read I/O port. + @param Port The I/O port to read. =20 @return The value read. @@ -249,9 +276,13 @@ IoRead32 ( =20 Flag =3D FilterBeforeIoRead (FilterWidth32, Port, &Value); if (Flag) { - _ReadWriteBarrier (); - Value =3D _inpd ((UINT16)Port); - _ReadWriteBarrier (); + if (IsTdxGuest ()) { + Value =3D TdIoRead32 (Port); + } else { + _ReadWriteBarrier (); + Value =3D _inpd ((UINT16)Port); + _ReadWriteBarrier (); + } } =20 FilterAfterIoRead (FilterWidth32, Port, &Value); @@ -269,6 +300,8 @@ IoRead32 ( If 32-bit I/O port operations are not supported, then ASSERT(). If Port is not aligned on a 32-bit boundary, then ASSERT(). =20 + For Td guest TDVMCALL_IO is invoked to write I/O port. + @param Port The I/O port to write. @param Value The value to write to the I/O port. =20 @@ -288,9 +321,13 @@ IoWrite32 ( =20 Flag =3D FilterBeforeIoWrite (FilterWidth32, Port, &Value); if (Flag) { - _ReadWriteBarrier (); - _outpd ((UINT16)Port, Value); - _ReadWriteBarrier (); + if (IsTdxGuest ()) { + TdIoWrite32 (Port, Value); + } else { + _ReadWriteBarrier (); + _outpd ((UINT16)Port, Value); + _ReadWriteBarrier (); + } } =20 FilterAfterIoWrite (FilterWidth32, Port, &Value); --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85980): https://edk2.groups.io/g/devel/message/85980 Mute This Topic: https://groups.io/mt/88617505/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Apr 29 10:32:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+85981+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85981+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1642901875; cv=none; d=zohomail.com; s=zohoarc; b=YcdvqPoqD799i05Ly4fPmfLJ6/MdntMcVskVl/uLsSFsuIWoE7tjO8cz6QqHZ7kRqwvtTpVseC79AiLi1cHE4axPBXFUJ2A+c/OGsR95KxBe/uRzeiLuezaMX49rV25/NrmeVegi4nEnrkaroouexpcBhRS9qxhsU67uJMvaUFE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1642901875; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=sfLlV296iykXFh6VG2y8IsyDJDxatTrYq1gPWfyc2cc=; b=g9PztUCboquEBnpS8wM9xx+75jMCxp7+zpTtoG1UKdx4JDljCghE1h8M/GTe8bnoQFYwtCOuP0/e52kMjymR4lbxX1iKKTlLpmGPnLBWFjcdYoLePWBRlSLsaX+VGal2ye3IVZ1nzDm/zRAr5tC2UAgsS7/qkApaSUzyg8YNWrI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85981+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1642901874816769.3453591762453; Sat, 22 Jan 2022 17:37:54 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id xxU9YY1788612xShm1B6FEho; Sat, 22 Jan 2022 17:37:54 -0800 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web12.4557.1642901847770499599 for ; Sat, 22 Jan 2022 17:37:53 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10235"; a="243454816" X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="243454816" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:37:53 -0800 X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="695033026" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.255.30.84]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:37:50 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Eric Dong , Ray Ni , Rahul Kumar , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann Subject: [edk2-devel] [PATCH V5 11/33] UefiCpuPkg: Support TDX in BaseXApicX2ApicLib Date: Sun, 23 Jan 2022 09:36:42 +0800 Message-Id: <0fdb911dd2c4d4502a89eb28a1841fc10a94e143.1642899774.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: 701NJteEdjU3LToacGFIasQvx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1642901874; bh=Rfpiz5K7sdl0SAUdybGf1D2r92YjuKEa0nRV3De3WOo=; h=Cc:Date:From:Reply-To:Subject:To; b=ir0Z7z+IyAbi3JxE8VD10V5URUOtXtxC7nssgGk11qTpEmto4W07m5VsZqyMFpRpWcL KdX7L4QCOYpcvN0+ykBEWjJ69slgEVVX0axuTi/DJ6ngWquaJ6NaskUoDLDUV5idC3g0y y48rHVPFyHPKGAaKwz7aQJK0snUifkatZnA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1642901876759100001 Content-Type: text/plain; charset="utf-8" RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 MSR is accessed in BaseXApicX2ApicLib. In TDX some MSRs are accessed directly from/to CPU. Some should be accessed via explicit requests from the host VMM using TDCALL(TDG.VP.VMCALL). This is done by the help of TdxLib. Please refer to [TDX] Section 18.1 TDX: https://software.intel.com/content/dam/develop/external/us/en/ documents/tdx-module-1.0-public-spec-v0.931.pdf Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Signed-off-by: Min Xu --- .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 160 +++++++++++++++++- 1 file changed, 152 insertions(+), 8 deletions(-) diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/U= efiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c index aaa42ff8450b..2d17177df12b 100644 --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c @@ -23,11 +23,155 @@ #include #include #include +#include =20 // // Library internal functions // =20 +/** + Some MSRs in TDX are accessed via TdCall. + Some are directly read/write from/to CPU. + + @param MsrIndex Index of the MSR + @retval TRUE MSR accessed via TdCall. + @retval FALSE MSR accessed not via TdCall. + +**/ +BOOLEAN +AccessMsrTdxCall ( + IN UINT32 MsrIndex + ) +{ + if (!TdIsEnabled ()) { + return FALSE; + } + + switch (MsrIndex) { + case MSR_IA32_X2APIC_TPR: + case MSR_IA32_X2APIC_PPR: + case MSR_IA32_X2APIC_EOI: + case MSR_IA32_X2APIC_ISR0: + case MSR_IA32_X2APIC_ISR1: + case MSR_IA32_X2APIC_ISR2: + case MSR_IA32_X2APIC_ISR3: + case MSR_IA32_X2APIC_ISR4: + case MSR_IA32_X2APIC_ISR5: + case MSR_IA32_X2APIC_ISR6: + case MSR_IA32_X2APIC_ISR7: + case MSR_IA32_X2APIC_TMR0: + case MSR_IA32_X2APIC_TMR1: + case MSR_IA32_X2APIC_TMR2: + case MSR_IA32_X2APIC_TMR3: + case MSR_IA32_X2APIC_TMR4: + case MSR_IA32_X2APIC_TMR5: + case MSR_IA32_X2APIC_TMR6: + case MSR_IA32_X2APIC_TMR7: + case MSR_IA32_X2APIC_IRR0: + case MSR_IA32_X2APIC_IRR1: + case MSR_IA32_X2APIC_IRR2: + case MSR_IA32_X2APIC_IRR3: + case MSR_IA32_X2APIC_IRR4: + case MSR_IA32_X2APIC_IRR5: + case MSR_IA32_X2APIC_IRR6: + case MSR_IA32_X2APIC_IRR7: + return FALSE; + default: + break; + } + + return TRUE; +} + +/** + Read MSR value. + + @param MsrIndex Index of the MSR to read + @retval 64-bit Value of MSR. + +**/ +UINT64 +LocalApicReadMsrReg64 ( + IN UINT32 MsrIndex + ) +{ + UINT64 Val; + UINT64 Status; + + if (AccessMsrTdxCall (MsrIndex)) { + Status =3D TdVmCall (TDVMCALL_RDMSR, (UINT64)MsrIndex, 0, 0, 0, &Val); + if (Status !=3D 0) { + TdVmCall (TDVMCALL_HALT, 0, 0, 0, 0, 0); + } + } else { + Val =3D AsmReadMsr64 (MsrIndex); + } + + return Val; +} + +/** + Write to MSR. + + @param MsrIndex Index of the MSR to write to + @param Value Value to be written to the MSR + + @return Value + +**/ +UINT64 +LocalApicWriteMsrReg64 ( + IN UINT32 MsrIndex, + IN UINT64 Value + ) +{ + UINT64 Status; + + if (AccessMsrTdxCall (MsrIndex)) { + Status =3D TdVmCall (TDVMCALL_WRMSR, (UINT64)MsrIndex, Value, 0, 0, 0); + if (Status !=3D 0) { + TdVmCall (TDVMCALL_HALT, 0, 0, 0, 0, 0); + } + } else { + AsmWriteMsr64 (MsrIndex, Value); + } + + return Value; +} + +/** + Read MSR value. + + @param MsrIndex Index of the MSR to read + @retval 32-bit Value of MSR. + +**/ +UINT32 +LocalApicReadMsrReg32 ( + IN UINT32 MsrIndex + ) +{ + return (UINT32)LocalApicReadMsrReg64 (MsrIndex); +} + +/** + Write to MSR. + + @param MsrIndex Index of the MSR to write to + @param Value Value to be written to the MSR + + @return Value + +**/ +UINT32 +LocalApicWriteMsrReg32 ( + IN UINT32 MsrIndex, + IN UINT32 Value + ) +{ + return (UINT32)LocalApicWriteMsrReg64 (MsrIndex, Value); +} + /** Determine if the CPU supports the Local APIC Base Address MSR. =20 @@ -78,7 +222,7 @@ GetLocalApicBaseAddress ( return PcdGet32 (PcdCpuLocalApicBaseAddress); } =20 - ApicBaseMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_APIC_BASE); + ApicBaseMsr.Uint64 =3D LocalApicReadMsrReg64 (MSR_IA32_APIC_BASE); =20 return (UINTN)(LShiftU64 ((UINT64)ApicBaseMsr.Bits.ApicBaseHi, 32)) + (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12); @@ -109,12 +253,12 @@ SetLocalApicBaseAddress ( return; } =20 - ApicBaseMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_APIC_BASE); + ApicBaseMsr.Uint64 =3D LocalApicReadMsrReg64 (MSR_IA32_APIC_BASE); =20 ApicBaseMsr.Bits.ApicBase =3D (UINT32)(BaseAddress >> 12); ApicBaseMsr.Bits.ApicBaseHi =3D (UINT32)(RShiftU64 ((UINT64)BaseAddress,= 32)); =20 - AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64); + LocalApicWriteMsrReg64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64); } =20 /** @@ -154,7 +298,7 @@ ReadLocalApicReg ( ASSERT (MmioOffset !=3D XAPIC_ICR_HIGH_OFFSET); =20 MsrIndex =3D (UINT32)(MmioOffset >> 4) + X2APIC_MSR_BASE_ADDRESS; - return AsmReadMsr32 (MsrIndex); + return LocalApicReadMsrReg32 (MsrIndex); } } =20 @@ -203,7 +347,7 @@ WriteLocalApicReg ( // Use memory fence here to force the serializing semantics to be cons= isent with xAPIC mode. // MemoryFence (); - AsmWriteMsr32 (MsrIndex, Value); + LocalApicWriteMsrReg32 (MsrIndex, Value); } } =20 @@ -309,7 +453,7 @@ GetApicMode ( return LOCAL_APIC_MODE_XAPIC; } =20 - ApicBaseMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_APIC_BASE); + ApicBaseMsr.Uint64 =3D LocalApicReadMsrReg64 (MSR_IA32_APIC_BASE); // // Local APIC should have been enabled // @@ -354,9 +498,9 @@ SetApicMode ( case LOCAL_APIC_MODE_XAPIC: break; case LOCAL_APIC_MODE_X2APIC: - ApicBaseMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_APIC_BASE); + ApicBaseMsr.Uint64 =3D LocalApicReadMsrReg64 (MSR_IA32_APIC_BAS= E); ApicBaseMsr.Bits.EXTD =3D 1; - AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64); + LocalApicWriteMsrReg64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64); break; default: ASSERT (FALSE); --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85981): https://edk2.groups.io/g/devel/message/85981 Mute This Topic: https://groups.io/mt/88617507/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Apr 29 10:32:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+85982+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85982+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1642901932; cv=none; d=zohomail.com; s=zohoarc; b=a2rfkQp+FfYyiaDrmSc6jDh0sWHqXxOksxgfLmFPYtduVwdagwoauh1M5y/r+58iVRFfyRaWRU3CYNYPhcZIifX+0iFY8LBXHYi5utt1zOLgUfDRPO1IGjyzbAOVIZJ4juIlcS8+uYLv8boF2Flig9ChTel5DZlwgKCAeFCYfT4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1642901932; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=b7di8pI9k4ZLDVyUmVJSns/mZVu0JiAnw0VaySKZ0jg=; b=Y3oQOtwKfsqeyKEZ6ICtN/rj2uCs2rxdUMG0Tr4M7NPW2jIT+flD8o72rbbxyyjRMx1zyUpumVmgPYYRqcRbV3Xg2/SoqRMfbmfbbeTcOTZjQbjslZHK26+LWlA3K2uqlLMNsr5UjBFwFfsqP+OI4DE0hN5pTvvRxhqNyI/r908= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85982+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1642901932497901.0660704802523; Sat, 22 Jan 2022 17:38:52 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id zZmJYY1788612xEnrhA9i3DN; Sat, 22 Jan 2022 17:38:52 -0800 X-Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web12.4573.1642901931649293959 for ; Sat, 22 Jan 2022 17:38:51 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10235"; a="244685988" X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="244685988" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:38:50 -0800 X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="695033148" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.255.30.84]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:38:47 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Michael Roth , Ray Ni , Rahul Kumar , Eric Dong , James Bottomley , Jiewen Yao , Tom Lendacky , Jordan Justen , Ard Biesheuvel , Erdem Aktas , Gerd Hoffmann Subject: [edk2-devel] [PATCH V5 12/33] MdePkg: Add macro to check SEV / TDX guest Date: Sun, 23 Jan 2022 09:36:43 +0800 Message-Id: In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: qYiB3rCyY7jktItSvvT2x38Hx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1642901932; bh=lHQ3hefy0a0YM3U2cmWYD6O1RaNxOhSKpuR7PIkjr4Q=; h=Cc:Date:From:Reply-To:Subject:To; b=S27qjU+yRhGFTk1GleCLka0/dMqzBlCFssn4RQi1cXWOlThAtASAkcwcIqOh/xEaXuR ZpaUVJ3tbRZ/10TnHv3PYNXy70T4aNLx4IOEIdJMkU2cHTQHZxTBHTISFxjPhPRqUN7nS ZbUewXFtgC+AtTbqPIYs6DJkhLlTPb1TiAM= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1642901933474100002 Content-Type: text/plain; charset="utf-8" RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 Add macros CC_GUEST_IS_SEV / CC_GUEST_IS_TDX to check SEV / TDX guest. Cc: Michael Roth Cc: Ray Ni Cc: Rahul Kumar Cc: Eric Dong Cc: James Bottomley Cc: Min Xu Cc: Jiewen Yao Cc: Tom Lendacky Cc: Jordan Justen Cc: Ard Biesheuvel Cc: Erdem Aktas Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Signed-off-by: Min Xu --- MdePkg/Include/ConfidentialComputingGuestAttr.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/MdePkg/Include/ConfidentialComputingGuestAttr.h b/MdePkg/Inclu= de/ConfidentialComputingGuestAttr.h index 6a1301801519..dd2541c6dcdf 100644 --- a/MdePkg/Include/ConfidentialComputingGuestAttr.h +++ b/MdePkg/Include/ConfidentialComputingGuestAttr.h @@ -22,4 +22,7 @@ typedef enum { CCAttrIntelTdx =3D 0x200, } CONFIDENTIAL_COMPUTING_GUEST_ATTR; =20 +#define CC_GUEST_IS_TDX(x) ((x) =3D=3D CCAttrIntelTdx) +#define CC_GUEST_IS_SEV(x) ((x) =3D=3D CCAttrAmdSev || (x) =3D=3D CCAttrA= mdSevEs || (x) =3D=3D CCAttrAmdSevSnp) + #endif --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85982): https://edk2.groups.io/g/devel/message/85982 Mute This Topic: https://groups.io/mt/88617523/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Apr 29 10:32:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+85983+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85983+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1642901935; cv=none; d=zohomail.com; s=zohoarc; b=P341fTIBwzWfcNt+jgVuTuZyg9xmh+5a5WoY8JXFQCHHKyzYXDiDYN7DIGbQ0WYZBhHodrRjW6C7XE3p0vHX62G2qlNbcRhtWsIlL7FM2YxmP2462NwLzjjDEQElEr0of9YOLvQY5CrbN5ci/dNx6IVoPNPPG7kbaL2qKNsD9g8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1642901935; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=uzKuVoBFSNaU4XcPBUun1Tbtejdz8i0cZukQqp7X6gc=; b=jtWVrwJFkEwwVm67eBKCxAhU4wIntKdgeMIcDATca3FzngGAMbCuvSb8/Hm8ru/Q2P6WQXgmnrYWqYQsRfcpUDwBbM+jSj/xJ4LOYgBRoXBehqdmhpABXQ6/KKekHKLPXgirhDqps8Q8hjyxVLdlltwMgngbRqfd5Mm5pew0L90= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85983+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1642901935178349.6309511297668; Sat, 22 Jan 2022 17:38:55 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id a6fKYY1788612xZbB9EaYc4i; Sat, 22 Jan 2022 17:38:54 -0800 X-Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web12.4573.1642901931649293959 for ; Sat, 22 Jan 2022 17:38:54 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10235"; a="244686001" X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="244686001" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:38:53 -0800 X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="695033154" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.255.30.84]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:38:50 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [PATCH V5 13/33] UefiCpuPkg: Enable Tdx support in MpInitLib Date: Sun, 23 Jan 2022 09:36:44 +0800 Message-Id: <49ded7d86f0beffca4501b2db01ebe9ceeef66a0.1642899774.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: GHwb4J4j8T113TEiiHpTBe8Fx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1642901934; bh=PFnFBzWBRePgs+a3rKKii+08XVRNd/z609jJjGC3e+Y=; h=Cc:Date:From:Reply-To:Subject:To; b=YxpGADnf4lxA4ZM9WCRNGQOfj/TEmT4yW/mto09zDFh/3YFyFJem43armH5JC1SPqKs YQDZmrOXVeLSTlaXQwfa8uayUyn+ybiww32m3/KIqmq0FGksQU/I/TnsucfSGt14csdSq G5dXrJMIKBh5tlmOpOYOVPBQzdNlFMDTlHw= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1642901935670100006 Content-Type: text/plain; charset="utf-8" RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 In TDVF BSP and APs are simplified. BSP is the vCPU-0, while the others are treated as APs. So MP intialization is rather simple. The processor info is retrieved by TDCALL, ApWorker is not supported, BSP is always the working processor, while the APs are just in a wait-for-precedure state. Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Signed-off-by: Min Xu --- UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf | 3 + UefiCpuPkg/Library/MpInitLib/DxeMpLib.c | 15 +- UefiCpuPkg/Library/MpInitLib/MpIntelTdx.h | 71 ++++++++++ UefiCpuPkg/Library/MpInitLib/MpLib.c | 27 ++++ UefiCpuPkg/Library/MpInitLib/MpLibTdx.c | 128 ++++++++++++++++++ UefiCpuPkg/Library/MpInitLib/MpLibTdxNull.c | 73 ++++++++++ UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf | 3 + 7 files changed, 319 insertions(+), 1 deletion(-) create mode 100644 UefiCpuPkg/Library/MpInitLib/MpIntelTdx.h create mode 100644 UefiCpuPkg/Library/MpInitLib/MpLibTdx.c create mode 100644 UefiCpuPkg/Library/MpInitLib/MpLibTdxNull.c diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf b/UefiCpuPkg/Lib= rary/MpInitLib/DxeMpInitLib.inf index e1cd0b350008..159b4d16ed0e 100644 --- a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf +++ b/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf @@ -24,10 +24,12 @@ [Sources.IA32] Ia32/AmdSev.c Ia32/MpFuncs.nasm + MpLibTdxNull.c =20 [Sources.X64] X64/AmdSev.c X64/MpFuncs.nasm + MpLibTdx.c =20 [Sources.common] AmdSev.c @@ -36,6 +38,7 @@ MpLib.c MpLib.h Microcode.c + MpIntelTdx.h =20 [Packages] MdePkg/MdePkg.dec diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c b/UefiCpuPkg/Library/M= pInitLib/DxeMpLib.c index 60d14a5a0e10..237cad8c5fd6 100644 --- a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c @@ -7,6 +7,7 @@ **/ =20 #include "MpLib.h" +#include "MpIntelTdx.h" =20 #include #include @@ -15,8 +16,8 @@ #include #include #include - #include +#include =20 #define AP_SAFE_STACK_SIZE 128 =20 @@ -824,6 +825,10 @@ MpInitLibStartupThisAP ( { EFI_STATUS Status; =20 + if (CC_GUEST_IS_TDX (PcdGet64 (PcdConfidentialComputingGuestAttr))) { + return EFI_UNSUPPORTED; + } + // // temporarily stop checkAllApsStatus for avoid resource dead-lock. // @@ -880,6 +885,10 @@ MpInitLibSwitchBSP ( EFI_TIMER_ARCH_PROTOCOL *Timer; UINT64 TimerPeriod; =20 + if (CC_GUEST_IS_TDX (PcdGet64 (PcdConfidentialComputingGuestAttr))) { + return EFI_UNSUPPORTED; + } + TimerPeriod =3D 0; // // Locate Timer Arch Protocol @@ -953,6 +962,10 @@ MpInitLibEnableDisableAP ( EFI_STATUS Status; BOOLEAN TempStopCheckState; =20 + if (CC_GUEST_IS_TDX (PcdGet64 (PcdConfidentialComputingGuestAttr))) { + return EFI_UNSUPPORTED; + } + TempStopCheckState =3D FALSE; // // temporarily stop checkAllAPsStatus for initialize parameters. diff --git a/UefiCpuPkg/Library/MpInitLib/MpIntelTdx.h b/UefiCpuPkg/Library= /MpInitLib/MpIntelTdx.h new file mode 100644 index 000000000000..b2136f466ce6 --- /dev/null +++ b/UefiCpuPkg/Library/MpInitLib/MpIntelTdx.h @@ -0,0 +1,71 @@ +/** @file + Intel Tdx header file. + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef MP_INTEL_TDX_H_ +#define MP_INTEL_TDX_H_ + +#include +#include +#include +#include +#include + +/** + Gets detailed MP-related information on the requested processor at the + instant this call is made. This service may only be called from the BSP. + + @param[in] ProcessorNumber The handle number of processor. + @param[out] ProcessorInfoBuffer A pointer to the buffer where informat= ion for + the requested processor is deposited. + @param[out] HealthData Return processor health data. + + @retval EFI_SUCCESS Processor information was returned. + @retval EFI_DEVICE_ERROR The calling processor is an AP. + @retval EFI_INVALID_PARAMETER ProcessorInfoBuffer is NULL. + @retval EFI_NOT_FOUND The processor with the handle specified = by + ProcessorNumber does not exist in the pl= atform. + @retval EFI_NOT_READY MP Initialize Library is not initialized. + +**/ +EFI_STATUS +EFIAPI +TdxMpInitLibGetProcessorInfo ( + IN UINTN ProcessorNumber, + OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer, + OUT EFI_HEALTH_FLAGS *HealthData OPTIONAL + ); + +/** + Retrieves the number of logical processor in the platform and the number= of + those logical processors that are enabled on this boot. This service may= only + be called from the BSP. + + @param[out] NumberOfProcessors Pointer to the total number of l= ogical + processors in the system, includ= ing the BSP + and disabled APs. + @param[out] NumberOfEnabledProcessors Pointer to the number of enabled= logical + processors that exist in system,= including + the BSP. + + @retval EFI_SUCCESS The number of logical processors and ena= bled + logical processors was retrieved. + @retval EFI_DEVICE_ERROR The calling processor is an AP. + @retval EFI_INVALID_PARAMETER NumberOfProcessors is NULL and NumberOfE= nabledProcessors + is NULL. + @retval EFI_NOT_READY MP Initialize Library is not initialized. + +**/ +EFI_STATUS +EFIAPI +TdxMpInitLibGetNumberOfProcessors ( + OUT UINTN *NumberOfProcessors, OPTIONAL + OUT UINTN *NumberOfEnabledProcessors OPTIONAL + ); + +#endif diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpIn= itLib/MpLib.c index 4a73787ee43a..de2ed8e6c294 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -9,9 +9,11 @@ **/ =20 #include "MpLib.h" +#include "MpIntelTdx.h" #include #include #include +#include =20 EFI_GUID mCpuInitMpLibHobGuid =3D CPU_INIT_MP_LIB_HOB_GUID; =20 @@ -1803,6 +1805,10 @@ MpInitLibInitialize ( UINTN BackupBufferAddr; UINTN ApIdtBase; =20 + if (CC_GUEST_IS_TDX (PcdGet64 (PcdConfidentialComputingGuestAttr))) { + return EFI_SUCCESS; + } + OldCpuMpData =3D GetCpuMpDataFromGuidedHob (); if (OldCpuMpData =3D=3D NULL) { MaxLogicalProcessorNumber =3D PcdGet32 (PcdCpuMaxLogicalProcessorNumbe= r); @@ -2073,6 +2079,10 @@ MpInitLibGetProcessorInfo ( CPU_INFO_IN_HOB *CpuInfoInHob; UINTN OriginalProcessorNumber; =20 + if (CC_GUEST_IS_TDX (PcdGet64 (PcdConfidentialComputingGuestAttr))) { + return TdxMpInitLibGetProcessorInfo (ProcessorNumber, ProcessorInfoBuf= fer, HealthData); + } + CpuMpData =3D GetCpuMpData (); CpuInfoInHob =3D (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob; =20 @@ -2307,6 +2317,10 @@ EnableDisableApWorker ( CPU_MP_DATA *CpuMpData; UINTN CallerNumber; =20 + if (CC_GUEST_IS_TDX (PcdGet64 (PcdConfidentialComputingGuestAttr))) { + return EFI_UNSUPPORTED; + } + CpuMpData =3D GetCpuMpData (); =20 // @@ -2367,6 +2381,11 @@ MpInitLibWhoAmI ( return EFI_INVALID_PARAMETER; } =20 + if (CC_GUEST_IS_TDX (PcdGet64 (PcdConfidentialComputingGuestAttr))) { + *ProcessorNumber =3D 0; + return EFI_SUCCESS; + } + CpuMpData =3D GetCpuMpData (); =20 return GetProcessorNumber (CpuMpData, ProcessorNumber); @@ -2405,6 +2424,10 @@ MpInitLibGetNumberOfProcessors ( UINTN EnabledProcessorNumber; UINTN Index; =20 + if (CC_GUEST_IS_TDX (PcdGet64 (PcdConfidentialComputingGuestAttr))) { + return TdxMpInitLibGetNumberOfProcessors (NumberOfProcessors, NumberOf= EnabledProcessors); + } + CpuMpData =3D GetCpuMpData (); =20 if ((NumberOfProcessors =3D=3D NULL) && (NumberOfEnabledProcessors =3D= =3D NULL)) { @@ -2490,6 +2513,10 @@ StartupAllCPUsWorker ( BOOLEAN HasEnabledAp; CPU_STATE ApState; =20 + if (CC_GUEST_IS_TDX (PcdGet64 (PcdConfidentialComputingGuestAttr))) { + return EFI_SUCCESS; + } + CpuMpData =3D GetCpuMpData (); =20 if (FailedCpuList !=3D NULL) { diff --git a/UefiCpuPkg/Library/MpInitLib/MpLibTdx.c b/UefiCpuPkg/Library/M= pInitLib/MpLibTdx.c new file mode 100644 index 000000000000..d31d043b20b7 --- /dev/null +++ b/UefiCpuPkg/Library/MpInitLib/MpLibTdx.c @@ -0,0 +1,128 @@ +/** @file + CPU MP Initialize Library common functions. + + Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.
+ Copyright (c) 2020, AMD Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "MpLib.h" +#include "MpIntelTdx.h" +#include +#include +#include +#include + +/** + Gets detailed MP-related information on the requested processor at the + instant this call is made. This service may only be called from the BSP. + + @param[in] ProcessorNumber The handle number of processor. + @param[out] ProcessorInfoBuffer A pointer to the buffer where informat= ion for + the requested processor is deposited. + @param[out] HealthData Return processor health data. + + @retval EFI_SUCCESS Processor information was returned. + @retval EFI_DEVICE_ERROR The calling processor is an AP. + @retval EFI_INVALID_PARAMETER ProcessorInfoBuffer is NULL. + @retval EFI_NOT_FOUND The processor with the handle specified = by + ProcessorNumber does not exist in the pl= atform. + @retval EFI_NOT_READY MP Initialize Library is not initialized. + +**/ +EFI_STATUS +EFIAPI +TdxMpInitLibGetProcessorInfo ( + IN UINTN ProcessorNumber, + OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer, + OUT EFI_HEALTH_FLAGS *HealthData OPTIONAL + ) +{ + EFI_STATUS Status; + TD_RETURN_DATA TdReturnData; + + if (ProcessorInfoBuffer =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + Status =3D TdCall (TDCALL_TDINFO, 0, 0, 0, &TdReturnData); + ASSERT (Status =3D=3D EFI_SUCCESS); + + if (ProcessorNumber >=3D TdReturnData.TdInfo.NumVcpus) { + return EFI_NOT_FOUND; + } + + ProcessorInfoBuffer->ProcessorId =3D ProcessorNumber; + ProcessorInfoBuffer->StatusFlag =3D 0; + if (ProcessorNumber =3D=3D 0) { + ProcessorInfoBuffer->StatusFlag |=3D PROCESSOR_AS_BSP_BIT; + } + + ProcessorInfoBuffer->StatusFlag |=3D PROCESSOR_ENABLED_BIT; + + // + // Get processor location information + // + GetProcessorLocationByApicId ( + (UINT32)ProcessorNumber, + &ProcessorInfoBuffer->Location.Package, + &ProcessorInfoBuffer->Location.Core, + &ProcessorInfoBuffer->Location.Thread + ); + + if (HealthData !=3D NULL) { + HealthData->Uint32 =3D 0; + } + + return Status; +} + +/** + Retrieves the number of logical processor in the platform and the number= of + those logical processors that are enabled on this boot. This service may= only + be called from the BSP. + + @param[out] NumberOfProcessors Pointer to the total number of l= ogical + processors in the system, includ= ing the BSP + and disabled APs. + @param[out] NumberOfEnabledProcessors Pointer to the number of enabled= logical + processors that exist in system,= including + the BSP. + + @retval EFI_SUCCESS The number of logical processors and ena= bled + logical processors was retrieved. + @retval EFI_DEVICE_ERROR The calling processor is an AP. + @retval EFI_INVALID_PARAMETER NumberOfProcessors is NULL and NumberOfE= nabledProcessors + is NULL. + @retval EFI_NOT_READY MP Initialize Library is not initialized. + +**/ +EFI_STATUS +EFIAPI +TdxMpInitLibGetNumberOfProcessors ( + OUT UINTN *NumberOfProcessors, OPTIONAL + OUT UINTN *NumberOfEnabledProcessors OPTIONAL + ) +{ + EFI_STATUS Status; + TD_RETURN_DATA TdReturnData; + + if ((NumberOfProcessors =3D=3D NULL) && (NumberOfEnabledProcessors =3D= =3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + Status =3D TdCall (TDCALL_TDINFO, 0, 0, 0, &TdReturnData); + ASSERT (Status =3D=3D EFI_SUCCESS); + + if (NumberOfProcessors !=3D NULL) { + *NumberOfProcessors =3D TdReturnData.TdInfo.NumVcpus; + } + + if (NumberOfEnabledProcessors !=3D NULL) { + *NumberOfEnabledProcessors =3D TdReturnData.TdInfo.MaxVcpus; + } + + return Status; +} diff --git a/UefiCpuPkg/Library/MpInitLib/MpLibTdxNull.c b/UefiCpuPkg/Libra= ry/MpInitLib/MpLibTdxNull.c new file mode 100644 index 000000000000..2849e13f2aaa --- /dev/null +++ b/UefiCpuPkg/Library/MpInitLib/MpLibTdxNull.c @@ -0,0 +1,73 @@ +/** @file + CPU MP Initialize Library common functions. + + Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.
+ Copyright (c) 2020, AMD Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "MpLib.h" +#include "MpIntelTdx.h" +#include + +/** + Gets detailed MP-related information on the requested processor at the + instant this call is made. This service may only be called from the BSP. + + @param[in] ProcessorNumber The handle number of processor. + @param[out] ProcessorInfoBuffer A pointer to the buffer where informat= ion for + the requested processor is deposited. + @param[out] HealthData Return processor health data. + + @retval EFI_SUCCESS Processor information was returned. + @retval EFI_DEVICE_ERROR The calling processor is an AP. + @retval EFI_INVALID_PARAMETER ProcessorInfoBuffer is NULL. + @retval EFI_NOT_FOUND The processor with the handle specified = by + ProcessorNumber does not exist in the pl= atform. + @retval EFI_NOT_READY MP Initialize Library is not initialized. + +**/ +EFI_STATUS +EFIAPI +TdxMpInitLibGetProcessorInfo ( + IN UINTN ProcessorNumber, + OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer, + OUT EFI_HEALTH_FLAGS *HealthData OPTIONAL + ) +{ + ASSERT (FALSE); + return EFI_UNSUPPORTED; +} + +/** + Retrieves the number of logical processor in the platform and the number= of + those logical processors that are enabled on this boot. This service may= only + be called from the BSP. + + @param[out] NumberOfProcessors Pointer to the total number of l= ogical + processors in the system, includ= ing the BSP + and disabled APs. + @param[out] NumberOfEnabledProcessors Pointer to the number of enabled= logical + processors that exist in system,= including + the BSP. + + @retval EFI_SUCCESS The number of logical processors and ena= bled + logical processors was retrieved. + @retval EFI_DEVICE_ERROR The calling processor is an AP. + @retval EFI_INVALID_PARAMETER NumberOfProcessors is NULL and NumberOfE= nabledProcessors + is NULL. + @retval EFI_NOT_READY MP Initialize Library is not initialized. + +**/ +EFI_STATUS +EFIAPI +TdxMpInitLibGetNumberOfProcessors ( + OUT UINTN *NumberOfProcessors, OPTIONAL + OUT UINTN *NumberOfEnabledProcessors OPTIONAL + ) +{ + ASSERT (FALSE); + return EFI_UNSUPPORTED; +} diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf b/UefiCpuPkg/Lib= rary/MpInitLib/PeiMpInitLib.inf index 5facf4db9499..894be0f8daab 100644 --- a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf +++ b/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf @@ -24,10 +24,12 @@ [Sources.IA32] Ia32/AmdSev.c Ia32/MpFuncs.nasm + MpLibTdxNull.c =20 [Sources.X64] X64/AmdSev.c X64/MpFuncs.nasm + MpLibTdx.c =20 [Sources.common] AmdSev.c @@ -36,6 +38,7 @@ MpLib.c MpLib.h Microcode.c + MpIntelTdx.h =20 [Packages] MdePkg/MdePkg.dec --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85983): https://edk2.groups.io/g/devel/message/85983 Mute This Topic: https://groups.io/mt/88617524/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Apr 29 10:32:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+85984+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85984+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1642901937; cv=none; d=zohomail.com; s=zohoarc; b=KGE5wCYrPuuEfawI93aWVo2AHH5g/IKkjOJmK7V/m3NBEDlUOUgkaZViH0udDvVn9IhiPccewHambR8pt+WVXlMlZsxY7vjeYRNRz7TEq3zIBr+xPrv6weW/Xuy+1AhLaJc7Re95VmqENiTU94mNDgX5LEaLhDlp5wSbdNAEDpo= ARC-Message-Signature: i=1; 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Sat, 22 Jan 2022 17:38:56 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10235"; a="244686012" X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="244686012" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:38:56 -0800 X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="695033162" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.255.30.84]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:38:54 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann Subject: [edk2-devel] [PATCH V5 14/33] OvmfPkg: Add IntelTdx.h in OvmfPkg/Include/IndustryStandard Date: Sun, 23 Jan 2022 09:36:45 +0800 Message-Id: <19a93ec6de906be8822d6fce1f3942a731d90ed5.1642899774.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: D7wlCMUelLBRcVVD8dA3b7Klx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1642901937; bh=CP2dMy4PkGRDOpJqsld3g7AMJkCU4x2bDlPUcJDTYXE=; h=Cc:Date:From:Reply-To:Subject:To; b=IrmnDQxwIZedqyP5rtwkxJ5ZqiW4ore6N773Fr1ULXoxOElFNIQ7HhKdfsslkY8Bu/j 4UQvV4rMQWXMtg7AGb4Y8ehJRmPdnd+JJWkG7l1VsqbHKR+7dFDBg25l2IXI4AKQ/StCq /amUbixxpHcx5irz0F0uJXFEeX4hnXe5hyA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1642901939724100011 Content-Type: text/plain; charset="utf-8" RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 IntelTdx.h defines the defitions used by TDX in OvmfPkg: - Mailbox related defitions,such as the data structure, command code, AP relocation defitions. - EFI_HOB_PLATFORM_INFO describes the TDX platform information See Table 5.44 Multiprocessor Wakeup Mailbox Structure in below link. https://uefi.org/specs/ACPI/6.4/05_ACPI_Software_Programming_Model/ ACPI_Software_Programming_Model.html#multiprocessor-wakeup-structure Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Signed-off-by: Min Xu Acked-by: Gerd Hoffmann --- OvmfPkg/Include/IndustryStandard/IntelTdx.h | 72 +++++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 OvmfPkg/Include/IndustryStandard/IntelTdx.h diff --git a/OvmfPkg/Include/IndustryStandard/IntelTdx.h b/OvmfPkg/Include/= IndustryStandard/IntelTdx.h new file mode 100644 index 000000000000..44155adefd58 --- /dev/null +++ b/OvmfPkg/Include/IndustryStandard/IntelTdx.h @@ -0,0 +1,72 @@ +/** @file + Defines the defitions used by TDX in OvmfPkg. + + Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef OVMF_INTEL_TDX_H_ +#define OVMF_INTEL_TDX_H_ + +#include +#include +#include +#include + +#define MP_CPU_PROTECTED_MODE_MAILBOX_APICID_INVALID 0xFFFFFFFF +#define MP_CPU_PROTECTED_MODE_MAILBOX_APICID_BROADCAST 0xFFFFFFFE + +typedef enum { + MpProtectedModeWakeupCommandNoop =3D 0, + MpProtectedModeWakeupCommandWakeup =3D 1, + MpProtectedModeWakeupCommandSleep =3D 2, + MpProtectedModeWakeupCommandAcceptPages =3D 3, +} MP_CPU_PROTECTED_MODE_WAKEUP_CMD; + +#pragma pack(1) + +// +// Describes the CPU MAILBOX control structure use to +// wakeup cpus spinning in long mode +// +typedef struct { + UINT16 Command; + UINT16 Resv; + UINT32 ApicId; + UINT64 WakeUpVector; + UINT8 ResvForOs[2032]; + // + // Arguments available for wakeup code + // + UINT64 WakeUpArgs1; + UINT64 WakeUpArgs2; + UINT64 WakeUpArgs3; + UINT64 WakeUpArgs4; + UINT8 Pad1[0xe0]; + UINT64 NumCpusArriving; + UINT8 Pad2[0xf8]; + UINT64 NumCpusExiting; + UINT32 Tallies[256]; + UINT8 Errors[256]; + UINT8 Pad3[0xf8]; +} MP_WAKEUP_MAILBOX; + +// +// AP relocation code information including code address and size, +// this structure will be shared be C code and assembly code. +// It is natural aligned by design. +// +typedef struct { + UINT8 *RelocateApLoopFuncAddress; + UINTN RelocateApLoopFuncSize; +} MP_RELOCATION_MAP; + +typedef struct { + EFI_HOB_GUID_TYPE GuidHeader; + UINT16 HostBridgePciDevId; +} EFI_HOB_PLATFORM_INFO; + +#pragma pack() + +#endif --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85984): https://edk2.groups.io/g/devel/message/85984 Mute This Topic: https://groups.io/mt/88617526/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Apr 29 10:32:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+85985+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85985+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1642901940; cv=none; d=zohomail.com; s=zohoarc; b=fbW6UWu0P6sh2FNfg1qDmDtF3dsNvXuZe3vCJJMAtQCZJL+s6qsLMH0GFEVsYL71hteynBFgTDjwkSjKdY5cvEduJWe2Lp8JH6lXj+9F2uZlxYq98JdJTkHZAZKcs2nE3FBMN9g1wbKsgYRAf5HhUYZdvJ7FgCaR0zjVBVwuVH8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1642901940; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=dRjyuOLi6lc3i+w+zhJmx1kZrH8i6s8FBhxrs8ndLXA=; b=PDO9u+tQGHH185AZ3vUseW7T/OSOa+3XuERf5IypYH6qDng2ok+S7Jo2/26hb3uGREfjiPa4D+2bE4XCzFZP4b4BFiMOJVpooLEhz+NSUne2oG+lHZ3s6iaRKh2RAFn8a+aCVXmsenpnX3cyNZqObvqWRa392saEgTj23w+hL/M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85985+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 16429019402942.896502052701294; Sat, 22 Jan 2022 17:39:00 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id OwMBYY1788612xm3uG8efa4k; Sat, 22 Jan 2022 17:38:59 -0800 X-Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web12.4573.1642901931649293959 for ; Sat, 22 Jan 2022 17:38:59 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10235"; a="244686023" X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="244686023" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:38:59 -0800 X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="695033180" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.255.30.84]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:38:56 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann Subject: [edk2-devel] [PATCH V5 15/33] OvmfPkg: Add TdxMailboxLib Date: Sun, 23 Jan 2022 09:36:46 +0800 Message-Id: <08e94e5704bfae864e14ab12744cd03ae9b4fbae.1642899774.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: VGlU5QL4iUxX6CO5yNOOkD9Fx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1642901939; bh=CUNvWHmYZFdhqwMz3lJ+wJtgdl3TKqUS002qNVsybDg=; h=Cc:Date:From:Reply-To:Subject:To; b=setkojWWREdWJvt/SU8U12DD+28PweqG3Rn0z2obiSMo/qTKEu/kBLySwidbZ1pehHV BLLHPPYXam2Gzx9cj6MpV6T/Cclo9dI+o9brhnkKXkFmFLTtE8X8EAYh+ttAr/QJ24cgO 0o4gxF0R4IbLsf+QFLGLTKIXtLbctHCrjkI= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1642901941937100001 Content-Type: text/plain; charset="utf-8" RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 In Tdx BSP may issues commands to APs for some task, for example, to accept pages paralelly. BSP also need to wait until all the APs have done the task. TdxMailboxLib wraps these common funtions for BSP. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Signed-off-by: Min Xu --- OvmfPkg/Include/Library/TdxMailboxLib.h | 76 ++++++++++ OvmfPkg/Library/TdxMailboxLib/TdxMailbox.c | 140 ++++++++++++++++++ .../Library/TdxMailboxLib/TdxMailboxLib.inf | 52 +++++++ .../Library/TdxMailboxLib/TdxMailboxNull.c | 85 +++++++++++ OvmfPkg/OvmfPkg.dec | 4 + 5 files changed, 357 insertions(+) create mode 100644 OvmfPkg/Include/Library/TdxMailboxLib.h create mode 100644 OvmfPkg/Library/TdxMailboxLib/TdxMailbox.c create mode 100644 OvmfPkg/Library/TdxMailboxLib/TdxMailboxLib.inf create mode 100644 OvmfPkg/Library/TdxMailboxLib/TdxMailboxNull.c diff --git a/OvmfPkg/Include/Library/TdxMailboxLib.h b/OvmfPkg/Include/Libr= ary/TdxMailboxLib.h new file mode 100644 index 000000000000..166cab43bc02 --- /dev/null +++ b/OvmfPkg/Include/Library/TdxMailboxLib.h @@ -0,0 +1,76 @@ +/** @file + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef TDX_MAILBOX_LIB_H_ +#define TDX_MAILBOX_LIB_H_ + +#include +#include +#include +#include +#include +#include + +/** + This function will be called by BSP to get the CPU number. + + @retval CPU number +**/ +UINT32 +EFIAPI +GetCpusNum ( + VOID + ); + +/** + Get the address of Td mailbox. +**/ +volatile VOID * +EFIAPI +GetTdxMailBox ( + VOID + ); + +/** + This function will be called by BSP to wakeup APs the are spinning on ma= ilbox + in protected mode + + @param[in] Command Command to send APs + @param[in] WakeupVector If used, address for APs to start executing + @param[in] WakeArgsX Args to pass to APs for excuting commands +**/ +VOID +EFIAPI +MpSendWakeupCommand ( + IN UINT16 Command, + IN UINT64 WakeupVector, + IN UINT64 WakeupArgs1, + IN UINT64 WakeupArgs2, + IN UINT64 WakeupArgs3, + IN UINT64 WakeupArgs4 + ); + +/** + BSP wait until all the APs arriving. It means the task triggered by BSP = is started. +**/ +VOID +EFIAPI +MpSerializeStart ( + VOID + ); + +/** + BSP wait until all the APs arriving. It means the task triggered by BSP = is ended. +**/ +VOID +EFIAPI +MpSerializeEnd ( + VOID + ); + +#endif diff --git a/OvmfPkg/Library/TdxMailboxLib/TdxMailbox.c b/OvmfPkg/Library/T= dxMailboxLib/TdxMailbox.c new file mode 100644 index 000000000000..13612dc141e3 --- /dev/null +++ b/OvmfPkg/Library/TdxMailboxLib/TdxMailbox.c @@ -0,0 +1,140 @@ +/** @file + + Copyright (c) 2008, Intel Corporation. All rights reserved.
+ (C) Copyright 2016 Hewlett Packard Enterprise Development LP
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +volatile VOID *mMailBox =3D NULL; +UINT32 mNumOfCpus =3D 0; + +/** + This function will be called by BSP to get the CPU number. + + @retval CPU number +**/ +UINT32 +EFIAPI +GetCpusNum ( + VOID + ) +{ + if (mNumOfCpus =3D=3D 0) { + mNumOfCpus =3D TdVCpuNum (); + } + + return mNumOfCpus; +} + +/** + Get the address of Td mailbox. +**/ +volatile VOID * +EFIAPI +GetTdxMailBox ( + VOID + ) +{ + if (mMailBox =3D=3D NULL) { + mMailBox =3D (VOID *)(UINTN)PcdGet32 (PcdOvmfSecGhcbBackupBase); + } + + return mMailBox; +} + +/** + This function will be called by BSP to wakeup APs the are spinning on ma= ilbox + in protected mode + + @param[in] Command Command to send APs + @param[in] WakeupVector If used, address for APs to start executing + @param[in] WakeArgsX Args to pass to APs for excuting commands +**/ +VOID +EFIAPI +MpSendWakeupCommand ( + IN UINT16 Command, + IN UINT64 WakeupVector, + IN UINT64 WakeupArgs1, + IN UINT64 WakeupArgs2, + IN UINT64 WakeupArgs3, + IN UINT64 WakeupArgs4 + ) +{ + volatile MP_WAKEUP_MAILBOX *MailBox; + + MailBox =3D (volatile MP_WAKEUP_MAILBOX *)GetTdxMailBox (); + MailBox->ApicId =3D MP_CPU_PROTECTED_MODE_MAILBOX_APICID_INVALID; + MailBox->WakeUpVector =3D 0; + MailBox->Command =3D MpProtectedModeWakeupCommandNoop; + MailBox->ApicId =3D MP_CPU_PROTECTED_MODE_MAILBOX_APICID_BROADCAST; + MailBox->WakeUpVector =3D WakeupVector; + MailBox->WakeUpArgs1 =3D WakeupArgs1; + MailBox->WakeUpArgs2 =3D WakeupArgs2; + MailBox->WakeUpArgs3 =3D WakeupArgs3; + MailBox->WakeUpArgs4 =3D WakeupArgs4; + AsmCpuid (0x01, NULL, NULL, NULL, NULL); + MailBox->Command =3D Command; + AsmCpuid (0x01, NULL, NULL, NULL, NULL); + return; +} + +/** + BSP wait until all the APs arriving. It means the task triggered by BSP = is started. +**/ +VOID +EFIAPI +MpSerializeStart ( + VOID + ) +{ + volatile MP_WAKEUP_MAILBOX *MailBox; + UINT32 NumOfCpus; + + NumOfCpus =3D GetCpusNum (); + MailBox =3D (volatile MP_WAKEUP_MAILBOX *)GetTdxMailBox (); + + DEBUG ((DEBUG_VERBOSE, "Waiting for APs to arriving. NumOfCpus=3D%d, Mai= lBox=3D%p\n", NumOfCpus, MailBox)); + while (MailBox->NumCpusArriving !=3D (NumOfCpus -1)) { + CpuPause (); + } + + DEBUG ((DEBUG_VERBOSE, "Releasing APs\n")); + MailBox->NumCpusExiting =3D NumOfCpus; + InterlockedIncrement ((UINT32 *)&MailBox->NumCpusArriving); +} + +/** + BSP wait until all the APs arriving. It means the task triggered by BSP = is ended. +**/ +VOID +EFIAPI +MpSerializeEnd ( + VOID + ) +{ + volatile MP_WAKEUP_MAILBOX *MailBox; + + MailBox =3D (volatile MP_WAKEUP_MAILBOX *)GetTdxMailBox (); + DEBUG ((DEBUG_VERBOSE, "Waiting for APs to finish\n")); + while (MailBox->NumCpusExiting !=3D 1 ) { + CpuPause (); + } + + DEBUG ((DEBUG_VERBOSE, "Restarting APs\n")); + MailBox->Command =3D MpProtectedModeWakeupCommandNoop; + MailBox->NumCpusArriving =3D 0; + InterlockedDecrement ((UINT32 *)&MailBox->NumCpusExiting); +} diff --git a/OvmfPkg/Library/TdxMailboxLib/TdxMailboxLib.inf b/OvmfPkg/Libr= ary/TdxMailboxLib/TdxMailboxLib.inf new file mode 100644 index 000000000000..3cf3690a16c7 --- /dev/null +++ b/OvmfPkg/Library/TdxMailboxLib/TdxMailboxLib.inf @@ -0,0 +1,52 @@ +#/** @file +# +# TBD +# +# Copyright (c) 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2008, Apple Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +#**/ + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D TdxMailboxLib + FILE_GUID =3D 2F81A9BA-748E-4519-BB11-A63A039D561E + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D TdxMailboxLib + +# +# VALID_ARCHITECTURES =3D X64 IA32 +# + +[Sources.IA32] + TdxMailboxNull.c + +[Sources.X64] + TdxMailbox.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + OvmfPkg/OvmfPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + PcdLib + UefiCpuLib + DebugAgentLib + IoLib + SynchronizationLib + MemoryAllocationLib + +[Guids] + +[Pcd] + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBackupBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBackupSize diff --git a/OvmfPkg/Library/TdxMailboxLib/TdxMailboxNull.c b/OvmfPkg/Libra= ry/TdxMailboxLib/TdxMailboxNull.c new file mode 100644 index 000000000000..35b070361eb1 --- /dev/null +++ b/OvmfPkg/Library/TdxMailboxLib/TdxMailboxNull.c @@ -0,0 +1,85 @@ +/** @file + + Copyright (c) 2008, Intel Corporation. All rights reserved.
+ (C) Copyright 2016 Hewlett Packard Enterprise Development LP
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include + +/** + This function will be called by BSP to get the CPU number. + + @retval CPU number +**/ +UINT32 +EFIAPI +GetCpusNum ( + VOID + ) +{ + ASSERT (FALSE); + return 0; +} + +/** + Get the address of Td mailbox. +**/ +volatile VOID * +EFIAPI +GetTdxMailBox ( + VOID + ) +{ + ASSERT (FALSE); + return (volatile VOID *)NULL; +} + +/** + This function will be called by BSP to wakeup APs the are spinning on ma= ilbox + in protected mode + + @param[in] Command Command to send APs + @param[in] WakeupVector If used, address for APs to start executing + @param[in] WakeArgsX Args to pass to APs for excuting commands +**/ +VOID +EFIAPI +MpSendWakeupCommand ( + IN UINT16 Command, + IN UINT64 WakeupVector, + IN UINT64 WakeupArgs1, + IN UINT64 WakeupArgs2, + IN UINT64 WakeupArgs3, + IN UINT64 WakeupArgs4 + ) +{ + ASSERT (FALSE); +} + +/** + BSP wait until all the APs arriving. It means the task triggered by BSP = is started. +**/ +VOID +EFIAPI +MpSerializeStart ( + VOID + ) +{ + ASSERT (FALSE); +} + +/** + BSP wait until all the APs arriving. It means the task triggered by BSP = is ended. +**/ +VOID +EFIAPI +MpSerializeEnd ( + VOID + ) +{ + ASSERT (FALSE); +} diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec index 769bef0ffa12..9fb4bcb48399 100644 --- a/OvmfPkg/OvmfPkg.dec +++ b/OvmfPkg/OvmfPkg.dec @@ -109,6 +109,10 @@ # XenPlatformLib|Include/Library/XenPlatformLib.h =20 + ## @libraryclass TdxMailboxLib + # + TdxMailboxLib|Include/Library/TdxMailboxLib.h + [Guids] gUefiOvmfPkgTokenSpaceGuid =3D {0x93bb96af, 0xb9f2, 0x4eb8, {= 0x94, 0x62, 0xe0, 0xba, 0x74, 0x56, 0x42, 0x36}} gEfiXenInfoGuid =3D {0xd3b46f3b, 0xd441, 0x1244, {= 0x9a, 0x12, 0x0, 0x12, 0x27, 0x3f, 0xc1, 0x4d}} --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85985): https://edk2.groups.io/g/devel/message/85985 Mute This Topic: https://groups.io/mt/88617527/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Apr 29 10:32:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+85986+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85986+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1642901942; cv=none; d=zohomail.com; s=zohoarc; b=XkeN9NrVOxc2Bb/ZUS5r0ytMwZT+2vgttgTeb3sV77o5LZ16oyXKwJEEpViN05gIr59f1jhxw0lcHSeEzoiueRv7NPcxOEtRZcry+BsIFfPT0ngM7AL2PsQeCeaZml+M1woWoAMdc6C8zcxxTOdbbGvinnVqQxx0CRptaFaOB+Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1642901942; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=B1+AwCNtnh8tBiJZcVWF2ZPPFgPYSV+S21ZT9gQ5zVE=; b=BeBV6w0+RApKs876yQQburwDUbLfm6BROEwx89SePQYbcy4vrDnFAlAaxQyZpVJlkBxnPYHVYs0bXjvodBJNUopz5RLu9aUpflwoNN4uK94WdFLdpAmGAcBYJjmIVatl/IOgihYDtlcs+WXYL/Yuft4tDNGu2ycPzl2gYiHMT6U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85986+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1642901942774845.4537595915292; Sat, 22 Jan 2022 17:39:02 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 5GEwYY1788612xUCoV4mAklc; Sat, 22 Jan 2022 17:39:02 -0800 X-Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web12.4573.1642901931649293959 for ; Sat, 22 Jan 2022 17:39:01 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10235"; a="244686036" X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="244686036" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:39:01 -0800 X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="695033189" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.255.30.84]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:38:59 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky Subject: [edk2-devel] [PATCH V5 16/33] MdePkg: Add EFI_RESOURCE_ATTRIBUTE_ENCRYPTED in PiHob.h Date: Sun, 23 Jan 2022 09:36:47 +0800 Message-Id: In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: 3NAIUztA5nrVCeOAMGnNf5r3x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1642901942; bh=NaMiJ3iWYlIpX4Yb27ww3jz7Wh/ta85ZhNm486SeQbI=; h=Cc:Date:From:Reply-To:Subject:To; b=Yf4bQpoVuKgEgD5Lmp4AGSPgVMxUH0YKGauIOfKeR96olCNrTfiiLpKSzF+XvjDlAtt FQil8pjcC7oHZsNeZY3cwKdMhGFu4ILUTxdMwt7xxxAqudhMhtZVR2d7r8818a/1i06fD TW8mzLr4bejLhEgnPRcs0vQxgXvq6oVjouU= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1642901944017100006 Content-Type: text/plain; charset="utf-8" RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 EFI_RESOURCE_ATTRIBUTE_ENCRYPTED is Physical memory encrypted attribute. It indicates the memory uses platform encrpytion capabilities for protection. If this bit is clear, the memory does not use platform encryption protection. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Signed-off-by: Min Xu --- MdePkg/Include/Pi/PiHob.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MdePkg/Include/Pi/PiHob.h b/MdePkg/Include/Pi/PiHob.h index e9f0ab4309d1..5bb7fc843112 100644 --- a/MdePkg/Include/Pi/PiHob.h +++ b/MdePkg/Include/Pi/PiHob.h @@ -296,6 +296,14 @@ typedef UINT32 EFI_RESOURCE_ATTRIBUTE_TYPE; // #define EFI_RESOURCE_ATTRIBUTE_MORE_RELIABLE 0x02000000 =20 +// +// Physical memory encrypted attribute. This +// memory uses platform encrpytion capabilities for +// protection. If this bit is clear, the memory does +// not use platform encryption protection +// +#define EFI_RESOURCE_ATTRIBUTE_ENCRYPTED 0x04000000 + /// /// Describes the resource properties of all fixed, /// nonrelocatable resource ranges found on the processor --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85986): https://edk2.groups.io/g/devel/message/85986 Mute This Topic: https://groups.io/mt/88617528/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Apr 29 10:32:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+85987+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85987+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1642901946; cv=none; d=zohomail.com; s=zohoarc; b=hpWcETU1g4oryPOrO8qG7BXUpQ290q5JbY+jEw8sMAa1ArZXdNmmPIeMBWiuCQwRin7cNteDX4b56PGq5V/TkFJVgXS0y5GbYvdJpc9E+pNOrbMGByOTnLroMfaHfpD5g6f+MbHBbL5v16fTaVfETL4dGAMl5wWftkDOYS+bIHw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1642901946; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=vRyElr43by5Mrm3GkM3o7JtCWvfdVPBz0zDmHFkuamw=; b=l9JmwgALHdG9wsdZBhv7AsdEoToZ/UEgalKPTjZKkqu+aFvz7nqCeDRw5UIq0HB7g6LLpDxPWTFMWCK+9JKDo1DGE99ROTsQfpuQYEM3cdfntpoOdFQmXC+R4zUe/nlPXPgdyzSFo1Y9kPoiM1dTAM3ogWRtzUXe5og51yIhink= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85987+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1642901946035677.4621631224245; Sat, 22 Jan 2022 17:39:06 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id D1wXYY1788612xVCF6eWmnPF; Sat, 22 Jan 2022 17:39:05 -0800 X-Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web12.4573.1642901931649293959 for ; Sat, 22 Jan 2022 17:39:05 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10235"; a="244686052" X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="244686052" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:39:04 -0800 X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="695033202" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.255.30.84]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:39:01 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann Subject: [edk2-devel] [PATCH V5 17/33] OvmfPkg: Update Sec to support Tdx Date: Sun, 23 Jan 2022 09:36:48 +0800 Message-Id: In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: FzmMLbrhcyT3Fz83nyse8U4Lx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1642901945; bh=Raz6HJSbUsLrZhJRtEEV1yP/bGHz5AxOfCQVGKGFRN4=; h=Cc:Date:From:Reply-To:Subject:To; b=eq4DC+I2p2y+Si7612xyiQPPziEcxkqc5t+MPr7rjOhsZ7dPDn2nb1rrLqQkYdmBnfD tFCyJju1TmIvErfHMg0ZumD+1l83BGcfK+3pzLCHBwJYIqGgp1xuWWTr06cg71IHJiur/ sVKm1dVHMzTnwjpbl96CrYISLSlnMMmYFSo= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1642901948291100003 Content-Type: text/plain; charset="utf-8" RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 There are below major changes in this commit. 1. SecEntry.nasm In TDX BSP and APs goes to the same entry point in SecEntry.nasm. BSP initialize the temporary stack and then jumps to SecMain, just as legacy Ovmf does. APs spin in a modified mailbox loop using initial mailbox structure. Its structure defition is in OvmfPkg/Include/IndustryStandard/IntelTdx.h. APs wait for command to see if the command is for me. If so execute the command. 2. Sec/SecMain.c When host VMM create the Td guest, the system memory informations are stored in TdHob, which is a memory region described in Tdx metadata. The system memory region in TdHob should be accepted before it can be accessed. So the major task of this patch is to process the TdHobList to accept the memory. After that TDVF follow the standard OVMF flow and jump to PEI phase. Note: In this patch it is BSP which accepts the pages. So there maybe boot performance issue. There are some mitigations to this issue, such as lazy accept, 2M accept page size, etc. We will re-visit here in the future. PcdTdxAcceptPageSize is added for page accepting. Currently TDX supports 4K and 2M accept page size. The default value is 4K. PcdUse1GPageTable is set to FALSE by default in OvmfPkgX64.dsc. It gives no chance for Intel TDX to support 1G page table. To support 1G page table this PCD is set to TRUE in OvmfPkgX64.dsc. TDX only works on X64, so the code is only valid in X64 arch. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Signed-off-by: Min Xu --- OvmfPkg/AmdSev/AmdSevX64.dsc | 1 + OvmfPkg/Bhyve/BhyveX64.dsc | 1 + OvmfPkg/CloudHv/CloudHvX64.dsc | 1 + OvmfPkg/Include/TdxCommondefs.inc | 51 +++ OvmfPkg/Microvm/MicrovmX64.dsc | 1 + OvmfPkg/OvmfPkg.dec | 3 + OvmfPkg/OvmfPkgIa32X64.dsc | 2 + OvmfPkg/OvmfPkgX64.dsc | 6 + OvmfPkg/OvmfXen.dsc | 1 + OvmfPkg/Sec/IntelTdx.c | 503 ++++++++++++++++++++++++++++++ OvmfPkg/Sec/IntelTdx.h | 46 +++ OvmfPkg/Sec/SecMain.c | 46 ++- OvmfPkg/Sec/SecMain.inf | 7 + OvmfPkg/Sec/X64/SecEntry.nasm | 82 +++++ 14 files changed, 745 insertions(+), 6 deletions(-) create mode 100644 OvmfPkg/Include/TdxCommondefs.inc create mode 100644 OvmfPkg/Sec/IntelTdx.c create mode 100644 OvmfPkg/Sec/IntelTdx.h diff --git a/OvmfPkg/AmdSev/AmdSevX64.dsc b/OvmfPkg/AmdSev/AmdSevX64.dsc index 04ae61cf69d8..648d3accd95c 100644 --- a/OvmfPkg/AmdSev/AmdSevX64.dsc +++ b/OvmfPkg/AmdSev/AmdSevX64.dsc @@ -208,6 +208,7 @@ [LibraryClasses.common] BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf VmgExitLib|OvmfPkg/Library/VmgExitLib/VmgExitLib.inf + TdxLib|MdePkg/Library/TdxLib/TdxLib.inf =20 [LibraryClasses.common.SEC] TimerLib|OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.inf diff --git a/OvmfPkg/Bhyve/BhyveX64.dsc b/OvmfPkg/Bhyve/BhyveX64.dsc index 5fa08bebd73c..656e407473bb 100644 --- a/OvmfPkg/Bhyve/BhyveX64.dsc +++ b/OvmfPkg/Bhyve/BhyveX64.dsc @@ -228,6 +228,7 @@ [LibraryClasses.common] BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf + TdxLib|MdePkg/Library/TdxLib/TdxLib.inf =20 [LibraryClasses.common.SEC] !ifdef $(DEBUG_ON_SERIAL_PORT) diff --git a/OvmfPkg/CloudHv/CloudHvX64.dsc b/OvmfPkg/CloudHv/CloudHvX64.dsc index 8ac9227c5f50..191dd2c5053f 100644 --- a/OvmfPkg/CloudHv/CloudHvX64.dsc +++ b/OvmfPkg/CloudHv/CloudHvX64.dsc @@ -237,6 +237,7 @@ [LibraryClasses.common] BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf VmgExitLib|OvmfPkg/Library/VmgExitLib/VmgExitLib.inf + TdxLib|MdePkg/Library/TdxLib/TdxLib.inf =20 [LibraryClasses.common.SEC] TimerLib|OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.inf diff --git a/OvmfPkg/Include/TdxCommondefs.inc b/OvmfPkg/Include/TdxCommond= efs.inc new file mode 100644 index 000000000000..970eac96592a --- /dev/null +++ b/OvmfPkg/Include/TdxCommondefs.inc @@ -0,0 +1,51 @@ +;-------------------------------------------------------------------------= ----- +; @file +; TDX Common defitions used by the APs in mailbox +; +; Copyright (c) 2021, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;-------------------------------------------------------------------------= ----- + +CommandOffset equ 00h +ApicidOffset equ 04h +WakeupVectorOffset equ 08h +OSArgsOffset equ 10h +FirmwareArgsOffset equ 800h +WakeupArgsRelocatedMailBox equ 800h +AcceptPageArgsPhysicalStart equ 800h +AcceptPageArgsPhysicalEnd equ 808h +AcceptPageArgsChunkSize equ 810h +AcceptPageArgsPageSize equ 818h +CpuArrivalOffset equ 900h +CpusExitingOffset equ 0a00h +TalliesOffset equ 0a08h +ErrorsOffset equ 0e08h + +SIZE_4KB equ 1000h +SIZE_2MB equ 200000h +SIZE_1GB equ 40000000h + +PAGE_ACCEPT_LEVEL_4K equ 0 +PAGE_ACCEPT_LEVEL_2M equ 1 +PAGE_ACCEPT_LEVEL_1G equ 2 + +TDX_PAGE_ALREADY_ACCEPTED equ 0x00000b0a +TDX_PAGE_SIZE_MISMATCH equ 0xc0000b0b + +; Errors of APs in Mailbox +ERROR_NON equ 0 +ERROR_INVALID_ACCEPT_PAGE_SIZE equ 1 +ERROR_ACCEPT_PAGE_ERROR equ 2 +ERROR_INVALID_FALLBACK_PAGE_LEVEL equ 3 + +MpProtectedModeWakeupCommandNoop equ 0 +MpProtectedModeWakeupCommandWakeup equ 1 +MpProtectedModeWakeupCommandSleep equ 2 +MpProtectedModeWakeupCommandAcceptPages equ 3 + +MailboxApicIdInvalid equ 0xffffffff +MailboxApicidBroadcast equ 0xfffffffe + +%define TDCALL_TDINFO 0x1 +%define TDCALL_TDACCEPTPAGE 0x6 diff --git a/OvmfPkg/Microvm/MicrovmX64.dsc b/OvmfPkg/Microvm/MicrovmX64.dsc index 1c2e600febee..c45e37dc7da0 100644 --- a/OvmfPkg/Microvm/MicrovmX64.dsc +++ b/OvmfPkg/Microvm/MicrovmX64.dsc @@ -232,6 +232,7 @@ PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatfor= mHookLibNull.inf FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf VirtioMmioDeviceLib|OvmfPkg/Library/VirtioMmioDeviceLib/VirtioMmioDevice= Lib.inf + TdxLib|MdePkg/Library/TdxLib/TdxLib.inf =20 [LibraryClasses.common.SEC] QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgSecLib.inf diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec index 9fb4bcb48399..0e55912c8711 100644 --- a/OvmfPkg/OvmfPkg.dec +++ b/OvmfPkg/OvmfPkg.dec @@ -373,6 +373,9 @@ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecValidatedStart|0|UINT32|0x62 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecValidatedEnd|0|UINT32|0x63 =20 + ## The Tdx accept page size. 0x1000(4k),0x200000(2M) + gUefiOvmfPkgTokenSpaceGuid.PcdTdxAcceptPageSize|0x1000|UINT32|0x64 + [PcdsDynamic, PcdsDynamicEx] gUefiOvmfPkgTokenSpaceGuid.PcdEmuVariableEvent|0|UINT64|2 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashVariablesEnable|FALSE|BOOLEAN|0x10 diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc index 0ce122ddb50c..57e8bfb6b80f 100644 --- a/OvmfPkg/OvmfPkgIa32X64.dsc +++ b/OvmfPkg/OvmfPkgIa32X64.dsc @@ -238,6 +238,8 @@ [LibraryClasses.common] BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf + TdxLib|MdePkg/Library/TdxLib/TdxLib.inf + TdxMailboxLib|OvmfPkg/Library/TdxMailboxLib/TdxMailboxLib.inf =20 [LibraryClasses.common.SEC] TimerLib|OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.inf diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index 4589adff388d..843f7a2e7bf6 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -238,6 +238,8 @@ [LibraryClasses.common] BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf VmgExitLib|OvmfPkg/Library/VmgExitLib/VmgExitLib.inf + TdxLib|MdePkg/Library/TdxLib/TdxLib.inf + TdxMailboxLib|OvmfPkg/Library/TdxMailboxLib/TdxMailboxLib.inf =20 [LibraryClasses.common.SEC] TimerLib|OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.inf @@ -557,6 +559,10 @@ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|0x100 gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|0x100 =20 + # + # TDX need 1G PageTable support + gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|TRUE + # # Network Pcds # diff --git a/OvmfPkg/OvmfXen.dsc b/OvmfPkg/OvmfXen.dsc index de0d30bfb807..61a03d626195 100644 --- a/OvmfPkg/OvmfXen.dsc +++ b/OvmfPkg/OvmfXen.dsc @@ -227,6 +227,7 @@ [LibraryClasses.common] BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf + TdxLib|MdePkg/Library/TdxLib/TdxLib.inf =20 [LibraryClasses.common.SEC] QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgSecLib.inf diff --git a/OvmfPkg/Sec/IntelTdx.c b/OvmfPkg/Sec/IntelTdx.c new file mode 100644 index 000000000000..9b9cd9a75483 --- /dev/null +++ b/OvmfPkg/Sec/IntelTdx.c @@ -0,0 +1,503 @@ +/** @file + + Copyright (c) 2008, Intel Corporation. All rights reserved.
+ (C) Copyright 2016 Hewlett Packard Enterprise Development LP
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "IntelTdx.h" + +#define ALIGNED_2MB_MASK 0x1fffff + +/** + Check TDX is enabled. + + @retval TRUE TDX is enabled + @retval FALSE TDX is not enabled +**/ +BOOLEAN +SecTdxIsEnabled ( + VOID + ) +{ + CONFIDENTIAL_COMPUTING_WORK_AREA_HEADER *CcWorkAreaHeader; + + CcWorkAreaHeader =3D (CONFIDENTIAL_COMPUTING_WORK_AREA_HEADER *)FixedPcd= Get32 (PcdOvmfWorkAreaBase); + return (CcWorkAreaHeader !=3D NULL && CcWorkAreaHeader->GuestType =3D=3D= GUEST_TYPE_INTEL_TDX); +} + +/** + This function will be called to accept pages. Only BSP accepts pages. + + TDCALL(ACCEPT_PAGE) supports the accept page size of 4k and 2M. To + simplify the implementation, the Memory to be accpeted is splitted + into 3 parts: + ----------------- <-- StartAddress1 (not 2M aligned) + | part 1 | Length1 < 2M + |---------------| <-- StartAddress2 (2M aligned) + | | Length2 =3D Integer multiples of 2M + | part 2 | + | | + |---------------| <-- StartAddress3 + | part 3 | Length3 < 2M + |---------------| + + @param[in] PhysicalAddress Start physical adress + @param[in] PhysicalEnd End physical address + + @retval EFI_SUCCESS Accept memory successfully + @retval Others Other errors as indicated +**/ +EFI_STATUS +EFIAPI +BspAcceptMemoryResourceRange ( + IN EFI_PHYSICAL_ADDRESS PhysicalAddress, + IN EFI_PHYSICAL_ADDRESS PhysicalEnd + ) +{ + EFI_STATUS Status; + UINT32 AcceptPageSize; + UINT64 StartAddress1; + UINT64 StartAddress2; + UINT64 StartAddress3; + UINT64 TotalLength; + UINT64 Length1; + UINT64 Length2; + UINT64 Length3; + UINT64 Pages; + + AcceptPageSize =3D FixedPcdGet32 (PcdTdxAcceptPageSize); + TotalLength =3D PhysicalEnd - PhysicalAddress; + StartAddress1 =3D 0; + StartAddress2 =3D 0; + StartAddress3 =3D 0; + Length1 =3D 0; + Length2 =3D 0; + Length3 =3D 0; + + if (TotalLength =3D=3D 0) { + return EFI_SUCCESS; + } + + if ((AcceptPageSize =3D=3D SIZE_4KB) || (TotalLength <=3D SIZE_2MB)) { + // + // if total length is less than 2M, then we accept pages in 4k + // + StartAddress2 =3D PhysicalAddress; + Length2 =3D PhysicalEnd - PhysicalAddress; + AcceptPageSize =3D SIZE_4KB; + } else if (AcceptPageSize =3D=3D SIZE_2MB) { + // + // Total length is bigger than 2M and Page Accept size 2M is supported. + // + if ((PhysicalAddress & ALIGNED_2MB_MASK) =3D=3D 0) { + // + // Start address is 2M aligned + // + StartAddress2 =3D PhysicalAddress; + Length2 =3D TotalLength & ~(UINT64)ALIGNED_2MB_MASK; + + if (TotalLength > Length2) { + // + // There is remaining part 3) + // + StartAddress3 =3D StartAddress2 + Length2; + Length3 =3D TotalLength - Length2; + ASSERT (Length3 < SIZE_2MB); + } + } else { + // + // Start address is not 2M aligned and total length is bigger than 2= M. + // + StartAddress1 =3D PhysicalAddress; + ASSERT (TotalLength > SIZE_2MB); + Length1 =3D SIZE_2MB - (PhysicalAddress & ALIGNED_2MB_MASK); + if (TotalLength - Length1 < SIZE_2MB) { + // + // The Part 2) length is less than 2MB, so let's accept all the + // memory in 4K + // + Length1 =3D TotalLength; + } else { + StartAddress2 =3D PhysicalAddress + Length1; + Length2 =3D (TotalLength - Length1) & ~(UINT64)ALIGNED_2MB_M= ASK; + Length3 =3D TotalLength - Length1 - Length2; + StartAddress3 =3D Length3 > 0 ? StartAddress2 + Length2 : 0; + ASSERT (Length3 < SIZE_2MB); + } + } + } + + DEBUG ((DEBUG_INFO, "TdAccept: 0x%llx - 0x%llx\n", PhysicalAddress, Tota= lLength)); + DEBUG ((DEBUG_INFO, " Part1: 0x%llx - 0x%llx\n", StartAddress1, Length= 1)); + DEBUG ((DEBUG_INFO, " Part2: 0x%llx - 0x%llx\n", StartAddress2, Length= 2)); + DEBUG ((DEBUG_INFO, " Part3: 0x%llx - 0x%llx\n", StartAddress3, Length= 3)); + DEBUG ((DEBUG_INFO, " Page : 0x%x\n", AcceptPageSize)); + + Status =3D EFI_SUCCESS; + if (Length1 > 0) { + Pages =3D Length1 / SIZE_4KB; + Status =3D TdAcceptPages (StartAddress1, Pages, SIZE_4KB); + if (EFI_ERROR (Status)) { + return Status; + } + } + + if (Length2 > 0) { + Pages =3D Length2 / AcceptPageSize; + Status =3D TdAcceptPages (StartAddress2, Pages, AcceptPageSize); + if (EFI_ERROR (Status)) { + return Status; + } + } + + if (Length3 > 0) { + Pages =3D Length3 / SIZE_4KB; + Status =3D TdAcceptPages (StartAddress3, Pages, SIZE_4KB); + ASSERT (!EFI_ERROR (Status)); + if (EFI_ERROR (Status)) { + return Status; + } + } + + return Status; +} + +/** + Check the value whether in the valid list. + + @param[in] Value A value + @param[in] ValidList A pointer to valid list + @param[in] ValidListLength Length of valid list + + @retval TRUE The value is in valid list. + @retval FALSE The value is not in valid list. + +**/ +BOOLEAN +EFIAPI +IsInValidList ( + IN UINT32 Value, + IN UINT32 *ValidList, + IN UINT32 ValidListLength + ) +{ + UINT32 index; + + if (ValidList =3D=3D NULL) { + return FALSE; + } + + for (index =3D 0; index < ValidListLength; index++) { + if (ValidList[index] =3D=3D Value) { + return TRUE; + } + } + + return FALSE; +} + +/** + Check the integrity of VMM Hob List. + + @param[in] VmmHobList A pointer to Hob List + + @retval TRUE The Hob List is valid. + @retval FALSE The Hob List is invalid. + +**/ +BOOLEAN +EFIAPI +ValidateHobList ( + IN CONST VOID *VmmHobList + ) +{ + EFI_PEI_HOB_POINTERS Hob; + UINT32 EFI_BOOT_MODE_LIST[12] =3D { + BOOT_WITH_FULL_CONFIGURATION, + BOOT_WITH_MINIMAL_CONFIGURATION, + BOOT_ASSUMING_NO_CONFIGURATION_CHANGES, + BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS, + BOOT_WITH_DEFAULT_SETTINGS, + BOOT_ON_S4_RESUME, + BOOT_ON_S5_RESUME, + BOOT_WITH_MFG_MODE_SETTINGS, + BOOT_ON_S2_RESUME, + BOOT_ON_S3_RESUME, + BOOT_ON_FLASH_UPDATE, + BOOT_IN_RECOVERY_MODE + }; + + UINT32 EFI_RESOURCE_TYPE_LIST[8] =3D { + EFI_RESOURCE_SYSTEM_MEMORY, + EFI_RESOURCE_MEMORY_MAPPED_IO, + EFI_RESOURCE_IO, + EFI_RESOURCE_FIRMWARE_DEVICE, + EFI_RESOURCE_MEMORY_MAPPED_IO_PORT, + EFI_RESOURCE_MEMORY_RESERVED, + EFI_RESOURCE_IO_RESERVED, + EFI_RESOURCE_MAX_MEMORY_TYPE + }; + + if (VmmHobList =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "HOB: HOB data pointer is NULL\n")); + return FALSE; + } + + Hob.Raw =3D (UINT8 *)VmmHobList; + + // + // Parse the HOB list until end of list or matching type is found. + // + while (!END_OF_HOB_LIST (Hob)) { + if (Hob.Header->Reserved !=3D (UINT32)0) { + DEBUG ((DEBUG_ERROR, "HOB: Hob header Reserved filed should be zero\= n")); + return FALSE; + } + + if (Hob.Header->HobLength =3D=3D 0) { + DEBUG ((DEBUG_ERROR, "HOB: Hob header LEANGTH should not be zero\n")= ); + return FALSE; + } + + switch (Hob.Header->HobType) { + case EFI_HOB_TYPE_HANDOFF: + if (Hob.Header->HobLength !=3D sizeof (EFI_HOB_HANDOFF_INFO_TABLE)= ) { + DEBUG ((DEBUG_ERROR, "HOB: Hob length is not equal corresponding= hob structure. Type: 0x%04x\n", EFI_HOB_TYPE_HANDOFF)); + return FALSE; + } + + if (IsInValidList (Hob.HandoffInformationTable->BootMode, EFI_BOOT= _MODE_LIST, 12) =3D=3D FALSE) { + DEBUG ((DEBUG_ERROR, "HOB: Unknow HandoffInformationTable BootMo= de type. Type: 0x%08x\n", Hob.HandoffInformationTable->BootMode)); + return FALSE; + } + + if ((Hob.HandoffInformationTable->EfiFreeMemoryTop % 4096) !=3D 0)= { + DEBUG ((DEBUG_ERROR, "HOB: HandoffInformationTable EfiFreeMemory= Top address must be 4-KB aligned to meet page restrictions of UEFI.\ + Address: 0x%016lx\n", Hob.HandoffInformatio= nTable->EfiFreeMemoryTop)); + return FALSE; + } + + break; + + case EFI_HOB_TYPE_RESOURCE_DESCRIPTOR: + if (Hob.Header->HobLength !=3D sizeof (EFI_HOB_RESOURCE_DESCRIPTOR= )) { + DEBUG ((DEBUG_ERROR, "HOB: Hob length is not equal corresponding= hob structure. Type: 0x%04x\n", EFI_HOB_TYPE_RESOURCE_DESCRIPTOR)); + return FALSE; + } + + if (IsInValidList (Hob.ResourceDescriptor->ResourceType, EFI_RESOU= RCE_TYPE_LIST, 8) =3D=3D FALSE) { + DEBUG ((DEBUG_ERROR, "HOB: Unknow ResourceDescriptor ResourceTyp= e type. Type: 0x%08x\n", Hob.ResourceDescriptor->ResourceType)); + return FALSE; + } + + if ((Hob.ResourceDescriptor->ResourceAttribute & (~(EFI_RESOURCE_A= TTRIBUTE_PRESENT | + EFI_RESOURCE_A= TTRIBUTE_INITIALIZED | + EFI_RESOURCE_A= TTRIBUTE_TESTED | + EFI_RESOURCE_A= TTRIBUTE_READ_PROTECTED | + EFI_RESOURCE_A= TTRIBUTE_WRITE_PROTECTED | + EFI_RESOURCE_A= TTRIBUTE_EXECUTION_PROTECTED | + EFI_RESOURCE_A= TTRIBUTE_PERSISTENT | + EFI_RESOURCE_A= TTRIBUTE_SINGLE_BIT_ECC | + EFI_RESOURCE_A= TTRIBUTE_MULTIPLE_BIT_ECC | + EFI_RESOURCE_A= TTRIBUTE_ECC_RESERVED_1 | + EFI_RESOURCE_A= TTRIBUTE_ECC_RESERVED_2 | + EFI_RESOURCE_A= TTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_A= TTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_A= TTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_A= TTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_A= TTRIBUTE_16_BIT_IO | + EFI_RESOURCE_A= TTRIBUTE_32_BIT_IO | + EFI_RESOURCE_A= TTRIBUTE_64_BIT_IO | + EFI_RESOURCE_A= TTRIBUTE_UNCACHED_EXPORTED | + EFI_RESOURCE_A= TTRIBUTE_READ_PROTECTABLE | + EFI_RESOURCE_A= TTRIBUTE_WRITE_PROTECTABLE | + EFI_RESOURCE_A= TTRIBUTE_EXECUTION_PROTECTABLE | + EFI_RESOURCE_A= TTRIBUTE_PERSISTABLE | + EFI_RESOURCE_A= TTRIBUTE_READ_ONLY_PROTECTED | + EFI_RESOURCE_A= TTRIBUTE_READ_ONLY_PROTECTABLE | + EFI_RESOURCE_A= TTRIBUTE_MORE_RELIABLE | + EFI_RESOURCE_A= TTRIBUTE_ENCRYPTED))) !=3D 0) + { + DEBUG ((DEBUG_ERROR, "HOB: Unknow ResourceDescriptor ResourceAtt= ribute type. Type: 0x%08x\n", Hob.ResourceDescriptor->ResourceAttribute)); + return FALSE; + } + + break; + + // EFI_HOB_GUID_TYPE is variable length data, so skip check + case EFI_HOB_TYPE_GUID_EXTENSION: + break; + + case EFI_HOB_TYPE_FV: + if (Hob.Header->HobLength !=3D sizeof (EFI_HOB_FIRMWARE_VOLUME)) { + DEBUG ((DEBUG_ERROR, "HOB: Hob length is not equal corresponding= hob structure. Type: 0x%04x\n", EFI_HOB_TYPE_FV)); + return FALSE; + } + + break; + + case EFI_HOB_TYPE_FV2: + if (Hob.Header->HobLength !=3D sizeof (EFI_HOB_FIRMWARE_VOLUME2)) { + DEBUG ((DEBUG_ERROR, "HOB: Hob length is not equal corresponding= hob structure. Type: 0x%04x\n", EFI_HOB_TYPE_FV2)); + return FALSE; + } + + break; + + case EFI_HOB_TYPE_FV3: + if (Hob.Header->HobLength !=3D sizeof (EFI_HOB_FIRMWARE_VOLUME3)) { + DEBUG ((DEBUG_ERROR, "HOB: Hob length is not equal corresponding= hob structure. Type: 0x%04x\n", EFI_HOB_TYPE_FV3)); + return FALSE; + } + + break; + + case EFI_HOB_TYPE_CPU: + if (Hob.Header->HobLength !=3D sizeof (EFI_HOB_CPU)) { + DEBUG ((DEBUG_ERROR, "HOB: Hob length is not equal corresponding= hob structure. Type: 0x%04x\n", EFI_HOB_TYPE_CPU)); + return FALSE; + } + + for (UINT32 index =3D 0; index < 6; index++) { + if (Hob.Cpu->Reserved[index] !=3D 0) { + DEBUG ((DEBUG_ERROR, "HOB: Cpu Reserved field will always be s= et to zero.\n")); + return FALSE; + } + } + + break; + + default: + DEBUG ((DEBUG_ERROR, "HOB: Hob type is not know. Type: 0x%04x\n", = Hob.Header->HobType)); + return FALSE; + } + + // Get next HOB + Hob.Raw =3D (UINT8 *)(Hob.Raw + Hob.Header->HobLength); + } + + return TRUE; +} + +/** + Processing the incoming HobList for the TDX + + Firmware must parse list, and accept the pages of memory before their ca= n be + use by the guest. + + @param[in] VmmHobList The Hoblist pass the firmware + + @retval EFI_SUCCESS Process the HobList successfully + @retval Others Other errors as indicated + +**/ +EFI_STATUS +EFIAPI +ProcessHobList ( + IN CONST VOID *VmmHobList + ) +{ + EFI_STATUS Status; + EFI_PEI_HOB_POINTERS Hob; + EFI_PHYSICAL_ADDRESS PhysicalEnd; + + Status =3D EFI_SUCCESS; + ASSERT (VmmHobList !=3D NULL); + Hob.Raw =3D (UINT8 *)VmmHobList; + + // + // Parse the HOB list until end of list or matching type is found. + // + while (!END_OF_HOB_LIST (Hob)) { + if (Hob.Header->HobType =3D=3D EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { + DEBUG ((DEBUG_INFO, "\nResourceType: 0x%x\n", Hob.ResourceDescriptor= ->ResourceType)); + + if (Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_SYSTEM_= MEMORY) { + DEBUG ((DEBUG_INFO, "ResourceAttribute: 0x%x\n", Hob.ResourceDescr= iptor->ResourceAttribute)); + DEBUG ((DEBUG_INFO, "PhysicalStart: 0x%llx\n", Hob.ResourceDescrip= tor->PhysicalStart)); + DEBUG ((DEBUG_INFO, "ResourceLength: 0x%llx\n", Hob.ResourceDescri= ptor->ResourceLength)); + DEBUG ((DEBUG_INFO, "Owner: %g\n\n", &Hob.ResourceDescriptor->Owne= r)); + + PhysicalEnd =3D Hob.ResourceDescriptor->PhysicalStart + Hob.Resour= ceDescriptor->ResourceLength; + + Status =3D BspAcceptMemoryResourceRange ( + Hob.ResourceDescriptor->PhysicalStart, + PhysicalEnd + ); + if (EFI_ERROR (Status)) { + break; + } + } + } + + Hob.Raw =3D GET_NEXT_HOB (Hob); + } + + return Status; +} + +/** + In Tdx guest, some information need to be passed from host VMM to guest + firmware. For example, the memory resource, etc. These information are + prepared by host VMM and put in HobList which is described in TdxMetadat= a. + + Information in HobList is treated as external input. From the security + perspective before it is consumed, it should be validated. + + @retval EFI_SUCCESS Successfully process the hoblist + @retval Others Other error as indicated +**/ +EFI_STATUS +EFIAPI +ProcessTdxHobList ( + VOID + ) +{ + EFI_STATUS Status; + VOID *TdHob; + TD_RETURN_DATA TdReturnData; + + TdHob =3D (VOID *)(UINTN)FixedPcdGet32 (PcdOvmfSecGhcbBase); + Status =3D TdCall (TDCALL_TDINFO, 0, 0, 0, &TdReturnData); + if (EFI_ERROR (Status)) { + return Status; + } + + DEBUG (( + DEBUG_INFO, + "Intel Tdx Started with (GPAW: %d, Cpus: %d)\n", + TdReturnData.TdInfo.Gpaw, + TdReturnData.TdInfo.NumVcpus + )); + + // + // Validate HobList + // + if (ValidateHobList (TdHob) =3D=3D FALSE) { + return EFI_INVALID_PARAMETER; + } + + // + // Process Hoblist to accept memory + // + Status =3D ProcessHobList (TdHob); + + return Status; +} diff --git a/OvmfPkg/Sec/IntelTdx.h b/OvmfPkg/Sec/IntelTdx.h new file mode 100644 index 000000000000..ddd09eff34cd --- /dev/null +++ b/OvmfPkg/Sec/IntelTdx.h @@ -0,0 +1,46 @@ +/** @file + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SEC_INTEL_TDX_H_ +#define SEC_INTEL_TDX_H_ + +#include +#include +#include +#include +#include + +/** + Check TDX is enabled. + + @retval TRUE TDX is enabled + @retval FALSE TDX is not enabled +**/ +BOOLEAN +SecTdxIsEnabled ( + VOID + ); + +/** + In Tdx guest, some information need to be passed from host VMM to guest + firmware. For example, the memory resource, etc. These information are + prepared by host VMM and put in HobList which is described in TdxMetadat= a. + + Information in HobList is treated as external input. From the security + perspective before it is consumed, it should be validated. + + @retval EFI_SUCCESS Successfully process the hoblist + @retval Others Other error as indicated +**/ +EFI_STATUS +EFIAPI +ProcessTdxHobList ( + VOID + ); + +#endif diff --git a/OvmfPkg/Sec/SecMain.c b/OvmfPkg/Sec/SecMain.c index 2c5561661ef3..e2f3ede93901 100644 --- a/OvmfPkg/Sec/SecMain.c +++ b/OvmfPkg/Sec/SecMain.c @@ -26,9 +26,11 @@ #include #include #include - +#include +#include #include =20 +#include "IntelTdx.h" #include "AmdSev.h" =20 #define SEC_IDT_ENTRY_COUNT 34 @@ -738,6 +740,20 @@ SecCoreStartupWithStack ( UINT32 Index; volatile UINT8 *Table; =20 + #if defined (MDE_CPU_X64) + if (SecTdxIsEnabled ()) { + // + // For Td guests, the memory map info is in TdHobLib. It should be pro= cessed + // first so that the memory is accepted. Otherwise access to the unacc= epted + // memory will trigger tripple fault. + // + if (ProcessTdxHobList () !=3D EFI_SUCCESS) { + CpuDeadLoop (); + } + } + + #endif + // // To ensure SMM can't be compromised on S3 resume, we must force re-ini= t of // the BaseExtractGuidedSectionLib. Since this is before library contruc= tors @@ -756,13 +772,20 @@ SecCoreStartupWithStack ( // we use a loop rather than CopyMem. // IdtTableInStack.PeiService =3D NULL; + for (Index =3D 0; Index < SEC_IDT_ENTRY_COUNT; Index++) { - UINT8 *Src; - UINT8 *Dst; - UINTN Byte; + // + // Declare the local variables that actually move the data elements as + // volatile to prevent the optimizer from replacing this function with + // the intrinsic memcpy() + // + CONST UINT8 *Src; + volatile UINT8 *Dst; + UINTN Byte; + + Src =3D (CONST UINT8 *)&mIdtEntryTemplate; + Dst =3D (volatile UINT8 *)&IdtTableInStack.IdtTable[Index]; =20 - Src =3D (UINT8 *)&mIdtEntryTemplate; - Dst =3D (UINT8 *)&IdtTableInStack.IdtTable[Index]; for (Byte =3D 0; Byte < sizeof (mIdtEntryTemplate); Byte++) { Dst[Byte] =3D Src[Byte]; } @@ -808,6 +831,17 @@ SecCoreStartupWithStack ( AsmEnableCache (); } =20 + #if defined (MDE_CPU_X64) + if (SecTdxIsEnabled ()) { + // + // InitializeCpuExceptionHandlers () should be called in Td guests so = that + // #VE exceptions can be handled correctly. + // + InitializeCpuExceptionHandlers (NULL); + } + + #endif + DEBUG (( DEBUG_INFO, "SecCoreStartupWithStack(0x%x, 0x%x)\n", diff --git a/OvmfPkg/Sec/SecMain.inf b/OvmfPkg/Sec/SecMain.inf index 95cf0025e100..230ee5e465b9 100644 --- a/OvmfPkg/Sec/SecMain.inf +++ b/OvmfPkg/Sec/SecMain.inf @@ -30,6 +30,7 @@ Ia32/SecEntry.nasm =20 [Sources.X64] + IntelTdx.c X64/SecEntry.nasm =20 [Packages] @@ -55,6 +56,9 @@ MemEncryptSevLib CpuExceptionHandlerLib =20 +[LibraryClasses.X64] + TdxLib + [Ppis] gEfiTemporaryRamSupportPpiGuid # PPI ALWAYS_PRODUCED =20 @@ -77,6 +81,9 @@ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecValidatedStart gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecValidatedEnd + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBackupBase + gUefiOvmfPkgTokenSpaceGuid.PcdTdxAcceptPageSize + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaBase =20 [FeaturePcd] gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire diff --git a/OvmfPkg/Sec/X64/SecEntry.nasm b/OvmfPkg/Sec/X64/SecEntry.nasm index 1cc680a70716..4528fec309a0 100644 --- a/OvmfPkg/Sec/X64/SecEntry.nasm +++ b/OvmfPkg/Sec/X64/SecEntry.nasm @@ -10,12 +10,17 @@ ;-------------------------------------------------------------------------= ----- =20 #include +%include "TdxCommondefs.inc" =20 DEFAULT REL SECTION .text =20 extern ASM_PFX(SecCoreStartupWithStack) =20 +%macro tdcall 0 + db 0x66, 0x0f, 0x01, 0xcc +%endmacro + ; ; SecCore Entry Point ; @@ -35,6 +40,32 @@ extern ASM_PFX(SecCoreStartupWithStack) global ASM_PFX(_ModuleEntryPoint) ASM_PFX(_ModuleEntryPoint): =20 + ; + ; Guest type is stored in OVMF_WORK_AREA + ; + %define OVMF_WORK_AREA FixedPcdGet32 (PcdOvmfWorkAreaBase) + %define VM_GUEST_TYPE_TDX 2 + mov eax, OVMF_WORK_AREA + cmp byte[eax], VM_GUEST_TYPE_TDX + jne InitStack + + mov rax, TDCALL_TDINFO + tdcall + + ; + ; R8 [31:0] NUM_VCPUS + ; [63:32] MAX_VCPUS + ; R9 [31:0] VCPU_INDEX + ; Td Guest set the VCPU0 as the BSP, others are the APs + ; APs jump to spinloop and get released by DXE's MpInitLib + ; + mov rax, r9 + and rax, 0xffff + test rax, rax + jne ParkAp + +InitStack: + ; ; Fill the temporary RAM with the initial stack value. ; The loop below will seed the heap as well, but that's harmless. @@ -67,3 +98,54 @@ ASM_PFX(_ModuleEntryPoint): sub rsp, 0x20 call ASM_PFX(SecCoreStartupWithStack) =20 + ; + ; Note: BSP never gets here. APs will be unblocked by DXE + ; + ; R8 [31:0] NUM_VCPUS + ; [63:32] MAX_VCPUS + ; R9 [31:0] VCPU_INDEX + ; +ParkAp: + + mov rbp, r9 + +.do_wait_loop: + mov rsp, FixedPcdGet32 (PcdOvmfSecGhcbBackupBase) + + ; + ; register itself in [rsp + CpuArrivalOffset] + ; + mov rax, 1 + lock xadd dword [rsp + CpuArrivalOffset], eax + inc eax + +.check_arrival_cnt: + cmp eax, r8d + je .check_command + mov eax, dword[rsp + CpuArrivalOffset] + jmp .check_arrival_cnt + +.check_command: + mov eax, dword[rsp + CommandOffset] + cmp eax, MpProtectedModeWakeupCommandNoop + je .check_command + + cmp eax, MpProtectedModeWakeupCommandWakeup + je .do_wakeup + + ; Don't support this command, so ignore + jmp .check_command + +.do_wakeup: + ; + ; BSP sets these variables before unblocking APs + ; RAX: WakeupVectorOffset + ; RBX: Relocated mailbox address + ; RBP: vCpuId + ; + mov rax, 0 + mov eax, dword[rsp + WakeupVectorOffset] + mov rbx, [rsp + WakeupArgsRelocatedMailBox] + nop + jmp rax + jmp $ --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85987): https://edk2.groups.io/g/devel/message/85987 Mute This Topic: https://groups.io/mt/88617529/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Apr 29 10:32:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+85988+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85988+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1642901948; cv=none; d=zohomail.com; s=zohoarc; b=WYNuDEzJYo86kRV9K/GU5pvOB3eBBNuSuZWZ/Qr8AIpMMpDjH1XcZKXU70UWD+Dkz/ksQ3k6b2guHXgcnXtRHoB8Rws33RD3HAHzr7/qjMaZeX9A9wY4MxtZ8iqUntcou2oBCnYtHP0LBEHszXOKawDVrIAdQqDC+g4jhK66eOY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1642901948; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=/+yMZUsgu7OiYUZUPsTxmdbnoaEZsLw/MLPXvH/WYKE=; b=VVAM+CB17ggISaPR+ERB6NK6uubMrld4B7B5LX0JBCaThi262GDrAF0PxHx02zVRdFm/vrQ6NeGkRf+Wt1IaEA//JLCKbgoo3kAVNnrzced1pDZWtU/iNMqVMKC/jp+xjj3DqxQYTsGc7GUoIRSxfmNaLep3rg9gjVLlT+8f1Dg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85988+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1642901948385943.1966053238177; Sat, 22 Jan 2022 17:39:08 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id ke3gYY1788612xqRfr21IyAQ; Sat, 22 Jan 2022 17:39:08 -0800 X-Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web12.4573.1642901931649293959 for ; Sat, 22 Jan 2022 17:39:07 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10235"; a="244686067" X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="244686067" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:39:07 -0800 X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="695033208" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.255.30.84]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:39:04 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann Subject: [edk2-devel] [PATCH V5 18/33] OvmfPkg: Check Tdx in QemuFwCfgPei to avoid DMA operation Date: Sun, 23 Jan 2022 09:36:49 +0800 Message-Id: <37a90fcfe15738c0b6e0edba59b6db48dc36681c.1642899774.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: 5bkkPxUPlGu0IjRr4YJzjkp3x1787277AA= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1642901948; bh=G07D/lhfq55tKoXEWUEK5R1CIEZYrhFoaUO7HqrevcM=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=Z5AdsGDBrUbyyc7smLWfhD3D3F6OTQwExMDXX9Odepxj75A+39FexlkO2LQUeChLz+V IDvjea+Z3aL8lEbAlINw7rqP7w9mHVhkm33Tu2aPS9uVpHPtEJbb+PrClc+H7+XpeNryu 15p3zQfOOdujwUyz8EMdJKABJW9+rLGFEko= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1642901950438100002 RFC=EF=BC=9A https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 If TDX is enabled then we do not support DMA operation in PEI phase. This is mainly because DMA in TDX guest requires using bounce buffer (which need to allocate dynamic memory and allocating a PAGE size'd buffer can be challenge in PEI phase). Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Signed-off-by: Min Xu --- .../QemuFwCfgLib/QemuFwCfgLibInternal.h | 11 +++++++ OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPei.c | 32 +++++++++++++++++++ .../Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf | 2 ++ 3 files changed, 45 insertions(+) diff --git a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLibInternal.h b/OvmfPkg/= Library/QemuFwCfgLib/QemuFwCfgLibInternal.h index 0b77cad1c030..6f7beb6ac1c7 100644 --- a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLibInternal.h +++ b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLibInternal.h @@ -59,4 +59,15 @@ InternalQemuFwCfgDmaBytes ( IN UINT32 Control ); =20 +/** + Check if it is Tdx guest + + @retval TRUE It is Tdx guest + @retval FALSE It is not Tdx guest +**/ +BOOLEAN +QemuFwCfgIsTdxGuest ( + VOID + ); + #endif diff --git a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPei.c b/OvmfPkg/Library/= QemuFwCfgLib/QemuFwCfgPei.c index f696fb7cacaa..b8230613dcea 100644 --- a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPei.c +++ b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPei.c @@ -14,12 +14,30 @@ #include #include #include +#include =20 #include "QemuFwCfgLibInternal.h" =20 STATIC BOOLEAN mQemuFwCfgSupported =3D FALSE; STATIC BOOLEAN mQemuFwCfgDmaSupported; =20 +/** + Check if it is Tdx guest + + @retval TRUE It is Tdx guest + @retval FALSE It is not Tdx guest +**/ +BOOLEAN +QemuFwCfgIsTdxGuest ( + VOID + ) +{ + CONFIDENTIAL_COMPUTING_WORK_AREA_HEADER *CcWorkAreaHeader; + + CcWorkAreaHeader =3D (CONFIDENTIAL_COMPUTING_WORK_AREA_HEADER *)FixedPcd= Get32 (PcdOvmfWorkAreaBase); + return (CcWorkAreaHeader !=3D NULL && CcWorkAreaHeader->GuestType =3D=3D= GUEST_TYPE_INTEL_TDX); +} + /** Returns a boolean indicating if the firmware configuration interface is available or not. @@ -81,6 +99,14 @@ QemuFwCfgInitialize ( // if (MemEncryptSevIsEnabled ()) { DEBUG ((DEBUG_INFO, "SEV: QemuFwCfg fallback to IO Port interface.\n= ")); + } else if (QemuFwCfgIsTdxGuest ()) { + // + // If TDX is enabled then we do not support DMA operations in PEI ph= ase. + // This is mainly because DMA in TDX guest requires using bounce buf= fer + // (which need to allocate dynamic memory and allocating a PAGE size= 'd + // buffer can be challenge in PEI phase) + // + DEBUG ((DEBUG_INFO, "TDX: QemuFwCfg fallback to IO Port interface.\n= ")); } else { mQemuFwCfgDmaSupported =3D TRUE; DEBUG ((DEBUG_INFO, "QemuFwCfg interface (DMA) is supported.\n")); @@ -163,6 +189,12 @@ InternalQemuFwCfgDmaBytes ( // ASSERT (!MemEncryptSevIsEnabled ()); =20 + // + // TDX does not support DMA operations in PEI stage, we should + // not have reached here. + // + ASSERT (!QemuFwCfgIsTdxGuest ()); + Access.Control =3D SwapBytes32 (Control); Access.Length =3D SwapBytes32 (Size); Access.Address =3D SwapBytes64 ((UINTN)Buffer); diff --git a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf b/OvmfPkg/Lib= rary/QemuFwCfgLib/QemuFwCfgPeiLib.inf index 9f9af7d03201..3910511880c9 100644 --- a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf +++ b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf @@ -43,3 +43,5 @@ MemoryAllocationLib MemEncryptSevLib =20 +[Pcd] + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaBase --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85988): https://edk2.groups.io/g/devel/message/85988 Mute This Topic: https://groups.io/mt/88617531/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Apr 29 10:32:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+85989+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85989+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1642901975; cv=none; d=zohomail.com; s=zohoarc; b=D5yrsjMmM/05updlsRyJ2ZKaQmKmm8ogGe2aYUac8LqKVS2VIY5nZbLDxm7zAmF1nrYz2tRO9VVHLLscOovQuMvSSAkwVKTKl0v+SVMJZsUBVljomLmmy95n8fwvrYu7zuvv22eonMdAoHi/kmkrw8ExcLBuFdFoq+4vQNxq0Rk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1642901975; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=GpCMUdr3qZqQ0wRqhV7ZF2qRWsMkxuvxAP/mFFdyIy4=; b=AZIW70uv4XPGOWXo4wG3TQJEORKemH9bQOYc3tynZc0a0ZvFbmAwRw8y+ygpSm2LbXCoIlY5+gx580LfUe9HDBDRC9fNDRKk672nA0EVtqXzVJhl3W4lOOizKx2eao78M40rqwc2/05jydnJeenKhpfS6c8kNbqC/LTDUS7i28w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85989+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 164290197594744.97296814751462; Sat, 22 Jan 2022 17:39:35 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id vEIBYY1788612xKYjm3hUppE; Sat, 22 Jan 2022 17:39:35 -0800 X-Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web11.4554.1642901975017978470 for ; Sat, 22 Jan 2022 17:39:35 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10235"; a="244686081" X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="244686081" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:39:09 -0800 X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="695033220" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.255.30.84]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:39:07 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Jian J Wang , Hao A Wu , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann Subject: [edk2-devel] [PATCH V5 19/33] MdeModulePkg: EFER should not be changed in TDX Date: Sun, 23 Jan 2022 09:36:50 +0800 Message-Id: <03c535b90c1590c9107e83c002d75c8c8c8edf21.1642899774.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: MYiIbBl779C2K0TRFwZH7sdWx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1642901975; bh=WKLuivrJ7RebsAt0fFB/GF2MEOJm+OOeyoXKsCl1iE4=; h=Cc:Date:From:Reply-To:Subject:To; b=KweivknF96CmW1nAnFhaYz37osIykSVIJf9C9Ieae77GVc+OSHdet1C3xj9Ekgt6RpN HCZgw8aw/QdgMdZh5NMUpW5iDYasuBdvWLAoH4Tt7gR+8l/9b1AhDh2bUDsOCSCC8z6Sr bZxonEKNXKbq/UUOdwQ1F+RUt0UWEKcGCds= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1642901977898100002 Content-Type: text/plain; charset="utf-8" RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 In TDX IA32_ERER is RO to host VMM. It could not be changed. PcdIa32EferChangeAllowed is added in MdeModulePkg.dec and it is to be set to FALSE in Tdx guest. Cc: Jian J Wang Cc: Hao A Wu Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Signed-off-by: Min Xu --- MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 1 + MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 7 +++++++ MdeModulePkg/MdeModulePkg.dec | 5 +++++ 3 files changed, 13 insertions(+) diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf b/MdeModulePkg/Core/Dx= eIplPeim/DxeIpl.inf index 19b8a4c8aefa..106b679b6bd0 100644 --- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf +++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf @@ -117,6 +117,7 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable ##= SOMETIMES_CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase ##= CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize ##= CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdIa32EferChangeAllowed ##= CONSUMES =20 [Pcd.IA32,Pcd.X64,Pcd.ARM,Pcd.AARCH64] gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack ## SOMETIM= ES_CONSUMES diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c b/MdeModulePk= g/Core/DxeIplPeim/X64/VirtualMemory.c index 0700f310b203..5c647c74e773 100644 --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c @@ -159,6 +159,13 @@ IsEnableNonExecNeeded ( return FALSE; } =20 + // + // Intel TDX sets this flag to FALSE. + // + if (!PcdGetBool (PcdIa32EferChangeAllowed)) { + return FALSE; + } + // // XD flag (BIT63) in page table entry is only valid if IA32_EFER.NXE is= set. // Features controlled by Following PCDs need this feature to be enabled. diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec index 463e889e9a68..453f2a74b11d 100644 --- a/MdeModulePkg/MdeModulePkg.dec +++ b/MdeModulePkg/MdeModulePkg.dec @@ -2138,6 +2138,11 @@ # @Prompt GHCB Pool Size gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize|0|UINT64|0x00030008 =20 + ## This dynamic PCD indicates if IA32_EFER can be changed. The default v= alue is TRUE but in + # Intel TDX change of IA32_EFER is not allowed. + # @Prompt The flag which indicates if IA32_EFER is allowed to be changed. + gEfiMdeModulePkgTokenSpaceGuid.PcdIa32EferChangeAllowed|TRUE|BOOLEAN|0x0= 0030009 + [PcdsDynamicEx] ## This dynamic PCD enables the default variable setting. # Its value is the default store ID value. The default value is zero as= Standard default. --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85989): https://edk2.groups.io/g/devel/message/85989 Mute This Topic: https://groups.io/mt/88617543/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Apr 29 10:32:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+85990+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85990+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1642901976; cv=none; d=zohomail.com; s=zohoarc; b=KF8DVaG/VCK2hSxNbYWtUkhy+/orN/c4Mm+dpDFvUEnCxSZ9z+FSbOB0jYffa0Nda/8XkNtm+MZ9JlW0JIxPbx8/Zp8MiJ3VjIde81N0PAMUevTBzzc959ZRL1FIppUEW0eTZJPfPHxdvxYAgm7Ygcw9yKMiuv4AEWXSTfrcR3E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1642901976; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=ZyABJ6UKaKsgT9mXF30YEgnr51bcDC1yCliypJ8gKcs=; b=GtelTpIMShdDx19LmmyJroEp/7l4TCjscTeI/Gf3S1Ff0rL9OvP+/u+k3RG8pvA0EdfcO9XKHcXRx2YKM03QHRqaEGYLvmWGbsZWZ1ga5hhQSJt7gQobhlrYve4ta2uSNWRUSdP0cHDQhNZnVhnj19z6Q7VuR6U7yebEW8SLcts= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85990+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1642901976508771.0484069051747; Sat, 22 Jan 2022 17:39:36 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id bip3YY1788612xyAnz0oghSH; Sat, 22 Jan 2022 17:39:36 -0800 X-Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web11.4554.1642901975017978470 for ; Sat, 22 Jan 2022 17:39:35 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10235"; a="244686087" X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="244686087" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:39:12 -0800 X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="695033232" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.255.30.84]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:39:10 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Jian J Wang , Hao A Wu , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann Subject: [edk2-devel] [PATCH V5 20/33] MdeModulePkg: Add PcdTdxSharedBitMask Date: Sun, 23 Jan 2022 09:36:51 +0800 Message-Id: In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: PqsuRjbXbSb9eBGqmc2UhIAix1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1642901976; bh=7hcEJMhx3vBctiDdwM5O2i1460peDMRbmIeRfQ4EVJM=; h=Cc:Date:From:Reply-To:Subject:To; b=MSTz4c2hFeOyF8l12dwp6kjeVU7SN2VH9tKeryLiJYZPbYOsylPZ27hTNmiXBOZONy7 LC/zOkM9EZVWqlOyqibijInb/WJvtL9ARu4+H3Gfq+jbHYlTBdu7o0n8t40VKhtYvrBDv vJG7VzzmCuQvnTmxbXvWo/5RqxOu3wNzlsQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1642901977918100003 Content-Type: text/plain; charset="utf-8" RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 Guest Physical Address (GPA) space in Td guest is divided into private and shared sub-spaces, determined by the SHARED bit of GPA. This PCD holds the shared bit mask. Its default value is 0 and it will be set in PlatformPei driver if it is of Td guest. Cc: Jian J Wang Cc: Hao A Wu Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Signed-off-by: Min Xu --- MdeModulePkg/MdeModulePkg.dec | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec index 453f2a74b11d..e90a7f38708c 100644 --- a/MdeModulePkg/MdeModulePkg.dec +++ b/MdeModulePkg/MdeModulePkg.dec @@ -2143,6 +2143,10 @@ # @Prompt The flag which indicates if IA32_EFER is allowed to be changed. gEfiMdeModulePkgTokenSpaceGuid.PcdIa32EferChangeAllowed|TRUE|BOOLEAN|0x0= 0030009 =20 + ## This PCD holds the shared bit mask for page table entries when Tdx is= enabled. + # @Prompt The shared bit mask when Intel Tdx is enabled. + gEfiMdeModulePkgTokenSpaceGuid.PcdTdxSharedBitMask|0x0|UINT64|0x0003000a + [PcdsDynamicEx] ## This dynamic PCD enables the default variable setting. # Its value is the default store ID value. The default value is zero as= Standard default. --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85990): https://edk2.groups.io/g/devel/message/85990 Mute This Topic: https://groups.io/mt/88617545/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Apr 29 10:32:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+85991+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85991+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1642901977; cv=none; d=zohomail.com; s=zohoarc; b=iVZluL8GlMGQAMw85V0PkTrBrWwt9wrV9QEhssEA3W2N8nFbxE2AQK8gc5anJ+gkc/qO+QINMs23vmEYItzQxs4ontRyB1ilKJpH6n0CKlYXHb2zB1nMMnHQzl4nyQeWdJ3gFib/R3KLj4KfcQiwK+AJFAWm9g6eQcWJOC1wXmA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1642901977; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=m/C9AHXUzQmefqxmDEotV0KdDX+2oc4Wf6/AZMYBLK4=; b=B6als2vgv0sakFeIED0tubY3nTEpak4bUa+wy6lnyQybRRE4GgIdoVz32fRxpxLYmyY1pL+637xvwtE0b5PCGcNRu/27R0YUiBw/JwfK4jDcsvvr1glHaH5MpL6xqKod5oas9PU9pMys60nn0VrabhFT4SuEZcUqxTRnT9b1opE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85991+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 164290197723990.8790010796422; Sat, 22 Jan 2022 17:39:37 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id hL6RYY1788612xLcT2aPmRzj; Sat, 22 Jan 2022 17:39:36 -0800 X-Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web08.4550.1642901975552765292 for ; Sat, 22 Jan 2022 17:39:35 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10235"; a="244686089" X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="244686089" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:39:15 -0800 X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="695033244" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.255.30.84]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:39:12 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [PATCH V5 21/33] UefiCpuPkg: Update AddressEncMask in CpuPageTable Date: Sun, 23 Jan 2022 09:36:52 +0800 Message-Id: <9215e23326338dbe0896266e18122b7618597ffb.1642899774.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: FJtxyQEWTU6KTqfZqHZ5WQ2Ix1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1642901976; bh=fAgSrK0LzmdsHJVYcF97aR8SUQ/q/K+BbgrqtC5du1o=; h=Cc:Date:From:Reply-To:Subject:To; b=fFWFo0THPMRLWXvbmDXFTJJgdlWo9exeue/G8Jpg0FKD12Dmml3suvqr7PqrVhJVwL6 kvKkJfcbWpgBwZZc+KAmW1TZKWz3E7prfi1HDIUdlMsuUp853SOlIaglAMxLSTUzwYdmU o+wEq1t6sE5xLhcUp3Mrd9vmPgPVvpr4bcY= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1642901977985100009 Content-Type: text/plain; charset="utf-8" RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 MMIO region in Tdx guest is set with PcdTdxSharedBitMask in TdxDxe's entry point. In SEV guest the page table entries is set with PcdPteMemoryEncryptionAddressOrMask when creating 1:1 identity table. So the AddressEncMask in GetPageTableEntry (@CpuPageTable.c) is either PcdPteMemoryEncryptionAddressOrMask (in SEV guest), or PcdTdxSharedBitMask (in TDX guest), or all-0 (in Legacy guest). Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Signed-off-by: Min Xu --- UefiCpuPkg/CpuDxe/CpuDxe.inf | 1 + UefiCpuPkg/CpuDxe/CpuPageTable.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf b/UefiCpuPkg/CpuDxe/CpuDxe.inf index d87fe503d152..235241899222 100644 --- a/UefiCpuPkg/CpuDxe/CpuDxe.inf +++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf @@ -80,6 +80,7 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask ##= CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList ##= CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize ##= CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdTdxSharedBitMask ##= CONSUMES =20 [Depex] TRUE diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.c b/UefiCpuPkg/CpuDxe/CpuPageTa= ble.c index d9e65ab4b22a..28982936fade 100644 --- a/UefiCpuPkg/CpuDxe/CpuPageTable.c +++ b/UefiCpuPkg/CpuDxe/CpuPageTable.c @@ -307,6 +307,9 @@ GetPageTableEntry ( // Make sure AddressEncMask is contained to smallest supported address f= ield. // AddressEncMask =3D PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGI= NG_1G_ADDRESS_MASK_64; + if (AddressEncMask =3D=3D 0) { + AddressEncMask =3D PcdGet64 (PcdTdxSharedBitMask) & PAGING_1G_ADDRESS_= MASK_64; + } =20 if (PagingContext->MachineType =3D=3D IMAGE_FILE_MACHINE_X64) { if ((PagingContext->ContextData.X64.Attributes & PAGE_TABLE_LIB_PAGING= _CONTEXT_IA32_X64_ATTRIBUTES_5_LEVEL) !=3D 0) { @@ -357,6 +360,7 @@ GetPageTableEntry ( =20 // 4k L1PageTable =3D (UINT64 *)(UINTN)(L2PageTable[Index2] & ~AddressEncMask = & PAGING_4K_ADDRESS_MASK_64); + if ((L1PageTable[Index1] =3D=3D 0) && (Address !=3D 0)) { *PageAttribute =3D PageNone; return NULL; --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85991): https://edk2.groups.io/g/devel/message/85991 Mute This Topic: https://groups.io/mt/88617546/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Apr 29 10:32:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+85992+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85992+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1642901977; cv=none; d=zohomail.com; s=zohoarc; b=Sj4xZQ4SiJhZlNsXBqxkXdf9h3CnJvQJmmnkZQLHWktuDndMcPIIc5bNMAeScDNVur8kkeEaIRlRsLtSpQmRZSP0k8IUQ15YpIZvTSC1oj5rnCR1q+w5BdqbPrs6Gdh4JqzBDwwdG3sRa8Nliu3kH4mGtSSzk0GV3R0I6YUCZX8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1642901977; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=vjHewn0JHsP3KpH3+CRyiosduFV5PqEEqqT1mRaowvI=; b=CBmylU7QXRGI4zt2rTzObEduvwO8q7CzYYRbCQQFq02uSHX0BsivLlrDmHIx7EYznM8GfJ00YieUG1TIS3vJzGe65x+9hPuwm+vvJ/MbQWdT4WFv2BilwwahxAy8qTjeB2EpH0msd0wGW+r/IzDeh1ameKwHG6EPrURHKt/F4uQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85992+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1642901977951969.1347724576974; Sat, 22 Jan 2022 17:39:37 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id f96gYY1788612x02GGXKlbFW; Sat, 22 Jan 2022 17:39:37 -0800 X-Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web11.4554.1642901975017978470 for ; Sat, 22 Jan 2022 17:39:35 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10235"; a="244686092" X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="244686092" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:39:18 -0800 X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="695033255" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.255.30.84]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:39:15 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann Subject: [edk2-devel] [PATCH V5 22/33] OvmfPkg: Add PlatformInitLib Date: Sun, 23 Jan 2022 09:36:53 +0800 Message-Id: In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: PcB2iUnXJlV2zxksu5lMfxcox1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1642901977; bh=5BPXDqloOMI72dc/me/RFDiFHUeSN9kEE2b52lYz1gg=; h=Cc:Date:From:Reply-To:Subject:To; b=GhKiWes4jJt9afzKwUSGmGnyZtCXc2lrhTRFIiwY0wv7deu+dvbPQkaPK+3FanzroPe 6ucyfXv31XxNuIh6eOT9pbgKn8hDj0vl6kgBGolWcCHN41/8ZEg2f0WcgXQbZnsuCoRaz LXI5IRPBws+I8xI8zeSmU/dXUQ4i3/cRwsw= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1642901980345100002 Content-Type: text/plain; charset="utf-8" RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 There are multi-variants of PlatformPei in OvmfPkg, for example, - OvmfPkg/PlatformPei - OvmfPkg/Bhyve/PlatformPei - OvmfPkg/XenPlatformPei These PlatformPeis share a lot of duplicated codes. It makes difficulty for reviwers and maintainers. The goal of PlatformInitLib is to wrap the common functions in these PlatformPei. As the first stage, below functions are included: - Cmos functions - System memory related functions - Platform initialization functions - Hob functions PlatformInitLib is designed for SEC and PEIM. So global variables cannot be used to pass information between different functions. Dynamic PCDs are not available either. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Signed-off-by: Min Xu --- OvmfPkg/Include/Library/PlatformInitLib.h | 249 ++++++ OvmfPkg/Library/PlatformInitLib/Cmos.c | 56 ++ OvmfPkg/Library/PlatformInitLib/MemDetect.c | 708 ++++++++++++++++++ OvmfPkg/Library/PlatformInitLib/Platform.c | 622 +++++++++++++++ .../PlatformInitLib/PlatformInitLib.inf | 86 +++ OvmfPkg/OvmfPkg.dec | 4 + 6 files changed, 1725 insertions(+) create mode 100644 OvmfPkg/Include/Library/PlatformInitLib.h create mode 100644 OvmfPkg/Library/PlatformInitLib/Cmos.c create mode 100644 OvmfPkg/Library/PlatformInitLib/MemDetect.c create mode 100644 OvmfPkg/Library/PlatformInitLib/Platform.c create mode 100644 OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf diff --git a/OvmfPkg/Include/Library/PlatformInitLib.h b/OvmfPkg/Include/Li= brary/PlatformInitLib.h new file mode 100644 index 000000000000..afab76e46623 --- /dev/null +++ b/OvmfPkg/Include/Library/PlatformInitLib.h @@ -0,0 +1,249 @@ +/** @file + PlatformInitLib header file. + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef PLATFORM_INIT_LIB_H_ +#define PLATFORM_INIT_LIB_H_ + +#include +#include + +/** + Reads 8-bits of CMOS data. + + Reads the 8-bits of CMOS data at the location specified by Index. + The 8-bit read value is returned. + + @param Index The CMOS location to read. + + @return The value read. + +**/ +UINT8 +EFIAPI +PlatformCmosRead8 ( + IN UINTN Index + ); + +/** + Writes 8-bits of CMOS data. + + Writes 8-bits of CMOS data to the location specified by Index + with the value specified by Value and returns Value. + + @param Index The CMOS location to write. + @param Value The value to write to CMOS. + + @return The value written to CMOS. + +**/ +UINT8 +EFIAPI +PlatformCmosWrite8 ( + IN UINTN Index, + IN UINT8 Value + ); + +/** + Dump the CMOS content + */ +VOID +EFIAPI +PlatformDebugDumpCmos ( + VOID + ); + +/** + * Return the highest address that DXE could possibly use, plus one. + * + * @param Pci64Base The 64-bit PCI host aperture base address. + * @param Pci64Size The 64-bit PCI host aperture size. + * @param DefaultPciMmio64Size The default 64-bit PCI host aperture size. + * + * @return The highest address that DXE could possibly use, plus one. + */ +UINT64 +EFIAPI +PlatformGetFirstNonAddress ( + OUT UINT64 *Pci64Base, + OUT UINT64 *Pci64Size, + IN UINT64 DefaultPciMmio64Size + ); + +/** + * Initialize the PhysMemAddressWidth variable, based on guest RAM size. + * + * @param FirstNonAddress The highest address that DXE could possibly = use, plus one. + * + * @return The physical memory address width based on the guest RAM size. + */ +UINT8 +EFIAPI +PlatformAddressWidthInitialization ( + IN UINT64 FirstNonAddress + ); + +/** + * Query Host Bridge Dev Id. + * + * @return Host Bridge Dev Id. + */ +UINT16 +EFIAPI +PlatformQueryHostBridgeDid ( + VOID + ); + +/** + Fetch the boot CPU count and the possible CPU count from QEMU. + + @param HostBridgeDevId The Host bridge Dev Id. + @param DefaultMaxCpuCount The default max cpu count. + @param MaxCpuCount The pointer to the returned max cpu count. + @param BootCpuCount The pointer to the returned boot cpu count. +**/ +VOID +EFIAPI +PlatformMaxCpuCountInitialization ( + IN UINT16 HostBridgeDevId, + IN UINT32 DefaultMaxCpuCount, + OUT UINT32 *MaxCpuCount, + OUT UINT16 *BootCpuCount + ); + +/** + * Get the memory size below 4GB. + * + * @return UINT32 The lower memory size. + */ +UINT32 +EFIAPI +PlatformGetSystemMemorySizeBelow4gb ( + VOID + ); + +/** + * Initializatoin of Qemu UC32Base. + * + * @param HostBridgeDevId The host bridge Dev Id. + * @param LowerMemorySize The lower memory size (under 4G). + * @return UINT32 The Qemu UC32 base address. + */ +UINT32 +EFIAPI +PlatformQemuUc32BaseInitialization ( + IN UINT16 HostBridgeDevId, + IN UINT32 LowerMemorySize + ); + +/** + * Initialize the Memory Map IO hobs. + * + * @param HostBridgeDevId The host bridge Dev Id. + * @param Uc32Base The Qemu Uc32Base address. + * @param PciBase The pointer to the Pci base address. + * @param PciSize The pointer to the Pci base size. + * @param PciIoBase The pointer to the Pci Io base address. + * @param PciIoSize The pointer to the Pci Io size. + */ +VOID +EFIAPI +PlatformMemMapInitialization ( + IN UINT16 HostBridgeDevId, + IN UINT32 Uc32Base, + OUT UINT32 *PciBase, + OUT UINT32 *PciSize, + OUT UINT64 *PciIoBase, + OUT UINT64 *PciIoSize + ); + +/** + * Fetch "opt/ovmf/PcdSetNxForStack" from QEMU + * + * @param Setting The pointer to the setting of "/opt/ovmf/PcdSetNxFor= Stack". + * @return EFI_SUCCESS Successfully fetch the settings. + */ +EFI_STATUS +EFIAPI +PlatformNoexecDxeInitialization ( + OUT BOOLEAN *Setting + ); + +/** + * Misc initialization, such as Disable A20 Mask, Build CPU Hob, + * PM settings, Set PCI Express Register Range Base Address. + * + * @param HostBridgeDevId The host bridge Dev id. + * @param PhysMemAddressWidth The physical memory address width. + */ +VOID +EFIAPI +PlatformMiscInitialization ( + IN UINT16 HostBridgeDevId, + IN UINT8 PhysMemAddressWidth + ); + +/** + Publish system RAM and reserve memory regions. + + @param Uc32Base + @param HostBridgeDevId + @param SmmSmramRequire + @param BootMode + @param S3Supported + @param LowerMemorySize + @param Q35TsegMbytes +**/ +VOID +EFIAPI +PlatformInitializeRamRegions ( + IN UINT32 Uc32Base, + IN UINT16 HostBridgeDevId, + IN BOOLEAN SmmSmramRequire, + IN EFI_BOOT_MODE BootMode, + IN BOOLEAN S3Supported, + IN UINT32 LowerMemorySize, + IN UINT16 Q35TsegMbytes + ); + +VOID +EFIAPI +PlatformAddIoMemoryBaseSizeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN UINT64 MemorySize + ); + +VOID +EFIAPI +PlatformAddIoMemoryRangeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN EFI_PHYSICAL_ADDRESS MemoryLimit + ); + +VOID +EFIAPI +PlatformAddMemoryBaseSizeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN UINT64 MemorySize + ); + +VOID +EFIAPI +PlatformAddMemoryRangeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN EFI_PHYSICAL_ADDRESS MemoryLimit + ); + +VOID +EFIAPI +PlatformAddReservedMemoryBaseSizeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN UINT64 MemorySize, + IN BOOLEAN Cacheable + ); + +#endif // PLATFORM_INIT_LIB_H_ diff --git a/OvmfPkg/Library/PlatformInitLib/Cmos.c b/OvmfPkg/Library/Platf= ormInitLib/Cmos.c new file mode 100644 index 000000000000..303cb5d7b6e5 --- /dev/null +++ b/OvmfPkg/Library/PlatformInitLib/Cmos.c @@ -0,0 +1,56 @@ +/** @file + PC/AT CMOS access routines + + Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// #include "Cmos.h" +#include +#include "Library/IoLib.h" + +/** + Reads 8-bits of CMOS data. + + Reads the 8-bits of CMOS data at the location specified by Index. + The 8-bit read value is returned. + + @param Index The CMOS location to read. + + @return The value read. + +**/ +UINT8 +EFIAPI +PlatformCmosRead8 ( + IN UINTN Index + ) +{ + IoWrite8 (0x70, (UINT8)Index); + return IoRead8 (0x71); +} + +/** + Writes 8-bits of CMOS data. + + Writes 8-bits of CMOS data to the location specified by Index + with the value specified by Value and returns Value. + + @param Index The CMOS location to write. + @param Value The value to write to CMOS. + + @return The value written to CMOS. + +**/ +UINT8 +EFIAPI +PlatformCmosWrite8 ( + IN UINTN Index, + IN UINT8 Value + ) +{ + IoWrite8 (0x70, (UINT8)Index); + IoWrite8 (0x71, Value); + return Value; +} diff --git a/OvmfPkg/Library/PlatformInitLib/MemDetect.c b/OvmfPkg/Library/= PlatformInitLib/MemDetect.c new file mode 100644 index 000000000000..42d998687598 --- /dev/null +++ b/OvmfPkg/Library/PlatformInitLib/MemDetect.c @@ -0,0 +1,708 @@ +/**@file + Memory Detection for Virtual Machines. + + Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +Module Name: + + MemDetect.c + +**/ + +// +// The package level header files this module uses +// +#include +#include +#include +#include +#include +// #include + +// +// The Library classes this module consumes +// +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/** + * Initializatoin of Qemu UC32Base. + * + * @param HostBridgeDevId The host bridge Dev Id. + * @param LowerMemorySize The lower memory size (under 4G). + * @return UINT32 The Qemu UC32 base address. + */ +UINT32 +EFIAPI +PlatformQemuUc32BaseInitialization ( + IN UINT16 HostBridgeDevId, + IN UINT32 LowerMemorySize + ) +{ + UINT32 Uc32Size; + UINT32 Uc32Base; + + if (HostBridgeDevId =3D=3D 0xffff /* microvm */) { + return 0; + } + + if (HostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { + // + // On q35, the 32-bit area that we'll mark as UC, through variable MTR= Rs, + // starts at PcdPciExpressBaseAddress. The platform DSC is responsible= for + // setting PcdPciExpressBaseAddress such that describing the + // [PcdPciExpressBaseAddress, 4GB) range require a very small number of + // variable MTRRs (preferably 1 or 2). + // + + ASSERT (FixedPcdGet64 (PcdPciExpressBaseAddress) <=3D MAX_UINT32); + Uc32Base =3D (UINT32)FixedPcdGet64 (PcdPciExpressBaseAddress); + return Uc32Base; + } + + if (HostBridgeDevId =3D=3D CLOUDHV_DEVICE_ID) { + Uc32Base =3D CLOUDHV_MMIO_HOLE_ADDRESS; + return Uc32Base; + } + + ASSERT (HostBridgeDevId =3D=3D INTEL_82441_DEVICE_ID); + // + // On i440fx, start with the [LowerMemorySize, 4GB) range. Make sure one + // variable MTRR suffices by truncating the size to a whole power of two, + // while keeping the end affixed to 4GB. This will round the base up. + // + Uc32Size =3D GetPowerOfTwo32 ((UINT32)(SIZE_4GB - LowerMemorySize)); + Uc32Base =3D (UINT32)(SIZE_4GB - Uc32Size); + // + // Assuming that LowerMemorySize is at least 1 byte, Uc32Size is at most= 2GB. + // Therefore mQemuUc32Base is at least 2GB. + // + ASSERT (Uc32Base >=3D BASE_2GB); + + if (Uc32Base !=3D LowerMemorySize) { + DEBUG (( + DEBUG_VERBOSE, + "%a: rounded UC32 base from 0x%x up to 0x%x, for " + "an UC32 size of 0x%x\n", + __FUNCTION__, + LowerMemorySize, + Uc32Base, + Uc32Size + )); + } + + return Uc32Base; +} + +/** + Iterate over the RAM entries in QEMU's fw_cfg E820 RAM map that start ou= tside + of the 32-bit address range. + + Find the highest exclusive >=3D4GB RAM address, or produce memory resour= ce + descriptor HOBs for RAM entries that start at or above 4GB. + + @param[out] MaxAddress If MaxAddress is NULL, then ScanOrAdd64BitE820Ra= m() + produces memory resource descriptor HOBs for RAM + entries that start at or above 4GB. + + Otherwise, MaxAddress holds the highest exclusive + >=3D4GB RAM address on output. If QEMU's fw_cfg = E820 + RAM map contains no RAM entry that starts outsid= e of + the 32-bit address range, then MaxAddress is exa= ctly + 4GB on output. + + @retval EFI_SUCCESS The fw_cfg E820 RAM map was found and proces= sed. + + @retval EFI_PROTOCOL_ERROR The RAM map was found, but its size wasn't a + whole multiple of sizeof(EFI_E820_ENTRY64). = No + RAM entry was processed. + + @return Error codes from QemuFwCfgFindFile(). No RAM + entry was processed. +**/ +EFI_STATUS +ScanOrAdd64BitE820Ram ( + IN BOOLEAN AddHighHob, + OUT UINT64 *LowMemory OPTIONAL, + OUT UINT64 *MaxAddress OPTIONAL + ) +{ + EFI_STATUS Status; + FIRMWARE_CONFIG_ITEM FwCfgItem; + UINTN FwCfgSize; + EFI_E820_ENTRY64 E820Entry; + UINTN Processed; + + Status =3D QemuFwCfgFindFile ("etc/e820", &FwCfgItem, &FwCfgSize); + if (EFI_ERROR (Status)) { + return Status; + } + + if (FwCfgSize % sizeof E820Entry !=3D 0) { + return EFI_PROTOCOL_ERROR; + } + + if (LowMemory !=3D NULL) { + *LowMemory =3D 0; + } + + if (MaxAddress !=3D NULL) { + *MaxAddress =3D BASE_4GB; + } + + QemuFwCfgSelectItem (FwCfgItem); + for (Processed =3D 0; Processed < FwCfgSize; Processed +=3D sizeof E820E= ntry) { + QemuFwCfgReadBytes (sizeof E820Entry, &E820Entry); + DEBUG (( + DEBUG_VERBOSE, + "%a: Base=3D0x%Lx Length=3D0x%Lx Type=3D%u\n", + __FUNCTION__, + E820Entry.BaseAddr, + E820Entry.Length, + E820Entry.Type + )); + if (E820Entry.Type =3D=3D EfiAcpiAddressRangeMemory) { + if (AddHighHob && (E820Entry.BaseAddr >=3D BASE_4GB)) { + UINT64 Base; + UINT64 End; + + // + // Round up the start address, and round down the end address. + // + Base =3D ALIGN_VALUE (E820Entry.BaseAddr, (UINT64)EFI_PAGE_SIZE); + End =3D (E820Entry.BaseAddr + E820Entry.Length) & + ~(UINT64)EFI_PAGE_MASK; + if (Base < End) { + PlatformAddMemoryRangeHob (Base, End); + DEBUG (( + DEBUG_VERBOSE, + "%a: PlatformAddMemoryRangeHob [0x%Lx, 0x%Lx)\n", + __FUNCTION__, + Base, + End + )); + } + } + + if (MaxAddress || LowMemory) { + UINT64 Candidate; + + Candidate =3D E820Entry.BaseAddr + E820Entry.Length; + if (MaxAddress && (Candidate > *MaxAddress)) { + *MaxAddress =3D Candidate; + DEBUG (( + DEBUG_VERBOSE, + "%a: MaxAddress=3D0x%Lx\n", + __FUNCTION__, + *MaxAddress + )); + } + + if (LowMemory && (Candidate > *LowMemory) && (Candidate < BASE_4GB= )) { + *LowMemory =3D Candidate; + DEBUG (( + DEBUG_VERBOSE, + "%a: LowMemory=3D0x%Lx\n", + __FUNCTION__, + *LowMemory + )); + } + } + } + } + + return EFI_SUCCESS; +} + +/** + * Get the memory size below 4GB. + * + * @return UINT32 The lower memory size. + */ +UINT32 +EFIAPI +PlatformGetSystemMemorySizeBelow4gb ( + VOID + ) +{ + EFI_STATUS Status; + UINT64 LowerMemorySize =3D 0; + UINT8 Cmos0x34; + UINT8 Cmos0x35; + + Status =3D ScanOrAdd64BitE820Ram (FALSE, &LowerMemorySize, NULL); + if ((Status =3D=3D EFI_SUCCESS) && (LowerMemorySize > 0)) { + return (UINT32)LowerMemorySize; + } + + // + // CMOS 0x34/0x35 specifies the system memory above 16 MB. + // * CMOS(0x35) is the high byte + // * CMOS(0x34) is the low byte + // * The size is specified in 64kb chunks + // * Since this is memory above 16MB, the 16MB must be added + // into the calculation to get the total memory size. + // + + Cmos0x34 =3D (UINT8)PlatformCmosRead8 (0x34); + Cmos0x35 =3D (UINT8)PlatformCmosRead8 (0x35); + + return (UINT32)(((UINTN)((Cmos0x35 << 8) + Cmos0x34) << 16) + SIZE_16MB); +} + +UINT64 +GetSystemMemorySizeAbove4gb ( + ) +{ + UINT32 Size; + UINTN CmosIndex; + + // + // CMOS 0x5b-0x5d specifies the system memory above 4GB MB. + // * CMOS(0x5d) is the most significant size byte + // * CMOS(0x5c) is the middle size byte + // * CMOS(0x5b) is the least significant size byte + // * The size is specified in 64kb chunks + // + + Size =3D 0; + for (CmosIndex =3D 0x5d; CmosIndex >=3D 0x5b; CmosIndex--) { + Size =3D (UINT32)(Size << 8) + (UINT32)PlatformCmosRead8 (CmosIndex); + } + + return LShiftU64 (Size, 16); +} + +/** + * Return the highest address that DXE could possibly use, plus one. + * + * @param Pci64Base The 64-bit PCI host aperture base address. + * @param Pci64Size The 64-bit PCI host aperture size. + * @param DefaultPciMmio64Size The default 64-bit PCI host aperture size. + * + * @return UINT64 The highest address that DXE could possibly use, pl= us one. + */ +UINT64 +EFIAPI +PlatformGetFirstNonAddress ( + OUT UINT64 *Pci64Base, + OUT UINT64 *Pci64Size, + IN UINT64 DefaultPciMmio64Size + ) +{ + UINT64 FirstNonAddress; + UINT32 FwCfgPciMmio64Mb; + EFI_STATUS Status; + FIRMWARE_CONFIG_ITEM FwCfgItem; + UINTN FwCfgSize; + UINT64 HotPlugMemoryEnd; + + // + // set FirstNonAddress to suppress incorrect compiler/analyzer warnings + // + FirstNonAddress =3D 0; + + // + // If QEMU presents an E820 map, then get the highest exclusive >=3D4GB = RAM + // address from it. This can express an address >=3D 4GB+1TB. + // + // Otherwise, get the flat size of the memory above 4GB from the CMOS (w= hich + // can only express a size smaller than 1TB), and add it to 4GB. + // + Status =3D ScanOrAdd64BitE820Ram (FALSE, NULL, &FirstNonAddress); + if (EFI_ERROR (Status)) { + FirstNonAddress =3D BASE_4GB + GetSystemMemorySizeAbove4gb (); + } + + // + // If DXE is 32-bit, then we're done; PciBusDxe will degrade 64-bit MMIO + // resources to 32-bit anyway. See DegradeResource() in + // "PciResourceSupport.c". + // + #ifdef MDE_CPU_IA32 + if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) { + return FirstNonAddress; + } + + #endif + + // + // Otherwise, in order to calculate the highest address plus one, we must + // consider the 64-bit PCI host aperture too. Fetch the default size. + // + *Pci64Size =3D DefaultPciMmio64Size; + + // + // See if the user specified the number of megabytes for the 64-bit PCI = host + // aperture. Accept an aperture size up to 16TB. + // + // As signaled by the "X-" prefix, this knob is experimental, and might = go + // away at any time. + // + Status =3D QemuFwCfgParseUint32 ( + "opt/ovmf/X-PciMmio64Mb", + FALSE, + &FwCfgPciMmio64Mb + ); + switch (Status) { + case EFI_UNSUPPORTED: + case EFI_NOT_FOUND: + break; + case EFI_SUCCESS: + if (FwCfgPciMmio64Mb <=3D 0x1000000) { + *Pci64Size =3D LShiftU64 (FwCfgPciMmio64Mb, 20); + break; + } + + // + // fall through + // + default: + DEBUG (( + DEBUG_WARN, + "%a: ignoring malformed 64-bit PCI host aperture size from fw_cfg\= n", + __FUNCTION__ + )); + break; + } + + if (*Pci64Size =3D=3D 0) { + DEBUG (( + DEBUG_INFO, + "%a: disabling 64-bit PCI host aperture\n", + __FUNCTION__ + )); + + // + // There's nothing more to do; the amount of memory above 4GB fully + // determines the highest address plus one. The memory hotplug area (s= ee + // below) plays no role for the firmware in this case. + // + return FirstNonAddress; + } + + // + // The "etc/reserved-memory-end" fw_cfg file, when present, contains an + // absolute, exclusive end address for the memory hotplug area. This area + // starts right at the end of the memory above 4GB. The 64-bit PCI host + // aperture must be placed above it. + // + Status =3D QemuFwCfgFindFile ( + "etc/reserved-memory-end", + &FwCfgItem, + &FwCfgSize + ); + if (!EFI_ERROR (Status) && (FwCfgSize =3D=3D sizeof HotPlugMemoryEnd)) { + QemuFwCfgSelectItem (FwCfgItem); + QemuFwCfgReadBytes (FwCfgSize, &HotPlugMemoryEnd); + DEBUG (( + DEBUG_VERBOSE, + "%a: HotPlugMemoryEnd=3D0x%Lx\n", + __FUNCTION__, + HotPlugMemoryEnd + )); + + ASSERT (HotPlugMemoryEnd >=3D FirstNonAddress); + FirstNonAddress =3D HotPlugMemoryEnd; + } + + // + // SeaBIOS aligns both boundaries of the 64-bit PCI host aperture to 1GB= , so + // that the host can map it with 1GB hugepages. Follow suit. + // + *Pci64Base =3D ALIGN_VALUE (FirstNonAddress, (UINT64)SIZE_1GB); + *Pci64Size =3D ALIGN_VALUE (*Pci64Size, (UINT64)SIZE_1GB); + + // + // The 64-bit PCI host aperture should also be "naturally" aligned. The + // alignment is determined by rounding the size of the aperture down to = the + // next smaller or equal power of two. That is, align the aperture by the + // largest BAR size that can fit into it. + // + *Pci64Base =3D ALIGN_VALUE (*Pci64Base, GetPowerOfTwo64 (*Pci64Size)); + + // + // The useful address space ends with the 64-bit PCI host aperture. + // + FirstNonAddress =3D *Pci64Base + *Pci64Size; + return FirstNonAddress; +} + +/** + * Initialize the PhysMemAddressWidth variable, based on guest RAM size. + * + * @param FirstNonAddress The highest address that DXE could possibly = use, plus one. + * + * @return The physical memory address width based on the guest RAM size. + */ +UINT8 +EFIAPI +PlatformAddressWidthInitialization ( + IN UINT64 FirstNonAddress + ) +{ + UINT8 PhysMemAddressWidth; + + // + // As guest-physical memory size grows, the permanent PEI RAM requiremen= ts + // are dominated by the identity-mapping page tables built by the DXE IP= L. + // The DXL IPL keys off of the physical address bits advertized in the C= PU + // HOB. To conserve memory, we calculate the minimum address width here. + // + PhysMemAddressWidth =3D (UINT8)HighBitSet64 (FirstNonAddress); + + // + // If FirstNonAddress is not an integral power of two, then we need an + // additional bit. + // + if ((FirstNonAddress & (FirstNonAddress - 1)) !=3D 0) { + ++PhysMemAddressWidth; + } + + // + // The minimum address width is 36 (covers up to and excluding 64 GB, wh= ich + // is the maximum for Ia32 + PAE). The theoretical architecture maximum = for + // X64 long mode is 52 bits, but the DXE IPL clamps that down to 48 bits= . We + // can simply assert that here, since 48 bits are good enough for 256 TB. + // + if (PhysMemAddressWidth <=3D 36) { + PhysMemAddressWidth =3D 36; + } + + #if defined (MDE_CPU_X64) + if (TdIsEnabled ()) { + if (TdSharedPageMask () =3D=3D (1ULL << 47)) { + PhysMemAddressWidth =3D 48; + } else { + PhysMemAddressWidth =3D 52; + } + } + + ASSERT (PhysMemAddressWidth <=3D 52); + #else + ASSERT (PhysMemAddressWidth <=3D 48); + #endif + + return PhysMemAddressWidth; +} + +VOID +PlatformQemuInitializeRamBelow1gb ( + VOID + ) +{ + PlatformAddMemoryRangeHob (0, BASE_512KB + BASE_128KB); +} + +/** + Peform Memory Detection for QEMU / KVM + +**/ +VOID +QemuInitializeRam ( + UINT32 Uc32Base, + UINT16 HostBridgeDevId, + EFI_BOOT_MODE BootMode, + BOOLEAN SmmSmramRequire, + UINT32 LowerMemorySize, + UINT16 Q35TsegMbytes + ) +{ + UINT64 UpperMemorySize; + MTRR_SETTINGS MtrrSettings; + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "%a called\n", __FUNCTION__)); + + if (BootMode =3D=3D BOOT_ON_S3_RESUME) { + // + // Create the following memory HOB as an exception on the S3 boot path. + // + // Normally we'd create memory HOBs only on the normal boot path. Howe= ver, + // CpuMpPei specifically needs such a low-memory HOB on the S3 path as + // well, for "borrowing" a subset of it temporarily, for the AP startup + // vector. + // + // CpuMpPei saves the original contents of the borrowed area in perman= ent + // PEI RAM, in a backup buffer allocated with the normal PEI services. + // CpuMpPei restores the original contents ("returns" the borrowed are= a) at + // End-of-PEI. End-of-PEI in turn is emitted by S3Resume2Pei before + // transferring control to the OS's wakeup vector in the FACS. + // + // We expect any other PEIMs that "borrow" memory similarly to CpuMpPe= i to + // restore the original contents. Furthermore, we expect all such PEIMs + // (CpuMpPei included) to claim the borrowed areas by producing memory + // allocation HOBs, and to honor preexistent memory allocation HOBs wh= en + // looking for an area to borrow. + // + PlatformQemuInitializeRamBelow1gb (); + } else { + // + // Create memory HOBs + // + PlatformQemuInitializeRamBelow1gb (); + + if (SmmSmramRequire) { + UINT32 TsegSize; + + TsegSize =3D Q35TsegMbytes * SIZE_1MB; + PlatformAddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize); + PlatformAddReservedMemoryBaseSizeHob ( + LowerMemorySize - TsegSize, + TsegSize, + TRUE + ); + } else { + PlatformAddMemoryRangeHob (BASE_1MB, LowerMemorySize); + } + + // + // If QEMU presents an E820 map, then create memory HOBs for the >=3D4= GB RAM + // entries. Otherwise, create a single memory HOB with the flat >=3D4GB + // memory size read from the CMOS. + // + Status =3D ScanOrAdd64BitE820Ram (TRUE, NULL, NULL); + if (EFI_ERROR (Status)) { + UpperMemorySize =3D GetSystemMemorySizeAbove4gb (); + if (UpperMemorySize !=3D 0) { + PlatformAddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize); + } + } + } + + // + // We'd like to keep the following ranges uncached: + // - [640 KB, 1 MB) + // - [LowerMemorySize, 4 GB) + // + // Everything else should be WB. Unfortunately, programming the inverse = (ie. + // keeping the default UC, and configuring the complement set of the abo= ve as + // WB) is not reliable in general, because the end of the upper RAM can = have + // practically any alignment, and we may not have enough variable MTRRs = to + // cover it exactly. + // + if (IsMtrrSupported () && (HostBridgeDevId !=3D CLOUDHV_DEVICE_ID)) { + MtrrGetAllMtrrs (&MtrrSettings); + + // + // MTRRs disabled, fixed MTRRs disabled, default type is uncached + // + ASSERT ((MtrrSettings.MtrrDefType & BIT11) =3D=3D 0); + ASSERT ((MtrrSettings.MtrrDefType & BIT10) =3D=3D 0); + ASSERT ((MtrrSettings.MtrrDefType & 0xFF) =3D=3D 0); + + // + // flip default type to writeback + // + SetMem (&MtrrSettings.Fixed, sizeof MtrrSettings.Fixed, 0x06); + ZeroMem (&MtrrSettings.Variables, sizeof MtrrSettings.Variables); + MtrrSettings.MtrrDefType |=3D BIT11 | BIT10 | 6; + MtrrSetAllMtrrs (&MtrrSettings); + + // + // Set memory range from 640KB to 1MB to uncacheable + // + Status =3D MtrrSetMemoryAttribute ( + BASE_512KB + BASE_128KB, + BASE_1MB - (BASE_512KB + BASE_128KB), + CacheUncacheable + ); + ASSERT_EFI_ERROR (Status); + + // + // Set the memory range from the start of the 32-bit MMIO area (32-bit= PCI + // MMIO aperture on i440fx, PCIEXBAR on q35) to 4GB as uncacheable. + // + Status =3D MtrrSetMemoryAttribute ( + Uc32Base, + SIZE_4GB - Uc32Base, + CacheUncacheable + ); + ASSERT_EFI_ERROR (Status); + } +} + +/** + Publish system RAM and reserve memory regions + +**/ +VOID +EFIAPI +PlatformInitializeRamRegions ( + IN UINT32 Uc32Base, + IN UINT16 HostBridgeDevId, + IN BOOLEAN SmmSmramRequire, + IN EFI_BOOT_MODE BootMode, + IN BOOLEAN S3Supported, + IN UINT32 LowerMemorySize, + IN UINT16 Q35TsegMbytes + ) +{ + QemuInitializeRam ( + Uc32Base, + HostBridgeDevId, + BootMode, + SmmSmramRequire, + LowerMemorySize, + Q35TsegMbytes + ); + + if (BootMode !=3D BOOT_ON_S3_RESUME) { + if (!SmmSmramRequire) { + // + // Reserve the lock box storage area + // + // Since this memory range will be used on S3 resume, it must be + // reserved as ACPI NVS. + // + // If S3 is unsupported, then various drivers might still write to t= he + // LockBox area. We ought to prevent DXE from serving allocation req= uests + // such that they would overlap the LockBox storage. + // + ZeroMem ( + (VOID *)(UINTN)FixedPcdGet32 (PcdOvmfLockBoxStorageBase), + (UINTN)FixedPcdGet32 (PcdOvmfLockBoxStorageSize) + ); + BuildMemoryAllocationHob ( + (EFI_PHYSICAL_ADDRESS)(UINTN)FixedPcdGet32 (PcdOvmfLockBoxStorageB= ase), + (UINT64)(UINTN)FixedPcdGet32 (PcdOvmfLockBoxStorageSize), + S3Supported ? EfiACPIMemoryNVS : EfiBootServicesData + ); + } + + #ifdef MDE_CPU_X64 + if (FixedPcdGet32 (PcdOvmfWorkAreaSize) !=3D 0) { + // + // Reserve the work area. + // + // Since this memory range will be used by the Reset Vector on S3 + // resume, it must be reserved as ACPI NVS. + // + // If S3 is unsupported, then various drivers might still write to t= he + // work area. We ought to prevent DXE from serving allocation reques= ts + // such that they would overlap the work area. + // + BuildMemoryAllocationHob ( + (EFI_PHYSICAL_ADDRESS)(UINTN)FixedPcdGet32 (PcdOvmfWorkAreaBase), + (UINT64)(UINTN)FixedPcdGet32 (PcdOvmfWorkAreaSize), + EfiBootServicesData + ); + } + + #endif + } +} diff --git a/OvmfPkg/Library/PlatformInitLib/Platform.c b/OvmfPkg/Library/P= latformInitLib/Platform.c new file mode 100644 index 000000000000..943883d42c2a --- /dev/null +++ b/OvmfPkg/Library/PlatformInitLib/Platform.c @@ -0,0 +1,622 @@ +/**@file + + Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2011, Andrei Warkentin + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +// The package level header files this module uses +// +#include + +// +// The Library classes this module consumes +// +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +VOID +EFIAPI +PlatformAddIoMemoryBaseSizeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN UINT64 MemorySize + ) +{ + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_MAPPED_IO, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED, + MemoryBase, + MemorySize + ); +} + +VOID +EFIAPI +PlatformAddReservedMemoryBaseSizeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN UINT64 MemorySize, + IN BOOLEAN Cacheable + ) +{ + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_RESERVED, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + (Cacheable ? + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE : + 0 + ) | + EFI_RESOURCE_ATTRIBUTE_TESTED, + MemoryBase, + MemorySize + ); +} + +VOID +EFIAPI +PlatformAddIoMemoryRangeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN EFI_PHYSICAL_ADDRESS MemoryLimit + ) +{ + PlatformAddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - Memor= yBase)); +} + +VOID +EFIAPI +PlatformAddMemoryBaseSizeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN UINT64 MemorySize + ) +{ + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED, + MemoryBase, + MemorySize + ); +} + +VOID +EFIAPI +PlatformAddMemoryRangeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN EFI_PHYSICAL_ADDRESS MemoryLimit + ) +{ + PlatformAddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryB= ase)); +} + +/** + * Initialize the Memory Map IO hobs. + * + * @param HostBridgeDevId The host bridge Dev Id. + * @param Uc32Base The Qemu Uc32Base address. + * @param PciBase The pointer to the Pci base address. + * @param PciSize The pointer to the Pci base size. + * @param PciIoBase The pointer to the Pci Io base address. + * @param PciIoSize The pointer to the Pci Io size. + */ +VOID +EFIAPI +PlatformMemMapInitialization ( + UINT16 HostBridgeDevId, + UINT32 Uc32Base, + UINT32 *PciBase, + UINT32 *PciSize, + UINT64 *PciIoBase, + UINT64 *PciIoSize + ) +{ + UINT32 TopOfLowRam; + UINT64 PciExBarBase; + + *PciIoBase =3D 0xC000; + *PciIoSize =3D 0x4000; + *PciBase =3D 0; + *PciSize =3D 0; + + // + // Video memory + Legacy BIOS region + // + PlatformAddIoMemoryRangeHob (0x0A0000, BASE_1MB); + + if (HostBridgeDevId =3D=3D 0xffff /* microvm */) { + PlatformAddIoMemoryBaseSizeHob (MICROVM_GED_MMIO_BASE, SIZE_4KB); + PlatformAddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); /* ioapic #1 */ + PlatformAddIoMemoryBaseSizeHob (0xFEC10000, SIZE_4KB); /* ioapic #2 */ + return; + } + + TopOfLowRam =3D PlatformGetSystemMemorySizeBelow4gb (); + PciExBarBase =3D 0; + if (HostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { + // + // The MMCONFIG area is expected to fall between the top of low RAM and + // the base of the 32-bit PCI host aperture. + // + PciExBarBase =3D FixedPcdGet64 (PcdPciExpressBaseAddress); + ASSERT (TopOfLowRam <=3D PciExBarBase); + ASSERT (PciExBarBase <=3D MAX_UINT32 - SIZE_256MB); + *PciBase =3D (UINT32)(PciExBarBase + SIZE_256MB); + } else { + ASSERT (TopOfLowRam <=3D Uc32Base); + *PciBase =3D Uc32Base; + } + + // + // address purpose size + // ------------ -------- ------------------------- + // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g) + // 0xFC000000 gap 44 MB + // 0xFEC00000 IO-APIC 4 KB + // 0xFEC01000 gap 1020 KB + // 0xFED00000 HPET 1 KB + // 0xFED00400 gap 111 KB + // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB + // 0xFED20000 gap 896 KB + // 0xFEE00000 LAPIC 1 MB + // + *PciSize =3D 0xFC000000 - *PciBase; + PlatformAddIoMemoryBaseSizeHob (*PciBase, *PciSize); + + PlatformAddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); + PlatformAddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB); + if (HostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { + PlatformAddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB); + // + // Note: there should be an + // + // AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB); + // + // call below, just like the one above for RCBA. However, Linux insists + // that the MMCONFIG area be marked in the E820 or UEFI memory map as + // "reserved memory" -- Linux does not content itself with a simple gap + // in the memory map wherever the MCFG ACPI table points to. + // + // This appears to be a safety measure. The PCI Firmware Specification + // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources c= an + // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory + // [...]". (Emphasis added here.) + // + // Normally we add memory resource descriptor HOBs in + // QemuInitializeRam(), and pre-allocate from those with memory + // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG ar= ea + // is most definitely not RAM; so, as an exception, cover it with + // uncacheable reserved memory right here. + // + PlatformAddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE); + BuildMemoryAllocationHob ( + PciExBarBase, + SIZE_256MB, + EfiReservedMemoryType + ); + } + + PlatformAddIoMemoryBaseSizeHob (FixedPcdGet32 (PcdCpuLocalApicBaseAddres= s), SIZE_1MB); + + // + // On Q35, the IO Port space is available for PCI resource allocations f= rom + // 0x6000 up. + // + if (HostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { + *PciIoBase =3D 0x6000; + *PciIoSize =3D 0xA000; + ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < *PciIoBase); + } + + // + // Add PCI IO Port space available for PCI resource allocations. + // + BuildResourceDescriptorHob ( + EFI_RESOURCE_IO, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED, + *PciIoBase, + *PciIoSize + ); +} + +/** + * Fetch "opt/ovmf/PcdSetNxForStack" from QEMU + * + * @param Setting The pointer to the setting of "/opt/ovmf/PcdSetNxFor= Stack". + * @return EFI_SUCCESS Successfully fetch the settings. + */ +EFI_STATUS +EFIAPI +PlatformNoexecDxeInitialization ( + OUT BOOLEAN *Setting + ) +{ + return QemuFwCfgParseBool ("opt/ovmf/PcdSetNxForStack", Setting); +} + +VOID +PciExBarInitialization ( + VOID + ) +{ + union { + UINT64 Uint64; + UINT32 Uint32[2]; + } PciExBarBase; + + // + // We only support the 256MB size for the MMCONFIG area: + // 256 buses * 32 devices * 8 functions * 4096 bytes config space. + // + // The masks used below enforce the Q35 requirements that the MMCONFIG a= rea + // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 G= B. + // + // Note that (b) also ensures that the minimum address width we have + // determined in AddressWidthInitialization(), i.e., 36 bits, will suffi= ce + // for DXE's page tables to cover the MMCONFIG area. + // + PciExBarBase.Uint64 =3D FixedPcdGet64 (PcdPciExpressBaseAddress); + ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) =3D=3D 0); + ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) =3D=3D 0); + + // + // Clear the PCIEXBAREN bit first, before programming the high register. + // + PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0); + + // + // Program the high register. Then program the low register, setting the + // MMCONFIG area size and enabling decoding at once. + // + PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[= 1]); + PciWrite32 ( + DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), + PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN + ); +} + +/** + * Misc initialization, such as Disable A20 Mask, Build CPU Hob, + * PM settings, Set PCI Express Register Range Base Address. + * + * @param HostBridgeDevId The host bridge Dev id. + * @param PhysMemAddressWidth The physical memory address width. + */ +VOID +EFIAPI +PlatformMiscInitialization ( + IN UINT16 HostBridgeDevId, + IN UINT8 PhysMemAddressWidth + ) +{ + UINTN PmCmd; + UINTN Pmba; + UINT32 PmbaAndVal; + UINT32 PmbaOrVal; + UINTN AcpiCtlReg; + UINT8 AcpiEnBit; + + // + // Disable A20 Mask + // + IoOr8 (0x92, BIT1); + + // + // Build the CPU HOB with guest RAM size dependent address width and 16-= bits + // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed dur= ing + // S3 resume as well, so we build it unconditionally.) + // + BuildCpuHob (PhysMemAddressWidth, 16); + + // + // Determine platform type and save Host Bridge DID to PCD + // + switch (HostBridgeDevId) { + case INTEL_82441_DEVICE_ID: + PmCmd =3D POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET); + Pmba =3D POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA); + PmbaAndVal =3D ~(UINT32)PIIX4_PMBA_MASK; + PmbaOrVal =3D PIIX4_PMBA_VALUE; + AcpiCtlReg =3D POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC); + AcpiEnBit =3D PIIX4_PMREGMISC_PMIOSE; + break; + case INTEL_Q35_MCH_DEVICE_ID: + PmCmd =3D POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET); + Pmba =3D POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE); + PmbaAndVal =3D ~(UINT32)ICH9_PMBASE_MASK; + PmbaOrVal =3D ICH9_PMBASE_VALUE; + AcpiCtlReg =3D POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL); + AcpiEnBit =3D ICH9_ACPI_CNTL_ACPI_EN; + break; + default: + DEBUG (( + DEBUG_ERROR, + "%a: Unknown Host Bridge Device ID: 0x%04x\n", + __FUNCTION__, + HostBridgeDevId + )); + ASSERT (FALSE); + return; + } + + // + // If the appropriate IOspace enable bit is set, assume the ACPI PMBA has + // been configured and skip the setup here. This matches the logic in + // AcpiTimerLibConstructor (). + // + if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) =3D=3D 0) { + // + // The PEI phase should be exited with fully accessibe ACPI PM IO spac= e: + // 1. set PMBA + // + PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal); + + // + // 2. set PCICMD/IOSE + // + PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE); + + // + // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN) + // + PciOr8 (AcpiCtlReg, AcpiEnBit); + } + + if (HostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { + // + // Set Root Complex Register Block BAR + // + PciWrite32 ( + POWER_MGMT_REGISTER_Q35 (ICH9_RCBA), + ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN + ); + + // + // Set PCI Express Register Range Base Address + // + PciExBarInitialization (); + } +} + +/** + Dump the CMOS content + */ +VOID +EFIAPI +PlatformDebugDumpCmos ( + VOID + ) +{ + UINT32 Loop; + + DEBUG ((DEBUG_INFO, "CMOS:\n")); + + for (Loop =3D 0; Loop < 0x80; Loop++) { + if ((Loop % 0x10) =3D=3D 0) { + DEBUG ((DEBUG_INFO, "%02x:", Loop)); + } + + DEBUG ((DEBUG_INFO, " %02x", PlatformCmosRead8 (Loop))); + if ((Loop % 0x10) =3D=3D 0xf) { + DEBUG ((DEBUG_INFO, "\n")); + } + } +} + +/** + Fetch the boot CPU count and the possible CPU count from QEMU. + + @param HostBridgeDevId The Host bridge Dev Id. + @param DefaultMaxCpuCount The default max cpu count. + @param MaxCpuCount The pointer to the returned max cpu count. + @param BootCpuCount The pointer to the returned boot cpu count. +**/ +VOID +EFIAPI +PlatformMaxCpuCountInitialization ( + IN UINT16 HostBridgeDevId, + IN UINT32 DefaultMaxCpuCount, + OUT UINT32 *MaxCpuCount, + OUT UINT16 *BootCpuCount + ) +{ + // + // Try to fetch the boot CPU count. + // + QemuFwCfgSelectItem (QemuFwCfgItemSmpCpuCount); + *BootCpuCount =3D QemuFwCfgRead16 (); + if (*BootCpuCount =3D=3D 0) { + // + // QEMU doesn't report the boot CPU count. (BootCpuCount =3D=3D 0) wil= l let + // MpInitLib count APs up to (PcdCpuMaxLogicalProcessorNumber - 1), or + // until PcdCpuApInitTimeOutInMicroSeconds elapses (whichever is reach= ed + // first). + // + DEBUG ((DEBUG_WARN, "%a: boot CPU count unavailable\n", __FUNCTION__)); + *MaxCpuCount =3D DefaultMaxCpuCount; + } else { + // + // We will expose BootCpuCount to MpInitLib. MpInitLib will count APs = up to + // (BootCpuCount - 1) precisely, regardless of timeout. + // + // Now try to fetch the possible CPU count. + // + UINTN CpuHpBase; + UINT32 CmdData2; + + CpuHpBase =3D ((HostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) ? + ICH9_CPU_HOTPLUG_BASE : PIIX4_CPU_HOTPLUG_BASE); + + // + // If only legacy mode is available in the CPU hotplug register block,= or + // the register block is completely missing, then the writes below are + // no-ops. + // + // 1. Switch the hotplug register block to modern mode. + // + IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, 0); + // + // 2. Select a valid CPU for deterministic reading of + // QEMU_CPUHP_R_CMD_DATA2. + // + // CPU#0 is always valid; it is the always present and non-removable + // BSP. + // + IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, 0); + // + // 3. Send a command after which QEMU_CPUHP_R_CMD_DATA2 is specified to + // read as zero, and which does not invalidate the selector. (The + // selector may change, but it must not become invalid.) + // + // Send QEMU_CPUHP_CMD_GET_PENDING, as it will prove useful later. + // + IoWrite8 (CpuHpBase + QEMU_CPUHP_W_CMD, QEMU_CPUHP_CMD_GET_PENDING); + // + // 4. Read QEMU_CPUHP_R_CMD_DATA2. + // + // If the register block is entirely missing, then this is an unass= igned + // IO read, returning all-bits-one. + // + // If only legacy mode is available, then bit#0 stands for CPU#0 in= the + // "CPU present bitmap". CPU#0 is always present. + // + // Otherwise, QEMU_CPUHP_R_CMD_DATA2 is either still reserved (retu= rning + // all-bits-zero), or it is specified to read as zero after the abo= ve + // steps. Both cases confirm modern mode. + // + CmdData2 =3D IoRead32 (CpuHpBase + QEMU_CPUHP_R_CMD_DATA2); + DEBUG ((DEBUG_VERBOSE, "%a: CmdData2=3D0x%x\n", __FUNCTION__, CmdData2= )); + if (CmdData2 !=3D 0) { + // + // QEMU doesn't support the modern CPU hotplug interface. Assume tha= t the + // possible CPU count equals the boot CPU count (precluding hotplug). + // + DEBUG (( + DEBUG_WARN, + "%a: modern CPU hotplug interface unavailable\n", + __FUNCTION__ + )); + *MaxCpuCount =3D *BootCpuCount; + } else { + // + // Grab the possible CPU count from the modern CPU hotplug interface. + // + UINT32 Present, Possible, Selected; + + Present =3D 0; + Possible =3D 0; + + // + // We've sent QEMU_CPUHP_CMD_GET_PENDING last; this ensures + // QEMU_CPUHP_RW_CMD_DATA can now be read usefully. However, + // QEMU_CPUHP_CMD_GET_PENDING may have selected a CPU with actual pe= nding + // hotplug events; therefore, select CPU#0 forcibly. + // + IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, Possible); + + do { + UINT8 CpuStatus; + + // + // Read the status of the currently selected CPU. This will help w= ith a + // sanity check against "BootCpuCount". + // + CpuStatus =3D IoRead8 (CpuHpBase + QEMU_CPUHP_R_CPU_STAT); + if ((CpuStatus & QEMU_CPUHP_STAT_ENABLED) !=3D 0) { + ++Present; + } + + // + // Attempt to select the next CPU. + // + ++Possible; + IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, Possible); + // + // If the selection is successful, then the following read will re= turn + // the selector (which we know is positive at this point). Otherwi= se, + // the read will return 0. + // + Selected =3D IoRead32 (CpuHpBase + QEMU_CPUHP_RW_CMD_DATA); + ASSERT (Selected =3D=3D Possible || Selected =3D=3D 0); + } while (Selected > 0); + + // + // Sanity check: fw_cfg and the modern CPU hotplug interface should + // return the same boot CPU count. + // + if (*BootCpuCount !=3D Present) { + DEBUG (( + DEBUG_WARN, + "%a: QEMU v2.7 reset bug: BootCpuCount=3D%d " + "Present=3D%u\n", + __FUNCTION__, + *BootCpuCount, + Present + )); + // + // The handling of QemuFwCfgItemSmpCpuCount, across CPU hotplug pl= us + // platform reset (including S3), was corrected in QEMU commit + // e3cadac073a9 ("pc: fix FW_CFG_NB_CPUS to account for -device ad= ded + // CPUs", 2016-11-16), part of release v2.8.0. + // + *BootCpuCount =3D (UINT16)Present; + } + + *MaxCpuCount =3D Possible; + } + } + + DEBUG (( + DEBUG_INFO, + "%a: BootCpuCount=3D%d MaxCpuCount=3D%u\n", + __FUNCTION__, + *BootCpuCount, + *MaxCpuCount + )); + ASSERT (*BootCpuCount <=3D *MaxCpuCount); +} + +/** + * Query Host Bridge Dev Id. + * + * @return Host Bridge Dev Id. + */ +UINT16 +EFIAPI +PlatformQueryHostBridgeDid ( + VOID + ) +{ + return PciRead16 (OVMF_HOSTBRIDGE_DID); +} diff --git a/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf b/OvmfPkg/= Library/PlatformInitLib/PlatformInitLib.inf new file mode 100644 index 000000000000..060ce0f54f2b --- /dev/null +++ b/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf @@ -0,0 +1,86 @@ +## @file +# Platform Initialization Lib +# +# This module provides platform specific function to detect boot mode. +# Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PlatformInitLib + FILE_GUID =3D 89f886b0-7109-46e1-9d28-503ad4ab6ee0 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PlatformInitLib|SEC PEIM + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 EBC +# + +[Sources] + Cmos.c + MemDetect.c + Platform.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + OvmfPkg/OvmfPkg.dec + +[Guids] + gEfiMemoryTypeInformationGuid + gFdtHobGuid + +[LibraryClasses] + BaseLib + DebugLib + HobLib + IoLib + PciLib + QemuFwCfgLib + QemuFwCfgSimpleParserLib + MtrrLib + PcdLib + +[FixedPcd] + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidSize + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBackupBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBackupSize + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaSize + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSnpSecretsBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSnpSecretsSize + + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesSize + + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize + + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableSize + + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbSize + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress + +[FeaturePcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec index 0e55912c8711..230d24bc7299 100644 --- a/OvmfPkg/OvmfPkg.dec +++ b/OvmfPkg/OvmfPkg.dec @@ -113,6 +113,10 @@ # TdxMailboxLib|Include/Library/TdxMailboxLib.h =20 + ## @libraryclass PlatformInitLib + # + PlatformInitLib|Include/Library/PlatformInitLib.h + [Guids] gUefiOvmfPkgTokenSpaceGuid =3D {0x93bb96af, 0xb9f2, 0x4eb8, {= 0x94, 0x62, 0xe0, 0xba, 0x74, 0x56, 0x42, 0x36}} gEfiXenInfoGuid =3D {0xd3b46f3b, 0xd441, 0x1244, {= 0x9a, 0x12, 0x0, 0x12, 0x27, 0x3f, 0xc1, 0x4d}} --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85992): https://edk2.groups.io/g/devel/message/85992 Mute This Topic: https://groups.io/mt/88617547/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Apr 29 10:32:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+85993+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85993+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1642901978; cv=none; d=zohomail.com; s=zohoarc; b=i3Bjy0XAFDG0LaypkLCui9exuAAd7x+F99nNWz2mR6ls3Hp9LGwnog+kmcW9W/1/960CCipdddAwgY8lSKJbC8qqKpZkLWYQ3CdPAWpy9IL4qOHihlC7P5BmMQ7eMIHztd++N75I1BeYbXxeCgaxdr4tLuuWPwMtUl1Gz18x6ps= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1642901978; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=cdeE8gnvV1NpOFoCspXcY//yKOI8fKpTZRJoiZxBR4w=; b=iRQPy6L8JxCLsfOT3Qu3L8QqZUWFTMKHPxkuyFkpCXSEF3x2Y6HJJXDJzoZuM7lYVa4An5FxE7FurO3Xr/SJG8IuNii1c0PMOa+eVUUstjuWMK1KzFEZs9ivEmG+4tC8KUpx6JX2Rx15/CyDGEHbgbIx6YUySwLKJst357VRDDM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85993+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1642901978569419.37326008521984; Sat, 22 Jan 2022 17:39:38 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id zTDPYY1788612xFMclIC0Xld; Sat, 22 Jan 2022 17:39:38 -0800 X-Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web08.4550.1642901975552765292 for ; Sat, 22 Jan 2022 17:39:36 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10235"; a="244686094" X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="244686094" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:39:22 -0800 X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="695033261" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.255.30.84]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:39:19 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann Subject: [edk2-devel] [PATCH V5 23/33] OvmfPkg: Refactor PlatformPei with PlatformInitLib Date: Sun, 23 Jan 2022 09:36:54 +0800 Message-Id: <69f38db6daff718e3d5a1856cb9e7b1eb2b2ff8e.1642899774.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: lztr7D99INAXJ26XEABDXiP2x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1642901978; bh=BvT0WzZWo1o3gnceDwWVD7HHy/mdl4x62s+17oUyQKU=; h=Cc:Date:From:Reply-To:Subject:To; b=jOmUC9pPEDzS8/bSxWzHwMcgE5r/QI2hg1mNIoCxl6Gf1/c8HSg9PeCOtBw4ru7E9nn HalAaHeHJJpdUyOz87U3eZ3BU9PxYgv+UvF4yYYooZuVdsVZoi9LBBD2JmMmqYBELLKjo mPvjenk7lGMkAyFQjXkIZg2ucs/76DG5IhQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1642901980420100006 Content-Type: text/plain; charset="utf-8" RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 PlatformInitLib wraps the common functions in OvmfPkg/PlatformPei. After it is introduced, OvmfPkg/PlatformPei is refactored with it. Other variants of PlatformPei will be refactored in the future as the next stages. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Signed-off-by: Min Xu --- OvmfPkg/AmdSev/AmdSevX64.dsc | 1 + OvmfPkg/CloudHv/CloudHvX64.dsc | 1 + OvmfPkg/Microvm/MicrovmX64.dsc | 1 + OvmfPkg/OvmfPkgIa32.dsc | 1 + OvmfPkg/OvmfPkgIa32X64.dsc | 1 + OvmfPkg/OvmfPkgX64.dsc | 1 + OvmfPkg/PlatformPei/Cmos.c | 55 --- OvmfPkg/PlatformPei/Cmos.h | 48 -- OvmfPkg/PlatformPei/MemDetect.c | 657 ++-------------------------- OvmfPkg/PlatformPei/Platform.c | 507 ++------------------- OvmfPkg/PlatformPei/Platform.h | 36 -- OvmfPkg/PlatformPei/PlatformPei.inf | 3 +- 12 files changed, 78 insertions(+), 1234 deletions(-) delete mode 100644 OvmfPkg/PlatformPei/Cmos.c delete mode 100644 OvmfPkg/PlatformPei/Cmos.h diff --git a/OvmfPkg/AmdSev/AmdSevX64.dsc b/OvmfPkg/AmdSev/AmdSevX64.dsc index 648d3accd95c..53464f3a54b9 100644 --- a/OvmfPkg/AmdSev/AmdSevX64.dsc +++ b/OvmfPkg/AmdSev/AmdSevX64.dsc @@ -277,6 +277,7 @@ QemuLoadImageLib|OvmfPkg/Library/GenericQemuLoadImageLib/GenericQemuLoad= ImageLib.inf PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf + PlatformInitLib|OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf =20 !include OvmfPkg/OvmfTpmLibsPeim.dsc.inc =20 diff --git a/OvmfPkg/CloudHv/CloudHvX64.dsc b/OvmfPkg/CloudHv/CloudHvX64.dsc index 191dd2c5053f..ddd2d67025e1 100644 --- a/OvmfPkg/CloudHv/CloudHvX64.dsc +++ b/OvmfPkg/CloudHv/CloudHvX64.dsc @@ -304,6 +304,7 @@ QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/PeiQemuFwCfgS3LibFwCfg.inf PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf + PlatformInitLib|OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf =20 !include OvmfPkg/OvmfTpmLibsPeim.dsc.inc =20 diff --git a/OvmfPkg/Microvm/MicrovmX64.dsc b/OvmfPkg/Microvm/MicrovmX64.dsc index c45e37dc7da0..a09f542c83fb 100644 --- a/OvmfPkg/Microvm/MicrovmX64.dsc +++ b/OvmfPkg/Microvm/MicrovmX64.dsc @@ -301,6 +301,7 @@ QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf =20 MemEncryptSevLib|OvmfPkg/Library/BaseMemEncryptSevLib/PeiMemEncryptSevLi= b.inf + PlatformInitLib|OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf =20 [LibraryClasses.common.DXE_CORE] HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc index 085cc7ece15d..3f52939ab6d2 100644 --- a/OvmfPkg/OvmfPkgIa32.dsc +++ b/OvmfPkg/OvmfPkgIa32.dsc @@ -300,6 +300,7 @@ QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/PeiQemuFwCfgS3LibFwCfg.inf PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf + PlatformInitLib|OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf =20 !include OvmfPkg/OvmfTpmLibsPeim.dsc.inc =20 diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc index 57e8bfb6b80f..30e01feeb539 100644 --- a/OvmfPkg/OvmfPkgIa32X64.dsc +++ b/OvmfPkg/OvmfPkgIa32X64.dsc @@ -306,6 +306,7 @@ QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/PeiQemuFwCfgS3LibFwCfg.inf PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf + PlatformInitLib|OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf =20 !include OvmfPkg/OvmfTpmLibsPeim.dsc.inc =20 diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index 843f7a2e7bf6..5fc6d14ee011 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -307,6 +307,7 @@ QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/PeiQemuFwCfgS3LibFwCfg.inf PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf + PlatformInitLib|OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf =20 !include OvmfPkg/OvmfTpmLibsPeim.dsc.inc =20 diff --git a/OvmfPkg/PlatformPei/Cmos.c b/OvmfPkg/PlatformPei/Cmos.c deleted file mode 100644 index a01b3866bee4..000000000000 --- a/OvmfPkg/PlatformPei/Cmos.c +++ /dev/null @@ -1,55 +0,0 @@ -/** @file - PC/AT CMOS access routines - - Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include "Cmos.h" -#include "Library/IoLib.h" - -/** - Reads 8-bits of CMOS data. - - Reads the 8-bits of CMOS data at the location specified by Index. - The 8-bit read value is returned. - - @param Index The CMOS location to read. - - @return The value read. - -**/ -UINT8 -EFIAPI -CmosRead8 ( - IN UINTN Index - ) -{ - IoWrite8 (0x70, (UINT8)Index); - return IoRead8 (0x71); -} - -/** - Writes 8-bits of CMOS data. - - Writes 8-bits of CMOS data to the location specified by Index - with the value specified by Value and returns Value. - - @param Index The CMOS location to write. - @param Value The value to write to CMOS. - - @return The value written to CMOS. - -**/ -UINT8 -EFIAPI -CmosWrite8 ( - IN UINTN Index, - IN UINT8 Value - ) -{ - IoWrite8 (0x70, (UINT8)Index); - IoWrite8 (0x71, Value); - return Value; -} diff --git a/OvmfPkg/PlatformPei/Cmos.h b/OvmfPkg/PlatformPei/Cmos.h deleted file mode 100644 index 2b3124d7ba36..000000000000 --- a/OvmfPkg/PlatformPei/Cmos.h +++ /dev/null @@ -1,48 +0,0 @@ -/** @file - PC/AT CMOS access routines - - Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef __CMOS_H__ -#define __CMOS_H__ - -/** - Reads 8-bits of CMOS data. - - Reads the 8-bits of CMOS data at the location specified by Index. - The 8-bit read value is returned. - - @param Index The CMOS location to read. - - @return The value read. - -**/ -UINT8 -EFIAPI -CmosRead8 ( - IN UINTN Index - ); - -/** - Writes 8-bits of CMOS data. - - Writes 8-bits of CMOS data to the location specified by Index - with the value specified by Value and returns Value. - - @param Index The CMOS location to write. - @param Value The value to write to CMOS. - - @return The value written to CMOS. - -**/ -UINT8 -EFIAPI -CmosWrite8 ( - IN UINTN Index, - IN UINT8 Value - ); - -#endif diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetec= t.c index 1bcb5a08bca6..0c930ab1d70e 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -36,9 +36,8 @@ Module Name: #include #include #include - +#include #include "Platform.h" -#include "Cmos.h" =20 UINT8 mPhysMemAddressWidth; =20 @@ -50,6 +49,7 @@ STATIC UINT16 mQ35TsegMbytes; BOOLEAN mQ35SmramAtDefaultSmbase; =20 UINT32 mQemuUc32Base; +UINT32 mLowerMemorySize =3D 0; =20 VOID Q35TsegMbytesInitialization ( @@ -140,406 +140,11 @@ QemuUc32BaseInitialization ( VOID ) { - UINT32 LowerMemorySize; - UINT32 Uc32Size; - if (mHostBridgeDevId =3D=3D 0xffff /* microvm */) { return; } =20 - if (mHostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { - // - // On q35, the 32-bit area that we'll mark as UC, through variable MTR= Rs, - // starts at PcdPciExpressBaseAddress. The platform DSC is responsible= for - // setting PcdPciExpressBaseAddress such that describing the - // [PcdPciExpressBaseAddress, 4GB) range require a very small number of - // variable MTRRs (preferably 1 or 2). - // - ASSERT (FixedPcdGet64 (PcdPciExpressBaseAddress) <=3D MAX_UINT32); - mQemuUc32Base =3D (UINT32)FixedPcdGet64 (PcdPciExpressBaseAddress); - return; - } - - if (mHostBridgeDevId =3D=3D CLOUDHV_DEVICE_ID) { - Uc32Size =3D CLOUDHV_MMIO_HOLE_SIZE; - mQemuUc32Base =3D CLOUDHV_MMIO_HOLE_ADDRESS; - return; - } - - ASSERT (mHostBridgeDevId =3D=3D INTEL_82441_DEVICE_ID); - // - // On i440fx, start with the [LowerMemorySize, 4GB) range. Make sure one - // variable MTRR suffices by truncating the size to a whole power of two, - // while keeping the end affixed to 4GB. This will round the base up. - // - LowerMemorySize =3D GetSystemMemorySizeBelow4gb (); - Uc32Size =3D GetPowerOfTwo32 ((UINT32)(SIZE_4GB - LowerMemorySize= )); - mQemuUc32Base =3D (UINT32)(SIZE_4GB - Uc32Size); - // - // Assuming that LowerMemorySize is at least 1 byte, Uc32Size is at most= 2GB. - // Therefore mQemuUc32Base is at least 2GB. - // - ASSERT (mQemuUc32Base >=3D BASE_2GB); - - if (mQemuUc32Base !=3D LowerMemorySize) { - DEBUG (( - DEBUG_VERBOSE, - "%a: rounded UC32 base from 0x%x up to 0x%x, for " - "an UC32 size of 0x%x\n", - __FUNCTION__, - LowerMemorySize, - mQemuUc32Base, - Uc32Size - )); - } -} - -/** - Iterate over the RAM entries in QEMU's fw_cfg E820 RAM map that start ou= tside - of the 32-bit address range. - - Find the highest exclusive >=3D4GB RAM address, or produce memory resour= ce - descriptor HOBs for RAM entries that start at or above 4GB. - - @param[out] MaxAddress If MaxAddress is NULL, then ScanOrAdd64BitE820Ra= m() - produces memory resource descriptor HOBs for RAM - entries that start at or above 4GB. - - Otherwise, MaxAddress holds the highest exclusive - >=3D4GB RAM address on output. If QEMU's fw_cfg = E820 - RAM map contains no RAM entry that starts outsid= e of - the 32-bit address range, then MaxAddress is exa= ctly - 4GB on output. - - @retval EFI_SUCCESS The fw_cfg E820 RAM map was found and proces= sed. - - @retval EFI_PROTOCOL_ERROR The RAM map was found, but its size wasn't a - whole multiple of sizeof(EFI_E820_ENTRY64). = No - RAM entry was processed. - - @return Error codes from QemuFwCfgFindFile(). No RAM - entry was processed. -**/ -STATIC -EFI_STATUS -ScanOrAdd64BitE820Ram ( - IN BOOLEAN AddHighHob, - OUT UINT64 *LowMemory OPTIONAL, - OUT UINT64 *MaxAddress OPTIONAL - ) -{ - EFI_STATUS Status; - FIRMWARE_CONFIG_ITEM FwCfgItem; - UINTN FwCfgSize; - EFI_E820_ENTRY64 E820Entry; - UINTN Processed; - - Status =3D QemuFwCfgFindFile ("etc/e820", &FwCfgItem, &FwCfgSize); - if (EFI_ERROR (Status)) { - return Status; - } - - if (FwCfgSize % sizeof E820Entry !=3D 0) { - return EFI_PROTOCOL_ERROR; - } - - if (LowMemory !=3D NULL) { - *LowMemory =3D 0; - } - - if (MaxAddress !=3D NULL) { - *MaxAddress =3D BASE_4GB; - } - - QemuFwCfgSelectItem (FwCfgItem); - for (Processed =3D 0; Processed < FwCfgSize; Processed +=3D sizeof E820E= ntry) { - QemuFwCfgReadBytes (sizeof E820Entry, &E820Entry); - DEBUG (( - DEBUG_VERBOSE, - "%a: Base=3D0x%Lx Length=3D0x%Lx Type=3D%u\n", - __FUNCTION__, - E820Entry.BaseAddr, - E820Entry.Length, - E820Entry.Type - )); - if (E820Entry.Type =3D=3D EfiAcpiAddressRangeMemory) { - if (AddHighHob && (E820Entry.BaseAddr >=3D BASE_4GB)) { - UINT64 Base; - UINT64 End; - - // - // Round up the start address, and round down the end address. - // - Base =3D ALIGN_VALUE (E820Entry.BaseAddr, (UINT64)EFI_PAGE_SIZE); - End =3D (E820Entry.BaseAddr + E820Entry.Length) & - ~(UINT64)EFI_PAGE_MASK; - if (Base < End) { - AddMemoryRangeHob (Base, End); - DEBUG (( - DEBUG_VERBOSE, - "%a: AddMemoryRangeHob [0x%Lx, 0x%Lx)\n", - __FUNCTION__, - Base, - End - )); - } - } - - if (MaxAddress || LowMemory) { - UINT64 Candidate; - - Candidate =3D E820Entry.BaseAddr + E820Entry.Length; - if (MaxAddress && (Candidate > *MaxAddress)) { - *MaxAddress =3D Candidate; - DEBUG (( - DEBUG_VERBOSE, - "%a: MaxAddress=3D0x%Lx\n", - __FUNCTION__, - *MaxAddress - )); - } - - if (LowMemory && (Candidate > *LowMemory) && (Candidate < BASE_4GB= )) { - *LowMemory =3D Candidate; - DEBUG (( - DEBUG_VERBOSE, - "%a: LowMemory=3D0x%Lx\n", - __FUNCTION__, - *LowMemory - )); - } - } - } - } - - return EFI_SUCCESS; -} - -UINT32 -GetSystemMemorySizeBelow4gb ( - VOID - ) -{ - EFI_STATUS Status; - UINT64 LowerMemorySize =3D 0; - UINT8 Cmos0x34; - UINT8 Cmos0x35; - - Status =3D ScanOrAdd64BitE820Ram (FALSE, &LowerMemorySize, NULL); - if ((Status =3D=3D EFI_SUCCESS) && (LowerMemorySize > 0)) { - return (UINT32)LowerMemorySize; - } - - // - // CMOS 0x34/0x35 specifies the system memory above 16 MB. - // * CMOS(0x35) is the high byte - // * CMOS(0x34) is the low byte - // * The size is specified in 64kb chunks - // * Since this is memory above 16MB, the 16MB must be added - // into the calculation to get the total memory size. - // - - Cmos0x34 =3D (UINT8)CmosRead8 (0x34); - Cmos0x35 =3D (UINT8)CmosRead8 (0x35); - - return (UINT32)(((UINTN)((Cmos0x35 << 8) + Cmos0x34) << 16) + SIZE_16MB); -} - -STATIC -UINT64 -GetSystemMemorySizeAbove4gb ( - ) -{ - UINT32 Size; - UINTN CmosIndex; - - // - // CMOS 0x5b-0x5d specifies the system memory above 4GB MB. - // * CMOS(0x5d) is the most significant size byte - // * CMOS(0x5c) is the middle size byte - // * CMOS(0x5b) is the least significant size byte - // * The size is specified in 64kb chunks - // - - Size =3D 0; - for (CmosIndex =3D 0x5d; CmosIndex >=3D 0x5b; CmosIndex--) { - Size =3D (UINT32)(Size << 8) + (UINT32)CmosRead8 (CmosIndex); - } - - return LShiftU64 (Size, 16); -} - -/** - Return the highest address that DXE could possibly use, plus one. -**/ -STATIC -UINT64 -GetFirstNonAddress ( - VOID - ) -{ - UINT64 FirstNonAddress; - UINT64 Pci64Base, Pci64Size; - UINT32 FwCfgPciMmio64Mb; - EFI_STATUS Status; - FIRMWARE_CONFIG_ITEM FwCfgItem; - UINTN FwCfgSize; - UINT64 HotPlugMemoryEnd; - RETURN_STATUS PcdStatus; - - // - // set FirstNonAddress to suppress incorrect compiler/analyzer warnings - // - FirstNonAddress =3D 0; - - // - // If QEMU presents an E820 map, then get the highest exclusive >=3D4GB = RAM - // address from it. This can express an address >=3D 4GB+1TB. - // - // Otherwise, get the flat size of the memory above 4GB from the CMOS (w= hich - // can only express a size smaller than 1TB), and add it to 4GB. - // - Status =3D ScanOrAdd64BitE820Ram (FALSE, NULL, &FirstNonAddress); - if (EFI_ERROR (Status)) { - FirstNonAddress =3D BASE_4GB + GetSystemMemorySizeAbove4gb (); - } - - // - // If DXE is 32-bit, then we're done; PciBusDxe will degrade 64-bit MMIO - // resources to 32-bit anyway. See DegradeResource() in - // "PciResourceSupport.c". - // - #ifdef MDE_CPU_IA32 - if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) { - return FirstNonAddress; - } - - #endif - - // - // Otherwise, in order to calculate the highest address plus one, we must - // consider the 64-bit PCI host aperture too. Fetch the default size. - // - Pci64Size =3D PcdGet64 (PcdPciMmio64Size); - - // - // See if the user specified the number of megabytes for the 64-bit PCI = host - // aperture. Accept an aperture size up to 16TB. - // - // As signaled by the "X-" prefix, this knob is experimental, and might = go - // away at any time. - // - Status =3D QemuFwCfgParseUint32 ( - "opt/ovmf/X-PciMmio64Mb", - FALSE, - &FwCfgPciMmio64Mb - ); - switch (Status) { - case EFI_UNSUPPORTED: - case EFI_NOT_FOUND: - break; - case EFI_SUCCESS: - if (FwCfgPciMmio64Mb <=3D 0x1000000) { - Pci64Size =3D LShiftU64 (FwCfgPciMmio64Mb, 20); - break; - } - - // - // fall through - // - default: - DEBUG (( - DEBUG_WARN, - "%a: ignoring malformed 64-bit PCI host aperture size from fw_cfg\= n", - __FUNCTION__ - )); - break; - } - - if (Pci64Size =3D=3D 0) { - if (mBootMode !=3D BOOT_ON_S3_RESUME) { - DEBUG (( - DEBUG_INFO, - "%a: disabling 64-bit PCI host aperture\n", - __FUNCTION__ - )); - PcdStatus =3D PcdSet64S (PcdPciMmio64Size, 0); - ASSERT_RETURN_ERROR (PcdStatus); - } - - // - // There's nothing more to do; the amount of memory above 4GB fully - // determines the highest address plus one. The memory hotplug area (s= ee - // below) plays no role for the firmware in this case. - // - return FirstNonAddress; - } - - // - // The "etc/reserved-memory-end" fw_cfg file, when present, contains an - // absolute, exclusive end address for the memory hotplug area. This area - // starts right at the end of the memory above 4GB. The 64-bit PCI host - // aperture must be placed above it. - // - Status =3D QemuFwCfgFindFile ( - "etc/reserved-memory-end", - &FwCfgItem, - &FwCfgSize - ); - if (!EFI_ERROR (Status) && (FwCfgSize =3D=3D sizeof HotPlugMemoryEnd)) { - QemuFwCfgSelectItem (FwCfgItem); - QemuFwCfgReadBytes (FwCfgSize, &HotPlugMemoryEnd); - DEBUG (( - DEBUG_VERBOSE, - "%a: HotPlugMemoryEnd=3D0x%Lx\n", - __FUNCTION__, - HotPlugMemoryEnd - )); - - ASSERT (HotPlugMemoryEnd >=3D FirstNonAddress); - FirstNonAddress =3D HotPlugMemoryEnd; - } - - // - // SeaBIOS aligns both boundaries of the 64-bit PCI host aperture to 1GB= , so - // that the host can map it with 1GB hugepages. Follow suit. - // - Pci64Base =3D ALIGN_VALUE (FirstNonAddress, (UINT64)SIZE_1GB); - Pci64Size =3D ALIGN_VALUE (Pci64Size, (UINT64)SIZE_1GB); - - // - // The 64-bit PCI host aperture should also be "naturally" aligned. The - // alignment is determined by rounding the size of the aperture down to = the - // next smaller or equal power of two. That is, align the aperture by the - // largest BAR size that can fit into it. - // - Pci64Base =3D ALIGN_VALUE (Pci64Base, GetPowerOfTwo64 (Pci64Size)); - - if (mBootMode !=3D BOOT_ON_S3_RESUME) { - // - // The core PciHostBridgeDxe driver will automatically add this range = to - // the GCD memory space map through our PciHostBridgeLib instance; her= e we - // only need to set the PCDs. - // - PcdStatus =3D PcdSet64S (PcdPciMmio64Base, Pci64Base); - ASSERT_RETURN_ERROR (PcdStatus); - PcdStatus =3D PcdSet64S (PcdPciMmio64Size, Pci64Size); - ASSERT_RETURN_ERROR (PcdStatus); - - DEBUG (( - DEBUG_INFO, - "%a: Pci64Base=3D0x%Lx Pci64Size=3D0x%Lx\n", - __FUNCTION__, - Pci64Base, - Pci64Size - )); - } - - // - // The useful address space ends with the 64-bit PCI host aperture. - // - FirstNonAddress =3D Pci64Base + Pci64Size; - return FirstNonAddress; + mQemuUc32Base =3D PlatformQemuUc32BaseInitialization (mHostBridgeDevId, = mLowerMemorySize); } =20 /** @@ -550,36 +155,19 @@ AddressWidthInitialization ( VOID ) { - UINT64 FirstNonAddress; - - // - // As guest-physical memory size grows, the permanent PEI RAM requiremen= ts - // are dominated by the identity-mapping page tables built by the DXE IP= L. - // The DXL IPL keys off of the physical address bits advertized in the C= PU - // HOB. To conserve memory, we calculate the minimum address width here. - // - FirstNonAddress =3D GetFirstNonAddress (); - mPhysMemAddressWidth =3D (UINT8)HighBitSet64 (FirstNonAddress); - - // - // If FirstNonAddress is not an integral power of two, then we need an - // additional bit. - // - if ((FirstNonAddress & (FirstNonAddress - 1)) !=3D 0) { - ++mPhysMemAddressWidth; - } - - // - // The minimum address width is 36 (covers up to and excluding 64 GB, wh= ich - // is the maximum for Ia32 + PAE). The theoretical architecture maximum = for - // X64 long mode is 52 bits, but the DXE IPL clamps that down to 48 bits= . We - // can simply assert that here, since 48 bits are good enough for 256 TB. - // - if (mPhysMemAddressWidth <=3D 36) { - mPhysMemAddressWidth =3D 36; - } - - ASSERT (mPhysMemAddressWidth <=3D 48); + UINT64 Pci64Base; + UINT64 Pci64Size; + UINT64 FirstNonAddress; + RETURN_STATUS PcdStatus; + + Pci64Base =3D 0; + Pci64Size =3D 0; + FirstNonAddress =3D PlatformGetFirstNonAddress (&Pci64Base, &Pci64S= ize, PcdGet64 (PcdPciMmio64Size)); + mPhysMemAddressWidth =3D PlatformAddressWidthInitialization (FirstNonAdd= ress); + PcdStatus =3D PcdSet64S (PcdPciMmio64Base, Pci64Base); + ASSERT_RETURN_ERROR (PcdStatus); + PcdStatus =3D PcdSet64S (PcdPciMmio64Size, Pci64Size); + ASSERT_RETURN_ERROR (PcdStatus); } =20 /** @@ -664,7 +252,7 @@ PublishPeiMemory ( UINT32 LowerMemorySize; UINT32 PeiMemoryCap; =20 - LowerMemorySize =3D GetSystemMemorySizeBelow4gb (); + LowerMemorySize =3D PlatformGetSystemMemorySizeBelow4gb (); if (FeaturePcdGet (PcdSmmSmramRequire)) { // // TSEG is chipped from the end of low RAM @@ -736,162 +324,6 @@ PublishPeiMemory ( return Status; } =20 -STATIC -VOID -QemuInitializeRamBelow1gb ( - VOID - ) -{ - if (FeaturePcdGet (PcdSmmSmramRequire) && mQ35SmramAtDefaultSmbase) { - AddMemoryRangeHob (0, SMM_DEFAULT_SMBASE); - AddReservedMemoryBaseSizeHob ( - SMM_DEFAULT_SMBASE, - MCH_DEFAULT_SMBASE_SIZE, - TRUE /* Cacheable */ - ); - STATIC_ASSERT ( - SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE < BASE_512KB + BASE_128= KB, - "end of SMRAM at default SMBASE ends at, or exceeds, 640KB" - ); - AddMemoryRangeHob ( - SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE, - BASE_512KB + BASE_128KB - ); - } else { - AddMemoryRangeHob (0, BASE_512KB + BASE_128KB); - } -} - -/** - Peform Memory Detection for QEMU / KVM - -**/ -STATIC -VOID -QemuInitializeRam ( - VOID - ) -{ - UINT64 LowerMemorySize; - UINT64 UpperMemorySize; - MTRR_SETTINGS MtrrSettings; - EFI_STATUS Status; - - DEBUG ((DEBUG_INFO, "%a called\n", __FUNCTION__)); - - // - // Determine total memory size available - // - LowerMemorySize =3D GetSystemMemorySizeBelow4gb (); - - if (mBootMode =3D=3D BOOT_ON_S3_RESUME) { - // - // Create the following memory HOB as an exception on the S3 boot path. - // - // Normally we'd create memory HOBs only on the normal boot path. Howe= ver, - // CpuMpPei specifically needs such a low-memory HOB on the S3 path as - // well, for "borrowing" a subset of it temporarily, for the AP startup - // vector. - // - // CpuMpPei saves the original contents of the borrowed area in perman= ent - // PEI RAM, in a backup buffer allocated with the normal PEI services. - // CpuMpPei restores the original contents ("returns" the borrowed are= a) at - // End-of-PEI. End-of-PEI in turn is emitted by S3Resume2Pei before - // transferring control to the OS's wakeup vector in the FACS. - // - // We expect any other PEIMs that "borrow" memory similarly to CpuMpPe= i to - // restore the original contents. Furthermore, we expect all such PEIMs - // (CpuMpPei included) to claim the borrowed areas by producing memory - // allocation HOBs, and to honor preexistent memory allocation HOBs wh= en - // looking for an area to borrow. - // - QemuInitializeRamBelow1gb (); - } else { - // - // Create memory HOBs - // - QemuInitializeRamBelow1gb (); - - if (FeaturePcdGet (PcdSmmSmramRequire)) { - UINT32 TsegSize; - - TsegSize =3D mQ35TsegMbytes * SIZE_1MB; - AddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize); - AddReservedMemoryBaseSizeHob ( - LowerMemorySize - TsegSize, - TsegSize, - TRUE - ); - } else { - AddMemoryRangeHob (BASE_1MB, LowerMemorySize); - } - - // - // If QEMU presents an E820 map, then create memory HOBs for the >=3D4= GB RAM - // entries. Otherwise, create a single memory HOB with the flat >=3D4GB - // memory size read from the CMOS. - // - Status =3D ScanOrAdd64BitE820Ram (TRUE, NULL, NULL); - if (EFI_ERROR (Status)) { - UpperMemorySize =3D GetSystemMemorySizeAbove4gb (); - if (UpperMemorySize !=3D 0) { - AddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize); - } - } - } - - // - // We'd like to keep the following ranges uncached: - // - [640 KB, 1 MB) - // - [LowerMemorySize, 4 GB) - // - // Everything else should be WB. Unfortunately, programming the inverse = (ie. - // keeping the default UC, and configuring the complement set of the abo= ve as - // WB) is not reliable in general, because the end of the upper RAM can = have - // practically any alignment, and we may not have enough variable MTRRs = to - // cover it exactly. - // - if (IsMtrrSupported () && (mHostBridgeDevId !=3D CLOUDHV_DEVICE_ID)) { - MtrrGetAllMtrrs (&MtrrSettings); - - // - // MTRRs disabled, fixed MTRRs disabled, default type is uncached - // - ASSERT ((MtrrSettings.MtrrDefType & BIT11) =3D=3D 0); - ASSERT ((MtrrSettings.MtrrDefType & BIT10) =3D=3D 0); - ASSERT ((MtrrSettings.MtrrDefType & 0xFF) =3D=3D 0); - - // - // flip default type to writeback - // - SetMem (&MtrrSettings.Fixed, sizeof MtrrSettings.Fixed, 0x06); - ZeroMem (&MtrrSettings.Variables, sizeof MtrrSettings.Variables); - MtrrSettings.MtrrDefType |=3D BIT11 | BIT10 | 6; - MtrrSetAllMtrrs (&MtrrSettings); - - // - // Set memory range from 640KB to 1MB to uncacheable - // - Status =3D MtrrSetMemoryAttribute ( - BASE_512KB + BASE_128KB, - BASE_1MB - (BASE_512KB + BASE_128KB), - CacheUncacheable - ); - ASSERT_EFI_ERROR (Status); - - // - // Set the memory range from the start of the 32-bit MMIO area (32-bit= PCI - // MMIO aperture on i440fx, PCIEXBAR on q35) to 4GB as uncacheable. - // - Status =3D MtrrSetMemoryAttribute ( - mQemuUc32Base, - SIZE_4GB - mQemuUc32Base, - CacheUncacheable - ); - ASSERT_EFI_ERROR (Status); - } -} - /** Publish system RAM and reserve memory regions =20 @@ -901,7 +333,15 @@ InitializeRamRegions ( VOID ) { - QemuInitializeRam (); + PlatformInitializeRamRegions ( + mQemuUc32Base, + mHostBridgeDevId, + FeaturePcdGet (PcdSmmSmramRequire), + mBootMode, + mS3Supported, + mLowerMemorySize, + mQ35TsegMbytes + ); =20 SevInitializeRam (); =20 @@ -979,28 +419,6 @@ InitializeRamRegions ( } =20 if (mBootMode !=3D BOOT_ON_S3_RESUME) { - if (!FeaturePcdGet (PcdSmmSmramRequire)) { - // - // Reserve the lock box storage area - // - // Since this memory range will be used on S3 resume, it must be - // reserved as ACPI NVS. - // - // If S3 is unsupported, then various drivers might still write to t= he - // LockBox area. We ought to prevent DXE from serving allocation req= uests - // such that they would overlap the LockBox storage. - // - ZeroMem ( - (VOID *)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageBase), - (UINTN)PcdGet32 (PcdOvmfLockBoxStorageSize) - ); - BuildMemoryAllocationHob ( - (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageBase), - (UINT64)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageSize), - mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData - ); - } - if (FeaturePcdGet (PcdSmmSmramRequire)) { UINT32 TsegSize; =20 @@ -1010,7 +428,7 @@ InitializeRamRegions ( // TsegSize =3D mQ35TsegMbytes * SIZE_1MB; BuildMemoryAllocationHob ( - GetSystemMemorySizeBelow4gb () - TsegSize, + PlatformGetSystemMemorySizeBelow4gb () - TsegSize, TsegSize, EfiReservedMemoryType ); @@ -1026,26 +444,5 @@ InitializeRamRegions ( ); } } - - #ifdef MDE_CPU_X64 - if (FixedPcdGet32 (PcdOvmfWorkAreaSize) !=3D 0) { - // - // Reserve the work area. - // - // Since this memory range will be used by the Reset Vector on S3 - // resume, it must be reserved as ACPI NVS. - // - // If S3 is unsupported, then various drivers might still write to t= he - // work area. We ought to prevent DXE from serving allocation reques= ts - // such that they would overlap the work area. - // - BuildMemoryAllocationHob ( - (EFI_PHYSICAL_ADDRESS)(UINTN)FixedPcdGet32 (PcdOvmfWorkAreaBase), - (UINT64)(UINTN)FixedPcdGet32 (PcdOvmfWorkAreaSize), - mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData - ); - } - - #endif } } diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index d0323c645162..05a5c94ce80a 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -37,9 +37,8 @@ #include #include #include - +#include #include "Platform.h" -#include "Cmos.h" =20 EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] =3D { { @@ -57,84 +56,7 @@ BOOLEAN mS3Supported =3D FALSE; =20 UINT32 mMaxCpuCount; =20 -VOID -AddIoMemoryBaseSizeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - UINT64 MemorySize - ) -{ - BuildResourceDescriptorHob ( - EFI_RESOURCE_MEMORY_MAPPED_IO, - EFI_RESOURCE_ATTRIBUTE_PRESENT | - EFI_RESOURCE_ATTRIBUTE_INITIALIZED | - EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | - EFI_RESOURCE_ATTRIBUTE_TESTED, - MemoryBase, - MemorySize - ); -} - -VOID -AddReservedMemoryBaseSizeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - UINT64 MemorySize, - BOOLEAN Cacheable - ) -{ - BuildResourceDescriptorHob ( - EFI_RESOURCE_MEMORY_RESERVED, - EFI_RESOURCE_ATTRIBUTE_PRESENT | - EFI_RESOURCE_ATTRIBUTE_INITIALIZED | - EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | - (Cacheable ? - EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE : - 0 - ) | - EFI_RESOURCE_ATTRIBUTE_TESTED, - MemoryBase, - MemorySize - ); -} - -VOID -AddIoMemoryRangeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - EFI_PHYSICAL_ADDRESS MemoryLimit - ) -{ - AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase)); -} - -VOID -AddMemoryBaseSizeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - UINT64 MemorySize - ) -{ - BuildResourceDescriptorHob ( - EFI_RESOURCE_SYSTEM_MEMORY, - EFI_RESOURCE_ATTRIBUTE_PRESENT | - EFI_RESOURCE_ATTRIBUTE_INITIALIZED | - EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | - EFI_RESOURCE_ATTRIBUTE_TESTED, - MemoryBase, - MemorySize - ); -} - -VOID -AddMemoryRangeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - EFI_PHYSICAL_ADDRESS MemoryLimit - ) -{ - AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase)); -} +extern UINT32 mLowerMemorySize; =20 VOID MemMapInitialization ( @@ -144,117 +66,19 @@ MemMapInitialization ( UINT64 PciIoBase; UINT64 PciIoSize; RETURN_STATUS PcdStatus; - UINT32 TopOfLowRam; - UINT64 PciExBarBase; UINT32 PciBase; UINT32 PciSize; =20 - PciIoBase =3D 0xC000; - PciIoSize =3D 0x4000; - - // - // Video memory + Legacy BIOS region - // - AddIoMemoryRangeHob (0x0A0000, BASE_1MB); - + PlatformMemMapInitialization (mHostBridgeDevId, mQemuUc32Base, &PciBase,= &PciSize, &PciIoBase, &PciIoSize); if (mHostBridgeDevId =3D=3D 0xffff /* microvm */) { - AddIoMemoryBaseSizeHob (MICROVM_GED_MMIO_BASE, SIZE_4KB); - AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); /* ioapic #1 */ - AddIoMemoryBaseSizeHob (0xFEC10000, SIZE_4KB); /* ioapic #2 */ return; } =20 - TopOfLowRam =3D GetSystemMemorySizeBelow4gb (); - PciExBarBase =3D 0; - if (mHostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { - // - // The MMCONFIG area is expected to fall between the top of low RAM and - // the base of the 32-bit PCI host aperture. - // - PciExBarBase =3D FixedPcdGet64 (PcdPciExpressBaseAddress); - ASSERT (TopOfLowRam <=3D PciExBarBase); - ASSERT (PciExBarBase <=3D MAX_UINT32 - SIZE_256MB); - PciBase =3D (UINT32)(PciExBarBase + SIZE_256MB); - } else { - ASSERT (TopOfLowRam <=3D mQemuUc32Base); - PciBase =3D mQemuUc32Base; - } - - // - // address purpose size - // ------------ -------- ------------------------- - // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g) - // 0xFC000000 gap 44 MB - // 0xFEC00000 IO-APIC 4 KB - // 0xFEC01000 gap 1020 KB - // 0xFED00000 HPET 1 KB - // 0xFED00400 gap 111 KB - // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB - // 0xFED20000 gap 896 KB - // 0xFEE00000 LAPIC 1 MB - // - PciSize =3D 0xFC000000 - PciBase; - AddIoMemoryBaseSizeHob (PciBase, PciSize); PcdStatus =3D PcdSet64S (PcdPciMmio32Base, PciBase); ASSERT_RETURN_ERROR (PcdStatus); PcdStatus =3D PcdSet64S (PcdPciMmio32Size, PciSize); ASSERT_RETURN_ERROR (PcdStatus); =20 - AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); - AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB); - if (mHostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { - AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB); - // - // Note: there should be an - // - // AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB); - // - // call below, just like the one above for RCBA. However, Linux insists - // that the MMCONFIG area be marked in the E820 or UEFI memory map as - // "reserved memory" -- Linux does not content itself with a simple gap - // in the memory map wherever the MCFG ACPI table points to. - // - // This appears to be a safety measure. The PCI Firmware Specification - // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources c= an - // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory - // [...]". (Emphasis added here.) - // - // Normally we add memory resource descriptor HOBs in - // QemuInitializeRam(), and pre-allocate from those with memory - // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG ar= ea - // is most definitely not RAM; so, as an exception, cover it with - // uncacheable reserved memory right here. - // - AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE); - BuildMemoryAllocationHob ( - PciExBarBase, - SIZE_256MB, - EfiReservedMemoryType - ); - } - - AddIoMemoryBaseSizeHob (PcdGet32 (PcdCpuLocalApicBaseAddress), SIZE_1MB); - - // - // On Q35, the IO Port space is available for PCI resource allocations f= rom - // 0x6000 up. - // - if (mHostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { - PciIoBase =3D 0x6000; - PciIoSize =3D 0xA000; - ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase); - } - - // - // Add PCI IO Port space available for PCI resource allocations. - // - BuildResourceDescriptorHob ( - EFI_RESOURCE_IO, - EFI_RESOURCE_ATTRIBUTE_PRESENT | - EFI_RESOURCE_ATTRIBUTE_INITIALIZED, - PciIoBase, - PciIoSize - ); PcdStatus =3D PcdSet64S (PcdPciIoBase, PciIoBase); ASSERT_RETURN_ERROR (PcdStatus); PcdStatus =3D PcdSet64S (PcdPciIoSize, PciIoSize); @@ -281,47 +105,6 @@ NoexecDxeInitialization ( UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack); } =20 -VOID -PciExBarInitialization ( - VOID - ) -{ - union { - UINT64 Uint64; - UINT32 Uint32[2]; - } PciExBarBase; - - // - // We only support the 256MB size for the MMCONFIG area: - // 256 buses * 32 devices * 8 functions * 4096 bytes config space. - // - // The masks used below enforce the Q35 requirements that the MMCONFIG a= rea - // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 G= B. - // - // Note that (b) also ensures that the minimum address width we have - // determined in AddressWidthInitialization(), i.e., 36 bits, will suffi= ce - // for DXE's page tables to cover the MMCONFIG area. - // - PciExBarBase.Uint64 =3D FixedPcdGet64 (PcdPciExpressBaseAddress); - ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) =3D=3D 0); - ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) =3D=3D 0); - - // - // Clear the PCIEXBAREN bit first, before programming the high register. - // - PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0); - - // - // Program the high register. Then program the low register, setting the - // MMCONFIG area size and enabling decoding at once. - // - PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[= 1]); - PciWrite32 ( - DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), - PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN - ); -} - static const UINT8 EmptyFdt[] =3D { 0xd0, 0x0d, 0xfe, 0xed, 0x00, 0x00, 0x00, 0x48, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x48, @@ -383,19 +166,23 @@ MicrovmInitialization ( *FdtHobData =3D (UINTN)NewBase; } =20 +/** + * Misc initialization for Microvm and Cloud-Hypervisor + * + * @return VOID + */ VOID -MiscInitialization ( +MiscInitialization2 ( VOID ) { - UINTN PmCmd; - UINTN Pmba; - UINT32 PmbaAndVal; - UINT32 PmbaOrVal; - UINTN AcpiCtlReg; - UINT8 AcpiEnBit; RETURN_STATUS PcdStatus; =20 + if ((mHostBridgeDevId !=3D 0xffff) && (mHostBridgeDevId !=3D CLOUDHV_DEV= ICE_ID)) { + ASSERT (FALSE); + return; + } + // // Disable A20 Mask // @@ -408,26 +195,7 @@ MiscInitialization ( // BuildCpuHob (mPhysMemAddressWidth, 16); =20 - // - // Determine platform type and save Host Bridge DID to PCD - // switch (mHostBridgeDevId) { - case INTEL_82441_DEVICE_ID: - PmCmd =3D POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET); - Pmba =3D POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA); - PmbaAndVal =3D ~(UINT32)PIIX4_PMBA_MASK; - PmbaOrVal =3D PIIX4_PMBA_VALUE; - AcpiCtlReg =3D POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC); - AcpiEnBit =3D PIIX4_PMREGMISC_PMIOSE; - break; - case INTEL_Q35_MCH_DEVICE_ID: - PmCmd =3D POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET); - Pmba =3D POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE); - PmbaAndVal =3D ~(UINT32)ICH9_PMBASE_MASK; - PmbaOrVal =3D ICH9_PMBASE_VALUE; - AcpiCtlReg =3D POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL); - AcpiEnBit =3D ICH9_ACPI_CNTL_ACPI_EN; - break; case 0xffff: /* microvm */ DEBUG ((DEBUG_INFO, "%a: microvm\n", __FUNCTION__)); MicrovmInitialization (); @@ -447,7 +215,7 @@ MiscInitialization ( return; default: DEBUG (( - DEBUG_ERROR, + DEBUG_INFO, "%a: Unknown Host Bridge Device ID: 0x%04x\n", __FUNCTION__, mHostBridgeDevId @@ -455,47 +223,24 @@ MiscInitialization ( ASSERT (FALSE); return; } +} + +VOID +MiscInitialization ( + VOID + ) +{ + RETURN_STATUS PcdStatus; + + if ((mHostBridgeDevId =3D=3D 0xffff) || (mHostBridgeDevId =3D=3D CLOUDHV= _DEVICE_ID)) { + MiscInitialization2 (); + return; + } + + PlatformMiscInitialization (mHostBridgeDevId, mPhysMemAddressWidth); =20 PcdStatus =3D PcdSet16S (PcdOvmfHostBridgePciDevId, mHostBridgeDevId); ASSERT_RETURN_ERROR (PcdStatus); - - // - // If the appropriate IOspace enable bit is set, assume the ACPI PMBA has - // been configured and skip the setup here. This matches the logic in - // AcpiTimerLibConstructor (). - // - if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) =3D=3D 0) { - // - // The PEI phase should be exited with fully accessibe ACPI PM IO spac= e: - // 1. set PMBA - // - PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal); - - // - // 2. set PCICMD/IOSE - // - PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE); - - // - // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN) - // - PciOr8 (AcpiCtlReg, AcpiEnBit); - } - - if (mHostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { - // - // Set Root Complex Register Block BAR - // - PciWrite32 ( - POWER_MGMT_REGISTER_Q35 (ICH9_RCBA), - ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN - ); - - // - // Set PCI Express Register Range Base Address - // - PciExBarInitialization (); - } } =20 VOID @@ -505,11 +250,11 @@ BootModeInitialization ( { EFI_STATUS Status; =20 - if (CmosRead8 (0xF) =3D=3D 0xFE) { + if (PlatformCmosRead8 (0xF) =3D=3D 0xFE) { mBootMode =3D BOOT_ON_S3_RESUME; } =20 - CmosWrite8 (0xF, 0x00); + PlatformCmosWrite8 (0xF, 0x00); =20 Status =3D PeiServicesSetBootMode (mBootMode); ASSERT_EFI_ERROR (Status); @@ -546,27 +291,6 @@ ReserveEmuVariableNvStore ( ASSERT_RETURN_ERROR (PcdStatus); } =20 -VOID -DebugDumpCmos ( - VOID - ) -{ - UINT32 Loop; - - DEBUG ((DEBUG_INFO, "CMOS:\n")); - - for (Loop =3D 0; Loop < 0x80; Loop++) { - if ((Loop % 0x10) =3D=3D 0) { - DEBUG ((DEBUG_INFO, "%02x:", Loop)); - } - - DEBUG ((DEBUG_INFO, " %02x", CmosRead8 (Loop))); - if ((Loop % 0x10) =3D=3D 0xf) { - DEBUG ((DEBUG_INFO, "\n")); - } - } -} - VOID S3Verification ( VOID @@ -629,160 +353,12 @@ MaxCpuCountInitialization ( UINT16 BootCpuCount; RETURN_STATUS PcdStatus; =20 - // - // Try to fetch the boot CPU count. - // - QemuFwCfgSelectItem (QemuFwCfgItemSmpCpuCount); - BootCpuCount =3D QemuFwCfgRead16 (); - if (BootCpuCount =3D=3D 0) { - // - // QEMU doesn't report the boot CPU count. (BootCpuCount =3D=3D 0) wil= l let - // MpInitLib count APs up to (PcdCpuMaxLogicalProcessorNumber - 1), or - // until PcdCpuApInitTimeOutInMicroSeconds elapses (whichever is reach= ed - // first). - // - DEBUG ((DEBUG_WARN, "%a: boot CPU count unavailable\n", __FUNCTION__)); - mMaxCpuCount =3D PcdGet32 (PcdCpuMaxLogicalProcessorNumber); - } else { - // - // We will expose BootCpuCount to MpInitLib. MpInitLib will count APs = up to - // (BootCpuCount - 1) precisely, regardless of timeout. - // - // Now try to fetch the possible CPU count. - // - UINTN CpuHpBase; - UINT32 CmdData2; - - CpuHpBase =3D ((mHostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) ? - ICH9_CPU_HOTPLUG_BASE : PIIX4_CPU_HOTPLUG_BASE); - - // - // If only legacy mode is available in the CPU hotplug register block,= or - // the register block is completely missing, then the writes below are - // no-ops. - // - // 1. Switch the hotplug register block to modern mode. - // - IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, 0); - // - // 2. Select a valid CPU for deterministic reading of - // QEMU_CPUHP_R_CMD_DATA2. - // - // CPU#0 is always valid; it is the always present and non-removable - // BSP. - // - IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, 0); - // - // 3. Send a command after which QEMU_CPUHP_R_CMD_DATA2 is specified to - // read as zero, and which does not invalidate the selector. (The - // selector may change, but it must not become invalid.) - // - // Send QEMU_CPUHP_CMD_GET_PENDING, as it will prove useful later. - // - IoWrite8 (CpuHpBase + QEMU_CPUHP_W_CMD, QEMU_CPUHP_CMD_GET_PENDING); - // - // 4. Read QEMU_CPUHP_R_CMD_DATA2. - // - // If the register block is entirely missing, then this is an unass= igned - // IO read, returning all-bits-one. - // - // If only legacy mode is available, then bit#0 stands for CPU#0 in= the - // "CPU present bitmap". CPU#0 is always present. - // - // Otherwise, QEMU_CPUHP_R_CMD_DATA2 is either still reserved (retu= rning - // all-bits-zero), or it is specified to read as zero after the abo= ve - // steps. Both cases confirm modern mode. - // - CmdData2 =3D IoRead32 (CpuHpBase + QEMU_CPUHP_R_CMD_DATA2); - DEBUG ((DEBUG_VERBOSE, "%a: CmdData2=3D0x%x\n", __FUNCTION__, CmdData2= )); - if (CmdData2 !=3D 0) { - // - // QEMU doesn't support the modern CPU hotplug interface. Assume tha= t the - // possible CPU count equals the boot CPU count (precluding hotplug). - // - DEBUG (( - DEBUG_WARN, - "%a: modern CPU hotplug interface unavailable\n", - __FUNCTION__ - )); - mMaxCpuCount =3D BootCpuCount; - } else { - // - // Grab the possible CPU count from the modern CPU hotplug interface. - // - UINT32 Present, Possible, Selected; - - Present =3D 0; - Possible =3D 0; - - // - // We've sent QEMU_CPUHP_CMD_GET_PENDING last; this ensures - // QEMU_CPUHP_RW_CMD_DATA can now be read usefully. However, - // QEMU_CPUHP_CMD_GET_PENDING may have selected a CPU with actual pe= nding - // hotplug events; therefore, select CPU#0 forcibly. - // - IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, Possible); - - do { - UINT8 CpuStatus; - - // - // Read the status of the currently selected CPU. This will help w= ith a - // sanity check against "BootCpuCount". - // - CpuStatus =3D IoRead8 (CpuHpBase + QEMU_CPUHP_R_CPU_STAT); - if ((CpuStatus & QEMU_CPUHP_STAT_ENABLED) !=3D 0) { - ++Present; - } - - // - // Attempt to select the next CPU. - // - ++Possible; - IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, Possible); - // - // If the selection is successful, then the following read will re= turn - // the selector (which we know is positive at this point). Otherwi= se, - // the read will return 0. - // - Selected =3D IoRead32 (CpuHpBase + QEMU_CPUHP_RW_CMD_DATA); - ASSERT (Selected =3D=3D Possible || Selected =3D=3D 0); - } while (Selected > 0); - - // - // Sanity check: fw_cfg and the modern CPU hotplug interface should - // return the same boot CPU count. - // - if (BootCpuCount !=3D Present) { - DEBUG (( - DEBUG_WARN, - "%a: QEMU v2.7 reset bug: BootCpuCount=3D%d " - "Present=3D%u\n", - __FUNCTION__, - BootCpuCount, - Present - )); - // - // The handling of QemuFwCfgItemSmpCpuCount, across CPU hotplug pl= us - // platform reset (including S3), was corrected in QEMU commit - // e3cadac073a9 ("pc: fix FW_CFG_NB_CPUS to account for -device ad= ded - // CPUs", 2016-11-16), part of release v2.8.0. - // - BootCpuCount =3D (UINT16)Present; - } - - mMaxCpuCount =3D Possible; - } - } - - DEBUG (( - DEBUG_INFO, - "%a: BootCpuCount=3D%d mMaxCpuCount=3D%u\n", - __FUNCTION__, - BootCpuCount, - mMaxCpuCount - )); - ASSERT (BootCpuCount <=3D mMaxCpuCount); + PlatformMaxCpuCountInitialization ( + mHostBridgeDevId, + PcdGet32 (PcdCpuMaxLogicalProcessorNumber), + &mMaxCpuCount, + &BootCpuCount + ); =20 PcdStatus =3D PcdSet32S (PcdCpuBootLogicalProcessorNumber, BootCpuCount); ASSERT_RETURN_ERROR (PcdStatus); @@ -810,7 +386,7 @@ InitializePlatform ( =20 DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n")); =20 - DebugDumpCmos (); + PlatformDebugDumpCmos (); =20 if (QemuFwCfgS3Enabled ()) { DEBUG ((DEBUG_INFO, "S3 support was detected on QEMU\n")); @@ -836,6 +412,11 @@ InitializePlatform ( Q35SmramAtDefaultSmbaseInitialization (); } =20 + // + // Fetch the lower memory size (Below 4G) + // + mLowerMemorySize =3D PlatformGetSystemMemorySizeBelow4gb (); + PublishPeiMemory (); =20 QemuUc32BaseInitialization (); diff --git a/OvmfPkg/PlatformPei/Platform.h b/OvmfPkg/PlatformPei/Platform.h index 24e4da4e1d93..64af9cde1002 100644 --- a/OvmfPkg/PlatformPei/Platform.h +++ b/OvmfPkg/PlatformPei/Platform.h @@ -11,37 +11,6 @@ =20 #include =20 -VOID -AddIoMemoryBaseSizeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - UINT64 MemorySize - ); - -VOID -AddIoMemoryRangeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - EFI_PHYSICAL_ADDRESS MemoryLimit - ); - -VOID -AddMemoryBaseSizeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - UINT64 MemorySize - ); - -VOID -AddMemoryRangeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - EFI_PHYSICAL_ADDRESS MemoryLimit - ); - -VOID -AddReservedMemoryBaseSizeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - UINT64 MemorySize, - BOOLEAN Cacheable - ); - VOID AddressWidthInitialization ( VOID @@ -62,11 +31,6 @@ PublishPeiMemory ( VOID ); =20 -UINT32 -GetSystemMemorySizeBelow4gb ( - VOID - ); - VOID QemuUc32BaseInitialization ( VOID diff --git a/OvmfPkg/PlatformPei/PlatformPei.inf b/OvmfPkg/PlatformPei/Plat= formPei.inf index 8ef404168c45..65e417b2f254 100644 --- a/OvmfPkg/PlatformPei/PlatformPei.inf +++ b/OvmfPkg/PlatformPei/PlatformPei.inf @@ -25,8 +25,6 @@ [Sources] AmdSev.c ClearCache.c - Cmos.c - Cmos.h FeatureControl.c Fv.c MemDetect.c @@ -64,6 +62,7 @@ MemEncryptSevLib PcdLib VmgExitLib + PlatformInitLib =20 [Pcd] gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85993): https://edk2.groups.io/g/devel/message/85993 Mute This Topic: https://groups.io/mt/88617548/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Apr 29 10:32:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+85994+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85994+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1642901978; cv=none; d=zohomail.com; s=zohoarc; b=Qh5WSXaRdkNrk3x7v2veDVJvSL56bhjV0y7U2Wm9LRoOAUBD9CDRUvQ8zd/iUnP+VU/+rnwjgcIc+4gUrSt/5yohaLIVPcuH0nMe0OrSHZgAbaC06wwx84U9ANzWPMOgjZ4mOFDJ9wSLrYHamZuAxIrZ5FzAomhiNj4OPQs/VLo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1642901978; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=toaO4XzC3Djeht688JNmhkUUgrilXj4GiqE34h0tDlw=; b=AuRoGJNz/KYJ7cRXlfcCmH2CUDdEX6iedfdCNw1fppcstZjqMTzDTr0GRuHns8sRvYFRdLDRd8b1+M62kPntJttEUflEOlqR2vkI2i/pIDyGdnnK6wUrSq4EOriKkN9FLv97KU/hrSZULxBLjFS7GIDowEjhcOw0gkekTqq5Hrg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85994+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1642901978562320.3896491784933; Sat, 22 Jan 2022 17:39:38 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id BSNYYY1788612xHms1K6Tn2B; Sat, 22 Jan 2022 17:39:38 -0800 X-Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web11.4554.1642901975017978470 for ; Sat, 22 Jan 2022 17:39:36 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10235"; a="244686096" X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="244686096" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:39:24 -0800 X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="695033265" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.255.30.84]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:39:22 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann Subject: [edk2-devel] [PATCH V5 24/33] OvmfPkg: Update PlatformInitLib to support Tdx guest Date: Sun, 23 Jan 2022 09:36:55 +0800 Message-Id: <4df4c77b9d0e8665867fb77b9889a4bd9e8d619d.1642899774.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: Egs2y7rWpHEV1KbTlIhcePq0x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1642901978; bh=R7dVxSjQ5dmH+8T5wUELb3p+zwgXiWG7ypDRWZgqQ4o=; h=Cc:Date:From:Reply-To:Subject:To; b=wXnuf7eAp3R1zNmW34iRJmnDhwbwyGURJspYuFQU4TtSEyXP3AywK6bJvAevn8ayOnF IsXaPloZce072/aeG+UTbtESqtr5qtfGMIT5ek+JPmd7B0kfrzrGi9Noec4fPQIdRNYdV KesntW+PlNQML5A4n8Xguf8mEx6XRqpE7SI= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1642901980368100003 Content-Type: text/plain; charset="utf-8" RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 In Tdx guest, the system memory is passed in TdHob by host VMM. So the major task of PlatformTdxPublishRamRegions is to walk thru the TdHob list and transfer the ResourceDescriptorHob and MemoryAllocationHob to the hobs in DXE phase. MemoryAllocationHob should also be created for Mailbox and Ovmf work area. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Signed-off-by: Min Xu Acked-by: Gerd Hoffmann --- OvmfPkg/Include/Library/PlatformInitLib.h | 6 + OvmfPkg/Library/PlatformInitLib/IntelTdx.c | 112 ++++++++++++++++++ .../PlatformInitLib/PlatformInitLib.inf | 4 + 3 files changed, 122 insertions(+) create mode 100644 OvmfPkg/Library/PlatformInitLib/IntelTdx.c diff --git a/OvmfPkg/Include/Library/PlatformInitLib.h b/OvmfPkg/Include/Li= brary/PlatformInitLib.h index afab76e46623..b81f5d314d53 100644 --- a/OvmfPkg/Include/Library/PlatformInitLib.h +++ b/OvmfPkg/Include/Library/PlatformInitLib.h @@ -246,4 +246,10 @@ PlatformAddReservedMemoryBaseSizeHob ( IN BOOLEAN Cacheable ); =20 +VOID +EFIAPI +PlatformTdxPublishRamRegions ( + VOID + ); + #endif // PLATFORM_INIT_LIB_H_ diff --git a/OvmfPkg/Library/PlatformInitLib/IntelTdx.c b/OvmfPkg/Library/P= latformInitLib/IntelTdx.c new file mode 100644 index 000000000000..00c89740f2f6 --- /dev/null +++ b/OvmfPkg/Library/PlatformInitLib/IntelTdx.c @@ -0,0 +1,112 @@ +/** @file + Initialize Intel TDX support. + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Transfer the incoming HobList for the TD to the final HobList for Dxe. + The Hobs transferred in this function are ResourceDescriptor hob and + MemoryAllocation hob. + + @param[in] VmmHobList The Hoblist pass the firmware + +**/ +VOID +EFIAPI +TransferTdxHobList ( + VOID + ) +{ + EFI_PEI_HOB_POINTERS Hob; + + // + // PcdOvmfSecGhcbBase is used as the TD_HOB in Tdx guest. + // + Hob.Raw =3D (UINT8 *)(UINTN)FixedPcdGet32 (PcdOvmfSecGhcbBase); + while (!END_OF_HOB_LIST (Hob)) { + switch (Hob.Header->HobType) { + case EFI_HOB_TYPE_RESOURCE_DESCRIPTOR: + BuildResourceDescriptorHob ( + Hob.ResourceDescriptor->ResourceType, + Hob.ResourceDescriptor->ResourceAttribute, + Hob.ResourceDescriptor->PhysicalStart, + Hob.ResourceDescriptor->ResourceLength + ); + break; + case EFI_HOB_TYPE_MEMORY_ALLOCATION: + BuildMemoryAllocationHob ( + Hob.MemoryAllocation->AllocDescriptor.MemoryBaseAddress, + Hob.MemoryAllocation->AllocDescriptor.MemoryLength, + Hob.MemoryAllocation->AllocDescriptor.MemoryType + ); + break; + } + + Hob.Raw =3D GET_NEXT_HOB (Hob); + } +} + +/** + + Publish memory regions in Intel TDX guest. + +**/ +VOID +EFIAPI +PlatformTdxPublishRamRegions ( + VOID + ) +{ + if (!TdIsEnabled ()) { + return; + } + + TransferTdxHobList (); + + // + // The memory region defined by PcdOvmfSecGhcbBackupBase is pre-allocate= d by + // host VMM and used as the td mailbox at the beginning of system boot. + // + BuildMemoryAllocationHob ( + FixedPcdGet32 (PcdOvmfSecGhcbBackupBase), + FixedPcdGet32 (PcdOvmfSecGhcbBackupSize), + EfiACPIMemoryNVS + ); + + if (FixedPcdGet32 (PcdOvmfWorkAreaSize) !=3D 0) { + // + // Reserve the work area. + // + // Since this memory range will be used by the Reset Vector on S3 + // resume, it must be reserved as ACPI NVS. + // + // If S3 is unsupported, then various drivers might still write to the + // work area. We ought to prevent DXE from serving allocation requests + // such that they would overlap the work area. + // + BuildMemoryAllocationHob ( + (EFI_PHYSICAL_ADDRESS)(UINTN)FixedPcdGet32 (PcdOvmfWorkAreaBase), + (UINT64)(UINTN)FixedPcdGet32 (PcdOvmfWorkAreaSize), + EfiBootServicesData + ); + } +} diff --git a/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf b/OvmfPkg/= Library/PlatformInitLib/PlatformInitLib.inf index 060ce0f54f2b..4a3a49cd38c8 100644 --- a/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf +++ b/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf @@ -26,6 +26,7 @@ Cmos.c MemDetect.c Platform.c + IntelTdx.c =20 [Packages] EmbeddedPkg/EmbeddedPkg.dec @@ -49,6 +50,9 @@ MtrrLib PcdLib =20 +[LibraryClasses.X64] + TdxLib + [FixedPcd] gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidSize --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85994): https://edk2.groups.io/g/devel/message/85994 Mute This Topic: https://groups.io/mt/88617549/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Apr 29 10:32:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+85995+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85995+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1642901979; cv=none; d=zohomail.com; s=zohoarc; b=XyEbHbHEurpqI++8/PnK7ToFsRINbWQfS9DQobWn7s93ybRsf0hAet+zi48o0oFuEGZIF1CjtPApNO2Vho2eHaSnh6jdWzl1MN0Orv0WJbWEEazpD+Wj6ZLhmgnM1t4g6p5fSWmVpE/+mUatEqeJrWhLlLP553R9maKaU2/ypmQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1642901979; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=7eYJUKYl4oLyrAxN5jSd6NS9hpojwMeMRiSR+8aamsk=; b=njJ+Mez2pF6fH6pMBQb0y4+dC9vp+/IGWCHHSuCe/V57zfPeZLUyR5m73TW8kxE0dMD+0eQmL7Xhaqf1ei4qeJEHboin/9wh6kp6kmfRkubcO7y9x2JJGkSeZWcfHtFLI0W5RpN2NRy1Xe6PRTZpiPu+rAUvj64eou8++n9vnN4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85995+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1642901979537259.93130012678466; Sat, 22 Jan 2022 17:39:39 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id OH7kYY1788612x9Hb4OBoA9T; Sat, 22 Jan 2022 17:39:39 -0800 X-Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web08.4550.1642901975552765292 for ; Sat, 22 Jan 2022 17:39:36 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10235"; a="244686098" X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="244686098" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:39:27 -0800 X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="695033270" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.255.30.84]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:39:25 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann Subject: [edk2-devel] [PATCH V5 25/33] OvmfPkg: Update PlatformPei to support Tdx guest Date: Sun, 23 Jan 2022 09:36:56 +0800 Message-Id: <4635cf3ec6e8ab5e24af1b06ef6b502740c142a1.1642899774.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: I6CUXrlZSrmwgBRbWy2m2plex1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1642901979; bh=1rKh85PR8l5z6TFbOnEXvrZYVo2znPehr3XUSYbKJYc=; h=Cc:Date:From:Reply-To:Subject:To; b=fVAQXqxrmxpI3iYlV7IqW/xvEq2b+I8D0wPLzHVS31eF2PTlEC98CbkclfdQDFkD8VS GyPqCDKxwd25Uk/yoY8IXnjgo+KkVYQ7O7d9ZNgCEtJymvJ4CnA84U7yGSaLF+XStGStF MdfaeD45/DxhkupGRTQcD2RMaOycajQvggQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1642901980464100011 Content-Type: text/plain; charset="utf-8" RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 OvmfPkg/PlatformPei is updated to support Tdx guest. There are below major changes. - Set Tdx related PCDs - Build Tdx PlatformInfoHob - Publish Tdx RamRegions Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Signed-off-by: Min Xu --- OvmfPkg/OvmfPkg.dec | 1 + OvmfPkg/PlatformPei/FeatureControl.c | 8 +++- OvmfPkg/PlatformPei/IntelTdx.c | 61 ++++++++++++++++++++++++++++ OvmfPkg/PlatformPei/MemDetect.c | 13 +++++- OvmfPkg/PlatformPei/Platform.c | 1 + OvmfPkg/PlatformPei/Platform.h | 11 +++++ OvmfPkg/PlatformPei/PlatformPei.inf | 7 ++++ 7 files changed, 100 insertions(+), 2 deletions(-) create mode 100644 OvmfPkg/PlatformPei/IntelTdx.c diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec index 230d24bc7299..7765962692b6 100644 --- a/OvmfPkg/OvmfPkg.dec +++ b/OvmfPkg/OvmfPkg.dec @@ -133,6 +133,7 @@ gGrubFileGuid =3D {0xb5ae312c, 0xbc8a, 0x43b1, {= 0x9c, 0x62, 0xeb, 0xb8, 0x26, 0xdd, 0x5d, 0x07}} gConfidentialComputingSecretGuid =3D {0xadf956ad, 0xe98c, 0x484c, {= 0xae, 0x11, 0xb5, 0x1c, 0x7d, 0x33, 0x64, 0x47}} gConfidentialComputingSevSnpBlobGuid =3D {0x067b1f5f, 0xcf26, 0x44c5, {= 0x85, 0x54, 0x93, 0xd7, 0x77, 0x91, 0x2d, 0x42}} + gUefiOvmfPkgTdxPlatformGuid =3D {0xdec9b486, 0x1f16, 0x47c7, {= 0x8f, 0x68, 0xdf, 0x1a, 0x41, 0x88, 0x8b, 0xa5}} =20 [Ppis] # PPI whose presence in the PPI database signals that the TPM base addre= ss diff --git a/OvmfPkg/PlatformPei/FeatureControl.c b/OvmfPkg/PlatformPei/Fea= tureControl.c index 9af58c2655f8..7ef1e9565869 100644 --- a/OvmfPkg/PlatformPei/FeatureControl.c +++ b/OvmfPkg/PlatformPei/FeatureControl.c @@ -12,6 +12,8 @@ #include #include #include +#include +#include =20 #include "Platform.h" =20 @@ -37,7 +39,11 @@ WriteFeatureControl ( IN OUT VOID *WorkSpace ) { - AsmWriteMsr64 (MSR_IA32_FEATURE_CONTROL, mFeatureControlValue); + if (TdIsEnabled ()) { + TdVmCall (TDVMCALL_WRMSR, (UINT64)MSR_IA32_FEATURE_CONTROL, mFeatureCo= ntrolValue, 0, 0, 0); + } else { + AsmWriteMsr64 (MSR_IA32_FEATURE_CONTROL, mFeatureControlValue); + } } =20 /** diff --git a/OvmfPkg/PlatformPei/IntelTdx.c b/OvmfPkg/PlatformPei/IntelTdx.c new file mode 100644 index 000000000000..09e3a4ceeb3f --- /dev/null +++ b/OvmfPkg/PlatformPei/IntelTdx.c @@ -0,0 +1,61 @@ +/** @file + Initialize Intel TDX support. + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "Platform.h" + +/** + This Function checks if TDX is available, if present then it sets + the dynamic PCDs for Tdx guest. It also builds Guid hob which contains + the Host Bridge DevId. + **/ +VOID +IntelTdxInitialize ( + VOID + ) +{ + #ifdef MDE_CPU_X64 + EFI_HOB_PLATFORM_INFO PlatformInfoHob; + RETURN_STATUS PcdStatus; + + if (!TdIsEnabled ()) { + return; + } + + PcdStatus =3D PcdSet64S (PcdConfidentialComputingGuestAttr, CCAttrIntelT= dx); + ASSERT_RETURN_ERROR (PcdStatus); + + PcdStatus =3D PcdSetBoolS (PcdIa32EferChangeAllowed, FALSE); + ASSERT_RETURN_ERROR (PcdStatus); + + PcdStatus =3D PcdSet64S (PcdTdxSharedBitMask, TdSharedPageMask ()); + ASSERT_RETURN_ERROR (PcdStatus); + + PcdStatus =3D PcdSetBoolS (PcdSetNxForStack, TRUE); + ASSERT_RETURN_ERROR (PcdStatus); + + ZeroMem (&PlatformInfoHob, sizeof (PlatformInfoHob)); + PlatformInfoHob.HostBridgePciDevId =3D mHostBridgeDevId; + + BuildGuidDataHob (&gUefiOvmfPkgTdxPlatformGuid, &PlatformInfoHob, sizeof= (EFI_HOB_PLATFORM_INFO)); + #endif +} diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetec= t.c index 0c930ab1d70e..fcd17e256ad0 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -37,6 +37,7 @@ Module Name: #include #include #include +#include #include "Platform.h" =20 UINT8 mPhysMemAddressWidth; @@ -218,7 +219,12 @@ GetPeiMemoryCap ( PdpEntries =3D 1 << (mPhysMemAddressWidth - 30); ASSERT (PdpEntries <=3D 0x200); } else { - Pml4Entries =3D 1 << (mPhysMemAddressWidth - 39); + if (TdIsEnabled ()) { + Pml4Entries =3D 0x200; + } else { + Pml4Entries =3D 1 << (mPhysMemAddressWidth - 39); + } + ASSERT (Pml4Entries <=3D 0x200); PdpEntries =3D 512; } @@ -333,6 +339,11 @@ InitializeRamRegions ( VOID ) { + if (TdIsEnabled ()) { + PlatformTdxPublishRamRegions (); + return; + } + PlatformInitializeRamRegions ( mQemuUc32Base, mHostBridgeDevId, diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 05a5c94ce80a..1be8b826227d 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -436,6 +436,7 @@ InitializePlatform ( =20 InstallClearCacheCallback (); AmdSevInitialize (); + IntelTdxInitialize (); MiscInitialization (); InstallFeatureControlCallback (); =20 diff --git a/OvmfPkg/PlatformPei/Platform.h b/OvmfPkg/PlatformPei/Platform.h index 64af9cde1002..a8484b3fa374 100644 --- a/OvmfPkg/PlatformPei/Platform.h +++ b/OvmfPkg/PlatformPei/Platform.h @@ -10,6 +10,7 @@ #define _PLATFORM_PEI_H_INCLUDED_ =20 #include +#include =20 VOID AddressWidthInitialization ( @@ -66,6 +67,16 @@ AmdSevInitialize ( VOID ); =20 +/** + This Function checks if TDX is available, if present then it sets + the dynamic PCDs for Tdx guest. It also builds Guid hob which contains + the Host Bridge DevId. + **/ +VOID +IntelTdxInitialize ( + VOID + ); + extern EFI_BOOT_MODE mBootMode; =20 VOID diff --git a/OvmfPkg/PlatformPei/PlatformPei.inf b/OvmfPkg/PlatformPei/Plat= formPei.inf index 65e417b2f254..2f9f0280b35d 100644 --- a/OvmfPkg/PlatformPei/PlatformPei.inf +++ b/OvmfPkg/PlatformPei/PlatformPei.inf @@ -31,6 +31,7 @@ MemTypeInfo.c Platform.c Platform.h + IntelTdx.c =20 [Packages] EmbeddedPkg/EmbeddedPkg.dec @@ -43,6 +44,7 @@ [Guids] gEfiMemoryTypeInformationGuid gFdtHobGuid + gUefiOvmfPkgTdxPlatformGuid =20 [LibraryClasses] BaseLib @@ -64,6 +66,9 @@ VmgExitLib PlatformInitLib =20 +[LibraryClasses.X64] + TdxLib + [Pcd] gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvSize @@ -109,6 +114,8 @@ gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled gEfiMdePkgTokenSpaceGuid.PcdConfidentialComputingGuestAttr gUefiCpuPkgTokenSpaceGuid.PcdGhcbHypervisorFeatures + gEfiMdeModulePkgTokenSpaceGuid.PcdIa32EferChangeAllowed + gEfiMdeModulePkgTokenSpaceGuid.PcdTdxSharedBitMask =20 [FixedPcd] gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidBase --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85995): https://edk2.groups.io/g/devel/message/85995 Mute This Topic: https://groups.io/mt/88617550/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Apr 29 10:32:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+85997+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85997+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1642901980; cv=none; d=zohomail.com; s=zohoarc; b=B4lDGKgpSw8sOIb/xw6B18++fLwGs2DJUSO+oQMEbgqRHArusAkMUDP1byZ9UZXuomFo4IoQnbmHrLyB0MELP87QpS8i3YbE2/VdpWDfOWx9alF9THqm0MbY3jr570QSDzHscBf0AgkmDSkiaPkRqeM6T1LtYyeDqgQMZ1px/DI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1642901980; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=sl2I92IyG853L0P8xBQ34w6+7DLcJuyEne3AAbDAyFA=; b=bsiAQ+P0JtVGceR5gwY6WExAZy5wHG/fLBbJKZZJlSlNaeGUqoqJlOSSn1tSMqwDt51O25dEXjOQY1Qq34EYcTwuM8N2Zk+yBSMkqecoUVthdp9ll9T9nAUB9nZrEzkH++g01tXIgX1vs/qyRxpMTLFhL7AeRKYeWQH9XhIFvR0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85997+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1642901980653341.49715349942016; Sat, 22 Jan 2022 17:39:40 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id XaXEYY1788612xb8ZowDuNnf; Sat, 22 Jan 2022 17:39:40 -0800 X-Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web08.4550.1642901975552765292 for ; Sat, 22 Jan 2022 17:39:36 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10235"; a="244686101" X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="244686101" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:39:30 -0800 X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="695033274" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.255.30.84]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:39:27 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann Subject: [edk2-devel] [PATCH V5 26/33] OvmfPkg: Update AcpiPlatformDxe to alter MADT table Date: Sun, 23 Jan 2022 09:36:57 +0800 Message-Id: <740fabb9dc707cddfda51b988257434106a49df6.1642899774.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: eoI4f3iMDP2qXh58GVDEjJXLx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1642901980; bh=3aBhRw/aJc3iQ1kiB6vX24ifLibJ1Yhdac23iHt8gJU=; h=Cc:Date:From:Reply-To:Subject:To; b=tGDjUlOcHCu+whSk+cSfoyptE20LMuNIuTwKNgPM9nD+Atdr4j/Eg1yKLDbYuCBxo72 48PU5wkHtcr7k8Ub99dSPwZfpFpLpshTZMesFQAKVUnggj1jvlphBqS89f9ll6b6CZubW v55IGJp1QYHzYTzfA5MAlduA0NSg+K+e7yM= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1642901982573100021 Content-Type: text/plain; charset="utf-8" RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 In TDX the guest firmware is designed to publish a multiprocessor-wakeup structure to let the guest-bootstrap processor wake up guest-application processors with a mailbox. The mailbox is memory that the guest firmware can reserve so each guest virtual processor can have the guest OS send a message to them. The address of the mailbox is recorded in the MADT table. See [ACPI]. To maintain the simplicity of the AcpiPlatformDxe, the MADT ACPI table will be altered in another driver (TdxDxe) by installing a protocol to notify that the ACPI table provided by Qemu is ready. Then in TdxDxe a notification functioin will be called to alter the MADT table to recorded the mailbox address. The protocol is gQemuAcpiTableNotifyProtocolGuid. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Signed-off-by: Min Xu --- OvmfPkg/AcpiPlatformDxe/AcpiPlatformDxe.inf | 1 + OvmfPkg/AcpiPlatformDxe/QemuFwCfgAcpi.c | 14 +++++++++- .../Include/Protocol/QemuAcpiTableNotify.h | 27 +++++++++++++++++++ 3 files changed, 41 insertions(+), 1 deletion(-) create mode 100644 OvmfPkg/Include/Protocol/QemuAcpiTableNotify.h diff --git a/OvmfPkg/AcpiPlatformDxe/AcpiPlatformDxe.inf b/OvmfPkg/AcpiPlat= formDxe/AcpiPlatformDxe.inf index b36b8413e007..e839e37e935b 100644 --- a/OvmfPkg/AcpiPlatformDxe/AcpiPlatformDxe.inf +++ b/OvmfPkg/AcpiPlatformDxe/AcpiPlatformDxe.inf @@ -49,6 +49,7 @@ [Protocols] gEfiAcpiTableProtocolGuid # PROTOCOL ALWAYS_CONSUMED gEfiPciIoProtocolGuid # PROTOCOL SOMETIMES_CONSU= MED + gQemuAcpiTableNotifyProtocolGuid # PROTOCOL PRODUCES =20 [Guids] gRootBridgesConnectedEventGroupGuid diff --git a/OvmfPkg/AcpiPlatformDxe/QemuFwCfgAcpi.c b/OvmfPkg/AcpiPlatform= Dxe/QemuFwCfgAcpi.c index b885965a601e..c8dee17c13e6 100644 --- a/OvmfPkg/AcpiPlatformDxe/QemuFwCfgAcpi.c +++ b/OvmfPkg/AcpiPlatformDxe/QemuFwCfgAcpi.c @@ -19,7 +19,10 @@ #include // QemuFwCfgS3Enabled() #include // gBS =20 +#include #include "AcpiPlatform.h" +EFI_HANDLE mQemuAcpiHandle =3D NULL; +QEMU_ACPI_TABLE_NOTIFY_PROTOCOL mAcpiNotifyProtocol; =20 // // The user structure for the ordered collection that will track the fw_cfg @@ -1273,7 +1276,16 @@ UninstallAcpiTables: AcpiProtocol->UninstallAcpiTable (AcpiProtocol, InstalledKey[Install= ed]); } } else { - DEBUG ((DEBUG_INFO, "%a: installed %d tables\n", __FUNCTION__, Install= ed)); + // + // Install a protocol to notify that the ACPI table provided by Qemu is + // ready. + // + gBS->InstallProtocolInterface ( + &mQemuAcpiHandle, + &gQemuAcpiTableNotifyProtocolGuid, + EFI_NATIVE_INTERFACE, + &mAcpiNotifyProtocol + ); } =20 for (SeenPointerEntry =3D OrderedCollectionMin (SeenPointers); diff --git a/OvmfPkg/Include/Protocol/QemuAcpiTableNotify.h b/OvmfPkg/Inclu= de/Protocol/QemuAcpiTableNotify.h new file mode 100644 index 000000000000..a3dd2fc1dc91 --- /dev/null +++ b/OvmfPkg/Include/Protocol/QemuAcpiTableNotify.h @@ -0,0 +1,27 @@ +/** @file + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef QEMU_ACPI_TABLE_NOTIFY_H_ +#define QEMU_ACPI_TABLE_NOTIFY_H_ + +#define QEMU_ACPI_TABLE_NOTIFY_GUID \ + { 0x928939b2, 0x4235, 0x462f, { 0x95, 0x80, 0xf6, 0xa2, 0xb2, 0xc2, 0x1a= , 0x4f } }; + +/// +/// Forward declaration +/// +typedef struct _QEMU_ACPI_TABLE_NOTIFY_PROTOCOL QEMU_ACPI_TABLE_NOTIFY_PRO= TOCOL; + +/// +/// Protocol structure +/// +struct _QEMU_ACPI_TABLE_NOTIFY_PROTOCOL { + UINT8 Notify; +}; + +extern EFI_GUID gQemuAcpiTableNotifyProtocolGuid; + +#endif --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85997): https://edk2.groups.io/g/devel/message/85997 Mute This Topic: https://groups.io/mt/88617552/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Apr 29 10:32:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+85996+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85996+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1642901980; cv=none; d=zohomail.com; s=zohoarc; b=OEx13Us7lF8hltDQc9cVytvmVL0SlQo3ramxte0kJ8yuvIn3ZTeM3kK4JcDKjDvDJ65sWJNiVYTK0UREaZvar5Fyv5qaVf6NvnymsyfGKI/OvoiwNdBPwuSGxFrZX+KJw++NdWysPRmSpZnoIGwgaV/7ZPca0rbWcqoB2MudtjM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1642901980; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=ecIk3Ulxrhc9aLgWnbMP4cdW9zFkAgcRkBd+sx72FCU=; b=YCZWsculkw1VJchaKZFmCa8Nt8qFMQm2UDEoR3Ore/Rl4u3uwdCa08fWlGYm4t5wycgHHXBWrj6OW3/ruke7qc3E/I5WD2JU7A4ouo4Kh+s1XgJYLXLnJTklxotT32DCV6cHytaGsDYO4RxaNvOTdgTQmpx6FoFR+mpDjrDj2wQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85996+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1642901980265582.8126959844192; Sat, 22 Jan 2022 17:39:40 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id sexEYY1788612xET85CoOj1g; Sat, 22 Jan 2022 17:39:39 -0800 X-Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web11.4554.1642901975017978470 for ; Sat, 22 Jan 2022 17:39:36 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10235"; a="244686103" X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="244686103" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:39:33 -0800 X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="695033279" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.255.30.84]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:39:30 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann Subject: [edk2-devel] [PATCH V5 27/33] OvmfPkg/BaseMemEncryptTdxLib: Add TDX helper library Date: Sun, 23 Jan 2022 09:36:58 +0800 Message-Id: <113d9d5ef138ae717d13a819471dff0304b12c2e.1642899774.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: NZlu7U5YdjPERncd0oegnNovx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1642901979; bh=qIxnFq7Zt7Su6zFj2I3YfLxUb2GgEqch/LX7y2eAqDs=; h=Cc:Date:From:Reply-To:Subject:To; b=I5xO8hOzBcENOti1arWQItzNqh8gMoyoS7zEpXCMqOES2y4b5KKQnb/TVUpnVbyv5yc guAb08OvnOg8achSIJh2nG9sw7S91M6yG1f9jci8elSKa3Fkgmzuqa74IONRCNTRCbMAs CFLV/jdTNpDdJzIWYfxQgHJsMa0TL8mqbCI= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1642901982515100019 Content-Type: text/plain; charset="utf-8" RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 Add Intel Tdx helper library. The library provides the routines to: - set or clear Shared bit for a given memory region. - query whether TDX is enabled. Please be noted, there a lot of duplicated codes for Page Table operations. These codes should be moved to a common library (PageTablesLib) so that it is more friendly for review and maintain. There is a new feature requirement https://bugzilla.tianocore.org/show_bug.cgi?id=3D847 which is to implement the library. After the lib is introduced, BaseMemEncryptTdxLib will be refactored. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Signed-off-by: Min Xu Acked-by: Gerd Hoffmann --- OvmfPkg/Include/Library/MemEncryptTdxLib.h | 81 ++ .../BaseMemEncryptTdxLib.inf | 44 + .../BaseMemEncryptTdxLibNull.inf | 35 + .../BaseMemoryEncryptionNull.c | 90 ++ .../BaseMemEncryptTdxLib/MemoryEncryption.c | 948 ++++++++++++++++++ .../BaseMemEncryptTdxLib/VirtualMemory.h | 181 ++++ OvmfPkg/OvmfPkg.dec | 4 + OvmfPkg/OvmfPkgIa32.dsc | 1 + OvmfPkg/OvmfPkgIa32X64.dsc | 1 + 9 files changed, 1385 insertions(+) create mode 100644 OvmfPkg/Include/Library/MemEncryptTdxLib.h create mode 100644 OvmfPkg/Library/BaseMemEncryptTdxLib/BaseMemEncryptTdxL= ib.inf create mode 100644 OvmfPkg/Library/BaseMemEncryptTdxLib/BaseMemEncryptTdxL= ibNull.inf create mode 100644 OvmfPkg/Library/BaseMemEncryptTdxLib/BaseMemoryEncrypti= onNull.c create mode 100644 OvmfPkg/Library/BaseMemEncryptTdxLib/MemoryEncryption.c create mode 100644 OvmfPkg/Library/BaseMemEncryptTdxLib/VirtualMemory.h diff --git a/OvmfPkg/Include/Library/MemEncryptTdxLib.h b/OvmfPkg/Include/L= ibrary/MemEncryptTdxLib.h new file mode 100644 index 000000000000..2350dd47bc30 --- /dev/null +++ b/OvmfPkg/Include/Library/MemEncryptTdxLib.h @@ -0,0 +1,81 @@ +/** @file + + Define Memory Encrypted Virtualization base library helper function + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef MEM_ENCRYPT_TDX_LIB_H_ +#define MEM_ENCRYPT_TDX_LIB_H_ + +#include + +/** + Returns boolean to indicate whether to indicate which, if any, memory en= cryption is enabled + + @param[in] Type Bitmask of encryption technologies to check is= enabled + + @retval TRUE The encryption type(s) are enabled + @retval FALSE The encryption type(s) are not enabled +**/ +BOOLEAN +EFIAPI +MemEncryptTdxIsEnabled ( + VOID + ); + +/** + This function clears memory encryption bit for the memory region specifi= ed by + BaseAddress and NumPages from the current page table context. + + @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use + current CR3) + @param[in] BaseAddress The physical address that is the sta= rt + address of a memory region. + @param[in] NumPages The number of pages from start memory + region. + + @retval RETURN_SUCCESS The attributes were cleared for the + memory region. + @retval RETURN_INVALID_PARAMETER Number of pages is zero. + @retval RETURN_UNSUPPORTED Clearing the memory encryption attri= bute + is not supported +**/ +RETURN_STATUS +EFIAPI +MemEncryptTdxSetPageSharedBit ( + IN PHYSICAL_ADDRESS Cr3BaseAddress, + IN PHYSICAL_ADDRESS BaseAddress, + IN UINTN NumPages + ); + +/** + This function sets memory encryption bit for the memory region specified= by + BaseAddress and NumPages from the current page table context. + + @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use + current CR3) + @param[in] BaseAddress The physical address that is the sta= rt + address of a memory region. + @param[in] NumPages The number of pages from start memory + region. + + @retval RETURN_SUCCESS The attributes were set for the memo= ry + region. + @retval RETURN_INVALID_PARAMETER Number of pages is zero. + @retval RETURN_UNSUPPORTED Setting the memory encryption attrib= ute + is not supported +**/ +RETURN_STATUS +EFIAPI +MemEncryptTdxClearPageSharedBit ( + IN PHYSICAL_ADDRESS Cr3BaseAddress, + IN PHYSICAL_ADDRESS BaseAddress, + IN UINTN NumPages + ); + +#endif // _MEM_ENCRYPT_TDX_LIB_H_ diff --git a/OvmfPkg/Library/BaseMemEncryptTdxLib/BaseMemEncryptTdxLib.inf = b/OvmfPkg/Library/BaseMemEncryptTdxLib/BaseMemEncryptTdxLib.inf new file mode 100644 index 000000000000..a8abfec12fa3 --- /dev/null +++ b/OvmfPkg/Library/BaseMemEncryptTdxLib/BaseMemEncryptTdxLib.inf @@ -0,0 +1,44 @@ +## @file +# Library for TDX Memory Encryption +# +# Copyright (c) 2021, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 1.25 + BASE_NAME =3D MemEncryptTdxLib + FILE_GUID =3D 7E6651B2-B775-4593-A410-FC05B8C61993 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D MemEncryptTdxLib|PEIM DXE_DRIVER DXE_= RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_DRIVER + +# +# The following information is for reference only and not required by the = build +# tools. +# +# VALID_ARCHITECTURES =3D X64 +# + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + OvmfPkg/OvmfPkg.dec + +[Sources] + VirtualMemory.h + MemoryEncryption.c + +[LibraryClasses] + BaseLib + CacheMaintenanceLib + CpuLib + DebugLib + MemoryAllocationLib + PcdLib + TdxLib + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdConfidentialComputingGuestAttr diff --git a/OvmfPkg/Library/BaseMemEncryptTdxLib/BaseMemEncryptTdxLibNull.= inf b/OvmfPkg/Library/BaseMemEncryptTdxLib/BaseMemEncryptTdxLibNull.inf new file mode 100644 index 000000000000..a050edb5b734 --- /dev/null +++ b/OvmfPkg/Library/BaseMemEncryptTdxLib/BaseMemEncryptTdxLibNull.inf @@ -0,0 +1,35 @@ +## @file +# Library for Memory Encryption +# +# Copyright (c) 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 Advanced Micro Devices. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 1.25 + BASE_NAME =3D MemEncryptTdxLibNull + FILE_GUID =3D 3C69C4CA-DE46-44D7-8AA5-6EE51A4E3EA7 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D MemEncryptTdxLib|PEIM DXE_DRIVER DXE_= RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_DRIVER + +# +# The following information is for reference only and not required by the = build +# tools. +# +# VALID_ARCHITECTURES =3D X64 IA32 +# + +[Packages] + MdePkg/MdePkg.dec + OvmfPkg/OvmfPkg.dec + +[Sources] + BaseMemoryEncryptionNull.c + +[LibraryClasses] + BaseLib diff --git a/OvmfPkg/Library/BaseMemEncryptTdxLib/BaseMemoryEncryptionNull.= c b/OvmfPkg/Library/BaseMemEncryptTdxLib/BaseMemoryEncryptionNull.c new file mode 100644 index 000000000000..137d4674d499 --- /dev/null +++ b/OvmfPkg/Library/BaseMemEncryptTdxLib/BaseMemoryEncryptionNull.c @@ -0,0 +1,90 @@ +/** @file + + Virtual Memory Management Services to set or clear the memory encryption + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + + Code is derived from MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c + +**/ + +#include +#include +#include +#include + +/** + Returns boolean to indicate whether to indicate which, if any, memory en= cryption is enabled + + @param[in] Type Bitmask of encryption technologies to check is= enabled + + @retval TRUE The encryption type(s) are enabled + @retval FALSE The encryption type(s) are not enabled +**/ +BOOLEAN +EFIAPI +MemEncryptTdxIsEnabled ( + VOID + ) +{ + return FALSE; +} + +/** + This function clears memory encryption bit for the memory region specifi= ed by + BaseAddress and NumPages from the current page table context. + + @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use + current CR3) + @param[in] BaseAddress The physical address that is the sta= rt + address of a memory region. + @param[in] NumPages The number of pages from start memory + region. + + @retval RETURN_SUCCESS The attributes were cleared for the + memory region. + @retval RETURN_INVALID_PARAMETER Number of pages is zero. + @retval RETURN_UNSUPPORTED Clearing the memory encryption attri= bute + is not supported +**/ +RETURN_STATUS +EFIAPI +MemEncryptTdxSetPageSharedBit ( + IN PHYSICAL_ADDRESS Cr3BaseAddress, + IN PHYSICAL_ADDRESS BaseAddress, + IN UINTN NumPages + ) +{ + return EFI_UNSUPPORTED; +} + +/** + This function sets memory encryption bit for the memory region specified= by + BaseAddress and NumPages from the current page table context. + + @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use + current CR3) + @param[in] BaseAddress The physical address that is the sta= rt + address of a memory region. + @param[in] NumPages The number of pages from start memory + region. + + @retval RETURN_SUCCESS The attributes were set for the memo= ry + region. + @retval RETURN_INVALID_PARAMETER Number of pages is zero. + @retval RETURN_UNSUPPORTED Setting the memory encryption attrib= ute + is not supported +**/ +RETURN_STATUS +EFIAPI +MemEncryptTdxClearPageSharedBit ( + IN PHYSICAL_ADDRESS Cr3BaseAddress, + IN PHYSICAL_ADDRESS BaseAddress, + IN UINTN NumPages + ) +{ + return EFI_UNSUPPORTED; +} diff --git a/OvmfPkg/Library/BaseMemEncryptTdxLib/MemoryEncryption.c b/Ovmf= Pkg/Library/BaseMemEncryptTdxLib/MemoryEncryption.c new file mode 100644 index 000000000000..9d11c6e4df72 --- /dev/null +++ b/OvmfPkg/Library/BaseMemEncryptTdxLib/MemoryEncryption.c @@ -0,0 +1,948 @@ +/** @file + + Virtual Memory Management Services to set or clear the memory encryption. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + + Code is derived from MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c + + Note: + There a lot of duplicated codes for Page Table operations. These + codes should be moved to a common library (PageTablesLib) so that it is + more friendly for review and maintain. There is a new feature requirement + https://bugzilla.tianocore.org/show_bug.cgi?id=3D847 which is to impleme= nt + the library. After the lib is introduced, this file will be refactored. + +**/ + +#include +#include +#include +#include +#include +#include +#include "VirtualMemory.h" +#include +#include +#include + +typedef enum { + SetSharedBit, + ClearSharedBit +} TDX_PAGETABLE_MODE; + +STATIC PAGE_TABLE_POOL *mPageTablePool =3D NULL; + +/** + Returns boolean to indicate whether to indicate which, if any, memory en= cryption is enabled + + @param[in] Type Bitmask of encryption technologies to check is= enabled + + @retval TRUE The encryption type(s) are enabled + @retval FALSE The encryption type(s) are not enabled +**/ +BOOLEAN +EFIAPI +MemEncryptTdxIsEnabled ( + VOID + ) +{ + return CC_GUEST_IS_TDX (PcdGet64 (PcdConfidentialComputingGuestAttr)); +} + +/** + Get the memory encryption mask + + @param[out] EncryptionMask contains the pte mask. + +**/ +STATIC +UINT64 +GetMemEncryptionAddressMask ( + VOID + ) +{ + return TdSharedPageMask (); +} + +/** + Initialize a buffer pool for page table use only. + + To reduce the potential split operation on page table, the pages reserve= d for + page table should be allocated in the times of PAGE_TABLE_POOL_UNIT_PAGE= S and + at the boundary of PAGE_TABLE_POOL_ALIGNMENT. So the page pool is always + initialized with number of pages greater than or equal to the given + PoolPages. + + Once the pages in the pool are used up, this method should be called aga= in to + reserve at least another PAGE_TABLE_POOL_UNIT_PAGES. Usually this won't + happen often in practice. + + @param[in] PoolPages The least page number of the pool to be create= d. + + @retval TRUE The pool is initialized successfully. + @retval FALSE The memory is out of resource. +**/ +STATIC +BOOLEAN +InitializePageTablePool ( + IN UINTN PoolPages + ) +{ + VOID *Buffer; + + // + // Always reserve at least PAGE_TABLE_POOL_UNIT_PAGES, including one pag= e for + // header. + // + PoolPages +=3D 1; // Add one page for header. + PoolPages =3D ((PoolPages - 1) / PAGE_TABLE_POOL_UNIT_PAGES + 1) * + PAGE_TABLE_POOL_UNIT_PAGES; + Buffer =3D AllocateAlignedPages (PoolPages, PAGE_TABLE_POOL_ALIGNMENT); + if (Buffer =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "ERROR: Out of aligned pages\r\n")); + return FALSE; + } + + // + // Link all pools into a list for easier track later. + // + if (mPageTablePool =3D=3D NULL) { + mPageTablePool =3D Buffer; + mPageTablePool->NextPool =3D mPageTablePool; + } else { + ((PAGE_TABLE_POOL *)Buffer)->NextPool =3D mPageTablePool->NextPool; + mPageTablePool->NextPool =3D Buffer; + mPageTablePool =3D Buffer; + } + + // + // Reserve one page for pool header. + // + mPageTablePool->FreePages =3D PoolPages - 1; + mPageTablePool->Offset =3D EFI_PAGES_TO_SIZE (1); + + return TRUE; +} + +/** + This API provides a way to allocate memory for page table. + + This API can be called more than once to allocate memory for page tables. + + Allocates the number of 4KB pages and returns a pointer to the allocated + buffer. The buffer returned is aligned on a 4KB boundary. + + If Pages is 0, then NULL is returned. + If there is not enough memory remaining to satisfy the request, then NUL= L is + returned. + + @param Pages The number of 4 KB pages to allocate. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +STATIC +VOID * +EFIAPI +AllocatePageTableMemory ( + IN UINTN Pages + ) +{ + VOID *Buffer; + + if (Pages =3D=3D 0) { + return NULL; + } + + // + // Renew the pool if necessary. + // + if ((mPageTablePool =3D=3D NULL) || + (Pages > mPageTablePool->FreePages)) + { + if (!InitializePageTablePool (Pages)) { + return NULL; + } + } + + Buffer =3D (UINT8 *)mPageTablePool + mPageTablePool->Offset; + + mPageTablePool->Offset +=3D EFI_PAGES_TO_SIZE (Pages); + mPageTablePool->FreePages -=3D Pages; + + DEBUG (( + DEBUG_VERBOSE, + "%a:%a: Buffer=3D0x%Lx Pages=3D%ld\n", + gEfiCallerBaseName, + __FUNCTION__, + Buffer, + Pages + )); + + return Buffer; +} + +/** + Split 2M page to 4K. + + @param[in] PhysicalAddress Start physical address the 2M page + covered. + @param[in, out] PageEntry2M Pointer to 2M page entry. + @param[in] StackBase Stack base address. + @param[in] StackSize Stack size. + +**/ +STATIC +VOID +Split2MPageTo4K ( + IN PHYSICAL_ADDRESS PhysicalAddress, + IN OUT UINT64 *PageEntry2M, + IN PHYSICAL_ADDRESS StackBase, + IN UINTN StackSize, + IN UINT64 AddressEncMask + ) +{ + PHYSICAL_ADDRESS PhysicalAddress4K; + UINTN IndexOfPageTableEntries; + PAGE_TABLE_4K_ENTRY *PageTableEntry, *PageTableEntry1; + + PageTableEntry =3D AllocatePageTableMemory (1); + + PageTableEntry1 =3D PageTableEntry; + + if (PageTableEntry =3D=3D NULL) { + ASSERT (FALSE); + return; + } + + PhysicalAddress4K =3D PhysicalAddress; + for (IndexOfPageTableEntries =3D 0; + IndexOfPageTableEntries < 512; + (IndexOfPageTableEntries++, + PageTableEntry++, + PhysicalAddress4K +=3D SIZE_4KB)) + { + // + // Fill in the Page Table entries + // + PageTableEntry->Uint64 =3D (UINT64)PhysicalAddress4K | Address= EncMask; + PageTableEntry->Bits.ReadWrite =3D 1; + PageTableEntry->Bits.Present =3D 1; + if ((PhysicalAddress4K >=3D StackBase) && + (PhysicalAddress4K < StackBase + StackSize)) + { + // + // Set Nx bit for stack. + // + PageTableEntry->Bits.Nx =3D 1; + } + } + + // + // Fill in 2M page entry. + // + *PageEntry2M =3D ((UINT64)(UINTN)PageTableEntry1 | + IA32_PG_P | IA32_PG_RW | AddressEncMask); +} + +/** + Set one page of page table pool memory to be read-only. + + @param[in] PageTableBase Base address of page table (CR3). + @param[in] Address Start address of a page to be set as read-on= ly. + @param[in] Level4Paging Level 4 paging flag. + +**/ +STATIC +VOID +SetPageTablePoolReadOnly ( + IN UINTN PageTableBase, + IN EFI_PHYSICAL_ADDRESS Address, + IN BOOLEAN Level4Paging + ) +{ + UINTN Index; + UINTN EntryIndex; + UINT64 AddressEncMask; + UINT64 ActiveAddressEncMask; + EFI_PHYSICAL_ADDRESS PhysicalAddress; + UINT64 *PageTable; + UINT64 *NewPageTable; + UINT64 PageAttr; + UINT64 LevelSize[5]; + UINT64 LevelMask[5]; + UINTN LevelShift[5]; + UINTN Level; + UINT64 PoolUnitSize; + + if (PageTableBase =3D=3D 0) { + ASSERT (FALSE); + return; + } + + // + // Since the page table is always from page table pool, which is always + // located at the boundary of PcdPageTablePoolAlignment, we just need to + // set the whole pool unit to be read-only. + // + Address =3D Address & PAGE_TABLE_POOL_ALIGN_MASK; + + LevelShift[1] =3D PAGING_L1_ADDRESS_SHIFT; + LevelShift[2] =3D PAGING_L2_ADDRESS_SHIFT; + LevelShift[3] =3D PAGING_L3_ADDRESS_SHIFT; + LevelShift[4] =3D PAGING_L4_ADDRESS_SHIFT; + + LevelMask[1] =3D PAGING_4K_ADDRESS_MASK_64; + LevelMask[2] =3D PAGING_2M_ADDRESS_MASK_64; + LevelMask[3] =3D PAGING_1G_ADDRESS_MASK_64; + LevelMask[4] =3D PAGING_1G_ADDRESS_MASK_64; + + LevelSize[1] =3D SIZE_4KB; + LevelSize[2] =3D SIZE_2MB; + LevelSize[3] =3D SIZE_1GB; + LevelSize[4] =3D SIZE_512GB; + + AddressEncMask =3D GetMemEncryptionAddressMask () & + PAGING_1G_ADDRESS_MASK_64; + PageTable =3D (UINT64 *)(UINTN)PageTableBase; + PoolUnitSize =3D PAGE_TABLE_POOL_UNIT_SIZE; + + for (Level =3D (Level4Paging) ? 4 : 3; Level > 0; --Level) { + Index =3D ((UINTN)RShiftU64 (Address, LevelShift[Level])); + Index &=3D PAGING_PAE_INDEX_MASK; + + PageAttr =3D PageTable[Index]; + ActiveAddressEncMask =3D GetMemEncryptionAddressMask () & PageAttr; + + if ((PageAttr & IA32_PG_PS) =3D=3D 0) { + // + // Go to next level of table. + // + PageTable =3D (UINT64 *)(UINTN)(PageAttr & ~AddressEncMask & + PAGING_4K_ADDRESS_MASK_64); + continue; + } + + if (PoolUnitSize >=3D LevelSize[Level]) { + // + // Clear R/W bit if current page granularity is not larger than pool= unit + // size. + // + if ((PageAttr & IA32_PG_RW) !=3D 0) { + while (PoolUnitSize > 0) { + // + // PAGE_TABLE_POOL_UNIT_SIZE and PAGE_TABLE_POOL_ALIGNMENT are f= it in + // one page (2MB). Then we don't need to update attributes for p= ages + // crossing page directory. ASSERT below is for that purpose. + // + ASSERT (Index < EFI_PAGE_SIZE/sizeof (UINT64)); + + PageTable[Index] &=3D ~(UINT64)IA32_PG_RW; + PoolUnitSize -=3D LevelSize[Level]; + + ++Index; + } + } + + break; + } else { + // + // The smaller granularity of page must be needed. + // + ASSERT (Level > 1); + + NewPageTable =3D AllocatePageTableMemory (1); + if (NewPageTable =3D=3D NULL) { + ASSERT (FALSE); + return; + } + + PhysicalAddress =3D PageAttr & LevelMask[Level]; + for (EntryIndex =3D 0; + EntryIndex < EFI_PAGE_SIZE/sizeof (UINT64); + ++EntryIndex) + { + NewPageTable[EntryIndex] =3D PhysicalAddress | ActiveAddressEncMa= sk | + IA32_PG_P | IA32_PG_RW; + if (Level > 2) { + NewPageTable[EntryIndex] |=3D IA32_PG_PS; + } + + PhysicalAddress +=3D LevelSize[Level - 1]; + } + + PageTable[Index] =3D (UINT64)(UINTN)NewPageTable | ActiveAddressEncM= ask | + IA32_PG_P | IA32_PG_RW; + PageTable =3D NewPageTable; + } + } +} + +/** + Prevent the memory pages used for page table from been overwritten. + + @param[in] PageTableBase Base address of page table (CR3). + @param[in] Level4Paging Level 4 paging flag. + +**/ +STATIC +VOID +EnablePageTableProtection ( + IN UINTN PageTableBase, + IN BOOLEAN Level4Paging + ) +{ + PAGE_TABLE_POOL *HeadPool; + PAGE_TABLE_POOL *Pool; + UINT64 PoolSize; + EFI_PHYSICAL_ADDRESS Address; + + if (mPageTablePool =3D=3D NULL) { + return; + } + + // + // SetPageTablePoolReadOnly might update mPageTablePool. It's safer to + // remember original one in advance. + // + HeadPool =3D mPageTablePool; + Pool =3D HeadPool; + do { + Address =3D (EFI_PHYSICAL_ADDRESS)(UINTN)Pool; + PoolSize =3D Pool->Offset + EFI_PAGES_TO_SIZE (Pool->FreePages); + + // + // The size of one pool must be multiple of PAGE_TABLE_POOL_UNIT_SIZE, + // which is one of page size of the processor (2MB by default). Let's = apply + // the protection to them one by one. + // + while (PoolSize > 0) { + SetPageTablePoolReadOnly (PageTableBase, Address, Level4Paging); + Address +=3D PAGE_TABLE_POOL_UNIT_SIZE; + PoolSize -=3D PAGE_TABLE_POOL_UNIT_SIZE; + } + + Pool =3D Pool->NextPool; + } while (Pool !=3D HeadPool); +} + +/** + Split 1G page to 2M. + + @param[in] PhysicalAddress Start physical address the 1G page + covered. + @param[in, out] PageEntry1G Pointer to 1G page entry. + @param[in] StackBase Stack base address. + @param[in] StackSize Stack size. + +**/ +STATIC +VOID +Split1GPageTo2M ( + IN PHYSICAL_ADDRESS PhysicalAddress, + IN OUT UINT64 *PageEntry1G, + IN PHYSICAL_ADDRESS StackBase, + IN UINTN StackSize + ) +{ + PHYSICAL_ADDRESS PhysicalAddress2M; + UINTN IndexOfPageDirectoryEntries; + PAGE_TABLE_ENTRY *PageDirectoryEntry; + UINT64 AddressEncMask; + UINT64 ActiveAddressEncMask; + + PageDirectoryEntry =3D AllocatePageTableMemory (1); + if (PageDirectoryEntry =3D=3D NULL) { + return; + } + + AddressEncMask =3D GetMemEncryptionAddressMask (); + ASSERT (PageDirectoryEntry !=3D NULL); + + ActiveAddressEncMask =3D *PageEntry1G & AddressEncMask; + // + // Fill in 1G page entry. + // + *PageEntry1G =3D ((UINT64)(UINTN)PageDirectoryEntry | + IA32_PG_P | IA32_PG_RW | ActiveAddressEncMask); + + PhysicalAddress2M =3D PhysicalAddress; + for (IndexOfPageDirectoryEntries =3D 0; + IndexOfPageDirectoryEntries < 512; + (IndexOfPageDirectoryEntries++, + PageDirectoryEntry++, + PhysicalAddress2M +=3D SIZE_2MB)) + { + if ((PhysicalAddress2M < StackBase + StackSize) && + ((PhysicalAddress2M + SIZE_2MB) > StackBase)) + { + // + // Need to split this 2M page that covers stack range. + // + Split2MPageTo4K ( + PhysicalAddress2M, + (UINT64 *)PageDirectoryEntry, + StackBase, + StackSize, + ActiveAddressEncMask + ); + } else { + // + // Fill in the Page Directory entries + // + PageDirectoryEntry->Uint64 =3D (UINT64)PhysicalAddress2M | A= ctiveAddressEncMask; + PageDirectoryEntry->Bits.ReadWrite =3D 1; + PageDirectoryEntry->Bits.Present =3D 1; + PageDirectoryEntry->Bits.MustBe1 =3D 1; + } + } +} + +/** + Set or Clear the memory shared bit + + @param[in] PagetablePoint Page table entry pointer (PTE). + @param[in] Mode Set or Clear shared bit + +**/ +STATIC VOID +SetOrClearSharedBit ( + IN OUT UINT64 *PageTablePointer, + IN TDX_PAGETABLE_MODE Mode, + IN PHYSICAL_ADDRESS PhysicalAddress, + IN UINT64 Length + ) +{ + UINT64 AddressEncMask; + UINT64 Status; + + AddressEncMask =3D GetMemEncryptionAddressMask (); + + // + // Set or clear page table entry. Also, set shared bit in physical addre= ss, before calling MapGPA + // + if (Mode =3D=3D SetSharedBit) { + *PageTablePointer |=3D AddressEncMask; + PhysicalAddress |=3D AddressEncMask; + } else { + *PageTablePointer &=3D ~AddressEncMask; + PhysicalAddress &=3D ~AddressEncMask; + } + + Status =3D TdVmCall (TDVMCALL_MAPGPA, PhysicalAddress, Length, 0, 0, NUL= L); + + // + // If changing shared to private, must accept-page again + // + if (Mode =3D=3D ClearSharedBit) { + TdAcceptPages (PhysicalAddress, Length / EFI_PAGE_SIZE, EFI_PAGE_SIZE); + } + + DEBUG (( + DEBUG_VERBOSE, + "%a:%a: pte=3D0x%Lx AddressEncMask=3D0x%Lx Mode=3D0x%x MapGPA Status= =3D0x%x\n", + gEfiCallerBaseName, + __FUNCTION__, + *PageTablePointer, + AddressEncMask, + Mode, + Status + )); +} + +/** + Check the WP status in CR0 register. This bit is used to lock or unlock w= rite + access to pages marked as read-only. + + @retval TRUE Write protection is enabled. + @retval FALSE Write protection is disabled. +**/ +STATIC +BOOLEAN +IsReadOnlyPageWriteProtected ( + VOID + ) +{ + return ((AsmReadCr0 () & BIT16) !=3D 0); +} + +/** + Disable Write Protect on pages marked as read-only. +**/ +STATIC +VOID +DisableReadOnlyPageWriteProtect ( + VOID + ) +{ + AsmWriteCr0 (AsmReadCr0 () & ~BIT16); +} + +/** + Enable Write Protect on pages marked as read-only. +**/ +VOID +EnableReadOnlyPageWriteProtect ( + VOID + ) +{ + AsmWriteCr0 (AsmReadCr0 () | BIT16); +} + +/** + This function either sets or clears memory encryption for the memory + region specified by PhysicalAddress and Length from the current page tab= le + context. + + The function iterates through the PhysicalAddress one page at a time, an= d set + or clears the memory encryption in the page table. If it encounters + that a given physical address range is part of large page then it attemp= ts to + change the attribute at one go (based on size), otherwise it splits the + large pages into smaller (e.g 2M page into 4K pages) and then try to set= or + clear the shared bit on the smallest page size. + + @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use + current CR3) + @param[in] PhysicalAddress The physical address that is the sta= rt + address of a memory region. + @param[in] Length The length of memory region + @param[in] Mode Set or Clear mode + + @retval RETURN_SUCCESS The attributes were cleared for the + memory region. + @retval RETURN_INVALID_PARAMETER Number of pages is zero. + @retval RETURN_UNSUPPORTED Setting the memory encyrption attrib= ute + is not supported +**/ +STATIC +RETURN_STATUS +EFIAPI +SetMemorySharedOrPrivate ( + IN PHYSICAL_ADDRESS Cr3BaseAddress, + IN PHYSICAL_ADDRESS PhysicalAddress, + IN UINTN Length, + IN TDX_PAGETABLE_MODE Mode + ) +{ + PAGE_MAP_AND_DIRECTORY_POINTER *PageMapLevel4Entry; + PAGE_MAP_AND_DIRECTORY_POINTER *PageUpperDirectoryPointerEntry; + PAGE_MAP_AND_DIRECTORY_POINTER *PageDirectoryPointerEntry; + PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry; + PAGE_TABLE_ENTRY *PageDirectory2MEntry; + PAGE_TABLE_4K_ENTRY *PageTableEntry; + UINT64 PgTableMask; + UINT64 AddressEncMask; + UINT64 ActiveEncMask; + BOOLEAN IsWpEnabled; + RETURN_STATUS Status; + IA32_CR4 Cr4; + BOOLEAN Page5LevelSupport; + + // + // Set PageMapLevel4Entry to suppress incorrect compiler/analyzer warnin= gs. + // + PageMapLevel4Entry =3D NULL; + + DEBUG (( + DEBUG_VERBOSE, + "%a:%a: Cr3Base=3D0x%Lx Physical=3D0x%Lx Length=3D0x%Lx Mode=3D%a\n", + gEfiCallerBaseName, + __FUNCTION__, + Cr3BaseAddress, + PhysicalAddress, + (UINT64)Length, + (Mode =3D=3D SetSharedBit) ? "Shared" : "Private" + )); + + // + // Check if we have a valid memory encryption mask + // + AddressEncMask =3D GetMemEncryptionAddressMask (); + + PgTableMask =3D AddressEncMask | EFI_PAGE_MASK; + + if (Length =3D=3D 0) { + return RETURN_INVALID_PARAMETER; + } + + // + // Make sure that the page table is changeable. + // + IsWpEnabled =3D IsReadOnlyPageWriteProtected (); + if (IsWpEnabled) { + DisableReadOnlyPageWriteProtect (); + } + + // + // If Cr3BaseAddress is not specified then read the current CR3 + // + if (Cr3BaseAddress =3D=3D 0) { + Cr3BaseAddress =3D AsmReadCr3 (); + } + + // + // CPU will already have LA57 enabled so just check CR4 + // + Cr4.UintN =3D AsmReadCr4 (); + + Page5LevelSupport =3D (Cr4.Bits.LA57 ? TRUE : FALSE); + // + // If 5-level pages, adjust Cr3BaseAddress to point to first 4-level pag= e directory, + // we will only have 1 + // + if (Page5LevelSupport) { + Cr3BaseAddress =3D *(UINT64 *)Cr3BaseAddress & ~PgTableMask; + } + + Status =3D EFI_SUCCESS; + + while (Length) { + PageMapLevel4Entry =3D (VOID *)(Cr3BaseAddress & ~PgTableMask); + PageMapLevel4Entry +=3D PML4_OFFSET (PhysicalAddress); + if (!PageMapLevel4Entry->Bits.Present) { + DEBUG (( + DEBUG_ERROR, + "%a:%a: bad PML4 for Physical=3D0x%Lx\n", + gEfiCallerBaseName, + __FUNCTION__, + PhysicalAddress + )); + Status =3D RETURN_NO_MAPPING; + goto Done; + } + + PageDirectory1GEntry =3D (VOID *)( + (PageMapLevel4Entry->Bits.PageTableBas= eAddress << + 12) & ~PgTableMask + ); + PageDirectory1GEntry +=3D PDP_OFFSET (PhysicalAddress); + if (!PageDirectory1GEntry->Bits.Present) { + DEBUG (( + DEBUG_ERROR, + "%a:%a: bad PDPE for Physical=3D0x%Lx\n", + gEfiCallerBaseName, + __FUNCTION__, + PhysicalAddress + )); + Status =3D RETURN_NO_MAPPING; + goto Done; + } + + // + // If the MustBe1 bit is not 1, it's not actually a 1GB entry + // + if (PageDirectory1GEntry->Bits.MustBe1) { + // + // Valid 1GB page + // If we have at least 1GB to go, we can just update this entry + // + if (!(PhysicalAddress & (BIT30 - 1)) && (Length >=3D BIT30)) { + SetOrClearSharedBit (&PageDirectory1GEntry->Uint64, Mode, Physical= Address, BIT30); + DEBUG (( + DEBUG_VERBOSE, + "%a:%a: updated 1GB entry for Physical=3D0x%Lx\n", + gEfiCallerBaseName, + __FUNCTION__, + PhysicalAddress + )); + PhysicalAddress +=3D BIT30; + Length -=3D BIT30; + } else { + // + // We must split the page + // + DEBUG (( + DEBUG_VERBOSE, + "%a:%a: splitting 1GB page for Physical=3D0x%Lx\n", + gEfiCallerBaseName, + __FUNCTION__, + PhysicalAddress + )); + Split1GPageTo2M ( + (UINT64)PageDirectory1GEntry->Bits.PageTableBaseAddress << 30, + (UINT64 *)PageDirectory1GEntry, + 0, + 0 + ); + continue; + } + } else { + // + // Actually a PDP + // + PageUpperDirectoryPointerEntry =3D + (PAGE_MAP_AND_DIRECTORY_POINTER *)PageDirectory1GEntry; + PageDirectory2MEntry =3D + (VOID *)( + (PageUpperDirectoryPointerEntry->Bits.PageTableBaseAddres= s << + 12) & ~PgTableMask + ); + PageDirectory2MEntry +=3D PDE_OFFSET (PhysicalAddress); + if (!PageDirectory2MEntry->Bits.Present) { + DEBUG (( + DEBUG_ERROR, + "%a:%a: bad PDE for Physical=3D0x%Lx\n", + gEfiCallerBaseName, + __FUNCTION__, + PhysicalAddress + )); + Status =3D RETURN_NO_MAPPING; + goto Done; + } + + // + // If the MustBe1 bit is not a 1, it's not a 2MB entry + // + if (PageDirectory2MEntry->Bits.MustBe1) { + // + // Valid 2MB page + // If we have at least 2MB left to go, we can just update this ent= ry + // + if (!(PhysicalAddress & (BIT21-1)) && (Length >=3D BIT21)) { + SetOrClearSharedBit (&PageDirectory2MEntry->Uint64, Mode, Physic= alAddress, BIT21); + PhysicalAddress +=3D BIT21; + Length -=3D BIT21; + } else { + // + // We must split up this page into 4K pages + // + DEBUG (( + DEBUG_VERBOSE, + "%a:%a: splitting 2MB page for Physical=3D0x%Lx\n", + gEfiCallerBaseName, + __FUNCTION__, + PhysicalAddress + )); + + ActiveEncMask =3D PageDirectory2MEntry->Uint64 & AddressEncMask; + + Split2MPageTo4K ( + (UINT64)PageDirectory2MEntry->Bits.PageTableBaseAddress << 21, + (UINT64 *)PageDirectory2MEntry, + 0, + 0, + ActiveEncMask + ); + continue; + } + } else { + PageDirectoryPointerEntry =3D + (PAGE_MAP_AND_DIRECTORY_POINTER *)PageDirectory2MEntry; + PageTableEntry =3D + (VOID *)( + (PageDirectoryPointerEntry->Bits.PageTableBaseAddress << + 12) & ~PgTableMask + ); + PageTableEntry +=3D PTE_OFFSET (PhysicalAddress); + if (!PageTableEntry->Bits.Present) { + DEBUG (( + DEBUG_ERROR, + "%a:%a: bad PTE for Physical=3D0x%Lx\n", + gEfiCallerBaseName, + __FUNCTION__, + PhysicalAddress + )); + Status =3D RETURN_NO_MAPPING; + goto Done; + } + + SetOrClearSharedBit (&PageTableEntry->Uint64, Mode, PhysicalAddres= s, EFI_PAGE_SIZE); + PhysicalAddress +=3D EFI_PAGE_SIZE; + Length -=3D EFI_PAGE_SIZE; + } + } + } + + // + // Protect the page table by marking the memory used for page table to be + // read-only. + // + if (IsWpEnabled) { + EnablePageTableProtection ((UINTN)PageMapLevel4Entry, TRUE); + } + + // + // Flush TLB + // + CpuFlushTlb (); + +Done: + // + // Restore page table write protection, if any. + // + if (IsWpEnabled) { + EnableReadOnlyPageWriteProtect (); + } + + return Status; +} + +/** + This function clears memory shared bit for the memory region specified by + BaseAddress and NumPages from the current page table context. + + @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use + current CR3) + @param[in] BaseAddress The physical address that is the sta= rt + address of a memory region. + @param[in] NumPages The number of pages from start memory + region. + + @retval RETURN_SUCCESS The attributes were cleared for the + memory region. + @retval RETURN_INVALID_PARAMETER Number of pages is zero. + @retval RETURN_UNSUPPORTED Clearing the memory encryption attri= bute + is not supported +**/ +RETURN_STATUS +EFIAPI +MemEncryptTdxSetPageSharedBit ( + IN PHYSICAL_ADDRESS Cr3BaseAddress, + IN PHYSICAL_ADDRESS BaseAddress, + IN UINTN NumPages + ) +{ + return SetMemorySharedOrPrivate ( + Cr3BaseAddress, + BaseAddress, + EFI_PAGES_TO_SIZE (NumPages), + SetSharedBit + ); +} + +/** + This function sets memory shared bit for the memory region specified by + BaseAddress and NumPages from the current page table context. + + @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use + current CR3) + @param[in] BaseAddress The physical address that is the sta= rt + address of a memory region. + @param[in] NumPages The number of pages from start memory + region. + + @retval RETURN_SUCCESS The attributes were set for the memo= ry + region. + @retval RETURN_INVALID_PARAMETER Number of pages is zero. + @retval RETURN_UNSUPPORTED Setting the memory encryption attrib= ute + is not supported +**/ +RETURN_STATUS +EFIAPI +MemEncryptTdxClearPageSharedBit ( + IN PHYSICAL_ADDRESS Cr3BaseAddress, + IN PHYSICAL_ADDRESS BaseAddress, + IN UINTN NumPages + ) +{ + return SetMemorySharedOrPrivate ( + Cr3BaseAddress, + BaseAddress, + EFI_PAGES_TO_SIZE (NumPages), + ClearSharedBit + ); +} diff --git a/OvmfPkg/Library/BaseMemEncryptTdxLib/VirtualMemory.h b/OvmfPkg= /Library/BaseMemEncryptTdxLib/VirtualMemory.h new file mode 100644 index 000000000000..e9403798d98d --- /dev/null +++ b/OvmfPkg/Library/BaseMemEncryptTdxLib/VirtualMemory.h @@ -0,0 +1,181 @@ +/** @file + + Virtual Memory Management Services to set or clear the memory encryption= bit + + Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + + Code is derived from MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h + +**/ + +#ifndef TDX_VIRTUAL_MEMORY_ +#define TDX_VIRTUAL_MEMORY_ + +#include +#include +#include +#include +#include +#include + +#define SYS_CODE64_SEL 0x38 + +#pragma pack(1) + +// +// Page-Map Level-4 Offset (PML4) and +// Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB +// + +typedef union { + struct { + UINT64 Present : 1; // 0 =3D Not present in memory, + // 1 =3D Present in memory + UINT64 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read/Wri= te + UINT64 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser + UINT64 WriteThrough : 1; // 0 =3D Write-Back caching, + // 1 =3D Write-Through caching + UINT64 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cached + UINT64 Accessed : 1; // 0 =3D Not accessed, + // 1 =3D Accessed (set by CPU) + UINT64 Reserved : 1; // Reserved + UINT64 MustBeZero : 2; // Must Be Zero + UINT64 Available : 3; // Available for use by system so= ftware + UINT64 PageTableBaseAddress : 40; // Page Table Base Address + UINT64 AvabilableHigh : 11; // Available for use by system so= ftware + UINT64 Nx : 1; // No Execute bit + } Bits; + UINT64 Uint64; +} PAGE_MAP_AND_DIRECTORY_POINTER; + +// +// Page Table Entry 4KB +// +typedef union { + struct { + UINT64 Present : 1; // 0 =3D Not present in memory, + // 1 =3D Present in memory + UINT64 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read/Wri= te + UINT64 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser + UINT64 WriteThrough : 1; // 0 =3D Write-Back caching, + // 1 =3D Write-Through caching + UINT64 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cached + UINT64 Accessed : 1; // 0 =3D Not accessed, + // 1 =3D Accessed (set by CPU) + UINT64 Dirty : 1; // 0 =3D Not Dirty, 1 =3D written= by + // processor on access to page + UINT64 PAT : 1; // + UINT64 Global : 1; // 0 =3D Not global page, 1 =3D g= lobal page + // TLB not cleared on CR3 write + UINT64 Available : 3; // Available for use by system so= ftware + UINT64 PageTableBaseAddress : 40; // Page Table Base Address + UINT64 AvabilableHigh : 11; // Available for use by system so= ftware + UINT64 Nx : 1; // 0 =3D Execute Code, + // 1 =3D No Code Execution + } Bits; + UINT64 Uint64; +} PAGE_TABLE_4K_ENTRY; + +// +// Page Table Entry 2MB +// +typedef union { + struct { + UINT64 Present : 1; // 0 =3D Not present in memory, + // 1 =3D Present in memory + UINT64 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read/Wri= te + UINT64 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser + UINT64 WriteThrough : 1; // 0 =3D Write-Back caching, + // 1=3DWrite-Through caching + UINT64 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cached + UINT64 Accessed : 1; // 0 =3D Not accessed, + // 1 =3D Accessed (set by CPU) + UINT64 Dirty : 1; // 0 =3D Not Dirty, 1 =3D written= by + // processor on access to page + UINT64 MustBe1 : 1; // Must be 1 + UINT64 Global : 1; // 0 =3D Not global page, 1 =3D g= lobal page + // TLB not cleared on CR3 write + UINT64 Available : 3; // Available for use by system so= ftware + UINT64 PAT : 1; // + UINT64 MustBeZero : 8; // Must be zero; + UINT64 PageTableBaseAddress : 31; // Page Table Base Address + UINT64 AvabilableHigh : 11; // Available for use by system so= ftware + UINT64 Nx : 1; // 0 =3D Execute Code, + // 1 =3D No Code Execution + } Bits; + UINT64 Uint64; +} PAGE_TABLE_ENTRY; + +// +// Page Table Entry 1GB +// +typedef union { + struct { + UINT64 Present : 1; // 0 =3D Not present in memory, + // 1 =3D Present in memory + UINT64 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read/Wri= te + UINT64 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser + UINT64 WriteThrough : 1; // 0 =3D Write-Back caching, + // 1 =3D Write-Through caching + UINT64 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cached + UINT64 Accessed : 1; // 0 =3D Not accessed, + // 1 =3D Accessed (set by CPU) + UINT64 Dirty : 1; // 0 =3D Not Dirty, 1 =3D written= by + // processor on access to page + UINT64 MustBe1 : 1; // Must be 1 + UINT64 Global : 1; // 0 =3D Not global page, 1 =3D g= lobal page + // TLB not cleared on CR3 write + UINT64 Available : 3; // Available for use by system so= ftware + UINT64 PAT : 1; // + UINT64 MustBeZero : 17; // Must be zero; + UINT64 PageTableBaseAddress : 22; // Page Table Base Address + UINT64 AvabilableHigh : 11; // Available for use by system so= ftware + UINT64 Nx : 1; // 0 =3D Execute Code, + // 1 =3D No Code Execution + } Bits; + UINT64 Uint64; +} PAGE_TABLE_1G_ENTRY; + +#pragma pack() + +#define IA32_PG_P BIT0 +#define IA32_PG_RW BIT1 +#define IA32_PG_PS BIT7 + +#define PAGING_PAE_INDEX_MASK 0x1FF + +#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull +#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull +#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull + +#define PAGING_L1_ADDRESS_SHIFT 12 +#define PAGING_L2_ADDRESS_SHIFT 21 +#define PAGING_L3_ADDRESS_SHIFT 30 +#define PAGING_L4_ADDRESS_SHIFT 39 + +#define PAGING_PML4E_NUMBER 4 + +#define PAGETABLE_ENTRY_MASK ((1UL << 9) - 1) +#define PML4_OFFSET(x) ( (x >> 39) & PAGETABLE_ENTRY_MASK) +#define PDP_OFFSET(x) ( (x >> 30) & PAGETABLE_ENTRY_MASK) +#define PDE_OFFSET(x) ( (x >> 21) & PAGETABLE_ENTRY_MASK) +#define PTE_OFFSET(x) ( (x >> 12) & PAGETABLE_ENTRY_MASK) +#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull + +#define PAGE_TABLE_POOL_ALIGNMENT BASE_2MB +#define PAGE_TABLE_POOL_UNIT_SIZE SIZE_2MB +#define PAGE_TABLE_POOL_UNIT_PAGES \ + EFI_SIZE_TO_PAGES (PAGE_TABLE_POOL_UNIT_SIZE) +#define PAGE_TABLE_POOL_ALIGN_MASK \ + (~(EFI_PHYSICAL_ADDRESS)(PAGE_TABLE_POOL_ALIGNMENT - 1)) + +typedef struct { + VOID *NextPool; + UINTN Offset; + UINTN FreePages; +} PAGE_TABLE_POOL; + +#endif diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec index 7765962692b6..b24b3d449924 100644 --- a/OvmfPkg/OvmfPkg.dec +++ b/OvmfPkg/OvmfPkg.dec @@ -34,6 +34,10 @@ # Virtualization (SEV) guests. MemEncryptSevLib|Include/Library/MemEncryptSevLib.h =20 + ## @libraryclass Declares helper functions for TDX guests. + # + MemEncryptTdxLib|Include/Library/MemEncryptTdxLib.h + ## @libraryclass Save and restore variables using a file # NvVarsFileLib|Include/Library/NvVarsFileLib.h diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc index 3f52939ab6d2..f270ca7249ec 100644 --- a/OvmfPkg/OvmfPkgIa32.dsc +++ b/OvmfPkg/OvmfPkgIa32.dsc @@ -176,6 +176,7 @@ VirtioLib|OvmfPkg/Library/VirtioLib/VirtioLib.inf LoadLinuxLib|OvmfPkg/Library/LoadLinuxLib/LoadLinuxLib.inf MemEncryptSevLib|OvmfPkg/Library/BaseMemEncryptSevLib/DxeMemEncryptSevLi= b.inf + MemEncryptTdxLib|OvmfPkg/Library/BaseMemEncryptTdxLib/BaseMemEncryptTdxL= ibNull.inf !if $(SMM_REQUIRE) =3D=3D FALSE LockBoxLib|OvmfPkg/Library/LockBoxLib/LockBoxBaseLib.inf !endif diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc index 30e01feeb539..6ccae56d1c44 100644 --- a/OvmfPkg/OvmfPkgIa32X64.dsc +++ b/OvmfPkg/OvmfPkgIa32X64.dsc @@ -180,6 +180,7 @@ VirtioLib|OvmfPkg/Library/VirtioLib/VirtioLib.inf LoadLinuxLib|OvmfPkg/Library/LoadLinuxLib/LoadLinuxLib.inf MemEncryptSevLib|OvmfPkg/Library/BaseMemEncryptSevLib/DxeMemEncryptSevLi= b.inf + MemEncryptTdxLib|OvmfPkg/Library/BaseMemEncryptTdxLib/BaseMemEncryptTdxL= ibNull.inf !if $(SMM_REQUIRE) =3D=3D FALSE LockBoxLib|OvmfPkg/Library/LockBoxLib/LockBoxBaseLib.inf !endif --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85996): https://edk2.groups.io/g/devel/message/85996 Mute This Topic: https://groups.io/mt/88617551/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Apr 29 10:32:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+85998+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85998+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1642901981; cv=none; d=zohomail.com; s=zohoarc; b=HB3jMSaoDeKDzmT2bFaa+WCssMU33jlSSFeV30NVvjBdfW8JeOf3qGwOUDE6Eeems+b7sBfnq2qMQVQB45E/JoF4tfZxiTam8yolOF1KV3lcGWz8m9TJFJnpE10Rodiv2TEcHDMH5WKPobwdXhYTqS1FJe3zSi09R2zq0M9fFuo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1642901981; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=AymorxWKQpdFzkvsDF11LWWhcHHA08Jw+9JWYCJNnKc=; b=N6mnEkvCML/QEtCgh1LKq/2mEgvMKEh5s0TJge3JV+ZsHWVEJrC/Nebqv0ZlWXjBcOhJ/rxmi3rbQhKovwz5lwcjj7zrz+IRIVg3Z7jpFWGX6A6RbUlWEodugMRzV3p6sHXYKIoz0qSYnAl5hyc/DCLXnXLkDJ+A6BFRhXU+6Qo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85998+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1642901981353341.46304855235894; Sat, 22 Jan 2022 17:39:41 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 5OFsYY1788612x5trYDYpLgG; Sat, 22 Jan 2022 17:39:41 -0800 X-Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web08.4551.1642901977372480965 for ; Sat, 22 Jan 2022 17:39:37 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10235"; a="244686123" X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="244686123" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:39:36 -0800 X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="695033292" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.255.30.84]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:39:33 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann Subject: [edk2-devel] [PATCH V5 28/33] OvmfPkg: Add TdxDxe driver Date: Sun, 23 Jan 2022 09:36:59 +0800 Message-Id: <41eba86a1f6113c3b40fca463784bd0e7a988913.1642899774.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: 50ixhisS9cBbQEagDbEl1Njvx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1642901981; bh=d5BuCQZX6Ofkrvd2xBN3Vh03qKZ6OM++9mGrx8mLk9Q=; h=Cc:Date:From:Reply-To:Subject:To; b=eV0HFWm2dOXVNfrNUozY3TOH0zY7m9cuGN4LaGF0t8G7fSjy3bp9+8cRRYTxlSqMjQw hcWL4/sa6v84aFrm2WkxR8RwQE8eBerkv4sSV6BdC5I9RZ5Vd1GmcRX+0UnErE4bSkzFO iT4xAf0QIrBCKXsyt3fnLE10WM28+Xs617c= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1642901982633100024 Content-Type: text/plain; charset="utf-8" RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 TdxDxe driver is dispatched early in DXE, due to being list in APRIORI. This module is responsible for below features: - Sets max logical cpus based on TDINFO - Sets PCI PCDs based on resource hobs - Set shared bit in MMIO region - Relocate Td mailbox and set its address in MADT table. 1. Set shared bit in MMIO region Qemu allows a ROM device to set to ROMD mode (default) or MMIO mode. When it is in ROMD mode, the device is mapped to guest memory and satisfies read access directly. In EDK2 Option ROM is treated as MMIO region. So Tdx guest access Option ROM via TDVMCALL(MMIO). But as explained above, since Qemu set the Option ROM to ROMD mode, the call of TDVMCALL(MMIO) always return INVALID_OPERAND. Tdvf then falls back to direct access. This requires to set the shared bit to corresponding PageTable entry. Otherwise it triggers GP fault. TdxDxe's entry point is the right place to set the shared bit in MMIO region because Option ROM has not been discoverd yet. 2. Relocate Td mailbox and set the new address in MADT Mutiprocessor Wakeup Table. In TDX the guest firmware is designed to publish a multiprocessor-wakeup structure to let the guest-bootstrap processor wake up guest-application processors with a mailbox. The mailbox is memory that the guest firmware can reserve so each guest virtual processor can have the guest OS send a message to them. The address of the mailbox is recorded in the MADT table. See [ACPI]. TdxDxe registers for protocol notification (gQemuAcpiTableNotifyProtocolGuid) to call the AlterAcpiTable(), in which MADT table is altered by the above Mailbox address. The protocol will be installed in AcpiPlatformDxe when the MADT table provided by Qemu is ready. This is to maintain the simplicity of the AcpiPlatformDxe. AlterAcpiTable is the registered function which traverses the ACPI table list to find the original MADT from Qemu. After the new MADT is configured and installed, the original one will be uninstalled. [ACPI] https://uefi.org/specs/ACPI/6.4/05_ACPI_Software_Programming_Model /ACPI_Software_Programming_Model.html#multiprocessor-wakeup-structure Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Signed-off-by: Min Xu --- OvmfPkg/OvmfPkg.dec | 1 + OvmfPkg/OvmfPkgX64.dsc | 2 + OvmfPkg/OvmfPkgX64.fdf | 3 + OvmfPkg/TdxDxe/TdxAcpiTable.c | 213 +++++++++++++++++++++++++ OvmfPkg/TdxDxe/TdxAcpiTable.h | 60 +++++++ OvmfPkg/TdxDxe/TdxDxe.c | 251 ++++++++++++++++++++++++++++++ OvmfPkg/TdxDxe/TdxDxe.inf | 64 ++++++++ OvmfPkg/TdxDxe/X64/ApRunLoop.nasm | 87 +++++++++++ 8 files changed, 681 insertions(+) create mode 100644 OvmfPkg/TdxDxe/TdxAcpiTable.c create mode 100644 OvmfPkg/TdxDxe/TdxAcpiTable.h create mode 100644 OvmfPkg/TdxDxe/TdxDxe.c create mode 100644 OvmfPkg/TdxDxe/TdxDxe.inf create mode 100644 OvmfPkg/TdxDxe/X64/ApRunLoop.nasm diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec index b24b3d449924..161ac9b48c21 100644 --- a/OvmfPkg/OvmfPkg.dec +++ b/OvmfPkg/OvmfPkg.dec @@ -162,6 +162,7 @@ gEfiLegacyInterruptProtocolGuid =3D {0x31ce593d, 0x108a, 0x485d, {= 0xad, 0xb2, 0x78, 0xf2, 0x1f, 0x29, 0x66, 0xbe}} gEfiVgaMiniPortProtocolGuid =3D {0xc7735a2f, 0x88f5, 0x4882, {= 0xae, 0x63, 0xfa, 0xac, 0x8c, 0x8b, 0x86, 0xb3}} gOvmfLoadedX86LinuxKernelProtocolGuid =3D {0xa3edc05d, 0xb618, 0x4ff6, {= 0x95, 0x52, 0x76, 0xd7, 0x88, 0x63, 0x43, 0xc8}} + gQemuAcpiTableNotifyProtocolGuid =3D {0x928939b2, 0x4235, 0x462f, {= 0x95, 0x80, 0xf6, 0xa2, 0xb2, 0xc2, 0x1a, 0x4f}} =20 [PcdsFixedAtBuild] gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase|0x0|UINT32|0 diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index 5fc6d14ee011..2eb45c6d0bad 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -944,6 +944,8 @@ } OvmfPkg/IoMmuDxe/IoMmuDxe.inf =20 + OvmfPkg/TdxDxe/TdxDxe.inf + !if $(SMM_REQUIRE) =3D=3D TRUE OvmfPkg/SmmAccess/SmmAccess2Dxe.inf OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.inf diff --git a/OvmfPkg/OvmfPkgX64.fdf b/OvmfPkg/OvmfPkgX64.fdf index ba7f26d01dc4..d7c18bbc6ec1 100644 --- a/OvmfPkg/OvmfPkgX64.fdf +++ b/OvmfPkg/OvmfPkgX64.fdf @@ -214,6 +214,7 @@ READ_LOCK_STATUS =3D TRUE APRIORI DXE { INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + INF OvmfPkg/TdxDxe/TdxDxe.inf INF OvmfPkg/AmdSevDxe/AmdSevDxe.inf !if $(SMM_REQUIRE) =3D=3D FALSE INF OvmfPkg/QemuFlashFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf @@ -318,6 +319,8 @@ INF ShellPkg/Application/Shell/Shell.inf =20 INF MdeModulePkg/Logo/LogoDxe.inf =20 +INF OvmfPkg/TdxDxe/TdxDxe.inf + # # Network modules # diff --git a/OvmfPkg/TdxDxe/TdxAcpiTable.c b/OvmfPkg/TdxDxe/TdxAcpiTable.c new file mode 100644 index 000000000000..8a1abe8b1d89 --- /dev/null +++ b/OvmfPkg/TdxDxe/TdxAcpiTable.c @@ -0,0 +1,213 @@ +/** @file + OVMF ACPI QEMU support + + Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.
+ + Copyright (C) 2012-2014, Red Hat, Inc. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + At the beginning of system boot, a 4K-aligned, 4K-size memory (Td mailbo= x) is + pre-allocated by host VMM. BSP & APs do the page accept together in that= memory + region. + + After that TDVF is designed to relocate the mailbox to a 4K-aligned, 4K-= size + memory block which is allocated in the ACPI Nvs memory. APs are waken up= and + spin around the relocated mailbox for further command. + + @return EFI_PHYSICAL_ADDRESS Address of the relocated mailbox +**/ +EFI_PHYSICAL_ADDRESS +EFIAPI +RelocateMailbox ( + VOID + ) +{ + EFI_PHYSICAL_ADDRESS Address; + VOID *ApLoopFunc; + UINT32 RelocationPages; + MP_RELOCATION_MAP RelocationMap; + MP_WAKEUP_MAILBOX *RelocatedMailBox; + EFI_STATUS Status; + + Address =3D 0; + ApLoopFunc =3D NULL; + ZeroMem (&RelocationMap, sizeof (RelocationMap)); + + // + // Get information needed to setup aps running in their + // run loop in allocated acpi reserved memory + // Add another page for mailbox + // + AsmGetRelocationMap (&RelocationMap); + if ((RelocationMap.RelocateApLoopFuncAddress =3D=3D 0) || (RelocationMap= .RelocateApLoopFuncSize =3D=3D 0)) { + DEBUG ((DEBUG_ERROR, "Failed to get the RelocationMap.\n")); + return 0; + } + + RelocationPages =3D EFI_SIZE_TO_PAGES ((UINT32)RelocationMap.RelocateApL= oopFuncSize) + 1; + + Status =3D gBS->AllocatePages (AllocateAnyPages, EfiACPIMemoryNVS, Reloc= ationPages, &Address); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Failed to allocate pages for MailboxRelocation. = %r\n", Status)); + return 0; + } + + ZeroMem ((VOID *)Address, EFI_PAGES_TO_SIZE (RelocationPages)); + + ApLoopFunc =3D (VOID *)((UINTN)Address + EFI_PAGE_SIZE); + + CopyMem ( + ApLoopFunc, + RelocationMap.RelocateApLoopFuncAddress, + RelocationMap.RelocateApLoopFuncSize + ); + + DEBUG (( + DEBUG_INFO, + "Ap Relocation: mailbox %llx, loop %p\n", + Address, + ApLoopFunc + )); + + // + // Initialize mailbox + // + RelocatedMailBox =3D (MP_WAKEUP_MAILBOX *)Address; + RelocatedMailBox->Command =3D MpProtectedModeWakeupCommandNoop; + RelocatedMailBox->ApicId =3D MP_CPU_PROTECTED_MODE_MAILBOX_APICID_= INVALID; + RelocatedMailBox->WakeUpVector =3D 0; + + // + // Wakup APs and have been move to the finalized run loop + // They will spin until guest OS wakes them + // + MpSerializeStart (); + + MpSendWakeupCommand ( + MpProtectedModeWakeupCommandWakeup, + (UINT64)ApLoopFunc, + (UINT64)RelocatedMailBox, + 0, + 0, + 0 + ); + + return Address; +} + +/** + Alter the MADT when ACPI Table from QEMU is available. + + @param[in] Event Event whose notification function is being invoked + @param[in] Context Pointer to the notification function's context +**/ +VOID +EFIAPI +AlterAcpiTable ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_ACPI_SDT_PROTOCOL *AcpiSdtProtocol; + EFI_ACPI_TABLE_PROTOCOL *AcpiTableProtocol; + EFI_STATUS Status; + UINTN Index; + EFI_ACPI_SDT_HEADER *Table; + EFI_ACPI_TABLE_VERSION Version; + UINTN OriginalTableKey; + UINTN NewTableKey; + UINT8 *NewMadtTable; + UINTN NewMadtTableLength; + EFI_PHYSICAL_ADDRESS RelocateMailboxAddr= ess; + EFI_ACPI_6_4_MULTIPROCESSOR_WAKEUP_STRUCTURE *MadtMpWk; + EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER *MadtHeader; + + Index =3D 0; + NewMadtTable =3D NULL; + MadtHeader =3D NULL; + + Status =3D gBS->LocateProtocol (&gEfiAcpiSdtProtocolGuid, NULL, (void **= )&AcpiSdtProtocol); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Unable to locate ACPI SDT protocol.\n")); + return; + } + + RelocateMailboxAddress =3D RelocateMailbox (); + if (RelocateMailboxAddress =3D=3D 0) { + ASSERT (FALSE); + DEBUG ((DEBUG_ERROR, "Failed to relocate Td mailbox\n")); + return; + } + + do { + Status =3D AcpiSdtProtocol->GetAcpiTable (Index, &Table, &Version, &Or= iginalTableKey); + + if (!EFI_ERROR (Status) && (Table->Signature =3D=3D EFI_ACPI_1_0_APIC_= SIGNATURE)) { + Status =3D gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (v= oid **)&AcpiTableProtocol); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Unable to locate ACPI Table protocol.\n")); + break; + } + + NewMadtTableLength =3D Table->Length + sizeof (EFI_ACPI_6_4_MULTIPRO= CESSOR_WAKEUP_STRUCTURE); + NewMadtTable =3D AllocatePool (NewMadtTableLength); + if (NewMadtTable =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: OUT_OF_SOURCES error.\n", __FUNCTION__)); + break; + } + + CopyMem (NewMadtTable, (UINT8 *)Table, Table->Length); + MadtHeader =3D (EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTIO= N_TABLE_HEADER *)NewMadtTable; + MadtHeader->Header.Length =3D (UINT32)NewMadtTableLength; + + MadtMpWk =3D (EFI_ACPI_6_4_MULTIPROCESSOR_WAKEUP_STR= UCTURE *)(NewMadtTable + Table->Length); + MadtMpWk->Type =3D EFI_ACPI_6_4_MULTIPROCESSOR_WAKEUP; + MadtMpWk->Length =3D sizeof (EFI_ACPI_6_4_MULTIPROCESSOR_WAK= EUP_STRUCTURE); + MadtMpWk->MailBoxVersion =3D 1; + MadtMpWk->Reserved =3D 0; + MadtMpWk->MailBoxAddress =3D RelocateMailboxAddress; + + Status =3D AcpiTableProtocol->InstallAcpiTable (AcpiTableProtocol, N= ewMadtTable, NewMadtTableLength, &NewTableKey); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Failed to install new MADT table. %r\n", Sta= tus)); + break; + } + + Status =3D AcpiTableProtocol->UninstallAcpiTable (AcpiTableProtocol,= OriginalTableKey); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Uninstall old MADT table error.\n")); + } + + break; + } + + Index++; + } while (!EFI_ERROR (Status)); + + if (NewMadtTable !=3D NULL) { + FreePool (NewMadtTable); + } +} diff --git a/OvmfPkg/TdxDxe/TdxAcpiTable.h b/OvmfPkg/TdxDxe/TdxAcpiTable.h new file mode 100644 index 000000000000..6b7615dc3687 --- /dev/null +++ b/OvmfPkg/TdxDxe/TdxAcpiTable.h @@ -0,0 +1,60 @@ +/** @file + + Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef TDX_ACPI_TABLE_H_ +#define TDX_ACPI_TABLE_H_ + +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +VOID +EFIAPI +AsmGetRelocationMap ( + OUT MP_RELOCATION_MAP *AddressMap + ); + +/** + At the beginning of system boot, a 4K-aligned, 4K-size memory (Td mailbo= x) is + pre-allocated by host VMM. BSP & APs do the page accept together in that= memory + region. + + After that TDVF is designed to relocate the mailbox to a 4K-aligned, 4K-= size + memory block which is allocated in the ACPI Nvs memory. APs are waken up= and + spin around the relocated mailbox for further command. + + @return EFI_PHYSICAL_ADDRESS Address of the relocated mailbox +**/ +EFI_PHYSICAL_ADDRESS +EFIAPI +RelocateMailbox ( + VOID + ); + +/** + Alter the MADT when ACPI Table from QEMU is available. + + @param[in] Event Event whose notification function is being invoked + @param[in] Context Pointer to the notification function's context +**/ +VOID +EFIAPI +AlterAcpiTable ( + IN EFI_EVENT Event, + IN VOID *Context + ); + +#endif diff --git a/OvmfPkg/TdxDxe/TdxDxe.c b/OvmfPkg/TdxDxe/TdxDxe.c new file mode 100644 index 000000000000..36ef5c510771 --- /dev/null +++ b/OvmfPkg/TdxDxe/TdxDxe.c @@ -0,0 +1,251 @@ +/** @file + + TDX Dxe driver. This driver is dispatched early in DXE, due to being list + in APRIORI. + + This module is responsible for: + - Sets max logical cpus based on TDINFO + - Sets PCI PCDs based on resource hobs + - Alter MATD table to record address of Mailbox + + Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Location of resource hob matching type and starting address + + @param[in] Type The type of resource hob to locate. + + @param[in] Start The resource hob must at least begin at add= ress. + + @retval pointer to resource Return pointer to a resource hob that match= es or NULL. +**/ +STATIC +EFI_HOB_RESOURCE_DESCRIPTOR * +GetResourceDescriptor ( + EFI_RESOURCE_TYPE Type, + EFI_PHYSICAL_ADDRESS Start, + EFI_PHYSICAL_ADDRESS End + ) +{ + EFI_PEI_HOB_POINTERS Hob; + EFI_HOB_RESOURCE_DESCRIPTOR *ResourceDescriptor =3D NULL; + + Hob.Raw =3D GetFirstHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR); + while (Hob.Raw !=3D NULL) { + DEBUG (( + DEBUG_INFO, + "%a:%d: resource type 0x%x %llx %llx\n", + __func__, + __LINE__, + Hob.ResourceDescriptor->ResourceType, + Hob.ResourceDescriptor->PhysicalStart, + Hob.ResourceDescriptor->ResourceLength + )); + + if ((Hob.ResourceDescriptor->ResourceType =3D=3D Type) && + (Hob.ResourceDescriptor->PhysicalStart >=3D Start) && + ((Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDescriptor->= ResourceLength) < End)) + { + ResourceDescriptor =3D Hob.ResourceDescriptor; + break; + } + + Hob.Raw =3D GET_NEXT_HOB (Hob); + Hob.Raw =3D GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, Hob.Raw); + } + + return ResourceDescriptor; +} + +/** + Location of resource hob matching type and highest address below end + + @param[in] Type The type of resource hob to locate. + + @param[in] End The resource hob return is the closest to t= he End address + + @retval pointer to resource Return pointer to a resource hob that match= es or NULL. +**/ +STATIC +EFI_HOB_RESOURCE_DESCRIPTOR * +GetHighestResourceDescriptor ( + EFI_RESOURCE_TYPE Type, + EFI_PHYSICAL_ADDRESS End + ) +{ + EFI_PEI_HOB_POINTERS Hob; + EFI_HOB_RESOURCE_DESCRIPTOR *ResourceDescriptor =3D NULL; + + Hob.Raw =3D GetFirstHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR); + while (Hob.Raw !=3D NULL) { + if ((Hob.ResourceDescriptor->ResourceType =3D=3D Type) && + (Hob.ResourceDescriptor->PhysicalStart < End)) + { + if (!ResourceDescriptor || + (ResourceDescriptor->PhysicalStart < Hob.ResourceDescriptor->Phy= sicalStart)) + { + ResourceDescriptor =3D Hob.ResourceDescriptor; + } + } + + Hob.Raw =3D GET_NEXT_HOB (Hob); + Hob.Raw =3D GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, Hob.Raw); + } + + return ResourceDescriptor; +} + +/** + Set the shared bit for mmio region in Tdx guest. + + In Tdx guest there are 2 ways to access mmio, TdVmcall or direct access. + For direct access, the shared bit of the PageTableEntry should be set. + The mmio region information is retrieved from hob list. + + @retval EFI_SUCCESS The shared bit is set successfully. + @retval EFI_UNSUPPORTED Setting the shared bit of memory reg= ion + is not supported +**/ +EFI_STATUS +SetMmioSharedBit ( + VOID + ) +{ + EFI_PEI_HOB_POINTERS Hob; + + Hob.Raw =3D (UINT8 *)GetHobList (); + + // + // Parse the HOB list until end of list or matching type is found. + // + while (!END_OF_HOB_LIST (Hob)) { + if ( (Hob.Header->HobType =3D=3D EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) + && (Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_MEMORY= _MAPPED_IO)) + { + MemEncryptTdxSetPageSharedBit ( + 0, + Hob.ResourceDescriptor->PhysicalStart, + EFI_SIZE_TO_PAGES (Hob.ResourceDescriptor->ResourceLength) + ); + } + + Hob.Raw =3D GET_NEXT_HOB (Hob); + } + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +TdxDxeEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + RETURN_STATUS PcdStatus; + EFI_HOB_RESOURCE_DESCRIPTOR *Res =3D NULL; + EFI_HOB_RESOURCE_DESCRIPTOR *MemRes =3D NULL; + EFI_HOB_PLATFORM_INFO *PlatformInfo =3D NULL; + EFI_HOB_GUID_TYPE *GuidHob; + UINT32 CpuMaxLogicalProcessorNumber; + TD_RETURN_DATA TdReturnData; + EFI_EVENT QemuAcpiTableEvent; + void *Registration; + + GuidHob =3D GetFirstGuidHob (&gUefiOvmfPkgTdxPlatformGuid); + + if (GuidHob =3D=3D NULL) { + return EFI_UNSUPPORTED; + } + + SetMmioSharedBit (); + + PlatformInfo =3D (EFI_HOB_PLATFORM_INFO *)GET_GUID_HOB_DATA (GuidHob); + + // + // Call TDINFO to get actual number of cpus in domain + // + Status =3D TdCall (TDCALL_TDINFO, 0, 0, 0, &TdReturnData); + ASSERT (Status =3D=3D EFI_SUCCESS); + + CpuMaxLogicalProcessorNumber =3D PcdGet32 (PcdCpuMaxLogicalProcessorNumb= er); + + // + // Adjust PcdCpuMaxLogicalProcessorNumber, if needed. If firmware is con= figured for + // more than number of reported cpus, update. + // + if (CpuMaxLogicalProcessorNumber > TdReturnData.TdInfo.NumVcpus) { + PcdStatus =3D PcdSet32S (PcdCpuMaxLogicalProcessorNumber, TdReturnData= .TdInfo.NumVcpus); + ASSERT_RETURN_ERROR (PcdStatus); + } + + // + // Register for protocol notifications to call the AlterAcpiTable(), + // the protocol will be installed in AcpiPlatformDxe when the ACPI + // table provided by Qemu is ready. + // + Status =3D gBS->CreateEvent ( + EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + AlterAcpiTable, + NULL, + &QemuAcpiTableEvent + ); + + Status =3D gBS->RegisterProtocolNotify ( + &gQemuAcpiTableNotifyProtocolGuid, + QemuAcpiTableEvent, + &Registration + ); + + #define INIT_PCDSET(NAME, RES) do {\ + PcdStatus =3D PcdSet64S (NAME##Base, (RES)->PhysicalStart); \ + ASSERT_RETURN_ERROR (PcdStatus); \ + PcdStatus =3D PcdSet64S (NAME##Size, (RES)->ResourceLength); \ + ASSERT_RETURN_ERROR (PcdStatus); \ +} while(0) + + if (PlatformInfo) { + PcdSet16S (PcdOvmfHostBridgePciDevId, PlatformInfo->HostBridgePciDevId= ); + + if ((Res =3D GetResourceDescriptor (EFI_RESOURCE_MEMORY_MAPPED_IO, (EF= I_PHYSICAL_ADDRESS)0x100000000, (EFI_PHYSICAL_ADDRESS)-1)) !=3D NULL) { + INIT_PCDSET (PcdPciMmio64, Res); + } + + if ((Res =3D GetResourceDescriptor (EFI_RESOURCE_IO, 0, 0x10001)) !=3D= NULL) { + INIT_PCDSET (PcdPciIo, Res); + } + + // + // To find low mmio, first find top of low memory, and then search for= io space. + // + if ((MemRes =3D GetHighestResourceDescriptor (EFI_RESOURCE_SYSTEM_MEMO= RY, 0xffc00000)) !=3D NULL) { + if ((Res =3D GetResourceDescriptor (EFI_RESOURCE_MEMORY_MAPPED_IO, M= emRes->PhysicalStart, 0x100000000)) !=3D NULL) { + INIT_PCDSET (PcdPciMmio32, Res); + } + } + } + + return EFI_SUCCESS; +} diff --git a/OvmfPkg/TdxDxe/TdxDxe.inf b/OvmfPkg/TdxDxe/TdxDxe.inf new file mode 100644 index 000000000000..077769bcf70c --- /dev/null +++ b/OvmfPkg/TdxDxe/TdxDxe.inf @@ -0,0 +1,64 @@ +#/** @file +# +# Driver clears the encryption attribute from MMIO regions when TDX is en= abled +# +# Copyright (c) 2017, AMD Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION =3D 1.25 + BASE_NAME =3D TdxDxe + FILE_GUID =3D E750224E-7BCE-40AF-B5BB-47E3611EB5C2 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D TdxDxeEntryPoint + +[Sources] + TdxDxe.c + TdxAcpiTable.c + X64/ApRunLoop.nasm + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + OvmfPkg/OvmfPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + DxeServicesTableLib + MemoryAllocationLib + PcdLib + UefiDriverEntryPoint + TdxLib + HobLib + TdxMailboxLib + MemEncryptTdxLib + +[Depex] + TRUE + +[Guids] + gUefiOvmfPkgTdxPlatformGuid ## CONSUMES + +[Protocols] + gQemuAcpiTableNotifyProtocolGuid ## CONSUMES + gEfiAcpiSdtProtocolGuid ## CONSUMES + gEfiAcpiTableProtocolGuid ## CONSUMES + +[Pcd] + gUefiOvmfPkgTokenSpaceGuid.PcdPciIoBase + gUefiOvmfPkgTokenSpaceGuid.PcdPciIoSize + gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Base + gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Size + gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Base + gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Size + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber + gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress diff --git a/OvmfPkg/TdxDxe/X64/ApRunLoop.nasm b/OvmfPkg/TdxDxe/X64/ApRunLo= op.nasm new file mode 100644 index 000000000000..0aad239348b0 --- /dev/null +++ b/OvmfPkg/TdxDxe/X64/ApRunLoop.nasm @@ -0,0 +1,87 @@ +;-------------------------------------------------------------------------= ----- ; +; Copyright (c) 2021, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; ApRunLoop.nasm +; +; Abstract: +; +; This is the assembly code for run loop for APs in the guest TD +; +;-------------------------------------------------------------------------= ------ + +%include "TdxCommondefs.inc" + +DEFAULT REL + +SECTION .text + +BITS 64 + +%define TDVMCALL_EXPOSE_REGS_MASK 0xffec +%define TDVMCALL 0x0 +%define EXIT_REASON_CPUID 0xa + +%macro tdcall 0 + db 0x66, 0x0f, 0x01, 0xcc +%endmacro + +; +; Relocated Ap Mailbox loop +; +; @param[in] RBX: Relocated mailbox address +; @param[in] RBP: vCpuId +; +; @return None This routine does not return +; +global ASM_PFX(AsmRelocateApMailBoxLoop) +ASM_PFX(AsmRelocateApMailBoxLoop): +AsmRelocateApMailBoxLoopStart: + + mov rax, TDVMCALL + mov rcx, TDVMCALL_EXPOSE_REGS_MASK + mov r11, EXIT_REASON_CPUID + mov r12, 0xb + tdcall + test rax, rax + jnz Panic + mov r8, r15 + +MailBoxLoop: + ; Spin until command set + cmp dword [rbx + CommandOffset], MpProtectedModeWakeupCommandNo= op + je MailBoxLoop + ; Determine if this is a broadcast or directly for my apic-id, if not,= ignore + cmp dword [rbx + ApicidOffset], MailboxApicidBroadcast + je MailBoxProcessCommand + cmp dword [rbx + ApicidOffset], r8d + jne MailBoxLoop +MailBoxProcessCommand: + cmp dword [rbx + CommandOffset], MpProtectedModeWakeupCommandWa= keup + je MailBoxWakeUp + cmp dword [rbx + CommandOffset], MpProtectedModeWakeupCommandSl= eep + je MailBoxSleep + ; Don't support this command, so ignore + jmp MailBoxLoop +MailBoxWakeUp: + mov rax, [rbx + WakeupVectorOffset] + jmp rax +MailBoxSleep: + jmp $ +Panic: + ud2 +BITS 64 +AsmRelocateApMailBoxLoopEnd: + +;-------------------------------------------------------------------------= ------------ +; AsmGetRelocationMap (&RelocationMap); +;-------------------------------------------------------------------------= ------------ +global ASM_PFX(AsmGetRelocationMap) +ASM_PFX(AsmGetRelocationMap): + lea rax, [ASM_PFX(AsmRelocateApMailBoxLoopStart)] + mov qword [rcx], rax + mov qword [rcx + 8h], AsmRelocateApMailBoxLoopEnd - AsmRelocat= eApMailBoxLoopStart + ret + --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85998): https://edk2.groups.io/g/devel/message/85998 Mute This Topic: https://groups.io/mt/88617553/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Apr 29 10:32:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+85999+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85999+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1642901981; cv=none; d=zohomail.com; s=zohoarc; b=CyuVx4gmdSQdD+mG+JpIcNN83qp0e+oL2gaKBwDJ6FW9rsWTr4NGAptrfWC8WsnEOTHPGTbpSGANebVE2sZIlllXe5p3jXt2Dot1EPX6o8lc3SeUFoenjwpY0Lma8ZHi5KJF9dQIY/CrjdNw4Hqn3unXj91sOFijnyBncVhQLck= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1642901981; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=9hCG57gxlVGPj5RpLBmYS0eiWwyGbR/61XMErfeUJjA=; b=ZhBFM2Cw2gKBZjB3/F64gACkmgSqapHL7KxbfoNQi2TVRli86GlwHlTPmtq9jMpZ5uyMzMkZeyhMuzEuUo1PilJn/ytTHH4BaRS2pQZWBD9BK+4fZ36IC1j7WfHGjGzXvBFwMrRAH28DCEHMH5cj85Ych9LqeNXBViaOIw9TCL8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85999+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1642901981652531.5499155597622; Sat, 22 Jan 2022 17:39:41 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 5DJxYY1788612xDJnIfarRxc; Sat, 22 Jan 2022 17:39:41 -0800 X-Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web08.4551.1642901977372480965 for ; Sat, 22 Jan 2022 17:39:39 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10235"; a="244686157" X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="244686157" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:39:39 -0800 X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="695033322" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.255.30.84]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:39:36 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann Subject: [edk2-devel] [PATCH V5 29/33] OvmfPkg/QemuFwCfgLib: Support Tdx in QemuFwCfgDxe Date: Sun, 23 Jan 2022 09:37:00 +0800 Message-Id: <1821e08a1ffab9596876c12ddece0cb0b7ce27e6.1642899774.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: n58QDMWmXwIbxeokk26BT4HKx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1642901981; bh=4VvVl6GS5SBADu5YX23GYY25uesGvrb1DYbLxsjX8PI=; h=Cc:Date:From:Reply-To:Subject:To; b=dxO91VURUN9qqyTqa+j7AJ6f4YZDJLquz6PeAPTpnroIGvUt3z5OSfA3v3O7irvyZe2 P5ub2/v3PQifDr68m6HVJFYCIyYK+6lLnw+Tlh3a2WmI8yNGymCw4sAnDgDcKYW4OfOdz NZPg9l1kBgi/p4BghSemNEgL1hmdRg3zL/U= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1642901982656100026 Content-Type: text/plain; charset="utf-8" RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 In the previous QemuFwCfgDxe only SEV is supported. This commit introduce TDX support in QemuFwCfgDxe. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Signed-off-by: Min Xu --- OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgDxe.c | 9 +++++---- OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgDxeLib.inf | 1 + 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgDxe.c b/OvmfPkg/Library/= QemuFwCfgLib/QemuFwCfgDxe.c index f5787cd24d38..6a810928a060 100644 --- a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgDxe.c +++ b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgDxe.c @@ -19,6 +19,7 @@ #include #include #include +#include #include =20 #include "QemuFwCfgLibInternal.h" @@ -85,7 +86,7 @@ QemuFwCfgInitialize ( DEBUG ((DEBUG_INFO, "QemuFwCfg interface (DMA) is supported.\n")); } =20 - if (mQemuFwCfgDmaSupported && MemEncryptSevIsEnabled ()) { + if (mQemuFwCfgDmaSupported && (MemEncryptSevIsEnabled () || (MemEncryptT= dxIsEnabled ()))) { EFI_STATUS Status; =20 // @@ -100,7 +101,7 @@ QemuFwCfgInitialize ( if (EFI_ERROR (Status)) { DEBUG (( DEBUG_ERROR, - "QemuFwCfgSevDma %a:%a Failed to locate IOMMU protocol.\n", + "QemuFwCfgDma %a:%a Failed to locate IOMMU protocol.\n", gEfiCallerBaseName, __FUNCTION__ )); @@ -411,10 +412,10 @@ InternalQemuFwCfgDmaBytes ( DataBuffer =3D Buffer; =20 // - // When SEV is enabled, map Buffer to DMA address before issuing the DMA + // When SEV or TDX is enabled, map Buffer to DMA address before issuing = the DMA // request // - if (MemEncryptSevIsEnabled ()) { + if (MemEncryptSevIsEnabled () || MemEncryptTdxIsEnabled ()) { VOID *AccessBuffer; EFI_PHYSICAL_ADDRESS DataBufferAddress; =20 diff --git a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgDxeLib.inf b/OvmfPkg/Lib= rary/QemuFwCfgLib/QemuFwCfgDxeLib.inf index 48899ff1236a..ce3eaa5ed8b4 100644 --- a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgDxeLib.inf +++ b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgDxeLib.inf @@ -43,6 +43,7 @@ IoLib MemoryAllocationLib MemEncryptSevLib + MemEncryptTdxLib =20 [Protocols] gEdkiiIoMmuProtocolGuid ## SOMETIMES_CONSUMES --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85999): https://edk2.groups.io/g/devel/message/85999 Mute This Topic: https://groups.io/mt/88617556/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Apr 29 10:32:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+86000+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+86000+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1642901983; cv=none; d=zohomail.com; s=zohoarc; b=TqbvxnSVumr2oNtFoP0jbhYz2YFbQwR32Jydq6MXcFyx1g0+gb/FhHsnzC3e2ZBmLYfD95rgXar7AUWAwweTvpXiUTm+jAxwME7HNvj9KP1XPoOtZ3e53EHIu/mmEOlm906MeX2i9C3gUZJ9RB6Bg/h1F/1HtYc1WsUIqYf4FTo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1642901983; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=5hoJTk1b9bt1fKSkjdpKERQcZ1syxxE8bh5ej7mNje8=; b=LKQeRNP40V2SbdM+a2eoKnYx2RFOHGl2xg9oBh8/+e6UWP+yXjuK4lQM5bHeDnKyp3wA/i3xYSBAr8SKOZsG7Gdlt408Y9dJosEv+doUKqUUUmjq3RH6DZKX0nxQYiq11zPDyd/qpWTy2ShjKIPRa3pHCwLIsbAdve4I8KHFdCI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+86000+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1642901983984461.2868038570497; Sat, 22 Jan 2022 17:39:43 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 2IX8YY1788612xon0oIsrWP2; Sat, 22 Jan 2022 17:39:43 -0800 X-Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web08.4551.1642901977372480965 for ; Sat, 22 Jan 2022 17:39:43 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10235"; a="244686184" X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="244686184" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:39:41 -0800 X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="695033338" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.255.30.84]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:39:39 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann Subject: [edk2-devel] [PATCH V5 30/33] OvmfPkg: Update IoMmuDxe to support TDX Date: Sun, 23 Jan 2022 09:37:01 +0800 Message-Id: <94e993115001a3add207bf5b9b489a70d6629129.1642899774.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: baURRgyyrXtlTF0JXeCqtIkOx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1642901983; bh=I65np85xtygIJLEvmIggOhMQ88XJzSSQKC2CMCFWlwA=; h=Cc:Date:From:Reply-To:Subject:To; b=hw4HTFgMGsnCSVESsrNjMjOq0CI9Owo1m1khpmdCFxAahB9ASQRQBO/HLmMQozGxTsb FC8CdurnnjIGtnuUQVFbkv1JwCw3qf6MWD2BW/lR0nYBfXedeK8GogFWBVqAmfFZBPxJW Kx+D0OBHdxSa20hvIYaUFtDcqwd+vWVwC3E= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1642901984743100001 Content-Type: text/plain; charset="utf-8" RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 The IOMMU protocol driver provides capabilities to set a DMA access attribute and methods to allocate, free, map and unmap the DMA memory for the PCI Bus devices. The current IoMmuDxe driver supports DMA operations inside SEV guest. To support DMA operation in TDX guest, CC_GUEST_IS_XXX (PcdConfidentialComputingGuestAttr) is used to determine if it is SEV guest or TDX guest. Due to security reasons all DMA operations inside the SEV/TDX guest must be performed on shared pages. The IOMMU protocol driver for the SEV/TDX guest uses a bounce buffer to map guest DMA buffer to shared pages in order to provide the support for DMA operations inside SEV/TDX guest. The call of SEV or TDX specific function to set/clear EncMask/SharedBit is determined by CC_GUEST_IS_XXX (PcdConfidentialComputingGuestAttr). Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Signed-off-by: Min Xu --- OvmfPkg/AmdSev/AmdSevX64.dsc | 1 + OvmfPkg/Bhyve/BhyveX64.dsc | 1 + OvmfPkg/CloudHv/CloudHvX64.dsc | 1 + OvmfPkg/IoMmuDxe/AmdSevIoMmu.c | 103 +++++++++++++++++++++------------ OvmfPkg/IoMmuDxe/AmdSevIoMmu.h | 6 +- OvmfPkg/IoMmuDxe/IoMmuDxe.c | 6 +- OvmfPkg/IoMmuDxe/IoMmuDxe.inf | 5 ++ OvmfPkg/Microvm/MicrovmX64.dsc | 1 + OvmfPkg/OvmfPkgX64.dsc | 2 + OvmfPkg/OvmfXen.dsc | 1 + 10 files changed, 85 insertions(+), 42 deletions(-) diff --git a/OvmfPkg/AmdSev/AmdSevX64.dsc b/OvmfPkg/AmdSev/AmdSevX64.dsc index 53464f3a54b9..21aeecf5859f 100644 --- a/OvmfPkg/AmdSev/AmdSevX64.dsc +++ b/OvmfPkg/AmdSev/AmdSevX64.dsc @@ -174,6 +174,7 @@ CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Customize= dDisplayLib.inf FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltL= ib.inf BlobVerifierLib|OvmfPkg/AmdSev/BlobVerifierLibSevHashes/BlobVerifierLibS= evHashes.inf + MemEncryptTdxLib|OvmfPkg/Library/BaseMemEncryptTdxLib/BaseMemEncryptTdxL= ib.inf =20 !if $(SOURCE_DEBUG_ENABLE) =3D=3D TRUE PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDeb= ug/PeCoffExtraActionLibDebug.inf diff --git a/OvmfPkg/Bhyve/BhyveX64.dsc b/OvmfPkg/Bhyve/BhyveX64.dsc index 656e407473bb..5d08b8925051 100644 --- a/OvmfPkg/Bhyve/BhyveX64.dsc +++ b/OvmfPkg/Bhyve/BhyveX64.dsc @@ -169,6 +169,7 @@ VirtioLib|OvmfPkg/Library/VirtioLib/VirtioLib.inf MemEncryptSevLib|OvmfPkg/Library/BaseMemEncryptSevLib/DxeMemEncryptSevLi= b.inf LockBoxLib|OvmfPkg/Library/LockBoxLib/LockBoxBaseLib.inf + MemEncryptTdxLib|OvmfPkg/Library/BaseMemEncryptTdxLib/BaseMemEncryptTdxL= ib.inf =20 CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Customize= dDisplayLib.inf FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltL= ib.inf diff --git a/OvmfPkg/CloudHv/CloudHvX64.dsc b/OvmfPkg/CloudHv/CloudHvX64.dsc index ddd2d67025e1..a4f47cfc94a3 100644 --- a/OvmfPkg/CloudHv/CloudHvX64.dsc +++ b/OvmfPkg/CloudHv/CloudHvX64.dsc @@ -184,6 +184,7 @@ !endif CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Customize= dDisplayLib.inf FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltL= ib.inf + MemEncryptTdxLib|OvmfPkg/Library/BaseMemEncryptTdxLib/BaseMemEncryptTdxL= ib.inf =20 !if $(SOURCE_DEBUG_ENABLE) =3D=3D TRUE PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDeb= ug/PeCoffExtraActionLibDebug.inf diff --git a/OvmfPkg/IoMmuDxe/AmdSevIoMmu.c b/OvmfPkg/IoMmuDxe/AmdSevIoMmu.c index 16b5b4eac8bc..6b65897f032a 100644 --- a/OvmfPkg/IoMmuDxe/AmdSevIoMmu.c +++ b/OvmfPkg/IoMmuDxe/AmdSevIoMmu.c @@ -1,9 +1,9 @@ /** @file =20 The protocol provides support to allocate, free, map and umap a DMA buff= er - for bus master (e.g PciHostBridge). When SEV is enabled, the DMA operati= ons - must be performed on unencrypted buffer hence we use a bounce buffer to = map - the guest buffer into an unencrypted DMA buffer. + for bus master (e.g PciHostBridge). When SEV or TDX is enabled, the DMA + operations must be performed on unencrypted buffer hence we use a bounce + buffer to map the guest buffer into an unencrypted DMA buffer. =20 Copyright (c) 2017, AMD Inc. All rights reserved.
Copyright (c) 2017, Intel Corporation. All rights reserved.
@@ -12,6 +12,8 @@ =20 **/ =20 +#include +#include #include "AmdSevIoMmu.h" =20 #define MAP_INFO_SIG SIGNATURE_64 ('M', 'A', 'P', '_', 'I', 'N', 'F', 'O') @@ -74,7 +76,7 @@ typedef struct { =20 /** Provides the controller-specific addresses required to access system mem= ory - from a DMA bus master. On SEV guest, the DMA operations must be performe= d on + from a DMA bus master. On SEV/TDX guest, the DMA operations must be perf= ormed on shared buffer hence we allocate a bounce buffer to map the HostAddress t= o a DeviceAddress. The Encryption attribute is removed from the DeviceAddress buffer. @@ -250,14 +252,28 @@ IoMmuMap ( goto FreeMapInfo; } =20 - // - // Clear the memory encryption mask on the plaintext buffer. - // - Status =3D MemEncryptSevClearPageEncMask ( - 0, - MapInfo->PlainTextAddress, - MapInfo->NumberOfPages - ); + if (CC_GUEST_IS_SEV (PcdGet64 (PcdConfidentialComputingGuestAttr))) { + // + // Clear the memory encryption mask on the plaintext buffer. + // + Status =3D MemEncryptSevClearPageEncMask ( + 0, + MapInfo->PlainTextAddress, + MapInfo->NumberOfPages + ); + } else if (CC_GUEST_IS_TDX (PcdGet64 (PcdConfidentialComputingGuestAttr)= )) { + // + // Set the memory shared bit. + // + Status =3D MemEncryptTdxSetPageSharedBit ( + 0, + MapInfo->PlainTextAddress, + MapInfo->NumberOfPages + ); + } else { + ASSERT (FALSE); + } + ASSERT_EFI_ERROR (Status); if (EFI_ERROR (Status)) { CpuDeadLoop (); @@ -358,7 +374,7 @@ IoMmuUnmapWorker ( } =20 MapInfo =3D (MAP_INFO *)Mapping; - + Status =3D EFI_SUCCESS; // // set CommonBufferHeader to suppress incorrect compiler/analyzer warnin= gs // @@ -404,15 +420,30 @@ IoMmuUnmapWorker ( break; } =20 - // - // Restore the memory encryption mask on the area we used to hold the - // plaintext. - // - Status =3D MemEncryptSevSetPageEncMask ( - 0, - MapInfo->PlainTextAddress, - MapInfo->NumberOfPages - ); + if (CC_GUEST_IS_SEV (PcdGet64 (PcdConfidentialComputingGuestAttr))) { + // + // Restore the memory encryption mask on the area we used to hold the + // plaintext. + // + Status =3D MemEncryptSevSetPageEncMask ( + 0, + MapInfo->PlainTextAddress, + MapInfo->NumberOfPages + ); + } else if (CC_GUEST_IS_TDX (PcdGet64 (PcdConfidentialComputingGuestAttr)= )) { + // + // Restore the memory shared bit mask on the area we used to hold the + // plaintext. + // + Status =3D MemEncryptTdxClearPageSharedBit ( + 0, + MapInfo->PlainTextAddress, + MapInfo->NumberOfPages + ); + } else { + ASSERT (FALSE); + } + ASSERT_EFI_ERROR (Status); if (EFI_ERROR (Status)) { CpuDeadLoop (); @@ -739,7 +770,7 @@ IoMmuSetAttribute ( return EFI_UNSUPPORTED; } =20 -EDKII_IOMMU_PROTOCOL mAmdSev =3D { +EDKII_IOMMU_PROTOCOL mIoMmu =3D { EDKII_IOMMU_PROTOCOL_REVISION, IoMmuSetAttribute, IoMmuMap, @@ -771,7 +802,7 @@ EDKII_IOMMU_PROTOCOL mAmdSev =3D { STATIC VOID EFIAPI -AmdSevExitBoot ( +IoMmuExitBoot ( IN EFI_EVENT Event, IN VOID *EventToSignal ) @@ -779,11 +810,11 @@ AmdSevExitBoot ( // // (1) The NotifyFunctions of all the events in // EFI_EVENT_GROUP_EXIT_BOOT_SERVICES will have been queued before - // AmdSevExitBoot() is entered. + // IoMmuExitBoot() is entered. // - // (2) AmdSevExitBoot() is executing minimally at TPL_CALLBACK. + // (2) IoMmuExitBoot() is executing minimally at TPL_CALLBACK. // - // (3) AmdSevExitBoot() has been queued in unspecified order relative to= the + // (3) IoMmuExitBoot() has been queued in unspecified order relative to = the // NotifyFunctions of all the other events in // EFI_EVENT_GROUP_EXIT_BOOT_SERVICES whose NotifyTpl is the same as // Event's. @@ -791,13 +822,13 @@ AmdSevExitBoot ( // Consequences: // // - If Event's NotifyTpl is TPL_CALLBACK, then some other NotifyFunctio= ns - // queued at TPL_CALLBACK may be invoked after AmdSevExitBoot() return= s. + // queued at TPL_CALLBACK may be invoked after IoMmuExitBoot() returns. // // - If Event's NotifyTpl is TPL_NOTIFY, then some other NotifyFunctions - // queued at TPL_NOTIFY may be invoked after AmdSevExitBoot() returns;= plus + // queued at TPL_NOTIFY may be invoked after IoMmuExitBoot() returns; = plus // *all* NotifyFunctions queued at TPL_CALLBACK will be invoked strict= ly // after all NotifyFunctions queued at TPL_NOTIFY, including - // AmdSevExitBoot(), have been invoked. + // IoMmuExitBoot(), have been invoked. // // - By signaling EventToSignal here, whose NotifyTpl is TPL_CALLBACK, we // queue EventToSignal's NotifyFunction after the NotifyFunctions of *= all* @@ -823,7 +854,7 @@ AmdSevExitBoot ( STATIC VOID EFIAPI -AmdSevUnmapAllMappings ( +IoMmuUnmapAllMappings ( IN EFI_EVENT Event, IN VOID *Context ) @@ -842,7 +873,7 @@ AmdSevUnmapAllMappings ( NextNode =3D GetNextNode (&mMapInfos, Node); MapInfo =3D CR (Node, MAP_INFO, Link, MAP_INFO_SIG); IoMmuUnmapWorker ( - &mAmdSev, // This + &mIoMmu, // This MapInfo, // Mapping TRUE // MemoryMapLocked ); @@ -855,7 +886,7 @@ AmdSevUnmapAllMappings ( **/ EFI_STATUS EFIAPI -AmdSevInstallIoMmuProtocol ( +InstallIoMmuProtocol ( VOID ) { @@ -871,7 +902,7 @@ AmdSevInstallIoMmuProtocol ( Status =3D gBS->CreateEvent ( EVT_NOTIFY_SIGNAL, // Type TPL_CALLBACK, // NotifyTpl - AmdSevUnmapAllMappings, // NotifyFunction + IoMmuUnmapAllMappings, // NotifyFunction NULL, // NotifyContext &UnmapAllMappingsEvent // Event ); @@ -886,7 +917,7 @@ AmdSevInstallIoMmuProtocol ( Status =3D gBS->CreateEvent ( EVT_SIGNAL_EXIT_BOOT_SERVICES, // Type TPL_CALLBACK, // NotifyTpl - AmdSevExitBoot, // NotifyFunction + IoMmuExitBoot, // NotifyFunction UnmapAllMappingsEvent, // NotifyContext &ExitBootEvent // Event ); @@ -898,7 +929,7 @@ AmdSevInstallIoMmuProtocol ( Status =3D gBS->InstallMultipleProtocolInterfaces ( &Handle, &gEdkiiIoMmuProtocolGuid, - &mAmdSev, + &mIoMmu, NULL ); if (EFI_ERROR (Status)) { diff --git a/OvmfPkg/IoMmuDxe/AmdSevIoMmu.h b/OvmfPkg/IoMmuDxe/AmdSevIoMmu.h index 8244f28b57fd..8fdfa9968593 100644 --- a/OvmfPkg/IoMmuDxe/AmdSevIoMmu.h +++ b/OvmfPkg/IoMmuDxe/AmdSevIoMmu.h @@ -21,17 +21,17 @@ #include #include #include +#include #include #include =20 /** - Install IOMMU protocol to provide the DMA support for PciHostBridge and - MemEncryptSevLib. + Install IOMMU protocol to provide the DMA support for PciHostBridge. =20 **/ EFI_STATUS EFIAPI -AmdSevInstallIoMmuProtocol ( +InstallIoMmuProtocol ( VOID ); =20 diff --git a/OvmfPkg/IoMmuDxe/IoMmuDxe.c b/OvmfPkg/IoMmuDxe/IoMmuDxe.c index bca8c14c4076..86777dd05c26 100644 --- a/OvmfPkg/IoMmuDxe/IoMmuDxe.c +++ b/OvmfPkg/IoMmuDxe/IoMmuDxe.c @@ -22,11 +22,11 @@ IoMmuDxeEntryPoint ( EFI_HANDLE Handle; =20 // - // When SEV is enabled, install IoMmu protocol otherwise install the + // When SEV or TDX is enabled, install IoMmu protocol otherwise install = the // placeholder protocol so that other dependent module can run. // - if (MemEncryptSevIsEnabled ()) { - Status =3D AmdSevInstallIoMmuProtocol (); + if (MemEncryptSevIsEnabled () || MemEncryptTdxIsEnabled ()) { + Status =3D InstallIoMmuProtocol (); } else { Handle =3D NULL; =20 diff --git a/OvmfPkg/IoMmuDxe/IoMmuDxe.inf b/OvmfPkg/IoMmuDxe/IoMmuDxe.inf index 2ebd74e5558c..e10be1dcff49 100644 --- a/OvmfPkg/IoMmuDxe/IoMmuDxe.inf +++ b/OvmfPkg/IoMmuDxe/IoMmuDxe.inf @@ -26,16 +26,21 @@ MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec OvmfPkg/OvmfPkg.dec +# UefiCpuPkg/UefiCpuPkg.dec =20 [LibraryClasses] BaseLib BaseMemoryLib DebugLib MemEncryptSevLib + MemEncryptTdxLib MemoryAllocationLib UefiBootServicesTableLib UefiDriverEntryPoint =20 +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdConfidentialComputingGuestAttr + [Protocols] gEdkiiIoMmuProtocolGuid ## SOMETIME_PRODUCES gIoMmuAbsentProtocolGuid ## SOMETIME_PRODUCES diff --git a/OvmfPkg/Microvm/MicrovmX64.dsc b/OvmfPkg/Microvm/MicrovmX64.dsc index a09f542c83fb..905cf52de92d 100644 --- a/OvmfPkg/Microvm/MicrovmX64.dsc +++ b/OvmfPkg/Microvm/MicrovmX64.dsc @@ -181,6 +181,7 @@ LockBoxLib|OvmfPkg/Library/LockBoxLib/LockBoxBaseLib.inf CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Customize= dDisplayLib.inf FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltL= ib.inf + MemEncryptTdxLib|OvmfPkg/Library/BaseMemEncryptTdxLib/BaseMemEncryptTdxL= ib.inf =20 !if $(SOURCE_DEBUG_ENABLE) =3D=3D TRUE PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDeb= ug/PeCoffExtraActionLibDebug.inf diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index 2eb45c6d0bad..ad02e4c1ba24 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -180,6 +180,8 @@ VirtioLib|OvmfPkg/Library/VirtioLib/VirtioLib.inf LoadLinuxLib|OvmfPkg/Library/LoadLinuxLib/LoadLinuxLib.inf MemEncryptSevLib|OvmfPkg/Library/BaseMemEncryptSevLib/DxeMemEncryptSevLi= b.inf + MemEncryptTdxLib|OvmfPkg/Library/BaseMemEncryptTdxLib/BaseMemEncryptTdxL= ib.inf + !if $(SMM_REQUIRE) =3D=3D FALSE LockBoxLib|OvmfPkg/Library/LockBoxLib/LockBoxBaseLib.inf !endif diff --git a/OvmfPkg/OvmfXen.dsc b/OvmfPkg/OvmfXen.dsc index 61a03d626195..e4fe304c496b 100644 --- a/OvmfPkg/OvmfXen.dsc +++ b/OvmfPkg/OvmfXen.dsc @@ -170,6 +170,7 @@ LockBoxLib|OvmfPkg/Library/LockBoxLib/LockBoxBaseLib.inf CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Customize= dDisplayLib.inf FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltL= ib.inf + MemEncryptTdxLib|OvmfPkg/Library/BaseMemEncryptTdxLib/BaseMemEncryptTdxL= ib.inf =20 !if $(SOURCE_DEBUG_ENABLE) =3D=3D TRUE PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDeb= ug/PeCoffExtraActionLibDebug.inf --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#86000): https://edk2.groups.io/g/devel/message/86000 Mute This Topic: https://groups.io/mt/88617557/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Apr 29 10:32:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+86001+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+86001+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1642901988; cv=none; d=zohomail.com; s=zohoarc; b=NofxzTdYIAq/mfFS99pqaBuG6w5J0/XMe3mvywZkHKI7pShB++kRtLDchcgMOYKLm2N/DtxCQofgKeY6c4Og1j483r8OCOc9oj684y6P2LN6JO0k3paPuNg07HBTgjCW6gD0OQOFx9KG7LtQfkS5GDg9PHKq7P/nCl2WG1RYvn8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1642901988; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=wgIY7CPJcVrUlj5d7ufB7cDFZ26HK/BodrWfW8zaUgM=; b=iSi4p5QjLsZ/3lKvCEm1jCkeoRGmTy7Dmat6kJnKuCqKECJnLwYnxJnRe7w+pjoCupRI2wFJ29fVV8Xpj/kRF1JLnyiVrYlOpu8uTB7z8b8vG9nZGCN/bt/yzD5yOfklpDFd0XsPZUVfOmK8E5V/M1wxO6RQoOS15wap2IpQJdc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+86001+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1642901988226577.5074928967709; Sat, 22 Jan 2022 17:39:48 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id dNnpYY1788612x4moDUX1IRI; Sat, 22 Jan 2022 17:39:47 -0800 X-Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web08.4551.1642901977372480965 for ; Sat, 22 Jan 2022 17:39:47 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10235"; a="244686223" X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="244686223" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:39:45 -0800 X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="695033357" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.255.30.84]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:39:42 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann , Anthony Perard , Julien Grall Subject: [edk2-devel] [PATCH V5 31/33] OvmfPkg: Rename XenTimerDxe to LocalApicTimerDxe Date: Sun, 23 Jan 2022 09:37:02 +0800 Message-Id: <56501c3ac2917c183b085a13f4db115822171b15.1642899774.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: qvVlwP72LXvYmbNjb6Ye1Je9x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1642901987; bh=UOTm2F2Kxp8eUltD3+CMZjcpwpLRTEYH2W8jtnH5450=; h=Cc:Date:From:Reply-To:Subject:To; b=NU8dXjzQdMK+qiuHpHTxIvWZSuWh+2kqhyLnlxzRWbVyCk6jB82gY1kYh3sVt7HTeuS fVaJip9oFN2zV1FdSYcVmp1G+9/Lg/NhMsf0lQz6KILfGLgbJ/hnfbp7opzMQ4R0zbAck Ib9tPRctMqH0VX+yYbPeh5kkI/coGzdlSVg= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1642901988988100001 Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3711 XenTimerDxe is a local Apic timer driver and it has nothing to do with Xen. So rename it to LocalApicTimerDxe. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Cc: Anthony Perard Cc: Julien Grall Acked-by: Anthony PERARD Signed-off-by: Min Xu --- OvmfPkg/CloudHv/CloudHvX64.dsc | 2 +- OvmfPkg/CloudHv/CloudHvX64.fdf | 2 +- .../XenTimerDxe.c =3D> LocalApicTimerDxe/LocalApicTimerDxe.c} | 2 +- .../XenTimerDxe.h =3D> LocalApicTimerDxe/LocalApicTimerDxe.h} | 4 ++-- .../LocalApicTimerDxe.inf} | 6 +++--- OvmfPkg/Microvm/MicrovmX64.dsc | 2 +- OvmfPkg/Microvm/MicrovmX64.fdf | 2 +- OvmfPkg/OvmfXen.dsc | 2 +- OvmfPkg/OvmfXen.fdf | 2 +- 9 files changed, 12 insertions(+), 12 deletions(-) rename OvmfPkg/{XenTimerDxe/XenTimerDxe.c =3D> LocalApicTimerDxe/LocalApic= TimerDxe.c} (96%) rename OvmfPkg/{XenTimerDxe/XenTimerDxe.h =3D> LocalApicTimerDxe/LocalApic= TimerDxe.h} (96%) rename OvmfPkg/{XenTimerDxe/XenTimerDxe.inf =3D> LocalApicTimerDxe/LocalAp= icTimerDxe.inf} (86%) diff --git a/OvmfPkg/CloudHv/CloudHvX64.dsc b/OvmfPkg/CloudHv/CloudHvX64.dsc index a4f47cfc94a3..36dfa5e54286 100644 --- a/OvmfPkg/CloudHv/CloudHvX64.dsc +++ b/OvmfPkg/CloudHv/CloudHvX64.dsc @@ -707,7 +707,7 @@ MdeModulePkg/Universal/EbcDxe/EbcDxe.inf UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf UefiCpuPkg/CpuDxe/CpuDxe.inf - OvmfPkg/XenTimerDxe/XenTimerDxe.inf + OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf OvmfPkg/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.inf OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf { diff --git a/OvmfPkg/CloudHv/CloudHvX64.fdf b/OvmfPkg/CloudHv/CloudHvX64.fdf index ce3302c6d6ed..60721d0f2f56 100644 --- a/OvmfPkg/CloudHv/CloudHvX64.fdf +++ b/OvmfPkg/CloudHv/CloudHvX64.fdf @@ -234,7 +234,7 @@ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStu= bDxe.inf INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf INF UefiCpuPkg/CpuDxe/CpuDxe.inf -INF OvmfPkg/XenTimerDxe/XenTimerDxe.inf +INF OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf INF OvmfPkg/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.= inf INF OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf diff --git a/OvmfPkg/XenTimerDxe/XenTimerDxe.c b/OvmfPkg/LocalApicTimerDxe/= LocalApicTimerDxe.c similarity index 96% rename from OvmfPkg/XenTimerDxe/XenTimerDxe.c rename to OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.c index bbd964eb7ad9..dd9352b12088 100644 --- a/OvmfPkg/XenTimerDxe/XenTimerDxe.c +++ b/OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.c @@ -8,7 +8,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ =20 -#include "XenTimerDxe.h" +#include "LocalApicTimerDxe.h" =20 // // The handle onto which the Timer Architectural Protocol will be installed diff --git a/OvmfPkg/XenTimerDxe/XenTimerDxe.h b/OvmfPkg/LocalApicTimerDxe/= LocalApicTimerDxe.h similarity index 96% rename from OvmfPkg/XenTimerDxe/XenTimerDxe.h rename to OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.h index b55ece0d941e..93706995f8ab 100644 --- a/OvmfPkg/XenTimerDxe/XenTimerDxe.h +++ b/OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.h @@ -7,8 +7,8 @@ Copyright (c) 2019, Citrix Systems, Inc. SPDX-License-Identifier: BSD-2-Clause-Patent **/ =20 -#ifndef _TIMER_H_ -#define _TIMER_H_ +#ifndef LOCAL_APIC_TIMER_H_ +#define LOCAL_APIC_TIMER_H_ =20 #include =20 diff --git a/OvmfPkg/XenTimerDxe/XenTimerDxe.inf b/OvmfPkg/LocalApicTimerDx= e/LocalApicTimerDxe.inf similarity index 86% rename from OvmfPkg/XenTimerDxe/XenTimerDxe.inf rename to OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf index add1d01bbf9c..63b75b75c921 100644 --- a/OvmfPkg/XenTimerDxe/XenTimerDxe.inf +++ b/OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf @@ -10,7 +10,7 @@ =20 [Defines] INF_VERSION =3D 0x00010005 - BASE_NAME =3D XenTimerDxe + BASE_NAME =3D LocalApicTimerDxe FILE_GUID =3D 52fe8196-f9de-4d07-b22f-51f77a0e7c41 MODULE_TYPE =3D DXE_DRIVER VERSION_STRING =3D 1.0 @@ -30,8 +30,8 @@ LocalApicLib =20 [Sources] - XenTimerDxe.h - XenTimerDxe.c + LocalApicTimerDxe.h + LocalApicTimerDxe.c =20 [Protocols] gEfiCpuArchProtocolGuid ## CONSUMES diff --git a/OvmfPkg/Microvm/MicrovmX64.dsc b/OvmfPkg/Microvm/MicrovmX64.dsc index 905cf52de92d..bac211bd5b0c 100644 --- a/OvmfPkg/Microvm/MicrovmX64.dsc +++ b/OvmfPkg/Microvm/MicrovmX64.dsc @@ -664,7 +664,7 @@ =20 MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf MdeModulePkg/Universal/EbcDxe/EbcDxe.inf - OvmfPkg/XenTimerDxe/XenTimerDxe.inf + OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf UefiCpuPkg/CpuDxe/CpuDxe.inf OvmfPkg/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.inf diff --git a/OvmfPkg/Microvm/MicrovmX64.fdf b/OvmfPkg/Microvm/MicrovmX64.fdf index 6999ac1a87b9..3adb492a4ad7 100644 --- a/OvmfPkg/Microvm/MicrovmX64.fdf +++ b/OvmfPkg/Microvm/MicrovmX64.fdf @@ -215,7 +215,7 @@ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf -INF OvmfPkg/XenTimerDxe/XenTimerDxe.inf +INF OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf INF UefiCpuPkg/CpuDxe/CpuDxe.inf INF OvmfPkg/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.= inf diff --git a/OvmfPkg/OvmfXen.dsc b/OvmfPkg/OvmfXen.dsc index e4fe304c496b..b583b4a58fea 100644 --- a/OvmfPkg/OvmfXen.dsc +++ b/OvmfPkg/OvmfXen.dsc @@ -556,7 +556,7 @@ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf =20 MdeModulePkg/Universal/EbcDxe/EbcDxe.inf - OvmfPkg/XenTimerDxe/XenTimerDxe.inf + OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf UefiCpuPkg/CpuDxe/CpuDxe.inf OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf diff --git a/OvmfPkg/OvmfXen.fdf b/OvmfPkg/OvmfXen.fdf index a6acf3b835aa..8e9c6721f183 100644 --- a/OvmfPkg/OvmfXen.fdf +++ b/OvmfPkg/OvmfXen.fdf @@ -298,7 +298,7 @@ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf -INF OvmfPkg/XenTimerDxe/XenTimerDxe.inf +INF OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf INF UefiCpuPkg/CpuDxe/CpuDxe.inf INF OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#86001): https://edk2.groups.io/g/devel/message/86001 Mute This Topic: https://groups.io/mt/88617558/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Apr 29 10:32:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+86002+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+86002+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1642901990; cv=none; d=zohomail.com; s=zohoarc; b=fTCRQm2cQLotRzmf2CqR30rMqjt0esHrTexMhnBKvB+A24V7/TCLw6M7JNUEPl928hqxkENEYqWBScROREyChofJalrSFvHLC6qSEkRrwr8IgNSw3gBrUYguDJYuFqJbKsbaWjuyEJW9pJpdWLENV4ejK97HikOPCauwo3Sv3vY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1642901990; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=GMO/eSiXVuBvUlEE9bXOK0CbMFQyq604B4uCdC3dAy4=; b=W8GQver9oVZzdJ6jD473jlwrXE+9c64lWXdebfUfWZI2mP7yOHWThiqf0PtiLlydat/uvsGQs0AU63rtppRhBPFj/kiHRFgu1KOMRA9CoRi6tIJkcWXyTwT3C4xKS1vrB5oNvQhqEEBqAPUtOqS0/xj3DqGHHB14HZmhz88MIco= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+86002+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1642901990833956.2275920563238; Sat, 22 Jan 2022 17:39:50 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id PIUdYY1788612xkQsrY3iD8p; Sat, 22 Jan 2022 17:39:50 -0800 X-Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web08.4551.1642901977372480965 for ; Sat, 22 Jan 2022 17:39:50 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10235"; a="244686251" X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="244686251" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:39:47 -0800 X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="695033377" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.255.30.84]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:39:45 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Jiewen Yao , Gerd Hoffmann , Anthony Perard , Julien Grall , Eric Dong , Ray Ni Subject: [edk2-devel] [PATCH V5 32/33] UefiCpuPkg: Setting initial-count register as the last step Date: Sun, 23 Jan 2022 09:37:03 +0800 Message-Id: In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: SPIfDO3wXh8XMyHHkJd4Ku9gx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1642901990; bh=jD46gZ2L2KB3cTvovh9v2jPHSS1SyQQXW6QunXRw9Hg=; h=Cc:Date:From:Reply-To:Subject:To; b=vbUqOnPtbppslmG4gG87XYOYG6ixOa48aL2QcpOv9do2ZKYOXCExEsmQFigEmNf6e6F SzQpaF9q/po1A5R6CEEr7BovmPf0tAEYw3ZZLoBmaCuu+04WRsK1GJwkrZ46yeZEtYPAB rOCL75PXWH05trlLia+s6eiBgMUVJP2p88s= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1642901993097100001 Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3711 Per SDM, changing the mode of APIC timer (from one-shot to periodic or vice versa) by writing to the timer LVT entry does not start the timer. To start the timer, it is necessary to write to the initial-count register. If initial-count is wrote before mode change, it's possible that timer expired before the mode change. Thus failing the periodic mode. Cc: Jiewen Yao Cc: Gerd Hoffmann Cc: Anthony Perard Cc: Julien Grall Cc: Eric Dong Cc: Ray Ni Acked-by: Gerd Hoffmann Signed-off-by: Min Xu --- .../Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/U= efiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c index 2d17177df12b..f26d9c93894f 100644 --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c @@ -967,11 +967,6 @@ InitializeApicTimer ( // InitializeLocalApicSoftwareEnable (TRUE); =20 - // - // Program init-count register. - // - WriteLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET, InitCount); - if (DivideValue !=3D 0) { ASSERT (DivideValue <=3D 128); ASSERT (DivideValue =3D=3D GetPowerOfTwo32 ((UINT32)DivideValue)); @@ -996,6 +991,11 @@ InitializeApicTimer ( LvtTimer.Bits.Mask =3D 0; LvtTimer.Bits.Vector =3D Vector; WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32); + + // + // Program init-count register. + // + WriteLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET, InitCount); } =20 /** --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#86002): https://edk2.groups.io/g/devel/message/86002 Mute This Topic: https://groups.io/mt/88617559/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Apr 29 10:32:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+86003+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+86003+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1642901992; cv=none; d=zohomail.com; s=zohoarc; b=cuSXz0VrQDhvPfZS54u++YPLmI5Wwz7qn1u9k3GzTsVN9FFtrZt2kUAZA4Y3G9OxE0c+4VeBwqEDaSpnzdNHwQ1snFqno1fqWYPtECIITh4qFPlH7mm4uKQ/JIlEqL52qPeUoy4ELIlCz0UwAlZ+3L0UKaNlf57ctzwB4yWnHx8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1642901992; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=7usx/hvpptnKSyNSMYgepwEEC7v9C4R00PsaImg9b0g=; b=DGFbB9MAi9I54I22hI8ypOtEtg5C3BXslodaeLq617hDfLeSOr5ENFhl1i/Mdy6OswIl50Ppocq68eCILQB8MiHi/62h4cijNl0nSedmfWgsXY8Rwmx/nG297JNttkgsVS1Q3trbeBawmfJ3L7ewwiDMhKgSIIxC4ixKltbhQxE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+86003+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1642901992565841.2234722447955; Sat, 22 Jan 2022 17:39:52 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id CG1fYY1788612xmJwUAsqG6s; Sat, 22 Jan 2022 17:39:52 -0800 X-Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web08.4551.1642901977372480965 for ; Sat, 22 Jan 2022 17:39:51 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10235"; a="244686271" X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="244686271" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:39:50 -0800 X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="695033398" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.255.30.84]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:39:47 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann Subject: [edk2-devel] [PATCH V5 33/33] OvmfPkg: Switch timer in build time for OvmfPkg Date: Sun, 23 Jan 2022 09:37:04 +0800 Message-Id: <65daa654674a633af99b383405c2399da5e661d7.1642899774.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: cGMGbhyt88nabn10JWViCulmx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1642901992; bh=iPTbfnmkV57GnVWygp/lstrJTaL1NQ7QhWSnBYZkkzA=; h=Cc:Date:From:Reply-To:Subject:To; b=Fl7xbswfxzYnUzTHAcxSyHrTNsTKhAUQ1eyDkFPpQEs0CYm99BPU2Il0xKsAwcCK7AX ktSHimowund+xk3wOlXxLYqs6MaQ/UgQYS2iy+TwwBc9avZJ907lsrnpozck9sUW+ZV3O tw88jtyo2Rz8xK9VkWEpKzqDehNd/aebE2M= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1642901993312100005 Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3711 Discussion in https://bugzilla.tianocore.org/show_bug.cgi?id=3D1496 shows that 8254TimerDxe was not written for OVMF. It was moved over from PcAtChipsetPkg to OvmfPkg in 2019. Probably because OVMF was the only user left. Most likely the reason OVMF used 8254TimerDxe initially was that it could just use the existing driver in PcAtChipsetPkg. And it simply hasn't been changed ever. CSM support was moved in 2019 too. (CSM support depends on 8254/8259 drivers). So 8254TimerDxe will be used when CSM_ENABLE=3DTRUE. There are 4 .dsc which include the 8254Timer. - OvmfPkg/AmdSev/AmdSevX64.dsc - OvmfPkg/OvmfPkgIa32.dsc - OvmfPkg/OvmfPkgIa32X64.dsc - OvmfPkg/OvmfPkgX64.dsc For the three OvmfPkg* configs using 8254TimerDxe with CSM_ENABLE=3DTRUE and LapicTimerDxe otherwise. For the AmdSev config it doesn't make sense to support a CSM. So use the lapic timer unconditionally. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Suggested-by: Gerd Hoffmann Acked-by: Gerd Hoffmann Signed-off-by: Min Xu --- OvmfPkg/AmdSev/AmdSevX64.dsc | 5 +++-- OvmfPkg/AmdSev/AmdSevX64.fdf | 3 +-- OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.c | 2 +- OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf | 1 + OvmfPkg/OvmfPkgIa32.dsc | 10 +++++++++- OvmfPkg/OvmfPkgIa32.fdf | 8 ++++++-- OvmfPkg/OvmfPkgIa32X64.dsc | 10 +++++++++- OvmfPkg/OvmfPkgIa32X64.fdf | 8 ++++++-- OvmfPkg/OvmfPkgX64.dsc | 10 +++++++++- OvmfPkg/OvmfPkgX64.fdf | 8 ++++++-- 10 files changed, 51 insertions(+), 14 deletions(-) diff --git a/OvmfPkg/AmdSev/AmdSevX64.dsc b/OvmfPkg/AmdSev/AmdSevX64.dsc index 21aeecf5859f..3fe6919773aa 100644 --- a/OvmfPkg/AmdSev/AmdSevX64.dsc +++ b/OvmfPkg/AmdSev/AmdSevX64.dsc @@ -570,6 +570,8 @@ =20 !include OvmfPkg/OvmfTpmPcds.dsc.inc =20 + gEfiMdePkgTokenSpaceGuid.PcdFSBClock|100000000 + [PcdsDynamicHii] !include OvmfPkg/OvmfTpmPcdsHii.dsc.inc =20 @@ -638,10 +640,9 @@ } =20 MdeModulePkg/Universal/EbcDxe/EbcDxe.inf - OvmfPkg/8259InterruptControllerDxe/8259.inf UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf UefiCpuPkg/CpuDxe/CpuDxe.inf - OvmfPkg/8254TimerDxe/8254Timer.inf + OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf OvmfPkg/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.inf OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf { diff --git a/OvmfPkg/AmdSev/AmdSevX64.fdf b/OvmfPkg/AmdSev/AmdSevX64.fdf index 14b5b5593f97..0d460569c0ef 100644 --- a/OvmfPkg/AmdSev/AmdSevX64.fdf +++ b/OvmfPkg/AmdSev/AmdSevX64.fdf @@ -200,10 +200,9 @@ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf -INF OvmfPkg/8259InterruptControllerDxe/8259.inf INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf INF UefiCpuPkg/CpuDxe/CpuDxe.inf -INF OvmfPkg/8254TimerDxe/8254Timer.inf +INF OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf INF OvmfPkg/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.= inf INF OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf diff --git a/OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.c b/OvmfPkg/LocalA= picTimerDxe/LocalApicTimerDxe.c index dd9352b12088..cbc17c979cb6 100644 --- a/OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.c +++ b/OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.c @@ -174,7 +174,7 @@ TimerDriverSetTimerPeriod ( // DisableApicTimerInterrupt (); } else { - TimerFrequency =3D PcdGet32 (PcdFSBClock) / DivideValue; + TimerFrequency =3D PcdGet32 (PcdFSBClock) / (UINT32)DivideValue; =20 // // Convert TimerPeriod into local APIC counts diff --git a/OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf b/OvmfPkg/Loca= lApicTimerDxe/LocalApicTimerDxe.inf index 63b75b75c921..3ad28a148c5b 100644 --- a/OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf +++ b/OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf @@ -1,5 +1,6 @@ ## @file # Local APIC timer driver that provides Timer Arch protocol. +# PcdFSBClock is defined in MdePkg and it should be set by the consumer. # # Copyright (c) 2005 - 2019, Intel Corporation. All rights reserved.
# Copyright (c) 2019, Citrix Systems, Inc. diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc index f270ca7249ec..e461956de499 100644 --- a/OvmfPkg/OvmfPkgIa32.dsc +++ b/OvmfPkg/OvmfPkgIa32.dsc @@ -641,6 +641,10 @@ # Set ConfidentialComputing defaults gEfiMdePkgTokenSpaceGuid.PcdConfidentialComputingGuestAttr|0 =20 +!if $(CSM_ENABLE) =3D=3D FALSE + gEfiMdePkgTokenSpaceGuid.PcdFSBClock|100000000 +!endif + [PcdsDynamicHii] !include OvmfPkg/OvmfTpmPcdsHii.dsc.inc =20 @@ -721,10 +725,14 @@ } =20 MdeModulePkg/Universal/EbcDxe/EbcDxe.inf - OvmfPkg/8259InterruptControllerDxe/8259.inf UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf UefiCpuPkg/CpuDxe/CpuDxe.inf +!ifdef $(CSM_ENABLE) + OvmfPkg/8259InterruptControllerDxe/8259.inf OvmfPkg/8254TimerDxe/8254Timer.inf +!else + OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf +!endif OvmfPkg/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.inf OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf { diff --git a/OvmfPkg/OvmfPkgIa32.fdf b/OvmfPkg/OvmfPkgIa32.fdf index a6b2142ccd0c..3ab1755749d4 100644 --- a/OvmfPkg/OvmfPkgIa32.fdf +++ b/OvmfPkg/OvmfPkgIa32.fdf @@ -206,10 +206,14 @@ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf -INF OvmfPkg/8259InterruptControllerDxe/8259.inf INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf INF UefiCpuPkg/CpuDxe/CpuDxe.inf -INF OvmfPkg/8254TimerDxe/8254Timer.inf +!ifdef $(CSM_ENABLE) + INF OvmfPkg/8259InterruptControllerDxe/8259.inf + INF OvmfPkg/8254TimerDxe/8254Timer.inf +!else + INF OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf +!endif INF OvmfPkg/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.= inf INF OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc index 6ccae56d1c44..1633450a61a6 100644 --- a/OvmfPkg/OvmfPkgIa32X64.dsc +++ b/OvmfPkg/OvmfPkgIa32X64.dsc @@ -651,6 +651,10 @@ # Set ConfidentialComputing defaults gEfiMdePkgTokenSpaceGuid.PcdConfidentialComputingGuestAttr|0 =20 +!if $(CSM_ENABLE) =3D=3D FALSE + gEfiMdePkgTokenSpaceGuid.PcdFSBClock|100000000 +!endif + [PcdsDynamicDefault.X64] # IPv4 and IPv6 PXE Boot support. gEfiNetworkPkgTokenSpaceGuid.PcdIPv4PXESupport|0x01 @@ -737,10 +741,14 @@ } =20 MdeModulePkg/Universal/EbcDxe/EbcDxe.inf - OvmfPkg/8259InterruptControllerDxe/8259.inf UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf UefiCpuPkg/CpuDxe/CpuDxe.inf +!ifdef $(CSM_ENABLE) + OvmfPkg/8259InterruptControllerDxe/8259.inf OvmfPkg/8254TimerDxe/8254Timer.inf +!else + OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf +!endif OvmfPkg/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.inf OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf { diff --git a/OvmfPkg/OvmfPkgIa32X64.fdf b/OvmfPkg/OvmfPkgIa32X64.fdf index 49266dd46768..e1638fa6ea38 100644 --- a/OvmfPkg/OvmfPkgIa32X64.fdf +++ b/OvmfPkg/OvmfPkgIa32X64.fdf @@ -210,10 +210,14 @@ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf -INF OvmfPkg/8259InterruptControllerDxe/8259.inf INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf INF UefiCpuPkg/CpuDxe/CpuDxe.inf -INF OvmfPkg/8254TimerDxe/8254Timer.inf +!ifdef $(CSM_ENABLE) + INF OvmfPkg/8259InterruptControllerDxe/8259.inf + INF OvmfPkg/8254TimerDxe/8254Timer.inf +!else + INF OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf +!endif INF OvmfPkg/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.= inf INF OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index ad02e4c1ba24..dac961584cbf 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -659,6 +659,10 @@ # Set ConfidentialComputing defaults gEfiMdePkgTokenSpaceGuid.PcdConfidentialComputingGuestAttr|0 =20 +!if $(CSM_ENABLE) =3D=3D FALSE + gEfiMdePkgTokenSpaceGuid.PcdFSBClock|100000000 +!endif + [PcdsDynamicHii] !include OvmfPkg/OvmfTpmPcdsHii.dsc.inc =20 @@ -739,10 +743,14 @@ } =20 MdeModulePkg/Universal/EbcDxe/EbcDxe.inf - OvmfPkg/8259InterruptControllerDxe/8259.inf UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf UefiCpuPkg/CpuDxe/CpuDxe.inf +!ifdef $(CSM_ENABLE) + OvmfPkg/8259InterruptControllerDxe/8259.inf OvmfPkg/8254TimerDxe/8254Timer.inf +!else + OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf +!endif OvmfPkg/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.inf OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf { diff --git a/OvmfPkg/OvmfPkgX64.fdf b/OvmfPkg/OvmfPkgX64.fdf index d7c18bbc6ec1..71df28705ea8 100644 --- a/OvmfPkg/OvmfPkgX64.fdf +++ b/OvmfPkg/OvmfPkgX64.fdf @@ -233,10 +233,14 @@ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf -INF OvmfPkg/8259InterruptControllerDxe/8259.inf INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf INF UefiCpuPkg/CpuDxe/CpuDxe.inf -INF OvmfPkg/8254TimerDxe/8254Timer.inf +!ifdef $(CSM_ENABLE) + INF OvmfPkg/8259InterruptControllerDxe/8259.inf + INF OvmfPkg/8254TimerDxe/8254Timer.inf +!else + INF OvmfPkg/LocalApicTimerDxe/LocalApicTimerDxe.inf +!endif INF OvmfPkg/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.= inf INF OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#86003): https://edk2.groups.io/g/devel/message/86003 Mute This Topic: https://groups.io/mt/88617560/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-